Wiring substrate and electronic device

Abstract

The wiring substrate and electronic device provided by the present disclosure include a substrate; a first pad group located on the substrate, the first pad group including an output pad; a constant voltage signal line located on the same side of the substrate as the first pad group; and a second pad group, the second pad group including a plurality of sub-pad groups arranged in parallel, each of the sub-pad groups including a plurality of pad areas arranged in series.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a wiring substrate and an electronic device. Background Technology

[0002] Miniature light-emitting diodes (LEDs), with a size of approximately less than 500 μm, are increasingly used in the display field due to their smaller size, ultra-high brightness, and long lifespan. Summary of the Invention

[0003] The specific solutions for the wiring board and electronic device disclosed herein are as follows:

[0004] On one hand, embodiments of this disclosure provide a wiring substrate, including:

[0005] Substrate;

[0006] A first pad group is located on the substrate, and the first pad group includes output pads;

[0007] The constant voltage signal line is located on the same side of the substrate as the first pad group;

[0008] The second pad group includes multiple sub-pad groups arranged in parallel, and each sub-pad group includes multiple pad areas arranged in series.

[0009] In some embodiments, the wiring substrate provided in this disclosure further includes a connecting line, and the constant voltage signal line is coupled to the plurality of sub-pad groups arranged in parallel through the connecting line.

[0010] In some embodiments, in the wiring substrate provided in the present disclosure, there are multiple second pad groups arranged in an array on the substrate, and all the pad areas in the same second pad group are arranged in an array on the substrate;

[0011] At least a portion of the connecting line is located between at least two of the pad areas in the second pad group.

[0012] In some embodiments, in the wiring substrate provided in the present disclosure, the line width of the connecting line is greater than the line width of the constant voltage signal line.

[0013] In some embodiments, in the wiring substrate provided in the present disclosure, the connecting line includes a first trace portion extending in the same direction as the constant voltage signal line, and a second trace portion extending in a direction intersecting the constant voltage signal line, wherein the second trace portion connects the constant voltage signal line and the first trace portion.

[0014] In some embodiments, in the wiring substrate provided in the present disclosure, the orthographic projection of the first pad group on the substrate and the orthographic projection of the connecting line on the substrate do not overlap.

[0015] In some embodiments, in the wiring substrate provided in the present disclosure, the second pad group includes two sub-pad groups arranged in parallel, one of the sub-pad groups includes a first pad area and a second pad area arranged in series, and the other sub-pad group includes a third pad area and a fourth pad area arranged in series.

[0016] In some embodiments, in the wiring substrate provided in the present disclosure, the first pad area is arranged in the same column as the second pad area and in the same row as the third pad area, and the fourth pad area is arranged in the same row as the first pad area and in the same column as the third pad area.

[0017] In some embodiments, in the wiring substrate provided in the present disclosure, the first pad area is arranged in the same row as the second pad area and in the same column as the third pad area, and the fourth pad area is arranged in the same column as the second pad area and in the same row as the third pad area.

[0018] In some embodiments, in the wiring substrate provided in the present disclosure, the first pad area is arranged in the same column as the third pad area and in the same row as the fourth pad area, and the second pad area is arranged in the same row as the third pad area and in the same column as the fourth pad area.

[0019] On the other hand, embodiments of this disclosure provide an electronic device, including the wiring substrate provided in the embodiments of this disclosure, a micro driver chip coupled to the first pad group, and electronic components coupled to the second pad group.

[0020] In some embodiments, the electronic device provided in the present disclosure further includes a plurality of first transparent protective structures, wherein the orthographic projection of each first transparent protective structure on the substrate covers the orthographic projection of each electronic component on the substrate.

[0021] In some embodiments, in the electronic device provided in the present disclosure, the orthographic projection of the connecting line on the substrate and the orthographic projection of the first transparent protective structure on the substrate do not overlap.

[0022] In some embodiments, the electronic device described above provided in the present disclosure further includes a second transparent protective structure, the orthographic projection of the second transparent protective structure on the substrate covering the orthographic projection of the micro driver chip on the substrate.

[0023] In some embodiments, in the electronic device provided in the present disclosure, the orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the second transparent protective structure on the substrate in multiple portions.

[0024] In some embodiments, in the electronic device provided in the present disclosure, the connecting line has a recess in the intersection area of ​​the first wiring portion and the second wiring portion, and the orthographic projection of the first wiring portion on the substrate and the orthographic projection of the second wiring portion on the substrate do not overlap with the orthographic projection of the second transparent protective structure on the substrate. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the wiring substrate provided in the embodiments of this disclosure;

[0026] Figure 2 A schematic diagram of a structure of a first pad group and a second pad group coupled to it in a wiring substrate provided in an embodiment of the present disclosure;

[0027] Figure 3 This is another schematic diagram of the structure of a first pad group and a second pad group coupled to it in a wiring substrate provided in an embodiment of the present disclosure.

[0028] Figure 4 This is another schematic diagram of the structure of a first pad group and a second pad group coupled to it in a wiring substrate provided in an embodiment of the present disclosure.

[0029] Figure 5 A schematic diagram of a structure of an area containing a first pad group and a second pad group coupled thereto in an electronic device provided in an embodiment of this disclosure;

[0030] Figure 6 Another structural schematic diagram of an area containing a first pad group and a second pad group coupled thereto in an electronic device provided in an embodiment of this disclosure;

[0031] Figure 7 Another structural schematic diagram of an area containing a first pad group and a second pad group coupled thereto in an electronic device provided in an embodiment of this disclosure;

[0032] Figure 8 Another structural schematic diagram of an area containing a first pad group and a second pad group coupled thereto in an electronic device provided in an embodiment of this disclosure;

[0033] Figure 9 This is a schematic diagram of the structure of a micro driver chip provided in an embodiment of this disclosure. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0035] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0036] Micro LED display technology combines many advantages of liquid crystal display technology and organic light-emitting display technology. In particular, when micro LED display technology is applied to backlight, it can achieve more precise dynamic backlighting effects. While effectively improving screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, optimize the visual experience, and is more suitable for ultra-large screen products.

[0037] In large-scale electronic devices, multiple electronic components and a miniature driver chip constitute a functional area, with thousands of such functional areas arranged in an array. Without considering path losses, to ensure the normal operation of each electronic component at its rated power, the multiple electronic components in each functional area are connected in series. Therefore, the output power of the miniature driver chip providing drive signals to these multiple electronic components is at least I. 2 R 总 Where I is the rated current of the electronic component, and R... 总 It represents the total resistance of multiple electronic components within a functional area.

[0038] This disclosure provides a wiring substrate, such as... Figure 1 and Figure 2 As shown, it includes:

[0039] Substrate 101;

[0040] A first pad group 102 is located on a substrate 101, and the first pad group 102 includes an output pad Out.

[0041] The constant voltage signal line 103 is located on the same side of the substrate 101 as the first pad group 102;

[0042] The second pad group 104 includes multiple sub-pad groups 104' arranged in parallel. Each sub-pad group 104' includes multiple pad areas (e.g., E1 and E2, E3 and E4) arranged in series. Optionally, each pad area (e.g., E1 to E4) includes at least a first pad 41 and a second pad 42. In the series circuit of each sub-pad group 104', the first pad 41 of the first pad area (e.g., E1 or E3) is coupled to the constant voltage signal line 103, the second pad 42 of the nth pad area (e.g., E1 or E3) is coupled to the first pad 41 of the (n+1)th pad area (e.g., E2 or E4), and the second pad 42 of the last pad area (e.g., E2 or E4) is coupled to the output pad Out of the first pad group 102.

[0043] In the wiring substrate provided in this embodiment, by connecting each pad area (e.g., E1 to E4) in series to form multiple sub-pad groups 104' within a second pad group 104 (corresponding to one lamp area), and then connecting each sub-pad group 104' in parallel, the electronic components coupled to each pad area (e.g., E1 to E4) are connected in a series and parallel combination. Without considering path loss, to ensure that each electronic component operates normally at its rated power, the output power of the micro-driver chip coupled to the first pad group 102 is at least I. 2 / [ ], where I is the rated current of the electronic component, m is the total number of sub-pad groups 104' contained in a second pad group 104, t is an integer greater than or equal to 1 and less than or equal to m, R m This represents the total resistance of all electronic components connected in series within a sub-pad group 104'. This is the reciprocal of the sum of the resistances of the electronic components connected in parallel within a second pad group 104. Given a constant number N of electronic components coupled to a second pad group 104, and each electronic component having a resistance of R, For m 2 / (N R), in related technologies R 总 For N R, therefore the output power I of the micro driver chip in this disclosure 2 / [ ] is (N R I 2 ) / m 2The output power I of the micro-driver chip in related technologies 2 R 总 For N R I 2 As can be seen from the comparison, the output power of the micro-driver chip disclosed in this disclosure is less than that of the micro-driver chips in the related technologies. Therefore, the micro-driver chip with lower power and lower cost in this disclosure can replace the micro-driver chip with higher power and higher cost in the related technologies, thereby saving costs and improving product competitiveness.

[0044] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, it may also include a connecting line 105. The constant voltage signal line 103 is coupled to a plurality of parallel sub-pad groups 104' through the connecting line 105. Optionally, the constant voltage signal line 103 is connected to the first pad 41 of the first pad area (e.g., E1 and E3) in each sub-pad group 104' through the connecting line 105, so that the constant voltage signal provided by the constant voltage signal line 103 is transmitted to the first pad 41 of the first pad area (e.g., E1 and E3) in each sub-pad group 104' through the connecting line 105.

[0045] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the second pad group 104 consists of multiple pads (only 2 are shown in the figure). Two pads are arranged in an array on the substrate 101, and all pad areas (e.g., E1 to E4) in the same second pad group 104 are arranged in an array on the substrate 101; at least a portion of the connecting line 105 is located between at least two pad areas (e.g., E1 to E4) in the second pad group 104 to make reasonable use of the space between the pad areas (e.g., E1 to E4) for wiring.

[0046] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2As shown, to reduce the transmission loss of the constant voltage signal provided by the constant voltage signal line 103, the space between the pad areas (e.g., E1 to E4) can be fully utilized in the wiring design of the connecting line 105, making the line width of the connecting line 105 as large as possible, and correspondingly, the resistance of the connecting line 105 as small as possible. Optionally, the line width d1 of the connecting line 105 is greater than the line width d2 of the constant voltage signal line. For example, the line width d1 of the connecting line 105 is greater than 1000μm and less than or equal to 3553μm, and the line width d2 of the constant voltage signal line is greater than or equal to 1000μm and less than or equal to 1433μm. Specifically, the line width d1 of the connecting line 105 can be 1991.82μm, 2000μm, etc., and the line width d2 of the constant voltage signal line can be 1000μm, etc.

[0047] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the connecting line 105 may include a first trace portion 51 extending in the same direction as the constant voltage signal line 103, and a second trace portion 52 extending in a direction intersecting the constant voltage signal line 103. The second trace portion 52 connects the constant voltage signal line 103 and the first trace portion 51. Optionally, the first trace portion 51 may be arranged at the column gaps of each pad area (e.g., E1 to E4) in the same second pad group 104, and the line width d of the first trace portion 51 is... 11 The linewidth d of the first trace section 51 is greater than or equal to 2000μm and less than or equal to 3553μm. 11 The widths are 2000μm, 2500μm, 3000μm, 3500μm, etc. The second trace portion 52 can be positioned at the row gap between adjacent second pad groups 104, and the trace width d of the second trace portion 52 is... 12 The linewidth d is greater than 1000μm and less than or equal to 3200μm, for example, the linewidth d of the second trace section 52. 12 The sizes are 1500μm, 2000μm, 2500μm, 3000μm, etc.

[0048] With the linewidth d2 of the constant voltage signal line 103 being 1000μm, the linewidth d of the first trace portion 51 is... 11 The linewidth d of the second trace section 52 is 2000μm. 12 Taking a constant voltage signal line 103 with a thickness of 1991.82 μm, and the thickness of the first trace portion 51 and the second trace portion 52 all being 1.8 μm, and the sheet resistance of each being 0.011 Ω / □, the total resistance of the constant voltage signal line 103 in the related technology is calculated to be 0.1851 mΩ using software. In this disclosure, the first trace portion... 51 Second wiring section 52This design can compensate for the linewidth of the constant voltage signal line 103. The total resistance of the constant voltage signal line 103, the first trace 51, and the second trace 52 is calculated to be 0.17331 mΩ. Therefore, the resistance reduction rate along the constant voltage signal transmission path in this disclosure is (1 - 0.17331 / 0.1851). 100 = 6.4%. Therefore, this disclosure can reduce the voltage drop of constant voltage signals, improve the electrical characteristics of the circuit, and enhance product uniformity.

[0049] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the orthographic projection of the first pad group 102 on the substrate 101 and the orthographic projection of the connecting line 105 on the substrate 101 do not overlap, so that the connecting line 105 avoids the first pad group 102 and avoids short-circuiting between the connecting line 105 and the first pad group 102.

[0050] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figures 2 to 4 As shown, the second pad group 104 may include two sub-pad groups 104' arranged in parallel. One sub-pad group 104' includes a first pad area E1 and a second pad area E2 arranged in series, and the other sub-pad group 104' includes a third pad area E3 and a fourth pad area E4 arranged in series. Optionally, in Figure 2 In the middle, the first pad area E1 is arranged in the same column as the second pad area E2 and in the same row as the third pad area E3; the fourth pad area E4 is arranged in the same row as the first pad area E1 and in the same column as the third pad area E3; Figure 3 In the first pad area E1, it is arranged in the same row as the second pad area E2 and in the same column as the third pad area E3; the fourth pad area E4 is arranged in the same column as the second pad area E2 and in the same row as the third pad area E3. Figure 4 In the first pad area E1, the third pad area E3 is set in the same column and the fourth pad area E4 is set in the same row. The second pad area E2 is set in the same row as the third pad area E3 and the fourth pad area E4 is set in the same column.

[0051] It should be noted that this disclosure is only based on the example that the second pad group 104 includes two sub-pad groups 104', and each sub-pad group 104' includes two pad areas. In specific implementation, the second pad group 104 may also include more than two sub-pad groups 104', and each sub-pad group 104' may include more than two pad areas. This is not limited here.

[0052] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2As shown, the first pad group 102, in addition to the output pad Out, may also include an address pad Di, a power supply pad Pwr, and a ground pad Gnd. The address pad Di and the power supply pad Pwr, belonging to the same first pad group 102, are spaced apart in the row direction X and spaced apart from the output pad Out in the column direction Y. The ground pad Gnd is spaced apart from the power supply pad Pwr in the column direction Y and spaced apart from the output pad Out in the row direction X. For example, the output pad Out is located at the upper left corner of the first pad group 102, the address pad Di is located at the lower left corner of the first pad group 102, the ground pad Gnd is located at the upper right corner of the first pad group 102, and the power supply pad Pwr is located at the lower right corner of the first pad group 102.

[0053] Optionally, each first pad group 102 can be coupled to a micro-driver chip 002, and each second pad group 104 can be coupled to multiple electronic components 003. In some embodiments, the address pad Di can receive an address signal to select the micro-driver chip 002 at the corresponding address. The power supply pad Pwr can provide operating voltage and communication data to the micro-driver chip 002, which can be used to control the operating state of the corresponding electronic component. The output pad Out can output a relay signal and a drive signal at different time periods. Optionally, the relay signal is an address signal provided to the address pad Di in the next-level first pad group 102, and the drive signal is a drive current used to drive the electronic component coupled to the first pad group 102 where the output pad Out is located. The ground pad Gnd receives a common voltage signal.

[0054] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, in the column direction Y, each first pad group 102 can be cascaded. Optionally, the address pad Di of the first-level first pad group 102 in the same column is connected to the address signal line 107, the output pad Out of the k-th (k is a positive integer)-level first pad group 102 and the address pad Di of the (k+1)-th-level first pad group 102 are connected through the cascading line 106, and the output pad Out of the last-level first pad group 102 is connected to the feedback signal line 108.

[0055] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2As shown, it may also include a power signal line 109 having multiple segments 109', each segment 109' being connected to a power supply pad of a first pad group 102 in a column. Optionally, two adjacent segments 109' in the column direction Y can be connected to each other through a connecting lead 110, so that the same power signal line 109 supplies power to the power supply pads Pwr of multiple cascaded first pad groups 102 in the same column. Optionally, the connecting lead 110 and the segment 109' are an integral structure.

[0056] In some embodiments, in the wiring substrate provided in the present disclosure, such as Figure 1 and Figure 2 As shown, it may also include a common voltage signal line 111, and the grounding pads Gnd of all the first pad groups 102 cascaded in a row can be connected to the same common voltage signal line 111.

[0057] In some embodiments, in the wiring substrate provided in this disclosure, to reduce process steps and save manufacturing costs, the constant voltage signal line 103, cascade line 106, address signal line 107, feedback signal line 108, power signal line 109, connecting lead 110, and common voltage signal line 111 can be arranged in the same layer. In this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a film layer for a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses.

[0058] In some embodiments, the wiring substrate provided in this disclosure further includes an insulating layer with multiple cutout structures disposed on the side of all line layers furthest from the substrate, each cutout structure exposing the end of a portion of the line to form a respective pad area (e.g., Figure 1 (E1 to E4 in the diagram) and the first pad group 102. Optionally, the insulating layer may be made of a material with high reflectivity, such as white ink.

[0059] Based on the same inventive concept, embodiments of this disclosure provide an electronic device, such as... Figure 5As shown, the device includes the wiring substrate 001 provided in this embodiment, a micro driver chip 002 coupled to the first pad group 102, and an electronic component 003 coupled to the second pad group 104. Specific implementations of the electronic device provided in this embodiment can be found in the specific implementations of the wiring substrate provided in this embodiment; repeated details will not be repeated. Optionally, the projected area of ​​the micro driver chip 002 on the substrate 101 is no greater than 300,000 μm. 2 Electronic component 003 is a light-emitting element, and the light-emitting area of ​​the light-emitting element does not exceed 300,000 μm. 2 Specifically, it can be no more than 40,000 μm. 2 The light-emitting element has two pins, and each pad area (e.g., E1 to E4) includes a first pad 41 and a second pad 42, which are respectively connected to the two pins of the light-emitting element. It is understood that when electronic component 003 is another component, it may have a different number of pins, and correspondingly, each pad area (e.g., E1 to E4) has the same number of pads as the pins of the component.

[0060] In some embodiments, in the electronic devices provided in the present disclosure, such as Figures 5 to 7 As shown, it may also include a plurality of first transparent protective structures 112, the orthographic projection of each first transparent protective structure 112 on the substrate 101 respectively covers the orthographic projection of each electronic component 003 on the substrate 101, so as to protect each electronic component 003 through the first transparent protective structure 112, and when the electronic component 003 is a light-emitting element, the first transparent protective structure 112 can also play the role of improving light efficiency.

[0061] In some embodiments, the first transparent protective structure 112 can be fabricated by dispensing or stencil printing. Optionally, to achieve better protection and improve light efficiency, the first transparent protective structure 112 can be formed into a dome shape on the electronic component 003 (e.g., a light-emitting element). This shape of the first transparent protective structure 112 can be referred to as a droplet lens, and the orthogonal projection radius r of the first transparent protective structure 112 on the substrate 101 can be 1450 μm. However, considering that there may be deviations in the actual fabrication of the first transparent protective structure 112, for example, the deviation may be within ±150 μm, that is, the maximum orthogonal projection radius r of the first transparent protective structure 112 on the substrate 101 is... max 1600μm, minimum radius r min It is 1400μm.

[0062] In some embodiments, in the electronic devices provided in the present disclosure, such as Figures 5 to 7As shown, the space between each pad area E within the second pad group 104 is large enough to effectively ensure that the linewidth of the connection line 105 meets the voltage drop requirements. Therefore, the orthographic projection of the connection line 105 on the substrate 101 does not overlap with the orthographic projection of the first transparent protective structure 112 on the substrate 101, thus preventing the connection line 105 from being adhered to the first transparent protective structure 112. This avoids the connection line 105 from accidentally being pulled off by the first transparent protective structure 112 during production or transportation. Optionally, the distance between the orthographic projection of the connection line 105 on the substrate 101 and the maximum orthographic projection of the first transparent protective structure 112 on the substrate 101 (e.g., an orthographic projection radius of 1600 μm) is greater than or equal to 50 μm.

[0063] In some embodiments, in the electronic devices provided in the present disclosure, such as Figures 5 to 7 As shown, a second transparent protective structure 113 may also be included. The orthogonal projection of the second transparent protective structure 113 on the substrate 101 covers the orthogonal projection of the micro-driver chip 002 on the substrate 101, so as to protect the micro-driver chip 002 through the second transparent protective structure 113. For ease of fabrication, the fabrication requirements of the second transparent protective structure 113 and the first transparent protective structure 112 can be the same, and the two can be formed in the same process flow.

[0064] In some embodiments, in the electronic devices provided in the present disclosure, such as Figures 5 to 8 As shown, the orthographic projection of the connecting line 105 on the substrate 101 and the orthographic projection of the second transparent protective structure 113 on the substrate 101 overlap by at most part. This reduces the risk of the connecting line 105 being adhered to the second transparent protective structure 113, and the connecting line 105 being accidentally pulled off by the second transparent protective structure 113 during production and transportation. Optionally, the distance between the orthographic projection of the connecting line 105 on the substrate 101 and the minimum orthographic projection of the second transparent protective structure 113 (e.g., an orthographic projection radius of 1400 μm) is less than or equal to 50 μm, and the distance between the connecting line 105 and the die-bonding mark v of the micro-driver chip 002 is greater than or equal to 40 μm.

[0065] In some embodiments, in the electronic device provided in the present disclosure, if the space between adjacent second pad groups 104 is large enough, the line width of the connection line 105 can be effectively guaranteed to meet the voltage drop requirements. The connection line 105 can be configured to have a recess C in the intersection area of ​​the first trace portion 51 and the second trace portion 52. The orthographic projection of the first trace portion 51 on the substrate 101 and the orthographic projection of the second trace portion 52 on the substrate 101 do not overlap with the orthographic projection of the second transparent protective structure 113 on the substrate 101. In this way, the connection line 105 can avoid the second transparent protective structure 113 at the recess C.

[0066] In some examples, such as Figure 9 As shown, the micro driver chip 002 may include a demodulation circuit 201, a physical layer interface circuit 202, a data processing control circuit 203, a pulse width modulation circuit 204, a drive signal generation circuit 205, a relay signal generation circuit 206, and a power supply circuit 207.

[0067] In some embodiments, the demodulation circuit 201 is electrically connected to the power supply pad Pwr and the physical layer interface circuit 202, and is configured to demodulate the power line carrier communication signal input to the power supply pad Pwr to obtain communication data, and transmit the communication data to the physical layer interface circuit. When the electronic component 003 is a light-emitting element, the communication data can reflect the duration of light emission, thus representing the required light intensity. Compared to the conventional Serial Peripheral Interface (SPI) protocol, this embodiment of the disclosure effectively reduces the number of signal lines by employing the Power Line Carrier Communication (PLC) protocol, which superimposes the communication data onto the power signal.

[0068] In some embodiments, the physical layer interface circuit 202 is also electrically connected to the data processing control circuit 203 and is configured to process communication data to obtain data frames (e.g., frame rate data) and transmit the data frames to the data processing control circuit 203. The data frames obtained by the physical layer interface circuit 202 contain information that needs to be transmitted to the micro-driver chip 002, such as information related to the emission time (e.g., the specific duration of the emission time). Optionally, the physical layer interface circuit 202 is a typical port physical layer (PHY), and detailed descriptions can be found in conventional designs, which will not be elaborated here.

[0069] In some embodiments, the data processing control circuit 203 is also electrically connected to the address pad Di, the pulse width modulation circuit 204, and the relay signal generation circuit 206. The data processing control circuit 203 is configured to generate a pulse width control signal based on a data frame and transmit the pulse width control signal to the pulse width modulation circuit 204, and to generate a relay control signal based on an address signal and transmit the relay control signal to the relay signal generation circuit 206. For example, the required light emission duration of the light-emitting element connected to the micro-driver chip 002 can be determined from the data frame, and a corresponding pulse width control signal is generated based on this light emission duration. For example, the relay control signal is a signal generated by the data processing control circuit 203 after processing the first input signal. By processing the address signal (e.g., parsing, latching, decoding, etc.), the address signal corresponding to the micro-driver chip 002 can be determined, and a relay control signal corresponding to a subsequent address, which corresponds to another micro-driver chip 002, will be generated. Optionally, the data processing control circuit 203 can be implemented as a microcontroller, a central processing unit (CPU), a digital signal processor, etc.

[0070] In some embodiments, the pulse width modulation circuit 204 is also electrically connected to the drive signal generation circuit 205 and is configured to generate a pulse width modulation signal in response to a pulse width control signal, and transmit the pulse width modulation signal to the drive signal generation circuit 205. For example, the pulse width modulation signal generated by the pulse width modulation circuit 204 determines the light emission duration of the light-emitting element, for example, the effective pulse width duration is equal to the light emission duration of the light-emitting element.

[0071] In some embodiments, the drive signal generation circuit 205 is also electrically connected to the output pad Out, and is configured to generate a drive signal in response to a pulse width modulation signal, and output the drive signal from the output pad Out. Here, outputting the drive signal from the output pad Out can mean that the drive signal (e.g., drive current) flows from the output pad Out to the light-emitting element, or it can mean that the drive signal (e.g., drive current) flows from the light-emitting element into the output pad Out, and the specific current direction is not limited.

[0072] For example, in some examples, when the drive signal is a drive current, the drive signal generation circuit 205 may include a current source A and a transistor MOS. The control electrode of the transistor MOS receives the pulse width modulation signal transmitted by the pulse width modulation circuit 204, thereby turning it on or off under the control of the pulse width modulation signal. The first electrode of the transistor MOS is connected to the output pad Out, and the second electrode of the transistor MOS is connected to the first electrode of the current source A. The second electrode of the current source A is connected to the ground pad Gnd to receive a common voltage. Optionally, the current source A can be a constant current source. When the pulse width modulation signal is at an active level, the transistor MOS is turned on, and the current source A provides drive current through the output pad Out. When the pulse width modulation signal is at an inactive level, the transistor MOS is turned off, and the output pad Out does not provide drive current. The duration of the active level of the pulse width modulation signal is equal to the conduction duration of the transistor MOS, and the conduction duration of the transistor MOS is equal to the duration for which the output pad Out provides drive current. Thus, the light emission duration of the light-emitting element can be further controlled, thereby controlling the visual brightness of the light emission. In some embodiments, when the transistor MOS is turned on, the drive current flows from the output pad Out into the micro driver chip 002, and then flows sequentially through the transistor MOS and the current source A, before flowing into the ground terminal (e.g., the ground pad Gnd). It should be noted that in the embodiments of this disclosure, the drive signal generation circuit 205 can also adopt other circuit structures, and the embodiments of this disclosure do not limit this.

[0073] In some embodiments, the relay signal generation circuit 206 is also electrically connected to the output pad Out, configured to generate a relay signal based on a relay control signal, and output the relay signal from the output pad Out. For example, the relay control signal corresponds to a subsequent address, and the relay signal generated based on the relay control signal contains the subsequent address, which corresponds to another micro-driver chip 002. After the relay signal is output from the output pad Out, it is provided to the address pad Di of the next-level micro-driver chip 002, thereby enabling the next-level micro-driver chip 002 to obtain the corresponding address signal. The relay signal generation circuit 206 can be implemented by a latch, decoder, encoder, etc., and the embodiments of this disclosure are not limited thereto.

[0074] It should be noted that, in the embodiments of this disclosure, although both the drive signal generation circuit 205 and the relay signal generation circuit 206 are electrically connected to the output pad Out, the drive signal generation circuit 205 and the relay signal generation circuit 206 output drive signals and relay signals at different time periods. The drive signals and relay signals are transmitted through the output pad Out in a time-division manner, so they will not affect each other.

[0075] In some embodiments, the power supply circuit 207 is electrically connected to both the demodulation circuit 201 and the data processing control circuit 203, and is configured to receive electrical energy and supply power to the data processing control circuit 203. In some embodiments, after the demodulation circuit 201 demodulates the power line carrier communication signal input to the power supply pad Pwr, the DC power component (i.e., electrical energy) in the power line carrier communication signal is transmitted to the power supply circuit 207, and then provided to the data processing control circuit 203 by the power supply circuit 207. Of course, the embodiments of this disclosure are not limited to this; the power supply circuit 207 can also be electrically connected to other circuits in the micro-driver chip 002 to provide electrical energy. The power supply circuit 207 can be implemented by a switching circuit, a voltage conversion circuit, a voltage regulator circuit, etc., and the embodiments of this disclosure do not limit this.

[0076] It should be noted that the micro driver chip 002 provided in this disclosure may also include more circuits and components, not limited to the demodulation circuit 201, physical layer interface circuit 202, data processing control circuit 203, pulse width modulation circuit 204, drive signal generation circuit 205, relay signal generation circuit 206 and power supply circuit 207 mentioned above. This can be determined according to the functions to be implemented, and the embodiments of this disclosure do not limit this.

[0077] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A wiring substrate, wherein, include: Substrate; Multiple first pad groups are located on the substrate, and the multiple first pad groups are cascaded in the column direction. Each first pad group includes an output pad. The constant voltage signal line is located on the same side of the substrate as the first pad group; Multiple second pad groups, each second pad group including multiple sub-pad groups arranged in parallel, each sub-pad group including multiple pad areas arranged in series; The constant voltage signal line is coupled to the plurality of sub-pad groups arranged in parallel via the connecting line; The connecting line includes a first trace portion extending in the same direction as the constant voltage signal line, and a second trace portion extending in a direction intersecting the constant voltage signal line. The second trace portion connects the constant voltage signal line and the first trace portion. The first trace portion is located at the column gap of each pad area in the same second pad group. The second trace portion is located at the row gap of adjacent second pad groups.

2. The wiring substrate as claimed in claim 1, wherein, Multiple second pad groups are arranged in an array on the substrate, and all the pad areas in the same second pad group are arranged in an array on the substrate.

3. The wiring substrate as described in claim 2, wherein, The width of the connecting line is greater than the width of the constant voltage signal line.

4. The wiring substrate as described in claim 2 or 3, wherein, The orthographic projection of the first pad group on the substrate and the orthographic projection of the connecting line on the substrate do not overlap.

5. The wiring substrate according to any one of claims 1 to 3, wherein, The second pad group includes two sub-pad groups arranged in parallel, one of which includes a first pad area and a second pad area arranged in series, and the other includes a third pad area and a fourth pad area arranged in series.

6. The wiring substrate as claimed in claim 5, wherein, The first pad area is arranged in the same column as the second pad area and in the same row as the third pad area. The fourth pad area is arranged in the same row as the second pad area and in the same column as the third pad area.

7. The wiring substrate as claimed in claim 5, wherein, The first pad area is arranged in the same row as the second pad area and in the same column as the third pad area. The fourth pad area is arranged in the same column as the second pad area and in the same row as the third pad area.

8. The wiring substrate as claimed in claim 5, wherein, The first pad area is arranged in the same column as the third pad area and in the same row as the fourth pad area. The second pad area is arranged in the same row as the third pad area and in the same column as the fourth pad area.

9. An electronic device, wherein, It includes a wiring substrate as described in any one of claims 1 to 8, a micro driver chip coupled to the first pad group, and an electronic component coupled to the second pad group.

10. The electronic device of claim 9, wherein, It also includes multiple first transparent protective structures, each of which has its orthographic projection on the substrate covering the orthographic projection of the electronic component on the substrate.

11. The electronic device of claim 10, wherein, The orthographic projection of the connecting line on the substrate does not overlap with the orthographic projection of the first transparent protective structure on the substrate.

12. The electronic device according to any one of claims 9 to 11, wherein, It also includes a second transparent protective structure, the orthogonal projection of the second transparent protective structure on the substrate covering the orthogonal projection of the micro driver chip on the substrate.

13. The electronic device of claim 12, wherein, The orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the second transparent protective structure on the substrate in multiple parts.

14. The electronic device of claim 13, wherein, The connecting line has a recess in the intersection area of ​​the first wiring portion and the second wiring portion, and the orthographic projection of the first wiring portion on the substrate and the orthographic projection of the second wiring portion on the substrate do not overlap with the orthographic projection of the second transparent protective structure on the substrate.

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