A pixel driving circuit and a display panel

Abstract

The application discloses a pixel driving circuit and a display panel. The circuit comprises a light emitting device, an integral operation module configured to receive a first voltage signal with a constant voltage value and output a second voltage signal with a time-varying voltage value, and a driving control module connected with the light emitting device and the integral operation module respectively, and configured to receive the second voltage signal and control the light emitting time of the light emitting device according to the second voltage signal when performing picture display. The application can more quickly and accurately control the light emitting time of the light emitting device in the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panel driving, and in particular to a pixel driving circuit and a display panel. BACKGROUND

[0002] Liquid crystal displays (e.g., thin-film transistor liquid crystal displays (TFT-LCDs)) are popular due to their small size, light weight, low power consumption, and high display quality. Common driving methods for LED display technology include PWM and PAM.

[0003] Driving methods for display technology include PAM (Pulse Amplitude Modulation), PWM (Pulse Width Modulation), and PHM (a hybrid of PAM and PWM). PWM driving has high requirements for driving chips, PAM driving has poor image quality when displaying low gray levels, and PWM and PAM hybrid driving (PHM driving) can combine the advantages of both and improve the disadvantages of the other. Therefore, PHM driving has been widely researched.

[0004] However, the conventional PHM driving technology uses a triangular wave signal or a rectangular wave signal to control the light-emitting time, which makes it difficult to control the light-emitting time. SUMMARY

[0005] Embodiments of the present application provide a pixel driving circuit and a display panel, which solve the technical problem of being unable to achieve low-power shutdown display.

[0006] In a first aspect, the present application provides a pixel driving circuit, comprising:

[0007] a light-emitting device;

[0008] an integral operation module configured to receive a first voltage signal with a constant voltage value and output a second voltage signal with a time-varying voltage value;

[0009] a driving control module connected to the light-emitting device and the integral operation module, and configured to receive the second voltage signal and control the light-emitting time of the light-emitting device according to the second voltage signal when displaying a picture.

[0010] In some embodiments, the integral operation module comprises an operational amplifier, a first resistor, a second resistor, and a first capacitor.

[0011] a first end of the first resistor is connected to the first voltage signal;

[0012] an inverting input terminal of the operational amplifier is connected to a second end of the first resistor and a first end of the first capacitor.

[0013] The non-inverting input terminal of the operational amplifier is connected with the second resistor and then grounded;

[0014] The output terminal of the operational amplifier is connected with the second terminal of the first capacitor and the driving control module respectively, so as to output the second voltage signal to the driving control module.

[0015] In some embodiments, the relationship between the second voltage signal and the first voltage signal satisfies the following formula:

[0016] The relationship between the second voltage signal and the first voltage signal satisfies the following formula:

[0017]

[0018] Wherein, u o is the second voltage signal, u I is the first voltage signal, R is the resistance value of the first resistor, C is the capacitance value of the first capacitor, RC is the integration time constant, t2 is the opening time of the integration operation module receiving the first voltage signal, t1 is the closing time of the integration operation module receiving the first voltage signal, u0(t1) is the initial voltage value of the second voltage signal.

[0019] In some embodiments, the driving control module comprises a driving transistor, a pulse width modulation unit and a pulse amplitude modulation unit.

[0020] One of the source and drain of the driving transistor is connected with the anode of the light emitting device;

[0021] The first terminal of the pulse amplitude modulation unit is connected with a pulse amplitude control signal, the second terminal of the pulse amplitude modulation unit is connected with a second data signal, and the third terminal of the pulse amplitude modulation unit is connected with the gate of the driving transistor.

[0022] The first terminal of the pulse width modulation unit is connected with a pulse width control signal, the second terminal of the pulse amplitude modulation unit is connected with a first data signal, and the third terminal of the pulse width modulation unit is connected with the gate of the driving transistor, and the pulse width modulation unit is used for controlling the light emitting time of the light emitting device according to the second voltage signal.

[0023] In some embodiments, the pulse width modulation unit comprises:

[0024] A potential writing sub-unit, the first terminal of the potential writing sub-unit is connected with the pulse width control signal as the first terminal of the pulse width modulation unit, and the second terminal of the potential writing sub-unit is connected with the first data signal as the second terminal of the pulse amplitude modulation unit.

[0025] a light-emitting time control subunit, a first end of the light-emitting time control subunit is connected with a third end of the potential writing subunit and an output end of the operational amplifier respectively, a second end of the light-emitting time control subunit is connected with the gate of the driving transistor as a third end of the pulse width modulation unit, a third end of the light-emitting time control subunit is connected with a first control signal, and the light-emitting time control subunit is configured to control the light-emitting time of the light-emitting device according to the second voltage signal output by the output end of the operational amplifier.

[0026] In some embodiments, the light-emitting time control subunit comprises a fourth transistor, a gate of the fourth transistor is configured as the first end of the light-emitting time control subunit, one of a source and a drain of the fourth transistor is configured as the second end of the light-emitting time control subunit, and the other of the source and the drain of the fourth transistor is configured as the third end of the light-emitting time control subunit.

[0027] In some embodiments, the potential writing subunit comprises a fifth transistor, a gate of the fifth transistor is configured as the first end of the potential writing subunit, one of a source and a drain of the fifth transistor is configured as the second end of the potential writing subunit, and the other of the source and the drain of the fifth transistor is configured as the third end of the potential writing subunit.

[0028] In some embodiments, the pulse width modulation unit comprises a first transistor, a gate of the first transistor is configured as the first end of the pulse width modulation unit, one of a source and a drain of the first transistor is configured as the second end of the pulse width modulation unit, and the other of the source and the drain of the first transistor is configured as the third end of the pulse width modulation unit.

[0029] In some embodiments, the pixel driving circuit further comprises:

[0030] a storage capacitor, one end of the storage capacitor is connected with the gate of the driving transistor, and the other end of the storage capacitor is connected with one of the source and the drain of the driving transistor and the anode of the light-emitting device respectively;

[0031] a third transistor, one of a source and a drain of the third transistor is connected with one of the source and the drain of the driving transistor, the other of the source and the drain of the third transistor is connected with a reference voltage signal, and a gate of the third transistor is connected with a sensing control signal;

[0032] wherein the other of the source and the drain of the driving transistor is connected with a positive power supply signal, and a cathode of the light-emitting device is connected with a negative power supply signal.

[0033] In a second aspect, the present application provides a display panel comprising the pixel driving circuit.

[0034] Beneficial effects: The pixel driving circuit and the display panel provided by the embodiments of the present application can more quickly and more accurately control the display time or the light-emitting time of the light-emitting device in the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0036] Figure 1 The first circuit schematic diagram of the pixel driving circuit provided by the prior art solution.

[0037] Figure 2 The timing diagram of the pixel driving circuit shown in FIG. Figure 1

[0038] Figure 3 The second circuit schematic diagram of the pixel driving circuit provided by the prior art solution.

[0039] Figure 4 The timing diagram of the pixel driving circuit shown in FIG. Figure 3

[0040] Figure 5 A structural schematic diagram of the pixel driving circuit provided by the embodiments of the present application.

[0041] Figure 6 A circuit schematic diagram of the pixel driving circuit provided by the embodiments of the present application.

[0042] Figure 7 A timing diagram of the first voltage signal input by the integral operation module provided by the embodiments of the present application.

[0043] Figure 8 A timing diagram of the second voltage signal output by the integral operation module provided by the embodiments of the present application.

[0044] Figure 9 A timing diagram provided by the embodiments of the present application. DETAILED DESCRIPTION

[0045] ​​With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0046] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "one end", "the other end" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "two or more" is two or more, unless otherwise specifically limited.

[0047] It should be pointed out that the "connection" in the embodiments of the present application can be understood as an electrical connection, and the connection between two electrical elements can be a direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be that A and B are directly connected, or A and B are indirectly connected through one or more other electrical elements.

[0048] In the circuit structure provided by the embodiments of the present application, the nodes such as the first node and the second node do not represent actual existing components, but represent the convergence points of the relevant couplings in the circuit diagram, that is, these nodes are nodes equivalent to the convergence points of the relevant couplings in the circuit diagram.

[0049] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, reference numerals and / or reference letters can be repeated in different examples in the present application, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0050] The present application provides a pixel driving circuit and a display panel. The display panel in the embodiments of the present application can be used in mobile phones, tablet computers, desktop computers, laptop computers, e-readers, handheld computers, electronic display screens, notebook computers, ultra-mobile personal computers (UMPC), netbooks, and cellular phones, personal digital assistants (PDA), augmented reality (AR) \ virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, and the like.

[0051] The display panel can be a liquid crystal display panel. The present application does not limit the type of the liquid crystal display panel. The liquid crystal display panel provided by the present application can be a horizontal electric field type liquid crystal display panel, such as a fringe field switching (FFS) type liquid crystal display panel or an in-plane switching (IPS) type liquid crystal display panel, or a vertical electric field type liquid crystal display panel, such as a twisted nematic (TN) type liquid crystal display panel or a multi-domain vertical alignment (MVA) type liquid crystal display panel.

[0052] The driving mode of the display technology includes PAM, PWM, and a mixture of the two. Among them, the PWM driving mode has the advantages of constant current, high luminous efficiency, and good low gray scale display quality, so the PWM or the mixed driving mode based on PWM has been widely studied.

[0053] As shown in the pixel driving circuit shown in Figure 1 , the pixel driving circuit adopts the PWM driving mode, and the display time of the pixel driving circuit can be controlled by the signal SPWM, but the signal SPWM needs a high frequency, and when it is generated by a gate drive IC (Integrated Circuit), the gate drive IC needs to have high performance, and the number of rows of pixel driving circuits that can be driven by the gate drive IC is not large.

[0054] As shown in the pixel driving circuit shown in Figure 2 , the pixel driving circuit adopts the PWM driving mode, and the display time of the pixel driving circuit can be controlled by the signal SPWM, but the signal SPWM needs a high frequency, and when it is generated by a gate drive IC (Integrated Circuit), the gate drive IC needs to have high performance, and the number of rows of pixel driving circuits that can be driven by the gate drive IC is not large. Figure 1The working process of the pixel driving circuit includes a preparation stage and a light emitting stage. In the preparation stage, the potential V-G of the G point and the potential V-SPWM of the signal SPWM are both low potentials, so no light emitting current I-LED flows through the light emitting device LED. In the light emitting stage, when the potential V-G of the G point is a high potential, the light emitting current I-LED flows through the light emitting device LED. However, when the potential V-SPWM of the signal SPWM is a high potential, the light emitting current I-LED will stop flowing through the light emitting device LED.

[0055] As shown in the pixel driving circuit shown in Figure 3 , another PWM driving mode is adopted. The potential of the A point is initialized to a corresponding initial voltage, and the coupling effect of the capacitor C5 is used to make the potential of the A point rise uniformly. The time required for the potential of the A point to rise from different initial voltages to the threshold voltage of T4 is different, so the time when T4 is turned on or turned off is also different, and thus the display time or the light emitting time of the pixel driving circuit is also different. As shown in Figure 4 , the potential of the A point is initialized to a corresponding initial voltage, and the coupling effect of the capacitor C5 is used to make the potential of the A point rise uniformly. The time required for the potential of the A point to rise from different initial voltages to the threshold voltage of T4 is different, so the time when T4 is turned on or turned off is also different, and thus the display time or the light emitting time of the pixel driving circuit is also different. As shown in Figure 3 , the working process of the pixel driving circuit includes a preparation stage and a light emitting stage. In the preparation stage, the potential V-G of the G point and the potential V-Sweep of the signal Sweep are both low potentials, so no light emitting current I-LED flows through the light emitting device LED. In the light emitting stage, when the potential V-G of the G point is a high potential, the light emitting current I-LED flows through the light emitting device LED. However, as the potential V-Sweep of the signal Sweep gradually rises, the potential V-G of the G point has a slow decline process, which causes the light emitting current I-LED not to stop immediately, and thus the light emitting time of the pixel driving circuit is difficult to accurately control. Therefore, due to the uniform change of the potential of the A point, T4 and T2 have a slow turn-off or turn-off as shown in Figure 4 , and thus the light emitting time is difficult to accurately control.

[0056] The pixel driving circuit and the display panel of the present application are described below in conjunction with the drawings of the specification to solve the above problems.

[0057] Please refer to Figure 5 , a structure diagram of a pixel driving circuit 10 provided in an embodiment of the present application is shown in Figure 5 , the pixel driving circuit includes:

[0058] a light emitting device LED;

[0059] an integral operation module 100, configured to receive a first voltage signal u I with a constant voltage value and output a second voltage signal u o with a voltage value changing over time;

[0060] The driving control module 200 is connected with the light emitting device LED and the integral operation module 100 respectively, and the driving control module 200 is used for receiving the second voltage signal u o , and the light emitting time of the light emitting device LED is controlled according to the second voltage signal uo when the picture is displayed.

[0061] Specifically, as shown in Figure 5 , the anode of the light emitting device LED is connected with the voltage output end of the driving control module 200, and the electrical signal output end Out of the integral operation module 100 is connected with the voltage input end In2 of the driving control module 200. The integral operation module 100 includes an electrical signal input end In1 and an electrical signal output end Out, and at the initial moment, that is, when the pixel driving circuit is not powered on, the electrical signal input end In1 of the integral operation module 100 is not connected with the first voltage signal u I , and thus the voltage value of the electrical signal output end Out of the integral operation module 100 is 0. When the pixel driving circuit is powered on, the electrical signal input end In1 of the integral operation module 100 receives the direct current voltage with constant voltage value, that is, the first voltage signal u Figure 7 , as shown in I . After the electrical signal input end In1 receives the first voltage signal u I , the integral operation module 100 processes the received first voltage signal u I to obtain the second voltage signal u o with the voltage value changing linearly with time, and then inputs the second voltage signal u o to the voltage input end In2 of the driving control module 200 through the electrical signal output end Out of the integral operation module 100, and controls the light emitting time of the light emitting device LED in the pixel driving circuit of each pixel unit according to the received second voltage signal u o when the display panel needs to display the picture.

[0062] In some embodiments, the light emitting device LED can be any one of a mini light emitting diode, a micro light emitting diode, a quantum dot light emitting diode and an organic light emitting diode.

[0063] It can be understood that the pixel driving circuit provided by the embodiment receives the first voltage signal u I with constant voltage value through the integral operation module 100, generates the second voltage signal u o with the voltage value changing with time, and then controls the light emitting time of the light emitting device LED through the second voltage signal u o , so that the display time or the light emitting time of the light emitting device LED in the display panel can be controlled more quickly and more accurately.

[0064] In some embodiments of the present application, the integral operation module 100 comprises an operational amplifier PI, a first resistor R1, a second resistor R2 and a first capacitor C1.

[0065] The first end of the first resistor R1 is connected to the first voltage signal u I .

[0066] The inverting input terminal of the operational amplifier PI is connected to the second end of the first resistor R1 and the first end of the first capacitor C1 respectively.

[0067] The non-inverting input terminal of the operational amplifier PI is connected to the second resistor R2 and then grounded.

[0068] The output terminal of the operational amplifier PI is connected to the second end of the first capacitor C1 and the driving control module 200 respectively, so as to output the second voltage signal u o to the driving control module 200.

[0069] Specifically, as shown in Figure 5 , the first end of the first resistor R1 is connected to the electrical signal input terminal to access the first voltage signal u I , and the output terminal of the operational amplifier PI is connected to the electrical signal output terminal Out to provide the second voltage signal u o to the driving control module 200. The voltage across the first capacitor C1 and the current flowing through the capacitor have an integral relationship, so that the second voltage signal u o output by the output terminal of the operational amplifier PI is proportional to the voltage across the first capacitor C1, and the first voltage signal u I accessed by the electrical signal input terminal of the integral operation module 100 is proportional to the current flowing through the capacitor, so that the first voltage signal u I and the second voltage signal uo can have an integral operation relationship.

[0070] In some embodiments of the present application, a second capacitor C2 is connected in series between the output terminal of the operational amplifier PI and the electrical signal output terminal Out. The second voltage signal u o output by the output terminal of the operational amplifier PI can be filtered to obtain a direct current voltage, so as to prevent interference to the driving control module 200.

[0071] In some embodiments of the present application, in order to prevent the gain of low frequency signal from being too large, a third resistor is connected in parallel to the first capacitor C1, and the resistance value of the third resistor is greater than ten times the resistance value of the first resistor R1.

[0072] In some embodiments of the present application, the second voltage signal u o and the first voltage signal uI The relationship between the first voltage signal u

[0073]

[0074] wherein u o is the second voltage signal, u I is the first voltage signal, R is the resistance value of the first resistor, C is the capacitance value of the first capacitor, RC is the integration time constant, t2 is the opening time of the integration operation module receiving the first voltage signal, t1 is the closing time of the integration operation module receiving the first voltage signal, and u0(t1) is the initial voltage value of the second voltage signal.

[0075] Specifically, the current flowing through the first capacitor C1 is equal to the current flowing through the first resistor R1,

[0076] The first voltage signal u I is added to the inverting input terminal of the operational amplifier PI through the first resistor R1, and a deep negative feedback is introduced between the output terminal and the inverting input terminal of the operational amplifier PI through the first capacitor C1 to form a basic integration circuit.

[0077] In order to balance the resistance of the two input terminals of the operational amplifier PI to the ground, the resistance value of the second resistor R2 connected to the non-inverting input terminal is usually equal to the resistance value of the first resistor R1 connected to the inverting input terminal, i.e. R = R'. Wherein R' is the resistance value of the second resistor R2.

[0078] Since the inverting input terminal of the operational amplifier PI is "virtually short", the relationship between the second voltage signal uo and the voltage value across the first capacitor C1 satisfies uo = -uc, which shows that the second voltage signal uo is proportional to the voltage across the first capacitor C1. Wherein uc is the voltage value across the first capacitor C1. Since the inverting input terminal of the operational amplifier PI is "virtually open", the current flowing through the inverting input terminal of the operational amplifier PI is zero, so the current value flowing through the first resistor R1 and the current value flowing through the first capacitor C1 satisfy i1 = ic, wherein i1 is the current value flowing through the first resistor R1, and ic is the current value flowing through the first capacitor C1. Therefore, it can be deduced that u1 = i1R = icR, i.e. the first voltage signal u I is proportional to the current value flowing through the first capacitor C1. From the above expressions, it can be obtained that the relationship between the first voltage signal u I and the second voltage signal u o satisfies the following formula:

[0079]

[0080] The product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 is called the integration time constant. Wherein the second voltage signal uo With the first voltage signal u I The integral is directly proportional to the integral, and the negative sign indicates that the circuit implements an inverting function. Therefore, in this embodiment, the integral operation module 100 is essentially an inverting integral operation circuit. In order to satisfy the integral operation relationship, the integral time constant RC must be greater than the first voltage signal u. I The input cycle.

[0081] In some embodiments of this application, the drive control module 200 includes: a drive transistor T2, a pulse width modulation unit 210, and a pulse amplitude modulation unit 220;

[0082] One of the source and drain of the driving transistor T2 is connected to the anode of the light-emitting device LED;

[0083] The first terminal of the pulse amplitude modulation unit 220 is connected to the pulse amplitude control signal SPAM, the second terminal of the pulse amplitude modulation unit 220 is connected to the second data signal SPAM_data, and the third terminal of the pulse amplitude modulation unit 220 is connected to the gate of the driving transistor T2.

[0084] The first terminal of the pulse width modulation unit 210 is connected to the pulse width control signal SPWM, the second terminal of the pulse width modulation unit 210 is connected to the first data signal SPWM_data, and the third terminal of the pulse width modulation unit 210 is connected to the gate of the driving transistor T2, for use according to the second voltage signal u o Control the light-emitting time of the LED device.

[0085] Specifically, such as Figure 6 As shown, the drive control module 200 includes a drive transistor T2 connected to the anode of the LED. The gate of the drive transistor T2 is connected to both a pulse amplitude modulation unit 220 and a pulse width modulation unit 210. The pulse amplitude modulation unit 220 receives a pulse amplitude control signal SPAM, and the pulse width modulation unit 210 receives a pulse width control signal SPWM. This allows for precise control of the LED's emission time via the drive transistor T2, based on the duration of the SPAM signal, during low grayscale display. During high grayscale display, the pulse amplitude modulation unit 220 controls the LED's brightness via the drive transistor T2, based on the voltage value of the second data signal SPAM_data. In summary, PWM drive uses pulse width modulation to control brightness through time, meaning the voltage remains constant; PAM drive uses pulse amplitude modulation to control brightness through voltage, meaning the time remains constant.

[0086] In some embodiments of this application, the pulse width modulation unit 210 includes:

[0087] The potential writing subunit 211 has a first end connected to the first end of the pulse width modulation unit 210 to receive the pulse width control signal SPWM, and has a second end connected to the second end of the pulse width modulation unit 210 to receive the first data signal SPWM_data.

[0088] The light emitting time control subunit 212 has a first end connected to the third end of the potential writing subunit 211 and the output end of the operational amplifier PI, has a second end connected to the gate of the driving transistor T2 as the third end of the pulse width modulation unit 210, and has a third end connected to the first control signal Vneg. The light emitting time control subunit 212 is configured to control the light emitting time of the light emitting device LED according to the second voltage signal u0 outputted by the output end of the operational amplifier PI.

[0089] Specifically, the light emitting time control subunit 212 is configured to timely turn off the driving transistor T2. When the driving transistor T2 is an N-channel thin film transistor, the potential of the first control signal Vneg can be a low potential, for example, zero potential. When the driving transistor T2 is a P-channel thin film transistor, the potential of the first control signal Vneg can be a high potential. After the potential writing subunit 211 receives the first data signal SPWM_data and the pulse width control signal SPWM, the potential writing subunit 211 can write an initial potential to the light emitting time control subunit 212.

[0090] In some embodiments of the present application, the light emitting time control subunit 212 includes a fourth transistor T4, the gate of the fourth transistor T4 is configured as the first end of the light emitting time control subunit 212, one of the source and the drain of the fourth transistor T4 is configured as the second end of the light emitting time control subunit 212, and the other of the source and the drain of the fourth transistor T4 is configured as the third end of the light emitting time control subunit 212.

[0091] Specifically, the gate of the fourth transistor T4 is configured to be connected with the first end of the light-emitting time control subunit 212 and the first node B, one of the source and the drain of the fourth transistor T4 is configured to be connected with the second end of the light-emitting time control subunit 212 and the gate of the driving transistor T2 respectively, and the other of the source and the drain of the fourth transistor T4 is configured to be connected with the third end of the light-emitting time control subunit 212 and the first control signal Vneg. The first node B is connected with the output end of the operational amplifier PI in the integral operation module 100, that is, the gate of the fourth transistor T4 is connected with the second voltage signal uo output by the operational amplifier PI, as shown in Figure 8 The voltage value of the second voltage signal uo decreases over time, that is, the second voltage signal uo is high at the beginning of a frame, and then decreases to zero or negative over time.

[0092] In this case, as shown in Figure 8 The potential writing subunit 211 writes a high second voltage signal uo at the beginning of a frame, and the second voltage signal uo provided by the integral operation module 100 to the first node B decreases to zero or negative over time, which is sufficient to turn on the fourth transistor T4. When the fourth transistor T4 is turned on, the driving transistor T2 is turned off. When the second voltage signal uo provided by the integral operation module 100 to the first node B decreases to turn off the fourth transistor T4, the driving transistor T2 is turned on. Therefore, the switch of the fourth transistor T4 can be controlled by the second voltage signal uo provided by the integral operation module 100 to the first node B to control the switch state of the driving transistor T2, so as to control the light-emitting time of the light-emitting device LED connected with the driving transistor T2.

[0093] In this case, as shown in Figure 8As shown, the potential writing subunit 211 writes a high potential second voltage signal uo at the beginning of a frame, and over time, the second voltage signal uo provided by the integral operation module 100 to the first node B becomes zero potential or negative potential. The low level input to the gate of the fourth transistor T4 is converted to high level by the inverter, which is sufficient to turn on the fourth transistor T4. When the fourth transistor T4 is turned on, the driving transistor T2 is turned off. When the second voltage signal uo provided by the integral operation module 100 to the first node B is reduced to turn off the fourth transistor T4, the driving transistor T2 is turned on. Therefore, the switching of the fourth transistor T4 can be controlled by the second voltage signal uo provided by the integral operation module 100 to the first node B, so as to control the switching state of the driving transistor T2, thereby controlling the light-emitting time of the light-emitting device LED connected to the driving transistor T2.

[0094] Since the inverter 24 has a signal shaping function, the rising edge and / or falling edge of the signal can be made to approach the ideal vertical slope more closely, and the fourth transistor T4 can be turned on or off more quickly or timely, thereby turning off the driving transistor T2, and the light-emitting time of the light-emitting device LED can be controlled more accurately.

[0095] In some embodiments of the present application, the potential writing subunit 211 includes a fifth transistor T5, the gate of the fifth transistor T5 is configured as the first end of the potential writing subunit 211, one of the source and drain of the fifth transistor T5 is configured as the second end of the potential writing subunit 211, and the other of the source and drain of the fifth transistor T5 is configured as the third end of the potential writing subunit 211.

[0096] Specifically, one of the source and drain of the fifth transistor T5 is connected to the first node B, the other of the source and drain of the fifth transistor T5 is configured as the second end of the potential writing subunit 211 and connected to the first data signal SPWM_data, and the gate of the fifth transistor T5 is configured as the first end of the potential writing subunit 211 and connected to the pulse width control signal SPWM. The pulse width control signal SPWM controls the fifth transistor T5 to write the first data signal SPWM_data to the gate of the driving transistor T2.

[0097] In some embodiments of the present application, the pulse amplitude modulation unit 220 includes a first transistor T1, the gate of the first transistor T1 is configured as the first end of the pulse width modulation unit 220, one of the source and drain of the first transistor T1 is configured as the second end of the pulse width modulation unit 220, and the other of the source and drain of the first transistor T1 is configured as the third end of the pulse width modulation unit 220.

[0098] Specifically, the other of the source and the drain of the first transistor T1 is configured as the third terminal of the pulse amplitude modulation unit 220 and is connected with the gate of the driving transistor T2, the gate of the first transistor T1 is configured as the first terminal of the pulse width modulation unit 220 and is connected with the pulse amplitude control signal SPAM, one of the source and the drain of the first transistor T1 is configured as the second terminal of the pulse amplitude modulation unit and is connected with the second data signal SPAM_data. The pulse amplitude control signal SPAM controls the first transistor T1 to write the second data signal SPAM_data to the gate of the driving transistor T2. The first data signal SPWM_data and the second data signal SPAM_data can be the same or different.

[0099] In some embodiments of the present application, the pixel driving circuit further comprises:

[0100] a storage capacitor C3, one end of the storage capacitor C3 is connected with the gate of the driving transistor T2, and the other end of the storage capacitor C3 is connected with one of the source and the drain of the driving transistor T2 and the anode of the light emitting device LED respectively;

[0101] a third transistor T3, one of the source and the drain of the third transistor T3 is connected with one of the source and the drain of the driving transistor T2, the other of the source and the drain of the third transistor T3 is connected with a reference voltage signal, and the gate of the third transistor T3 is connected with a sensing control signal Sense;

[0102] wherein the other of the source and the drain of the driving transistor T2 is connected with a positive power supply signal, and the cathode of the light emitting device LED is connected with a negative power supply signal.

[0103] Specifically, Figure 6 The working process of the pixel driving circuit is as follows. In the preparation stage, under the control of the pulse amplitude control signal SPAM, the second data signal SPAM_data is written to the second node G, i.e., to the gate of the driving transistor T2, under the control of the pulse width control signal SPWM, the fifth transistor T5 is turned on, and the first data signal SPWM_data is written to the fourth transistor T4, i.e., to the first node B, to write an initial potential. The third transistor T3 writes the reference voltage signal to the third node S to initialize the third node S. At the same time, under the control of the sensing control signal Sense, the reference voltage signal Vref initializes the potential of the third node S, and the potential writing subunit 211 writes an initial potential to the first node B.

[0104] Reference Figure 9 is shown, Figure 9A timing diagram provided by the embodiment of the present application, during the initial period of the write stage, the first data signal SPWM_data provides different initial voltages to the first node B, through the second capacitor C2, the potential of the first node B is pulled down, because the initial potential input by the first node B is not the same, so the time when the first node B is pulled down to make the fourth transistor T4 open is also not the same, the time when the voltage of the first control signal Vneg is written to the second node G is also not the same, that is, the time when the driving transistor T2 is closed is also not the same, that is, the light-emitting time of the light-emitting device LED lamp is also not the same.

[0105] In the light-emitting stage, the potential V G That is, the gate potential of the driving transistor T2 jumps to a high potential, so that the driving transistor T2 is opened, and the light-emitting current can flow through the light-emitting device LED so that the light-emitting device LED starts to emit light. Subsequently, as time goes on, the second voltage signal uo provided by the integral operation module 100 to the first node B becomes zero potential or negative potential, so that the potential V A Continuously decreases, when it decreases to a preset voltage, due to the coupling effect of the storage capacitor C3, the fourth transistor T4 can be charged through the storage capacitor C3 until the fourth transistor T4 is opened, the driving transistor T2 is closed, and the light-emitting device LED stops displaying, so that the light-emitting time of the light-emitting device LED can be controlled.

[0106] The embodiment of the present application also provides a display panel, which comprises the pixel driving circuit as Figure 5 to Figure 6 The pixel driving circuit corresponding to the embodiment shown in the figure.

[0107] The pixel driving circuit provided by the embodiment, after the integral operation module 100 receives the first voltage signal uI with constant voltage value to generate the second voltage signal uo with time-varying voltage value, the light-emitting time of the light-emitting device LED is controlled through the second voltage signal uo, so that the display time or the light-emitting time of the light-emitting device LED in the display panel can be controlled more quickly and more accurately.

[0108] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0109] The pixel driving circuit and the display panel provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application, and the above description of the present application should not be understood as a limitation. In addition, those skilled in the art can make some improvements and refinements without departing from the principles of the present application, and these improvements and refinements are also regarded as the protection scope of the present application.

Claims

1. A pixel driving circuit, characterized by comprising: The application relates to a light-emitting device, an integral operation module, a driving control module and a light-emitting time control subunit. The application relates to a light-emitting device, an integral operation module, a driving control module and a light-emitting time control subunit. The integral operation module comprises an operational amplifier, a first resistor, a second resistor and a first capacitor, the first end of the first resistor is connected to the first voltage signal, the inverting input end of the operational amplifier is connected to the second end of the first resistor and the first end of the first capacitor, the non-inverting input end of the operational amplifier is connected to the second resistor and then grounded, and the output end of the operational amplifier is connected to the second end of the first capacitor and the driving control module to output the second voltage signal to the driving control module. The driving control module comprises a driving transistor and a light-emitting time control subunit, one of the source and the drain of the driving transistor is connected to the light-emitting device, the first end of the light-emitting time control subunit is connected to the output end of the integral operation module, the second end of the light-emitting time control subunit is connected to the gate of the driving transistor, the third end of the light-emitting time control subunit is connected to the first control signal, and the light-emitting time control subunit is used for lowering the potential of the gate of the driving transistor to turn off the driving transistor and control the light-emitting time of the light-emitting device when the second voltage signal lowers the potential of the first end of the light-emitting time control subunit to a preset voltage. The relationship between the second voltage signal and the first voltage signal satisfies the following formula: The driving control module further comprises a pulse width modulation unit and a pulse amplitude modulation unit.

2. The pixel driving circuit according to claim 1, characterized in that, The first end of the pulse amplitude modulation unit is connected to a pulse amplitude control signal, the second end of the pulse amplitude modulation unit is connected to a second data signal, and the third end of the pulse amplitude modulation unit is connected to the gate of the driving transistor. ； wherein u o is the second voltage signal, u I is the first voltage signal, R is the resistance value of the first resistor, C is the capacitance value of the first capacitor, RC is an integration time constant, t2 is the opening time of the integration operation module receiving the first voltage signal, t1 is the closing time of the integration operation module receiving the first voltage signal, and u0(t1) is the initial voltage value of the second voltage signal.

3. The pixel driving circuit of claim 1, wherein, The first end of the pulse width modulation unit is connected to a pulse width control signal, the second end of the pulse width modulation unit is connected to a first data signal, and the third end of the pulse width modulation unit is connected to the gate of the driving transistor, and the pulse width modulation unit is used for controlling the light-emitting time of the light-emitting device according to the second voltage signal. The pulse width modulation unit comprises: A potential writing subunit, the first end of the potential writing subunit is connected to the pulse width control signal as the first end of the pulse width modulation unit, and the second end of the potential writing subunit is connected to the first data signal as the second end of the pulse amplitude modulation unit.

4. The pixel driving circuit of claim 3, wherein, The first end of the light-emitting time control subunit is further connected to the third end of the potential writing subunit, and the light-emitting time control subunit is used for controlling the light-emitting time of the light-emitting device according to the second voltage signal output by the output end of the operational amplifier. ​ ​ 5. The pixel driving circuit of claim 4, wherein, The light-emitting time control subunit comprises a fourth transistor, a gate of the fourth transistor is configured as a first end of the light-emitting time control subunit, one of a source and a drain of the fourth transistor is configured as a second end of the light-emitting time control subunit, and the other of the source and the drain of the fourth transistor is configured as a third end of the light-emitting time control subunit.

6. The pixel driving circuit of claim 5, wherein, The potential writing subunit comprises a fifth transistor, a gate of the fifth transistor is configured as a first end of the potential writing subunit, one of a source and a drain of the fifth transistor is configured as a second end of the potential writing subunit, and the other of the source and the drain of the fifth transistor is configured as a third end of the potential writing subunit.

7. The pixel driving circuit of claim 6, wherein, The pulse amplitude modulation unit comprises a first transistor, a gate of the first transistor is configured as a first end of the pulse amplitude modulation unit, one of a source and a drain of the first transistor is configured as a second end of the pulse amplitude modulation unit, and the other of the source and the drain of the first transistor is configured as a third end of the pulse amplitude modulation unit.

8. The pixel driving circuit according to any one of claims 3 to 7, characterized in that, The pixel driving circuit further comprises: a storage capacitor, one end of the storage capacitor is connected with the gate of the driving transistor, and the other end of the storage capacitor is connected with one of the source and the drain of the driving transistor and the anode of the light-emitting device, respectively; a third transistor, one of a source and a drain of the third transistor is connected with one of the source and the drain of the driving transistor, the other of the source and the drain of the third transistor is connected with a reference voltage signal, and a gate of the third transistor is connected with a sensing control signal; wherein the other of the source and the drain of the driving transistor is connected with a positive power supply signal, and a cathode of the light-emitting device is connected with a negative power supply signal.

9. A display panel, characterized by, The pixel driving circuit comprises the pixel driving circuit according to any one of claims 1 to 8. The pixel driving circuit comprises the pixel driving circuit according to any one of claims 1 to 8.

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