An explosion-proof silicon solar cell based on physical deposition technology and its manufacturing process

Abstract

This invention discloses an explosion-proof silicon solar cell based on physical deposition technology and its manufacturing process. The cell structure includes a silicon substrate, with a P++ emitter, an aluminum oxide layer, a silicon nitride layer, and a metal electrode sequentially formed on the front side from the inside out. The back side is formed with a silicon oxide tunneling layer, a lightly doped and low-hydrogen polycrystalline silicon layer, a heavily doped and hydrogen-rich polycrystalline silicon layer, a silicon nitride layer, and a metal electrode sequentially from the inside out. The explosion-proof silicon solar cell manufacturing process of this invention is based on PVD technology, which does not cause winding plating. By adjusting the [H] content in the TOPCon structure, the occurrence of explosion defects is reduced, and subsequent ammonia annealing replenishes the [H] content, ensuring the passivation capability of the film. Compared with other disclosed preparation technologies, this PVD-based explosion-proof film process reduces the occurrence of explosion phenomena without winding plating, improves cell yield, and reduces defective products in module manufacturing.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to an explosion-proof silicon solar cell based on physical deposition technology and its manufacturing process. Background Technology

[0002] With the energy crisis and increasing environmental awareness, green and sustainable solar energy is gaining more attention. Solar cells are microelectronic devices that directly convert light energy into electrical energy. After years of development, they have various structures, including PERC (PERC with back-end passivation), TOPCon (TOPCon tunneling oxide passivation solar cell), and HJT (heterojunction solar cell). Currently, considering both cell efficiency and manufacturing cost, TOPCon cells are undoubtedly the mainstream. In industrial manufacturing, the key structures of TOPCon cells are mainly manufactured using three methods: LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), and PVD (physical vapor deposition).

[0003] Traditional TOPcon structures are fabricated using LPCVD (low-pressure chemical vapor deposition), a classic method that has matured significantly over the years due to its simplicity and low cost. However, as a vapor deposition technique, even when processing two silicon wafers stacked together, products will still be deposited on the other side and sides, resulting in "wavy plating." Since the materials deposited on both sides of the battery have completely opposite properties, wavy plating can lead to leakage and a deterioration in battery performance.

[0004] PVD technology has reduced process time and manufacturing costs while improving yield. However, to prepare n+poly layers, PH3 gas needs to be introduced into the PVD equipment to dope P atoms. Therefore, the a-Si layer contains a high concentration of [H], i.e., hydrogenated amorphous silicon (a-Si:H). Most of the [H] will exist in the disordered body and void surface of the film as Si-H bonds, but some of them can also remain in large voids as H2 molecules. The mass density of a-Si:H is slightly lower than that of pure a-Si film, and during annealing, the [H] in the internal voids will recombine and flow out. This will cause a-Si to tend to form relaxed polycrystalline silicon grains, and the accumulation pressure at the c-Si / SiOx and SiOx / poly interfaces will lead to film peeling, i.e., film explosion (e.g.). Figure 1 and Figure 2 As shown in the figure, the bursting of the passivation film will cause the passivation performance of the passivation film to fail, resulting in a decrease in the performance of the solar cell and a reduction in efficiency.

[0005] However, traditional LPCVD processes rarely produce film bursting. This is mainly because LPCVD uses high-temperature deposition, during which Si-H bonds are opened, resulting in a very low [H] content in the film layer. This makes it less likely for [H] to combine and generate H2 during subsequent annealing, leading to pressure buildup and a lower probability of film bursting. Therefore, reducing the [H] content can effectively reduce film bursting. However, the presence of [H] is also essential for the passivation performance of the SiOx / n+poly composite passivation layer. This is because a-Si lacks long-range order, resulting in localized band tails near the conduction band bottom and valence band top. Due to the presence of numerous dangling bonds, a large number of band gap states are formed in the middle of the band gap. Since [H] has a small volume and mass, it can easily enter the disordered network structure of a-Si without altering the network structure, passivating dangling bonds and reducing recombination density. Therefore, a certain amount of [H] is necessary.

[0006] It is evident that LPCVD technology can reduce the occurrence of film explosion defects, but it introduces coating wrapping; while PVD technology can reduce coating wrapping, but it introduces film explosion problems. Therefore, it is particularly important to develop and design a solar cell production technology that can both reduce coating wrapping and prevent film explosion. Summary of the Invention

[0007] In view of this, the present invention provides an explosion-proof silicon solar cell based on physical deposition technology and its manufacturing process. Based on PVD technology, a solar cell manufacturing process technology is designed that can reduce the amount of coating wrapped around the film and prevent the film from exploding.

[0008] To achieve the above objectives, the present invention employs the following:

[0009] This invention provides a manufacturing process for explosion-proof silicon solar cells based on physical deposition technology, characterized by comprising the following steps performed sequentially:

[0010] Step 1: Texturing, cleaning, and boron diffusion processes are performed on the silicon wafer;

[0011] Step 2: Use a laser to perform laser doping on the silicon wafer at the location where metal gate lines need to be printed to prepare P++ emitters;

[0012] Step 3: Use a chain machine and HF aqueous solution to remove the borosilicate glass from the back and sides of the silicon wafer;

[0013] Step 4: Perform alkaline polishing on the back of the silicon wafer. After pre-cleaning and polishing, increase the alkaline content in the post-cleaning solution to micro-etch the polished surface of the silicon wafer.

[0014] Step 5: Use PVD technology to prepare TOPCon structure on the back of silicon wafer. First, prepare an ultrathin tunneling oxide layer. The process of growing doped amorphous silicon is divided into two parts: (1) First, bombard the silicon target with argon ions in the cavity to deposit an intrinsic amorphous silicon film of a certain thickness on the back surface of the silicon wafer. At this time, doping source is not introduced to reduce the content of [H] in the film; (2) After depositing an intrinsic amorphous silicon film of a certain thickness, PH3 gas is introduced to dope phosphorus to obtain a doped amorphous silicon layer.

[0015] Step 6: Perform high-temperature annealing in an annealing furnace under a mixed atmosphere of nitrogen and ammonia to activate the doped atoms in the doped amorphous silicon layer and replenish the [H] reduced in the PVD process in step 5.

[0016] Step 7: After annealing, perform BOE cleaning;

[0017] Step 8: Prepare an aluminum oxide passivation layer on the positive surface of the silicon wafer using an atomic layer deposition (ALD) device;

[0018] Step 9: Prepare silicon nitride antireflection films on both the front and back sides of the silicon wafer using a plasma-enhanced chemical deposition system to reduce light reflection;

[0019] Step 10: Apply metal paste to the front and back of the silicon wafer using screen printing equipment, and process it at high temperature in a sintering furnace to prepare metal grid lines. This allows the metal material to combine with silicon to form an alloy, thereby extracting photogenerated carriers and completing the battery fabrication.

[0020] In step 1, the silicon wafer is texturized to remove the surface cutting damage layer and form a textured textured surface structure to reduce light loss. The silicon wafer is an n-type silicon wafer with a thickness of 130 μm and a sheet resistance of 1 Ω / □.

[0021] In step 1, after the silicon wafer is texturized and cleaned, it is placed in a boron diffusion furnace tube for boron diffusion. The boron diffusion process includes four steps: pre-oxidation, deposition, advancement, and post-oxidation.

[0022] The deposition time is reduced to 90–120 s, the propagation time is reduced to 350–400 s, and the sheet resistance of the silicon wafer after boron diffusion is approximately 150 Ω / □.

[0023] In step 4, the alkaline polishing process, the silicon wafer is placed in a post-cleaning tank. The traditional process involves adding pure water, sodium hydroxide, and hydrogen peroxide in a ratio of 90:1:4. The current process increases the alkaline content in the solution in the tank to achieve a ratio of 90:3:4 for pure water, sodium hydroxide, and hydrogen peroxide. After the post-cleaning process, the surface of the silicon wafer is cleaned with hydrochloric acid and hydrofluoric acid.

[0024] In step 4, the reflectivity of the back surface of the silicon wafer is appropriately reduced, decreasing from 35% to 25-30%.

[0025] In step 5, the deposition temperature is maintained at 350–400°C to reduce the [H] present in the doped amorphous silicon layer as Si-H bonds.

[0026] In step 6, the annealing is carried out at a temperature of about 600°C for about 300-500 seconds, and a certain amount of ammonia is added under a conventional nitrogen atmosphere. After 300 seconds, the ammonia is stopped, and the annealing temperature is increased to 850°C at a rate of 10°C / min and held at a constant temperature for 2000 seconds to activate the doped atoms in the doped amorphous silicon layer.

[0027] The present invention also provides an explosion-proof film silicon solar cell, the cell structure including a silicon substrate, wherein a P++ emitter, an aluminum oxide layer, a silicon nitride layer and a metal electrode are sequentially formed on the front side of the silicon substrate from the inside to the outside, and a silicon oxide tunneling layer, a lightly doped and low-hydrogen polycrystalline silicon layer, a heavily doped and hydrogen-rich polycrystalline silicon layer, a silicon nitride layer and a metal electrode are sequentially formed on the back side of the silicon substrate from the inside to the outside.

[0028] The present invention has the following technical effects:

[0029] The explosion-proof silicon solar cell manufacturing process of the present invention is based on the PVD process that does not cause winding plating. By adjusting the [H] content in the TOPCon structure, the occurrence of explosion defects is reduced, and the [H] content is replenished through subsequent ammonia annealing, thus ensuring the passivation capability of the film. Attached Figure Description

[0030] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0031] Figure 1 and Figure 2 This demonstrates the phenomenon of silicon wafer film bursting at both the macroscopic and microscopic levels;

[0032] Figure 3 This is a simplified structural diagram of the explosion-proof silicon solar cell prepared according to the present invention;

[0033] Figure 4 This is a comparison chart of the bursting ratio of traditional TOPCon batteries and Example 1. Detailed Implementation

[0034] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments, further clarifies the invention. Those skilled in the art should understand that the specific descriptions below are illustrative rather than restrictive, and should not be construed as limiting the scope of protection of the present invention.

[0035] Technical concept of the invention:

[0036] The excellent passivation performance of TOPCon cells originates from the field passivation provided by the extremely thin tunneling oxide layer (SiOxSiOx) and the heavily doped polycrystalline silicon (PolyPoly) layer. During fabrication, doped amorphous silicon is first prepared, and then the lattice is rearranged through high-temperature annealing to form an n+poly layer. However, before annealing, since most of the Si and O atoms in the tunneling oxide layer are unsaturated, O atoms can introduce acceptor defects. Therefore, during the annealing process, two different chemical passivation mechanisms are generated: "surface hydrogenation" and "oxidation-driven".

[0037] The main process related to film bursting is surface hydrogenation. To prepare an n+poly layer, PH3 gas is usually introduced into the PVD equipment to dope P atoms. Therefore, the a-Si layer contains a high concentration of [H], i.e., hydrogenated amorphous silicon (a-Si:H). Most of the [H] will exist in the disordered body and void surface of the film in the form of Si-H bonds. However, some of them can also remain in the large voids as H2 molecules. The mass density of a-Si:H is slightly lower than that of pure a-Si film. Moreover, during annealing, the [H] in the internal voids will recombine and flow out. This also explains why when the poly film is annealed, a-Si tends to form relaxed polycrystalline silicon grains, i.e., film bursting.

[0038] However, hydrogen (H) plays a crucial role in improving interface passivation. As an atomic number of 1, the low mass of hydrogen allows it to easily enter and exit a-Si, diffuse through the silicon network, passivate defective silicon bonds, and reduce defect density—a process known as hydrogen passivation. Therefore, the H content is key to controlling the passivation effect of SiO / n+Poly.

[0039] The bursting of the film is caused by the combination of atomic H in the silicon mesh to form H2. The hydrogen seepage comes from the breaking of SiH2 and SiH3 bonds, as well as free Si-H bonds. Because the atomic mass of H is small, it can accumulate at the interface between the doped Si layer (Poly) and the SiO2 layer, resulting in an increase in H2 pressure at the interface. When the H2 pressure exceeds a certain critical value, the bursting of the film occurs.

[0040] Due to the hydrogen transport mechanism of Si in metal-oxide-semiconductor (MOS) structures, the oxide layer in the MOS structure reduces the flux of hydrogen into the underlying (c-Si) layer, thus acting as a hydrogen diffusion barrier. However, in the case of a-Si:H / SiO / c-Si, H aggregates at the a-Si:H / SiO interface to form bubbles because hydrogen can permeate into the C-Si substrate in the a-Si:H / c-Si case. Therefore, the cause of film bursting is due to both H bonding and SiOx.

[0041] During annealing, the H atoms that detach introduce excessive defects at the interface, resulting in poor i-Voc of the a-Si:H / c-Si sample after annealing. It is generally believed that i-Voc is high when annealing at 600℃ for 1 min and at 800℃ for 1 and 5 min. When annealing at 600℃ for 1 min, the Si-H rearrangement at the interface increases i-Voc. After annealing at 600℃ for 5 min, the H concentration in the a-Si:H film further decreases, and the H concentration at the interface decreases. At temperatures above 400℃, H2 flows out of the film. Compared with the H level detected in the bulk region, it can be considered that all the H in the film precipitates after annealing at 600℃ for 5 min. In other words, after annealing at 600℃, the H atoms bound to silicon in the film become mobile and flow out, eventually being exhausted after annealing for 5 min.

[0042] Based on the above analysis, the present invention proposes the following improvements:

[0043] ① The cause of film delamination is the bonding of elemental hydrogen (H), which leads to accumulation pressure at the c-Si / SiOx and SiOx / poly interfaces, resulting in film peeling. Therefore, the first step is to improve the adhesion of SiOx at the c-Si / SiOx interface to better resist accumulation pressure and prevent film delamination. Corresponding improvement directions: In the back surface polishing process, increase the alkali ratio in the post-cleaning step and micro-etch the back surface to reduce its reflectivity from 35% to 25-30%. A slightly rougher back surface can provide more adhesion points for subsequent film layers, increasing the film's resistance to gas pressure.

[0044] ② When preparing poly using PVD, it can be divided into three steps: 1) After the PO cavity tunneling layer is prepared, a 1 / 3 thickness of a-Si is deposited in the first Paid cavity, and the deposition temperature is increased to above 450℃; 2) At this time, PH3 gas is not introduced, and intrinsic amorphous silicon is grown. Without changing the properties of a-Si and SiOx, the H content is reduced to prevent the film from bursting; 3) The remaining thickness of a-Si is prepared in the second Paid cavity. At this time, the temperature can be reduced to below 300℃, and PH3 is introduced to grow doped amorphous silicon. Finally, the a-Si is annealed in an NH3 atmosphere to transform it into poly to make up for the lost H.

[0045] Example:

[0046] This embodiment yields an explosion-proof film silicon solar cell, such as... Figure 3 As shown, the battery structure includes a silicon substrate 10. On the front side of the silicon substrate 10, from the inside out, a P++ emitter 11, an aluminum oxide layer 12, a silicon nitride layer 13, and a metal electrode are sequentially formed. On the back side of the silicon substrate 10, from the inside out, a silicon oxide tunneling layer 21, a lightly doped and low-hydrogen polycrystalline silicon layer 22, a heavily doped and hydrogen-rich polycrystalline silicon layer 23, a silicon nitride layer 24, and a metal electrode are sequentially formed. Figure 4As shown, the silicon solar cell fabricated in this embodiment has a significantly lower rate of film bursting compared to traditional TOPCon structure cells.

[0047] The specific implementation method for preparing the above-mentioned explosion-proof film silicon solar cell in this embodiment includes the following steps:

[0048] (1) Select an n-type silicon with a thickness of 130um and a sheet resistance of 1Ω / □ as a substrate, and perform texturing on it to remove the surface cutting damage layer and form a textured textured surface structure to reduce light loss.

[0049] (2) After texturing and cleaning, the silicon wafer is placed in a boron diffuser tube for boron diffusion. The boron diffusion is divided into four steps: pre-oxidation, deposition, propulsion and post-oxidation. Compared with the traditional process, the process time and diffusion concentration can be reduced. Preferably, the deposition time is reduced to 90-120s and the propulsion time is reduced to 350-400s. After diffusion, the sheet resistance is about 150Ω / □.

[0050] (3) Laser-assisted laser opening and heavy doping processes are performed on the front gate line positions of silicon wafers.

[0051] (4) Use a chain-type single-sided HF equipment to remove BSG from the back of the silicon wafer. The volume ratio of HF to DI Water in the machine is 1:10.

[0052] (5) After removing the BSG from the back of the silicon wafer, the back of the silicon wafer is alkali polished. The silicon wafer is placed in the alkali polishing tank. After alkali polishing, the silicon wafer is placed in the post-cleaning tank. The traditional process is to add pure water, sodium hydroxide and hydrogen peroxide in the tank in a ratio of 90:1:4. The current process is to increase the alkali content in the solution in the tank so that the ratio of pure water, sodium hydroxide and hydrogen peroxide in the tank reaches 90:3:4. The polished surface of the battery is micro-etched to provide higher adhesion for subsequent thin films. After the post-cleaning, the surface of the silicon wafer is cleaned with hydrochloric acid and hydrofluoric acid.

[0053] (6) TOPCon structure is prepared on the back side of silicon wafer using PVD technology. First, an ultrathin tunneling oxide layer is prepared. The Paid cavity for growing doped amorphous silicon is divided into two parts: a) First, argon ions are used to bombard the silicon target in the cavity to deposit an intrinsic amorphous silicon thin film (first intrinsic layer) of a certain thickness on the back surface of the silicon wafer. At this time, no doping source is introduced to reduce the content of [H] in the film; b) After depositing an intrinsic amorphous silicon thin film of a certain thickness, PH3 gas is introduced to dope phosphorus to obtain a doped amorphous silicon layer. It is worth noting that the deposition temperature is maintained at 350-400℃ to reduce the [H] present in Si-H bonds in the doped amorphous silicon layer.

[0054] (7) Perform high-temperature annealing treatment. Perform high-temperature annealing in an annealing furnace at a temperature of about 600°C for about 300-500s. Add a certain amount of ammonia gas under a conventional nitrogen atmosphere. Stop the supply of ammonia gas after 300s. Increase the annealing temperature to 850°C at a rate of 10°C / min and maintain the temperature for 2000s to activate the doped atoms in the doped amorphous silicon layer and replenish the [H] that was reduced in the PVD process.

[0055] (8) After annealing, BOE cleaning is carried out in a tank cleaning equipment. First, hydrogen peroxide and weak alkaline solution are used to clean the organic impurities on the surface, and then HF solution is used to remove the surface oxides.

[0056] (9) An aluminum oxide passivation layer is prepared on the positive surface of a silicon wafer using an atomic layer deposition (ALD) device.

[0057] (10) Silicon nitride antireflection films are prepared on both the front and back sides of a silicon wafer using a plasma-enhanced chemical deposition system (PECVD) to reduce light reflection.

[0058] (11) Using screen printing equipment, metal paste is applied to the front and back of the silicon wafer. After high-temperature processing in a sintering furnace, metal grid lines are prepared, so that the metal material is combined with silicon to form an alloy, and photogenerated charge carriers are extracted to complete the preparation of the battery.

[0059] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A manufacturing process for explosion-proof silicon solar cells based on physical deposition technology, characterized in that, This includes the following steps performed sequentially: Step 1: Texturing, cleaning, and boron diffusion processes are performed on the silicon wafer; Step 2: Use a laser to perform laser doping on the silicon wafer at the location where metal gate lines need to be printed to prepare P++ emitters; Step 3: Use a chain machine and HF aqueous solution to remove the borosilicate glass from the back and sides of the silicon wafer; Step 4: Perform alkaline polishing on the back of the silicon wafer. After pre-cleaning and polishing, increase the alkaline content in the post-cleaning solution to micro-etch the polished surface of the silicon wafer. Step 5: Use PVD technology to prepare TOPCon structure on the back of silicon wafer. First, prepare an ultrathin tunneling oxide layer. The process of growing doped amorphous silicon is divided into two parts: (1) First, use argon ions to bombard the silicon target in the cavity to deposit an intrinsic amorphous silicon film on the back surface of the silicon wafer. At this time, doping source is not introduced and the deposition temperature is maintained at 350-400℃ to reduce the content of [H] in the film; (2) After depositing the intrinsic amorphous silicon film, PH3 gas is introduced to dope phosphorus to obtain a doped amorphous silicon layer. Step 6: Anneal at 600℃ for 300-500s, and add ammonia under a conventional nitrogen atmosphere. After 300s, stop the ammonia supply and raise the annealing temperature to 850℃ at a rate of 10℃ / min. Hold the temperature for 2000s to activate the doped atoms in the doped amorphous silicon layer and replenish the [H] reduced in the PVD process in step 5. Step 7: After annealing, perform BOE cleaning; Step 8: Prepare an aluminum oxide passivation layer on the positive surface of the silicon wafer using an atomic layer deposition (ALD) device; Step 9: Prepare silicon nitride antireflection films on both the front and back sides of the silicon wafer using a plasma-enhanced chemical deposition system to reduce light reflection; Step 10: Apply metal paste to the front and back of the silicon wafer using screen printing equipment, and process it at high temperature in a sintering furnace to prepare metal grid lines. This allows the metal material to combine with silicon to form an alloy, thereby extracting photogenerated carriers and completing the battery fabrication.

2. The production process of explosion-proof silicon solar cells based on physical deposition technology according to claim 1, characterized in that, In step 1: the silicon wafer is texturized to remove the surface cutting damage layer and form a textured textured surface structure on its surface to reduce light loss; the silicon wafer is an n-type silicon wafer with a thickness of 130um and a sheet resistance of 1Ω / □.

3. The production process of explosion-proof silicon solar cells based on physical deposition technology according to claim 2, characterized in that, In step 1: after texturing and cleaning the silicon wafer, the silicon wafer is placed in a boron diffusion furnace tube for boron diffusion. The boron diffusion process includes four steps: pre-oxidation, deposition, advancement, and post-oxidation.

4. The production process of explosion-proof silicon solar cells based on physical deposition technology according to claim 3, characterized in that, The deposition time is reduced to 90–120 s, the advance time is reduced to 350–400 s, and the sheet resistance of the silicon wafer after boron diffusion is 150 Ω / □.

5. The production process of explosion-proof silicon solar cells based on physical deposition technology according to claim 1, characterized in that, In step 4, the alkaline polishing process, the silicon wafer is placed in the post-cleaning tank. The traditional process is to add pure water, sodium hydroxide, and hydrogen peroxide in the tank at a ratio of 90:1:

4. The current process increases the alkaline content in the solution in the tank so that the ratio of pure water, sodium hydroxide, and hydrogen peroxide in the tank reaches 90:3:

4. After the post-cleaning, the surface of the silicon wafer is cleaned with hydrochloric acid and hydrofluoric acid.

6. The production process of explosion-proof silicon solar cells based on physical deposition technology according to claim 5, characterized in that, Through the processing in step 4, the reflectivity of the back surface of the silicon wafer is appropriately reduced, decreasing from 35% to 25-30%.

7. An explosion-proof film silicon solar cell, characterized in that, The battery is manufactured using the production process described in any one of claims 1-6. The battery structure includes a silicon substrate, on the front side of which a P++ emitter, an aluminum oxide layer, a silicon nitride layer, and a metal electrode are sequentially formed from the inside to the outside. On the back side of the silicon substrate, a silicon oxide tunneling layer, a lightly doped and low-hydrogen polycrystalline silicon layer, a heavily doped and hydrogen-rich polycrystalline silicon layer, a silicon nitride layer, and a metal electrode are sequentially formed from the inside to the outside.

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