A method and apparatus for processing instructions in a processor debugging system
By controlling the instruction dispatch module to send the next instruction after the previous one has been executed in processor debug mode, the problem of disordered instruction processing order in processor debug mode is solved, simplifying the processor architecture and improving stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-24
- Publication Date
- 2026-03-31
AI Technical Summary
In debug mode, the processor's instruction processing order becomes disordered, leading to increased pipeline design complexity and frequent processor pauses and resumes, which affects stability.
In processor debug mode, the instruction dispatch module sends the next instruction only after the instruction execution module has completed executing the previous instruction. The debug module manages the instruction flow through control signals to prevent subsequent instructions from being executed prematurely, thus simplifying the processor architecture.
This ensures that the processor can be paused normally in debug mode, simplifying processor design, improving stability, reducing design complexity, and avoiding register backup and recovery logic.
Smart Images
Figure CN117472443B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal processing, and more particularly to a method and apparatus for processing instructions in a processor debugging system. Background Technology
[0002] The processor contains multiple functional modules, which process instructions in a preset order. Each module processes one instruction before moving on to the next instruction in that module.
[0003] A debug module can also be set up in the processor. This module is used to analyze the execution of applications during application development on the processor, and to check whether the actual execution results of the application are consistent with the expected results, so as to locate design problems in the application. Specifically, when the processor is in debug mode, breakpoint triggering conditions can be set to pause the processor, thereby enabling the acquisition and setting of the processor's internal state.
[0004] Because pausing the processor can disrupt the processing order of multiple instructions, a corresponding solution strategy needs to be set, which increases the complexity of the processor. Summary of the Invention
[0005] To address any of the aforementioned technical problems, embodiments of this application provide a method and apparatus for processing instructions in a processor debugging system.
[0006] To achieve the objectives of the embodiments of this application, the embodiments of this application provide an instruction processing apparatus in a processor debugging system. The apparatus includes at least two modules that are executed sequentially, wherein the at least two modules include an instruction dispatch module and an instruction execution module, wherein:
[0007] The instruction distribution module is used to send the stored instructions to the instruction execution module;
[0008] The instruction execution module is used to process the received instructions.
[0009] The device further includes:
[0010] The debug module is used to output control signals that enable the processor to be in debug mode.
[0011] The instruction dispatch module is further configured to, after the control signal indicates that the processor is in debug mode, obtain the execution status of the current instruction by the instruction execution module, and send the next instruction corresponding to the current instruction to the instruction execution module when the execution status is "execution completed".
[0012] A method for processing instructions in a processor debugging system, applied to the apparatus described above, the method comprising:
[0013] Receives a control signal to enable the processor to be in debug mode;
[0014] After the control signal indicates that the processor is in debug mode, the execution status of the instruction execution module for the current instruction is obtained;
[0015] Once the execution state is "execution completed", the next instruction corresponding to the current instruction is sent to the instruction execution module.
[0016] One of the above technical solutions has the following advantages or beneficial effects:
[0017] When the processor is in debug mode, the instruction dispatch module sends the next instruction to the instruction execution module only after the instruction execution module has completed executing the previous instruction. This avoids the problem of later-ordered instructions being executed ahead of time, ensuring that the processor can enter the pause state normally, greatly simplifying the processor architecture and ensuring the stability of the processor.
[0018] Other features and advantages of the embodiments of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the embodiments of this application. The objects and other advantages of the embodiments of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description
[0019] The accompanying drawings are used to provide a further understanding of the technical solutions of the embodiments of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0020] Figure 1 This is a schematic diagram illustrating how the processor processes instructions.
[0021] Figure 2 for Figure 1 The diagram illustrates one application scenario of instruction processing.
[0022] Figure 3 for Figure 1 This diagram illustrates another application scenario of instruction processing.
[0023] Figure 4 A schematic diagram of the structure of the instruction processing device in the processor debugging system provided in this application embodiment;
[0024] Figure 5 for Figure 4A schematic diagram of the instruction processing flow of the device shown;
[0025] Figure 6 The settings provided for the embodiments of this application include Figure 5 A schematic diagram of the processor structure of the device shown;
[0026] Figure 7 This is a flowchart illustrating the instruction processing method in the processor debugging system provided in this application embodiment. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.
[0028] Figure 1 This is a diagram illustrating how a processor processes instructions. (For example...) Figure 1 As shown, the processor includes four modules that execute sequentially: an instruction fetch module, a decode module, an instruction dispatch module, and an instruction execution module (Exe), wherein:
[0029] The instruction fetch module is used to read instructions from the program memory.
[0030] The decoding module (Decode) is used to decode the instructions;
[0031] The instruction dispatch module (Dispatch) is used to dispatch the decoded instructions to the execution units (Exe1, Exe2) in the instruction execution module (Exe).
[0032] The instruction execution module (Exe) is used to process the received instructions and write the execution result into the register (hereinafter abbreviated as regs) or access the data memory based on the execution result and write the return result returned by the data memory into the register (regs).
[0033] The Load Store Unit (LSU) is used to preprocess instruction data and to facilitate communication between registers (regs) and memory.
[0034] The above process describes the processor's pipelined processing method, which corresponds to the instruction fetch stage, instruction decode stage, instruction dispatch stage, instruction execution stage, and write-back register / access data memory stage of the processor pipeline.
[0035] The instruction execution level (Exe) may occupy one or more levels depending on the function of the instruction. For example, addition instructions, logical operation instructions, and comparison instructions can occupy one pipeline level; multiplication instructions occupy two pipeline levels; and division instructions occupy multiple pipeline levels.
[0036] During instruction execution, instructions enter the pipeline sequentially. Under normal pipeline operation, instructions pass through the instruction fetch stage, instruction decode stage, instruction dispatch stage, instruction execution stage, and write-back register / data memory access stage in sequence. Furthermore, in multi-issue processors, each stage of the pipeline can have multiple instructions that pass through the pipeline in parallel to the execution stage. The execution stage also has multiple execution units, allowing multiple instructions to be executed simultaneously, with the results written to registers or accessed from data memory.
[0037] During processor debugging, it's necessary to control the processor to pause when breakpoint trigger conditions are met. Then, the processor's internal state, such as PC value, register values, or variable values in the program, is read through the debug interface to determine if the application's execution result matches expectations. Alternatively, the PC value, register values, or variable values can be modified through the debug interface to change the application's running state. After completing the required operations through the debug interface, the processor is controlled to resume operation.
[0038] During normal application execution, the processor processes instructions sequentially in a pipelined manner. However, during application debugging, the processor needs to be stopped frequently, pausing the entire pipeline. This constant pausing and resuming complicates the processor's pipeline design, requiring the inclusion of extensive control logic to ensure proper pipeline operation in debug mode.
[0039] Figure 2 for Figure 1 The diagram illustrates one application scenario of instruction processing. For example... Figure 2 As shown, the instruction stream (ins1, ins2, ins3...) enters the processor pipeline sequentially. The breakpoint is triggered when the value of register (regs) equals value0.
[0040] During normal processor execution, each instruction completes its execution at the execution level, writes the result into a register, and the instruction's lifecycle ends.
[0041] During the processor's debugging process, execution begins with the instruction `ins1`. After instruction `ins2` completes, its result `value0` is written to register `regs`, changing the value of `regs` to `value0`. Since the breakpoint trigger condition is met, the processor enters a paused state. At this point, although instruction `ins3` is already in the pipeline, it cannot continue execution due to the processor pause and must remain in its current state. After debugging is complete, the program can resume execution, waiting for the next trigger condition to be met, and then re-enter the paused state.
[0042] In practical applications, because the number of cycles of instructions at the execution level is different and memory access instructions are usually multi-cycle instructions, when instruction ins2 writes the execution result to register (regs), instruction ins3 also writes the execution result to register (regs), thus failing to achieve the goal of not executing instruction ins3.
[0043] Figure 3 for Figure 1 This diagram illustrates another application scenario of the instruction processing shown. For example... Figure 3 As shown, the instruction stream (ins1, ins2, ins3, ...) enters the processor's pipeline sequentially. The execution result where the register (regs) value equals the instruction ins2 is used as the processor's breakpoint trigger condition.
[0044] Among them, the instruction ins2 occupies two levels of execution units (Exe1, Exe2) at the execution level, while the instruction ins3 occupies one level of execution unit (Exe1) at the execution level.
[0045] During the processor's debugging process, execution begins with the instruction `ins1`. After the instruction `ins2` is executed, its result `value0` is written to register `regs`. Simultaneously, the instruction `ins3` also writes its result to register `regs`. Since the value of register `regs` is updated to the result `value0` of instruction `ins2`, the breakpoint trigger condition is met, and the processor enters a paused state. However, when the breakpoint trigger condition is met, both instructions `ins2` and `ins3` have already completed execution, and their results have been written to register `regs`, making it impossible to achieve the debugging goal of pausing the processor after the execution of instruction `ins2`.
[0046] To solve the above problem, the value of the register (regs) will be backed up.
[0047] by Figure 3Taking the illustrated application scenario as an example, although the execution result of the instruction `ins3` modifies the value of the register (`regs`), because the register (`regs`) has a backup, by rolling back the value of the register (`regs`), the processor can be controlled to start execution from the instruction `ins3` again after resuming execution. However, when the processor enters a paused state, the instruction `ins3` has already been executed, and the execution result of the instruction `ins3` has already been written to the register (`regs`). Therefore, when the processor resumes execution, it needs to clear the pipeline so that the flow line of the instruction `ins3` starts from the instruction fetch module.
[0048] The aforementioned solutions make the processor pipeline extremely complex. Furthermore, the presence of multi-cycle instructions and other registers (such as control registers and status registers) exponentially increases the complexity of the entire processor in order to support debugging capabilities.
[0049] To address the aforementioned technical issues, embodiments of this application provide the following solutions, including:
[0050] Figure 4 This is a schematic diagram of the instruction processing device in the processor debugging system provided in an embodiment of this application. Figure 4 As shown, the device includes at least two modules that execute sequentially, wherein the at least two modules include an instruction dispatch module and an instruction execution module, wherein:
[0051] The instruction distribution module is used to send the stored instructions to the instruction execution module;
[0052] The instruction execution module is used to process the received instructions.
[0053] The device further includes:
[0054] The debug module is used to output control signals that enable the processor to be in debug mode.
[0055] Specifically, the debug module is connected to the instruction dispatch module and is used to notify the instruction dispatch module whether the processor is in debug mode.
[0056] The instruction distribution module is further configured to, after the control signal indicates that the processor is in debug mode, obtain the execution status of the current instruction by the instruction execution module, and send the next instruction corresponding to the current instruction to the instruction execution module when the execution status is "execution completed".
[0057] Specifically, when the processor is running in debug mode, the processor frequently pauses due to breakpoint triggering conditions, disrupting the instruction pipeline and requiring the processor to remain in a paused state. In this embodiment, when the processor is in debug mode, it caches the instruction stream in the instruction dispatch module, allowing only one instruction to enter the instruction execution module at a time. While the instruction is executing in the instruction execution module, subsequent instructions can only be cached in the instruction dispatch module and cannot enter the instruction execution module. Only after the instruction entering the instruction execution module has been fully executed and the execution result has been updated in the register (regs), will the instruction dispatch module send the cached next instruction to the instruction execution module. After the next instruction enters the instruction execution module, it continues to cache other received instructions until the instruction entering the instruction execution module has been executed. Only then will the instruction dispatch module send the cached next instruction to the instruction execution module, and so on, until the control signal indicates that the processor is no longer in debug mode.
[0058] The apparatus provided in this application embodiment, when the processor is in debug mode, sends the next instruction to the instruction execution module only after the instruction execution module has completed executing one instruction. This avoids the problem of later-ordered instructions being executed ahead of time, ensuring that the processor can enter the pause state normally, greatly simplifying the processor architecture and ensuring the stability of the processor.
[0059] Figure 5 for Figure 4 A schematic diagram of the instruction processing flow of the device shown. (As shown) Figure 5 As shown, the instruction stream (ins1, ins2, ins3...) enters the processor pipeline in sequence.
[0060] After the instruction dispatch module sends instruction ins1 to the instruction execution module, it caches other instructions (instructions ins2 and ins3) in the instruction stream.
[0061] After the execution result of instruction ins1 is written to register (regs), instruction ins2 is sent to the instruction execution module, and other instructions in the instruction stream (instruction ins3) are cached.
[0062] After the execution result of instruction ins2 is written to register (regs), instruction ins3 is sent to the instruction execution module, and other instructions in the instruction stream are cached, and so on.
[0063] In the above process, when the processor is in debug mode, the execution result of the instruction ins2, where the value of register (regs) equals the breakpoint trigger condition, is used. After instruction ins2 completes execution, the processor pauses because the value of register (regs) meets the breakpoint trigger condition. Since instruction ins3 is still cached in the instruction dispatch module and has not yet been sent to the instruction execution module, instruction ins3 is not executed. This solves the problem of later-ordered instructions being executed ahead of others, ensuring that the processor can normally enter the pause state.
[0064] from Figure 5 As shown in the instruction processing diagram, the instruction stream enters the instruction execution module serially. The next instruction can only begin execution after the previous one has been completely executed. Thus, after an instruction is executed, if the result of that instruction meets the breakpoint trigger condition, the processor pauses. Since the next instruction is still cached in the instruction dispatch module and has not yet been sent to the instruction execution module, the next instruction is not executed. This solves the problem of later-ordered instructions being executed prematurely under processor pause conditions, and eliminates the need for backing up and restoring registers (regs), significantly simplifying processor design.
[0065] Figure 6 The settings provided for the embodiments of this application include Figure 5 A schematic diagram of the processor in the illustrated device. Figure 6 As shown, the processor includes:
[0066] Program memory is used to store instructions;
[0067] Data memory is used to store data;
[0068] The instruction fetch module is used to read instructions from the instruction memory;
[0069] The decoding module is used to decode instructions.
[0070] The instruction dispatch module (Dispatch) is used to cache the decoded instructions and send the cached instructions to the execution units (Exe1, Exe2) in the instruction execution module.
[0071] The instruction execution module (Exe) is used to process the received instructions and write the execution result into the register, or to access the data memory based on the execution result and write the data returned by the data memory into the register (regs).
[0072] When the processor is in debug mode, the instruction dispatch module first dispatches the first instruction to the instruction execution module, and then waits for the execution result of the first instruction. After the instruction execution module completes the execution of the first instruction, it updates the result of the first instruction in the register (regs). The instruction dispatch module then allows the sending of the second instruction. The instruction dispatch module dispatches the second instruction, and then starts waiting for the execution result of the second instruction again. After the second instruction completes its execution and updates the result in the register (regs), it begins dispatching the third instruction, and so on, until the processor is no longer in debug mode.
[0073] When the processor is in debug mode, if the execution result of a certain instruction meets the breakpoint trigger condition, the processor enters a paused state. At this time, you can check the processor's internal state, such as register values, PC values, or variables. After checking, you can control the processor to continue executing instructions.
[0074] When the processor is in debug mode, instructions are executed sequentially. When the value of the register (regs) meets the breakpoint trigger condition, there is no issue of later-ordered instructions being executed. Therefore, there is no need to implement register backup functionality or design register recovery logic, thus reducing the complexity of processor architecture design.
[0075] When the processor is in debug mode, instructions are executed sequentially, which slows down program execution. However, in debug mode, the execution speed is generally not a concern, but rather a means to view program functions. Therefore, the reduction in instruction processing speed is tolerable.
[0076] Furthermore, the instruction dispatch module is used to determine the execution status as completed when any of the following conditions are met:
[0077] The execution result of the current instruction is detected and written directly to the register (regs);
[0078] Access the data memory based on the execution result, and write the return result returned by the data memory into the register (regs).
[0079] The execution status of an instruction can be determined by utilizing the conventional processing flow of the instruction, without requiring any changes to the instruction processing flow, thus offering high versatility.
[0080] Furthermore, the instruction distribution module is also configured to cache instructions that have been received but not sent to the instruction execution module after the control signal indicates that the processor is in debug mode.
[0081] For the instruction dispatch module, the instruction dispatch speed in debug mode is lower than that in non-debug mode. A buffer can be set up to cache instructions that fail to be dispatched.
[0082] Furthermore, the instruction distribution module is also configured to, after the control signal indicates that the processor is not in debug mode, directly send another instruction stored in the instruction distribution module after completing the sending operation of one instruction stored in the instruction distribution module.
[0083] When the processor is not in debug mode, the instruction dispatch module distributes the cached instructions to the instruction execution module in the normal dispatch manner; correspondingly, the instructions enter the instruction execution module for normal execution and update the results in the registers (regs).
[0084] Furthermore, the instruction distribution module is used to perform instruction sending operations to the instruction execution module according to the order in which the instructions are received.
[0085] Specifically, following the first-in, first-out principle, instructions received earlier are given priority over instructions received later.
[0086] Figure 7 This is a flowchart illustrating the instruction processing method in the processor debugging system provided in this application embodiment. Figure 7 As shown, the method is applied to the apparatus described above, and the method includes:
[0087] Step 701: Receive a control signal to enable the processor to be in debug mode;
[0088] Step 702: After the control signal indicates that the processor is in debug mode, obtain the execution status of the instruction execution module for the current instruction;
[0089] Step 703: When the execution status is "execution completed", send the next instruction corresponding to the current instruction to the instruction execution module.
[0090] Specifically, the execution status is determined to be completed when any of the following conditions are met:
[0091] The execution result of the current instruction is detected and written directly into the register;
[0092] Access the data memory based on the execution result, and write the return result returned by the data memory into the register.
[0093] Optionally, the method further includes:
[0094] After the control signal indicates that the processor is in debug mode, the cache receives instructions that have not yet been sent to the instruction execution module.
[0095] Optionally, the method further includes:
[0096] After the control signal indicates that the processor is not in debug mode, after completing the sending operation of one instruction stored in the instruction distribution module, another instruction stored in the instruction distribution module is sent directly.
[0097] Furthermore, the instruction sending operation is performed on the instruction execution module according to the order in which the instructions are received.
[0098] The method provided in this application embodiment, when the processor is in debug mode, sends the next instruction to the instruction execution module only after the instruction execution module has completed executing one instruction. This avoids the problem of later-ordered instructions being executed ahead of time, ensuring that the processor can enter the pause state normally, greatly simplifying the processor architecture and ensuring the stability of the processor.
[0099] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
Claims
1. An apparatus for processing instructions in a processor debugging system, the apparatus comprising at least two modules executed sequentially, wherein the at least two modules comprise an instruction dispatch module and an instruction execution module, and wherein: the instruction dispatch module is configured to send stored instructions to the instruction execution module; the instruction execution module is configured to process received instructions in response; and wherein the apparatus further comprises: a debugging module configured to output a control signal for enabling a processor to be in a debugging mode; and wherein the instruction dispatch module is further configured to, after the control signal indicates that the processor is in the debugging mode, acquire an execution status of a current instruction by the instruction execution module, and send a next instruction corresponding to the current instruction to the instruction execution module after the execution status is execution complete; and wherein the instruction dispatch module is configured to determine that the execution status is execution complete when any of the following conditions is met, comprising: detecting that an execution result corresponding to the current instruction is directly written into a register; and accessing a data storage according to the execution result, and writing a return result returned by the data storage into a register.
2. The apparatus of claim 1, wherein: the instruction dispatch module is further configured to, after the control signal indicates that the processor is in the debugging mode, buffer instructions that have been acquired but not sent to the instruction execution module.
3. The apparatus of claim 1, wherein: the instruction dispatch module is further configured to, after the control signal indicates that the processor is not in the debugging mode, directly send another instruction stored in the instruction dispatch module after sending of a current instruction stored in the instruction dispatch module is completed.
4. The apparatus of any one of claims 1 to 3, wherein: the instruction dispatch module is configured to perform instruction sending operations to the instruction execution module in a receiving order of the instructions.
5. A method for processing instructions in a processor debugging system, applied to the apparatus of any one of claims 1 to 4, the method comprising: receiving a control signal for enabling a processor to be in a debugging mode; acquiring an execution status of a current instruction by the instruction execution module after the control signal indicates that the processor is in the debugging mode; and sending a next instruction corresponding to the current instruction to the instruction execution module after the execution status is execution complete; and wherein the method further comprises determining that the execution status is execution complete when any of the following conditions is met, comprising: detecting that an execution result corresponding to the current instruction is directly written into a register; and accessing a data storage according to the execution result, and writing a return result returned by the data storage into a register. the method further comprising: buffering instructions that have been acquired but not sent to the instruction execution module after the control signal indicates that the processor is in the debugging mode; the method further comprising: directly sending another instruction stored in the instruction dispatch module after sending of a current instruction stored in the instruction dispatch module is completed after the control signal indicates that the processor is not in the debugging mode; and performing instruction sending operations to the instruction execution module in a receiving order of the instructions. 6. The method of claim 5, wherein, 7. The method of claim 5, wherein, 8. The method of claim 5, wherein, 9. The method according to any one of claims 5 to 8, characterized in that,
Citation Information
Patent Citations
Dynamic tracking control
CN114253793A
High parallelism computing system and instruction scheduling method thereof
US20200004514A1