Goa circuit and display panel

Abstract

The application provides a GOA circuit and a display panel. The GOA circuit comprises a plurality of GOA units arranged in cascade, and each GOA unit comprises a pull-up control module, a pull-up module, a pull-down module and a pull-down maintenance module. The pull-up module is configured to output a scanning signal at a first node, a second node and a first level signal end, under the control of the potential of the first node, the potential of the second node and the potential of the first level signal end. Compared with the existing GOA circuit, the GOA circuit of the application sets the potential of the first level signal end to be less than the potential of the second level signal end, so that the pull-up module can be completely closed when the scanning signal is not output, the stability of the GOA circuit is improved, the GOA circuit is prevented from failing, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a GOA circuit and a display panel. Background Technology

[0002] Gate Driver On Array (GOA) technology integrates the gate driver circuitry onto the array substrate of the display panel to achieve line-by-line scanning. This technology eliminates the need for a gate driver, offering advantages such as reduced production costs and the ability to achieve narrow bezel designs.

[0003] However, existing GOA circuits are prone to malfunction, which can cause abnormal display on the display panel. Summary of the Invention

[0004] This application provides a GOA circuit and a display panel, which can solve the technical problem that the display panel displays abnormally because the GOA circuit is prone to functional failure.

[0005] In a first aspect, this application provides a GOA circuit, including multiple cascaded GOA units, wherein the GOA unit includes a pull-up control module, a pull-up module, a pull-down module, and a pull-down sustaining module;

[0006] The pull-up control module is electrically connected to the first node, and the pull-up control module is used to control the potential of the first node;

[0007] The pull-up module is electrically connected to the first node, the second node, the current level scan signal output terminal, and the first level signal terminal. The pull-up module is used to output a scan signal at the current level scan signal output terminal under the potential control of the first node, the potential control of the second node, and the potential control of the first level signal terminal.

[0008] The pull-down module is electrically connected to the first node, the current-level scan signal output terminal, and the second-level signal terminal. The pull-down module is used to pull down the potential of the first node and the current-level scan signal output terminal to the potential of the second-level signal terminal.

[0009] The pull-down sustaining module is electrically connected to the first node, the second node, the current-level scan signal output terminal, and the second-level signal terminal. The pull-down sustaining module is used to maintain the potential of the first node and the potential of the current-level scan signal output terminal at the potential of the second-level signal terminal, and to control the potential of the second node; wherein,

[0010] The potential of the first level signal terminal is less than the potential of the second level signal terminal.

[0011] In the GOA circuit provided in this application, the pull-up control module includes a pull-up control transistor and a capacitor;

[0012] The gate of the pull-up control transistor is electrically connected to the signal output terminal of the previous stage, the source of the pull-up control transistor is electrically connected to the scan signal output terminal of the previous stage, and the drain of the pull-up control transistor is electrically connected to the first node.

[0013] The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output terminal of the scanning signal of this stage.

[0014] In the GOA circuit provided in this application, the pull-up module includes a first pull-up transistor and a second pull-up transistor;

[0015] The first gate of the first pull-up transistor is electrically connected to the first node, the source of the first pull-up transistor is electrically connected to the clock signal terminal, and the drain of the first pull-up transistor is electrically connected to the scan signal output terminal of the current stage.

[0016] The gate of the second pull-up transistor is electrically connected to the second node, the source of the second pull-up transistor is electrically connected to the first level signal terminal, and the drain of the second pull-up transistor is electrically connected to the second gate of the first pull-up transistor.

[0017] In the GOA circuit provided in this application, the potential output from the first level signal terminal is adjustable.

[0018] In the GOA circuit provided in this application, the first gate is one of the top gate and the bottom gate, and the second gate is the other of the top gate and the bottom gate.

[0019] In the GOA circuit provided in this application, the pull-down module includes a first pull-down transistor and a second pull-down transistor;

[0020] The gates of the first pull-down transistor and the second pull-down transistor are both electrically connected to the next-level scan signal terminal, and the sources of the first pull-down transistor and the second pull-down transistor are both electrically connected to the second level signal terminal.

[0021] The drain of the first pull-down transistor is electrically connected to the first node, and the drain of the second pull-down transistor is electrically connected to the output terminal of the scan signal of this stage.

[0022] In the GOA circuit provided in this application, the pull-down sustaining module includes an inverter, a first pull-down sustaining transistor, and a second pull-down sustaining transistor;

[0023] The input terminal of the inverter is electrically connected to the first node, and the output terminal of the inverter is electrically connected to the gate of the first pull-down sustaining transistor, the gate of the second pull-down sustaining transistor, and the second node.

[0024] The source of both the first pull-down sustaining transistor and the source of the second pull-down sustaining transistor are electrically connected to the second level signal terminal;

[0025] The drain of the first pull-down sustaining transistor is electrically connected to the first node, and the drain of the second pull-down sustaining transistor is electrically connected to the output terminal of the scan signal of this stage.

[0026] In the GOA circuit provided in this application, the GOA unit further includes a cascading module. The cascading module is electrically connected to the first node and the cascading signal terminal of the current stage. The cascading module is used to output the cascading signal of the current stage at the cascading signal terminal under the potential control of the first node.

[0027] In the GOA circuit provided in this application, the stage transmission module includes a stage transmission transistor, the gate of the stage transmission transistor is electrically connected to the first node, the source of the stage transmission transistor is electrically connected to the clock signal terminal, and the drain of the stage transmission transistor is electrically connected to the stage transmission signal terminal.

[0028] Secondly, this application also provides a display panel that includes the GOA circuit described above.

[0029] This application provides a GOA circuit and a display panel. The GOA circuit includes multiple cascaded GOA units, each GOA unit comprising a pull-up control module, a pull-up module, a pull-down module, and a pull-down sustaining module. The pull-up module outputs a scan signal at the output terminal of its current scan level under the potential control of a first node, a second node, and a first-level signal terminal. Compared to existing GOA circuits, the GOA circuit of this application, by setting the potential of the first-level signal terminal to be lower than the potential of the second-level signal terminal, allows the pull-up module to be completely turned off when not outputting a scan signal, thus improving the stability of the GOA circuit, preventing GOA circuit malfunction, and enhancing the display effect of the display panel. Attached Figure Description

[0030] Figure 1 A schematic diagram of a first structure of a GOA unit in a GOA circuit provided in an embodiment of this application;

[0031] Figure 2 for Figure 1 The circuit diagram of the pull-up control module in the GOA unit shown;

[0032] Figure 3 for Figure 1 The circuit diagram of the pull-up module in the GOA unit is shown below;

[0033] Figure 4 for Figure 1 The circuit diagram of the pull-down module in the GOA unit shown;

[0034] Figure 5 for Figure 1 The circuit diagram of the pull-down sustaining module in the GOA unit shown;

[0035] Figure 6 for Figure 1 The complete circuit diagram of the GOA unit is shown below;

[0036] Figure 7 for Figure 6 The timing diagram of the complete circuit of the GOA unit shown;

[0037] Figure 8 This is a schematic diagram of a second structure of the GOA unit provided in an embodiment of this application;

[0038] Figure 9 for Figure 8 The circuit diagram of the intermediate transmission module in the GOA unit is shown below;

[0039] Figure 10 This is a schematic diagram of a display panel provided in an embodiment of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0042] This application provides a GOA circuit and a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application.

[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of a first structure of a GOA unit in a GOA circuit provided in an embodiment of this application. For example... Figure 1As shown in the embodiment of this application, the GOA circuit includes multiple cascaded GOA units 100. The GOA unit 100 includes a pull-up control module 101, a pull-up module 102, a pull-down module 103, and a pull-down maintenance module 104.

[0044] Pull-up control module 101 is electrically connected to the first node Q. Pull-up control module 101 controls the potential of the first node Q. Pull-up module 102 is electrically connected to the first node Q, the second node F, the current scan signal output terminal G(N), and the first level signal terminal VSS2. Pull-up module 102 outputs a scan signal at the current scan signal output terminal G(N) under the potential control of the first node Q, the second node F, and the first level signal terminal VSS2. Pull-down module 103 is electrically connected to the first node Q, the current scan signal output terminal G(N), and the second level signal terminal VSS1. Pull-down module 103 pulls down the potential of the first node Q and the current scan signal output terminal G(N) to the potential of the second level signal terminal VSS1. Pull-down sustaining module 104 is electrically connected to the first node Q, the second node F, the current scan signal output terminal G(N), and the second level signal terminal VSS1. The pull-down sustaining module 104 is used to maintain the potential of the first node Q and the potential of the current scan signal output terminal G(N) at the potential of the second level signal terminal VSS1, and control the potential of the second node F.

[0045] In this embodiment, the potential of the first level signal terminal VSS2 is lower than the potential of the second level signal terminal VSS1. Compared to existing GOA circuits, the GOA circuit in this application improves the stability of the GOA circuit and prevents GOA circuit malfunction by setting the potential of the first level signal terminal VSS2 to be lower than the potential of the second level signal terminal VSS1.

[0046] For details, please refer to Figure 2 , Figure 2 for Figure 1 The circuit diagram of the pull-up control module in the GOA unit is shown below. Figure 2 As shown, the pull-up control module 101 includes a pull-up control transistor T11 and a capacitor Cbt.

[0047] In this circuit, the gate of the pull-up control transistor T11 is electrically connected to the signal output terminal ST(N-1) of the previous stage. The source of the pull-up control transistor T11 is electrically connected to the scan signal output terminal G(N-1) of the previous stage. The drain of the pull-up control transistor T11 is electrically connected to the first node Q. The first terminal of the capacitor Cbt is electrically connected to the first node Q. The second terminal of the capacitor Cbt is electrically connected to the scan signal output terminal G(N) of this stage.

[0048] For details, please refer to Figure 3 , Figure 3 for Figure 1 The circuit diagram of the pull-up module in the GOA unit is shown below. Figure 3 As shown, the pull-up module 102 includes a first pull-up transistor T21 and a second pull-up transistor T51.

[0049] In this configuration, the first gate of the first pull-up transistor T21 is electrically connected to the first node Q. The source of the first pull-up transistor T21 is electrically connected to the clock signal terminal CK1. The drain of the first pull-up transistor T21 is electrically connected to the scan signal output terminal G(N) of this stage. The gate of the second pull-up transistor T51 is electrically connected to the second node F. The source of the second pull-up transistor T51 is electrically connected to the first level signal terminal VSS2. The drain of the second pull-up transistor T51 is electrically connected to the second gate of the first pull-up transistor T21.

[0050] In some embodiments, the potential output by the first level signal terminal VSS2 can be set to a certain value. In other embodiments, the potential output by the first level signal terminal VSS2 is adjustable; that is, in the embodiments of this application, the potential output by the first level signal terminal VSS2 can be adjusted in real time by detecting the potential output by the second level signal terminal VSS1, thereby avoiding the potential output by the first level signal terminal VSS2 from being greater than the potential output by the second level signal terminal VSS1 due to changes in the potential output by the second level signal terminal VSS1.

[0051] In some embodiments, the first gate is a top gate and the second gate is a bottom gate. In other embodiments, the first gate is a bottom gate and the second gate is a top gate. That is, the first gate is one of the top gate and the bottom gate, and the second gate is the other of the top gate and the bottom gate.

[0052] For details, please refer to Figure 4 , Figure 4 for Figure 1 The circuit diagram of the pull-down module in the GOA unit is shown below. Figure 4 As shown, the pull-down module 103 includes a first pull-down transistor T41 and a second pull-down transistor T31.

[0053] In this circuit, the gates of both the first pull-down transistor T41 and the second pull-down transistor T31 are electrically connected to the next-stage scan signal terminal G(N+1). The sources of both the first pull-down transistor T41 and the second pull-down transistor T31 are electrically connected to the second-level signal terminal VSS1. The drain of the first pull-down transistor T41 is electrically connected to the first node Q. The drain of the second pull-down transistor T31 is electrically connected to the current-stage scan signal output terminal G(N).

[0054] For details, please refer to Figure 5 , Figure 5 for Figure 1 The circuit diagram of the pull-down sustaining module in the GOA unit is shown below. Figure 5 As shown, the pull-down sustaining module 104 includes an inverter M, a first pull-down sustaining transistor T42, and a second pull-down sustaining transistor T32.

[0055] In this circuit, the input terminal of inverter M is electrically connected to the first node Q. The output terminal of inverter M is electrically connected to the gate of the first pull-down sustaining transistor T42, the gate of the second pull-down sustaining transistor T32, and the second node F. The sources of both the first pull-down sustaining transistor T42 and the second pull-down sustaining transistor T32 are electrically connected to the second level signal terminal VSS1. The drain of the first pull-down sustaining transistor T42 is electrically connected to the first node Q. The drain of the second pull-down sustaining transistor T32 is electrically connected to the scan signal output terminal G(N) of this stage.

[0056] It should be noted that, Figure 2 , Figure 3 , Figure 4 as well as Figure 5 The circuit diagrams of the various modules shown are merely one embodiment provided in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0057] The following will combine Figure 6 The complete circuit diagram shown is described in detail. Figure 6 for Figure 1 The complete circuit diagram of the GOA unit is shown.

[0058] in, Figure 6 The pull-up control module in the GOA unit shown is equivalent to Figure 2 The pull-up control module in the GOA unit shown. Figure 6 The pull-up module in the GOA unit shown is equivalent to Figure 3 The pull-up module in the GOA unit shown. Figure 6 The dropdown module in the GOA unit shown is equivalent to Figure 4 The dropdown module in the GOA unit shown. Figure 6 The pull-down sustaining module in the GOA unit shown is equivalent to Figure 5 The pull-down sustaining module in the GOA unit shown.

[0059] Among them, Figure 6 In the GOA unit shown, the pull-up control transistor T11, the first pull-up transistor T21, the second pull-up transistor T51, the first pull-down transistor T41, the second pull-down transistor T31, the first pull-down sustaining transistor T42, and the second pull-down sustaining transistor T32 are all N-type transistors.

[0060] Please see Figure 7 , Figure 7 for Figure 6 The timing diagram of the complete circuit of the GOA unit is shown. (Combined with...) Figure 6 , Figure 7 As shown, in the first stage t1, the previous stage scan signal output terminal G(N-1) outputs a high level, and the previous stage transmission signal output terminal ST(N-1) outputs a high level, thereby controlling the pull-up control crystal T11 to turn on, and the potential of the first node Q is pre-charged to a high potential. At this time, the potential of the first gate of the first pull-up transistor T21 is the potential of the first node Q, and the second gate of the first pull-up transistor T21 is floating, that is, no signal is connected to the second gate of the first pull-up transistor T21 at this time, and the first pull-up transistor T21 is turned on. At the same time, the clock signal terminal CK1 outputs a low potential. Since the first pull-up transistor T21 is turned on, the current stage scan signal output terminal G(N) outputs the low potential of the clock signal terminal CK1 at this time.

[0061] In the second stage t2, the clock signal terminal CK1 outputs a high potential. Due to the effect of capacitor Cbt, the potential of the first node Q rises to a higher potential. At this time, the first pull-up transistor T21 continues to be turned on, and the scan signal output terminal G(N) of this stage outputs the high potential of the clock signal terminal CK1.

[0062] In the third stage t3, the next-stage scan signal output terminal G(N+1) outputs a high potential, causing the first pull-down transistor T41 and the second pull-down transistor T31 to turn on. The low potential of the second-level signal terminal VSS1 is output to the first node Q and the current-stage scan signal output terminal G(N). At the same time, the low potential of the first node Q, after passing through the inverter M, makes the potential of the second node F high. At this time, the second pull-up transistor T51 turns on, and the potential of the first-level signal terminal VSS2 is output to the second gate of the first pull-up transistor T21. That is, the second gate of the first pull-up transistor T21 is pulled down to a potential lower than the potential of the second-level signal output terminal VSS1.

[0063] For the first pull-up transistor T21, the potential of the first gate and the potential of the drain of the first pull-up transistor T21 are both the potential of the second level signal terminal VSS1, and the potential of the second gate of the first pull-up transistor T21 is the potential of the first level signal terminal VSS2. This allows the first pull-up transistor T21 to be completely turned off, preventing the GOA circuit from failing when the transistor is negatively biased.

[0064] Please see Figure 8 , Figure 8 This is a schematic diagram of a second structure of the GOA unit provided in an embodiment of this application. Figure 8The GOA unit shown is Figure 1 The difference between the GOA units shown is: Figure 8 The GOA unit shown also includes a cascading module 105.

[0065] The cascade module 105 is electrically connected to the first node Q and the cascade signal terminal ST(N) of this stage. The cascade module 105 is used to output the cascade signal of this stage at the cascade signal terminal ST(N) under the potential control of the first node Q.

[0066] For details, please refer to Figure 9 , Figure 9 for Figure 8 The circuit diagram of the intermediate transmission module in the GOA unit is shown below. Figure 9 As shown, the stage transmission module 105 includes a stage transmission transistor T22. The gate of the stage transmission transistor T22 is electrically connected to the first node Q, the source of the stage transmission transistor T22 is electrically connected to the clock signal terminal CK1, and the drain of the stage transmission transistor T22 is electrically connected to the stage transmission signal terminal ST(N).

[0067] Accordingly, this application also provides a display panel that includes the GOA circuit described above. For details, please refer to [link to relevant documentation]. Figure 10 , Figure 10 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 10 As shown, the display panel 1000 includes a display area AA and a non-display area NA connected to the display area AA. A GOA circuit 200 is integrated into the non-display area NA. The structure and principle of this GOA circuit 200 are similar to those of the GOA circuit described above, and will not be repeated here. It should be noted that the display panel 1000 provided in this application is described using a single-sided driving method where the GOA circuit 200 is located on one side of the display area AA, but this should not be construed as a limitation of this application. In some embodiments, dual-sided driving or other driving methods may be used according to the actual needs of the display panel 1000, and this application provides specific limitations in this regard.

[0068] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application, and are not intended to limit the patent scope of this application. Any equivalent structural or procedural transformations made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A GOA circuit, characterized in that, include: Multiple cascaded GOA units, each GOA unit including a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintenance module; The pull-up control module is electrically connected to the first node, and the pull-up control module is used to control the potential of the first node; The pull-up module is electrically connected to the first node, the second node, the current level scan signal output terminal, and the first level signal terminal. The pull-up module is used to output a scan signal at the current level scan signal output terminal under the potential control of the first node, the potential control of the second node, and the potential control of the first level signal terminal. The pull-down module is electrically connected to the first node, the local scan signal output terminal, and the second level signal terminal. The pull-down module is used to pull down the potential of the first node and the potential of the local scan signal output terminal to the potential of the second level signal terminal. as well as The pull-down sustaining module is electrically connected to the first node, the second node, the current level scan signal output terminal, and the second level signal terminal. The pull-down sustaining module is used to maintain the potential of the first node and the potential of the current level scan signal output terminal at the potential of the second level signal terminal, and to control the potential of the second node. The pull-down sustaining module includes an inverter, a first pull-down sustaining transistor, and a second pull-down sustaining transistor; The input terminal of the inverter is electrically connected to the first node, and the output terminal of the inverter is electrically connected to the gate of the first pull-down sustaining transistor, the gate of the second pull-down sustaining transistor, and the second node. The source of both the first pull-down sustaining transistor and the source of the second pull-down sustaining transistor are electrically connected to the second level signal terminal; The drain of the first pull-down sustaining transistor is electrically connected to the first node, and the drain of the second pull-down sustaining transistor is electrically connected to the output terminal of the scan signal of this stage. Wherein, the potential of the first level signal terminal is less than the potential of the second level signal terminal.

2. The GOA circuit according to claim 1, characterized in that, The pull-up control module includes a pull-up control transistor and a capacitor; For the GOA units other than the first-level GOA unit in the multiple cascaded GOA units, the gate of the pull-up control transistor is electrically connected to the signal output terminal of the previous level, the source of the pull-up control transistor is electrically connected to the scan signal output terminal of the previous level, and the drain of the pull-up control transistor is electrically connected to the first node. The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output terminal of the scanning signal of this stage.

3. The GOA circuit according to claim 1, characterized in that, The pull-up module includes a first pull-up transistor and a second pull-up transistor; The first gate of the first pull-up transistor is electrically connected to the first node, the source of the first pull-up transistor is electrically connected to the clock signal terminal, and the drain of the first pull-up transistor is electrically connected to the scan signal output terminal of the current stage. The gate of the second pull-up transistor is electrically connected to the second node, the source of the second pull-up transistor is electrically connected to the first level signal terminal, and the drain of the second pull-up transistor is electrically connected to the second gate of the first pull-up transistor.

4. The GOA circuit according to claim 3, characterized in that, The potential output from the first level signal terminal is adjustable.

5. The GOA circuit according to claim 3, characterized in that, The first gate is one of the top gate and the bottom gate, and the second gate is the other of the top gate and the bottom gate.

6. The GOA circuit according to claim 1, characterized in that, The pull-down module includes a first pull-down transistor and a second pull-down transistor; For all GOA units except the last GOA unit in a cascaded configuration, the gate of the first pull-down transistor and the gate of the second pull-down transistor are electrically connected to the next level scan signal terminal, and the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected to the second level signal terminal. The drain of the first pull-down transistor is electrically connected to the first node, and the drain of the second pull-down transistor is electrically connected to the output terminal of the scan signal of this stage.

7. The GOA circuit according to any one of claims 1-6, characterized in that, The GOA unit also includes a transmission module, which is electrically connected to the first node and the transmission signal terminal of the current level. The transmission module is used to output the transmission signal of the current level at the transmission signal terminal under the potential control of the first node.

8. The GOA circuit according to claim 7, characterized in that, The cascading module includes a cascading transistor, the gate of which is electrically connected to the first node, the source of which is electrically connected to a clock signal terminal, and the drain of which is electrically connected to the cascading signal terminal of the current stage.

9. A display panel, characterized in that, Includes the GOA circuit as described in any one of claims 1-8.

Images