Display panel and manufacturing method thereof

Abstract

Embodiments of the present application provide a display panel and a preparation method thereof. The display panel comprises a first thin film transistor and a second thin film transistor which are located in a display area and electrically connected, and an etching stop layer located in a binding area, the etching stop layer being located in the same layer as a first active layer in the first thin film transistor. The display panel further comprises an etching stop layer and a first deep hole arranged between the binding area and the second thin film transistor, a metal layer being filled in the first deep hole and connected with a metal shielding layer. Since the etching efficiency of the etching stop layer is less than the etching efficiency of the original inorganic layer under the same etching condition, the etching depth in the vertical direction is reduced, and the first deep hole connected with the metal shielding layer is prevented from being over-etched.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel and its manufacturing method. Background Technology

[0002] Currently, in the display panel field, Organic Light-Emitting Diode (OLED) has seen significant development in order to achieve high-response, high-contrast, and high-brightness screen displays. However, with the development of wearable devices and wearable displays, and given the lack of significant breakthroughs in battery technology, the power consumption requirements for display devices are increasing. Low-temperature polycrystalline silicon (LTPO) technology, currently used to drive and switch thin-film transistors, is a mainstream trend due to its low power consumption. However, due to the high carrier mobility of LTPO, it suffers from high leakage current. Therefore, Low-Temperature Polycrystalline-Si Oxide (LTPO) technology has emerged. It combines the advantages of both LTPO and oxide technologies, forming an LTPO solution with fast response and lower power consumption.

[0003] However, during the fabrication of LTPO display panels, the use of different materials for different film layers can lead to over-etching of some film layers, thus affecting the stability of the entire display panel. Summary of the Invention

[0004] This invention provides a display panel designed to address the problem of over-etching during the manufacturing process of existing display panels, which affects the stability of the display panel.

[0005] To address the aforementioned problems, in a first aspect, this application provides a display panel, the display panel comprising:

[0006] A substrate, the substrate comprising a substrate and a metal shielding layer stacked together;

[0007] A thin-film transistor layer is disposed above the metal shielding layer, and the thin-film transistor layer includes a first thin-film transistor located in the display area and a second thin-film transistor electrically connected to the first thin-film transistor; the first thin-film transistor includes a first active layer and a first source-drain layer located above the metal shielding layer, and the first source-drain layer is connected to the first active layer through a first via.

[0008] The second thin-film transistor includes a second active layer and a second source-drain layer located above the metal shielding layer. The second source-drain layer is connected to the first active layer through a second via, and the second source-drain layer is connected to the second active layer through a third via.

[0009] The display panel further includes an etch barrier layer and a first deep hole disposed between the bonding area and the second thin film transistor. The etch barrier layer is located above the metal shielding layer. The first deep hole penetrates the thin film transistor layer and the etch barrier layer, and the first deep hole partially penetrates the substrate. A metal layer is formed in the first deep hole, and the metal layer is electrically connected to the metal shielding layer through the first deep hole.

[0010] In some possible embodiments, the etch barrier layer is located above the buffer layer and in the same layer as the first active layer, and the etch barrier layer and the first active layer are prepared simultaneously.

[0011] In some possible embodiments, the first deep hole is a stepped structure, the first deep hole includes a first sub-via and a second sub-via, the second sub-via is located below the first sub-via, and the diameter of the second sub-via is smaller than the diameter of the first sub-via.

[0012] In some possible embodiments, the substrate further includes:

[0013] A first buffer layer is disposed above the metal shielding layer and completely covers the metal shielding layer;

[0014] A second buffer layer is disposed above the first buffer layer and completely covers the first buffer layer;

[0015] In this configuration, the first sub-via transforms into the second sub-via within the first buffer layer. The bottom of the first sub-via is located within the first buffer layer, and the top of the second sub-via is located within the first buffer layer and is in direct contact with the bottom of the first sub-via.

[0016] In some possible embodiments, the display panel further includes a second deep hole located in the bonding area. The second deep hole has a stepped structure and includes a third sub-via and a fourth sub-via. The fourth sub-via is located below the third sub-via, and the diameter of the fourth sub-via is smaller than the diameter of the third sub-via.

[0017] The third sub-via is transformed into the fourth sub-via in the first buffer layer. The bottom of the third sub-via is located in the first buffer layer, and the top of the fourth sub-via is located in the first buffer layer and is in direct contact with the bottom of the third sub-via.

[0018] In some possible embodiments, the distance between the bottom of the first sub-via and the side of the etch barrier layer near the substrate is less than the distance between the bottom of the third sub-via and the side of the etch barrier layer near the substrate.

[0019] In some possible embodiments, the bottom of the first deep hole is located in the metal shielding layer, and the bottom of the second deep hole is located in the substrate.

[0020] Secondly, embodiments of this application also provide a method for manufacturing a display panel, the method comprising:

[0021] A substrate is provided, the substrate comprising a substrate and a metal shielding layer stacked together;

[0022] A separate first active layer and an etch barrier layer are fabricated above the substrate, wherein the first active layer and the etch barrier layer are located in the same layer;

[0023] A first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third gate layer, a first interlayer dielectric layer, a second active layer, a third insulating layer, a fourth gate layer, and a second interlayer dielectric layer are sequentially formed above the first active layer and the etch barrier layer.

[0024] The first etching operation is performed to obtain a first via and a second via that are in contact with the first active layer, a third via that is in contact with the second active layer, a first sub-via that penetrates the etch barrier layer, and a third sub-via located in the bonding area.

[0025] The first sub-via and the third sub-via are etched a second time to obtain a first deep hole and a second deep hole. The bottom of the first deep hole is located in the metal shielding layer, and the bottom of the second deep hole is located in the substrate.

[0026] In some possible embodiments, the method further includes:

[0027] Metal material is filled into the first via, the second via, the third via, and the first deep hole to obtain a first source-drain layer, a second source-drain layer, and a metal layer.

[0028] A first planarization layer is prepared above the first source-drain layer, the second source-drain layer, and the metal layer, and the material of the first planarization layer fills the interior and the top of the second deep hole.

[0029] Beneficial Effects: This application provides a display panel and its fabrication method. The display panel includes a first thin-film transistor and a second thin-film transistor located in the display area and electrically connected, and an etch barrier layer located in the bonding area. The etch barrier layer and the first active layer in the first thin-film transistor are located in the same layer. The display panel also includes an etch barrier layer and a first deep hole disposed between the bonding area and the second thin-film transistor. A metal layer fills the interior of the first deep hole and is connected to a metal shielding layer. Because the etch barrier layer has a lower etching efficiency than the original inorganic layer under the same etching conditions, the etching depth in the vertical direction is reduced, avoiding over-etching of the first deep hole connected to the metal shielding layer. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0032] Figure 2 This application provides a schematic diagram of the structure of the first deep hole and the second deep hole in an embodiment of the present application.

[0033] Figures 3-7 A schematic diagram of the film structure corresponding to the fabrication process of the display panel provided in the embodiments of this application;

[0034] Figure 8 This is a schematic flowchart of an embodiment of the method for manufacturing a display panel provided in this application. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0038] This invention provides a display panel and a method for manufacturing the same. These will be described in detail below.

[0039] like Figure 1 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application. Figure 1 The display panel includes a display area and a bonding area; vertically, it also includes a substrate 10 and a thin-film transistor layer 20 disposed above the substrate 10. The substrate 10 may include a substrate 101 and a metal shielding layer 102 disposed above it. In one specific embodiment, the substrate 101 may be a glass substrate; and the metal shielding layer may be made of materials such as molybdenum (Mo) or aluminum (Al). The metal shielding layer 102 at the bottom of the display panel can shield against static electricity within the panel, preventing interference with the display image.

[0040] exist Figure 1In this process, the substrate may further include a first buffer layer 103 disposed above the metal shielding layer 102, and a second buffer layer 104 disposed above the first buffer layer 103. Please refer to [reference needed]. Figure 1 The metal shielding layer 102 typically does not directly contact the substrate 101, but is instead disposed within the first buffer layer 103, which completely covers the metal shielding layer 102. The first buffer layer is positioned between the substrate 101 and the second buffer layer 104, primarily to increase the adhesion between the second buffer layer 104 and the substrate 101; on the other hand, it shields the metal shielding layer 103, preventing the metal shielding layer 102 from affecting the crystallization of the active layer material. In some embodiments, the first buffer layer 103 can be a multilayer structure; the specific structure can be configured according to actual needs and is not limited in this application.

[0041] Please refer to Figure 1 A thin-film transistor layer 20 is disposed above the metal shielding layer 102, and the thin-film transistor layer 20 includes a first thin-film transistor located in the display area and a second thin-film transistor electrically connected to the first thin-film transistor. The first thin-film transistor includes a first active layer 111 and a first source-drain layer 112 located above the metal shielding layer 102 (or the second buffer layer 104). The first source-drain layer 112 fills the interior of the first via 131, such that the first source-drain layer 112 is connected to the buffer layer 104 through the first via 131.

[0042] The second thin-film transistor also includes a second active layer 121 and a second source-drain layer 122 located above the metal shielding layer 102 (or the second buffer layer 104). The second source-drain layer 122 is connected to the first active layer 111 through a second via 132, and is also connected to the second active layer 121 through a third via 133.

[0043] Please refer to Figure 1 ,exist Figure 1 In the illustrated embodiment, a first active layer 111 is formed above the substrate, and a second active layer 121 is not located in the same layer as the first active layer 111. The second source electrode in the second source-drain layer 122 simultaneously fills the second via 132 and the third via 133, so that the first thin-film transistor and the second thin-film transistor are electrically connected.

[0044] The first thin-film transistor further includes a first gate layer 113 disposed above the first active layer, and a second gate layer 114 disposed above the first gate layer 113; wherein the first gate layer 113 and the second gate layer 114 are disposed opposite to the first active layer 111. The display panel further includes a first insulating layer 30 disposed above the first active layer 111, the first insulating layer 30 completely covering the first active layer 111; the first gate layer 113 is disposed on the first insulating layer 30 at a position corresponding to the first active layer 111. A second insulating layer 40 is also disposed on the first gate layer 113, the second insulating layer 40 completely covering the first gate layer 113; and a second gate layer 114 is disposed above the second insulating layer 40 at a position corresponding to the first gate layer 113. A first interlayer dielectric layer 50 and a third insulating layer 60 are also sequentially fabricated from bottom to top above the second gate layer 114.

[0045] For the second thin-film transistor, the second active layer 121 of the second thin-film transistor is disposed above the first interlayer dielectric layer, and the first interlayer dielectric layer completely covers the second active layer 121. The second thin-film transistor includes a third gate layer 123 and a fourth gate layer 124; the third gate layer 123 is located in the same layer as the second gate layer 114 of the first thin-film transistor; and the second gate layer 114 and the third gate layer 123 are fabricated simultaneously using the same process.

[0046] Because the second active layer 121 of the second thin-film transistor is disposed above the first interlayer dielectric layer 50 and not on the same layer as the first active layer 111, a third insulating layer 60 needs to be fabricated above the second active layer 121 to protect it. Furthermore, the fourth gate layer 124 of the second thin-film transistor is fabricated above the third insulating layer 60, therefore a second interlayer dielectric layer 70 needs to be fabricated above the fourth gate layer 124 to protect it.

[0047] It should be noted that both the first and second thin-film transistors in this application have a dual-gate structure; however, both gates of the first thin-film transistor are disposed on one side of the first active layer 111, while the two gates of the second thin-film transistor are disposed on opposite sides of the second active layer 121. Furthermore, in this embodiment, the display panel also includes an etch stop layer 80 located on the same layer as the first active layer 111; the etch stop layer 80 is located between the bonding area of ​​the second thin-film transistor and the display panel. The etch stop layer 80 effectively prevents over-etching during subsequent etching processes, which will be explained in detail later in conjunction with the fabrication process of the display panel.

[0048] In a practical display panel, the metal shielding layer 102 needs to shield against static electricity inside the display panel and requires an external electrical signal to be supplied to the metal shielding layer 102. Therefore, a hole needs to be drilled and a metal layer 90 fabricated in a location independent of the first and second thin-film transistors to receive the external electrical signal. This metal layer 90 also needs to be in direct contact with the metal shielding layer 102. Figure 1 In the display panel, the first deep hole 134 is disposed between the second thin film transistor and the bonding area, and the bottom of the first deep hole 134 is in direct contact with the metal shielding layer 102.

[0049] exist Figure 1 In this embodiment, metal material is filled into the first deep hole 134 to form a metal layer 80 connected to the metal shielding layer 102. The overall depth h1 of the first deep hole is the distance between the opening of the first deep hole formed on the side of the second interlayer dielectric layer away from the substrate and the bottom of the first deep hole located inside the metal shielding layer 102. The display panel of this embodiment also includes a second deep hole 135 disposed in the bonding area. Unlike the first deep hole 134, the second deep hole 135 typically needs to be etched to the substrate. Specifically, the overall depth h2 of the second deep hole can be the distance between the opening of the second deep hole formed on the side of the second interlayer dielectric layer away from the substrate and the bottom of the second deep hole located inside the substrate.

[0050] like Figure 2 The diagram shown is a structural schematic of the first deep hole and the second deep hole provided in an embodiment of this application. Figure 2 As can be seen from the image, the first deep hole 134 has a stepped structure. The first deep hole 134 may include a first sub-via and a second sub-via, with the second sub-via located below the first sub-via and having a smaller diameter than the first sub-via.

[0051] In this embodiment, the substrate further includes a first buffer layer 103 and a second buffer layer 104. The second buffer layer 104 is disposed above the first buffer layer 103 and completely covers the first buffer layer. The first sub-via 104 transforms into a second sub-via in the second buffer layer 104, with the bottom of the first sub-via located within the second buffer layer 104 and the top of the second sub-via located within the second buffer layer 104 and in direct contact with the bottom of the first sub-via. The second deep hole 135 also has a stepped structure and includes a third sub-via and a fourth sub-via. The fourth sub-via is located below the third sub-via, and its diameter is smaller than that of the third sub-via. The third sub-via transforms into a fourth sub-via in the second buffer layer 104, with the bottom of the third sub-via located within the second buffer layer 104 and the top of the fourth sub-via located within the second buffer layer 104 and in direct contact with the bottom of the third sub-via.

[0052] Although both the first deep via 134 and the second deep via 135 in this application have stepped structures, the distance h3 between the bottom of the first sub-via and the side of the etch stop layer near the substrate is smaller than the distance h4 between the bottom of the third sub-via and the side of the etch stop layer near the substrate. That is, the depths of the first and third sub-vias are not the same. The following will describe this in detail with reference to the fabrication process of the display panel.

[0053] Figures 3-7 This is a schematic diagram of the film structure corresponding to the fabrication process of the display panel provided in the embodiments of this application. Figure 3 In the process, after obtaining the substrate 10, a separate first active layer 111 and an etch barrier layer 80 are fabricated on top of the substrate. For example... Figure 4 As shown, other thin-film transistor structures, such as gate layer, insulating layer, and interlayer dielectric layer, are then sequentially fabricated above the first active layer 111 and the etch barrier layer 80. Specific fabrication methods and processes can be found in existing technologies and are not limited here.

[0054] like Figure 4 After fabricating the second interlayer dielectric layer 70 that completely covers the fourth gate layer 124, it is necessary to fabricate the source and drain layers corresponding to the first and second thin-film transistors. At this point, the display panel structure needs to be etched for the first time to fabricate the first via, the second via, and the first sub-via. For example... Figure 5 As shown, the first via 131 needs to penetrate all the film layers above the first active layer 111; Figure 5 In this process, the first via 131 actually includes two vias located on the left and right sides of the first active layer 111, to respectively fabricate the source and drain of the first thin-film transistor.

[0055] In this application, the first via 131, the second via 132, and the third via 133 can be etched using the same photomask. Simultaneously with etching the first via 131, etching is also performed above the newly added etch barrier layer 80, forming a first sub-via above the etch barrier layer 80. At the same time, the display panel film layer located in the bonding area is etched to obtain the third sub-via located in the bonding area.

[0056] During the etching of the first via, the film layer that needs to be etched for the first via, the second sub-via, and the third sub-via is the same: the film layer between the second interlayer dielectric layer and the first insulating layer. This is because the source and drain electrodes of the first thin-film transistor need to be connected to the first active layer, and the film layer that needs to be etched to prepare the first via is the film layer between the second interlayer dielectric layer and the first insulating layer. Under the same etching conditions, the film layer that needs to be etched for the first sub-via and the third sub-via is the same as the film layer that needs to be etched for the first via.

[0057] However, during the actual etching of the first via, the first deep via, and the second deep via, over-etching is common. That is, due to process limitations, it's often impossible to guarantee that the bottom of the etched first via 131 is exactly above the first active layer 111. Therefore, the first via 131 is usually etched through the first active layer, so that the bottom of the first via 131 reaches the buffer layer in the substrate. The first source / drain in the first via forms a side contact with the first active layer, which also ensures the normal operation of the first thin-film transistor. The bottoms of the first sub-via and the third sub-via are also located inside the second buffer layer 104.

[0058] Since the newly added etch barrier layer and the first active layer are located in the same layer, the etch barrier layer 80 is also etched during the etching process to obtain the first sub-via. However, during the etching process to obtain the third sub-via, neither the first active layer nor the etch barrier layer exists; only all the film layers between the first insulating layer and the second interlayer dielectric layer are required. Therefore, under the same etching conditions, the etching process for the first sub-via requires additional etching of the etch barrier layer, while the third sub-via does not require etching of either the etch barrier layer or the first active layer. Consequently, under the same etching conditions, the depth h3 of the first sub-via embedded in the second buffer layer 104 is less than the depth h4 of the second sub-via embedded in the second buffer layer 103. In one specific embodiment, the depth h3... h4 depth is

[0059] In the embodiments of this application, the first active layer and the etch barrier layer are typically fabricated simultaneously using the same process flow, which reduces the fabrication steps; and the materials of the first active layer and the etch barrier layer are usually the same. The etching rate of the etch barrier layer is typically lower than the etching efficiency of the insulating layer and the interlayer dielectric layer. Since the etch barrier layer needs to be etched additionally when fabricating the first sub-via, while no etch barrier layer is present when fabricating the third sub-via, the depth of the first sub-via is typically less than the depth of the third sub-via under the same etching conditions. Since the first sub-via requires etching of the etch barrier layer, and the first via requires etching of the first active layer of the same material, the depth of the first via and the depth of the first sub-via are typically the same under the same etching conditions.

[0060] Although the bottoms of the first via, the first sub-via, and the third sub-via are all inside the second buffer layer, the depths of the first sub-via and the third sub-via inside the second buffer layer are different, while the depths of the first via and the first sub-via inside the second buffer layer are the same.

[0061] It should be noted that in the above embodiment, during the etching of the first via, a third via 133 located between the first thin-film transistor and the second thin-film transistor is also etched. The third via 133 also penetrates the first active layer 111, and the bottom of the third via 133 is also located in the second buffer layer 104.

[0062] Please refer to Figure 6 After etching to obtain the first via, the first sub-via, and the third sub-via, it is necessary to etch to obtain the second via of the second thin-film transistor. At this time, the film layer above the second active layer is also etched using a photomask to obtain the second via located on the left and right sides of the second active layer.

[0063] Since the first sub-via obtained by etching is not connected to the metal shielding layer, a second etching is required for the other film layers below the first sub-via. Similarly, the third sub-via located in the bonding region is not etched to the substrate, therefore a second etching is also required for the film layers below the third sub-via. Figure 6 As shown, the second buffer layer below the first sub-via is then etched to obtain the second sub-via. Typically, the bottom of the second sub-via can be located on the upper surface of the metal shielding layer away from the substrate, so that the metal layer inside the second sub-via is in contact with the metal shielding layer. However, due to process limitations, the etching precision cannot be well controlled. Therefore, in actual etching, the bottom of the second via is usually controlled to be inside the metal shielding layer, meaning the second sub-via is partially embedded in the metal shielding layer. For example... Figure 2 As shown, the depth of the second sub-via can be: from the transition point where the first sub-via transforms into the second sub-via in the second buffer layer to the bottom of the portion of the second sub-via embedded in the metal shielding layer. The depth h5 of the portion of the second sub-via embedded in the metal shielding layer can be...

[0064] Similarly, when etching the other film layers below the third sub-via to obtain the fourth sub-via, the bottom of the fourth sub-via is also embedded in the substrate, rather than just reaching the top surface of the substrate. The depth of the fourth sub-via can be: from the transition point in the second buffer layer where the third sub-via transforms into the fourth sub-via, to the bottom of the portion of the fourth sub-via embedded in the substrate. The depth h6 of the portion of the fourth sub-via embedded in the substrate can be...

[0065] like Figure 7 As shown, the first deep hole 134 and the second deep hole 135 obtained by the final etching are both stepped structures. The diameter of the first sub-via is larger than that of the second sub-via, and the diameter of the third sub-via is larger than that of the fourth sub-via. The bottom of the first deep hole is located inside the metal shielding layer 102, and the bottom of the second deep hole is located inside the substrate 101.

[0066] In this application, multiple different vias can be etched simultaneously to save the number of times the photomask is used and the exposure etching process, thereby simplifying the manufacturing process of the display panel and reducing production costs. Although the first deep via 134 is still ultimately embedded in the metal shielding layer in this application, i.e., over-etching occurs, compared with the prior art, by setting an etching barrier layer 80 independent of the first active layer 111 on the same film layer where the first active layer 111 is located, the depth of over-etching is reduced; this avoids the problem that the metal layer 90 electrically connected to the metal shielding layer 102 will affect the electrical bonding of the display panel due to the deep over-etching of the first deep via 134.

[0067] After etching, metal material needs to be filled into the first via, the second via, and the third via to prepare the source / drain layers of the first thin-film transistor and the second thin-film transistor. Simultaneously, metal material is filled into the first deep hole to form a metal layer electrically connected to the metal shielding layer. A first planarization layer needs to be prepared above the source / drain layers and the metal layer, and the material of the first planarization layer fills the interior of the second deep hole. Other film layers of the display panel, such as pixel electrode layers, need to be prepared above the first planarization layer and then encapsulated to obtain the display panel provided in this embodiment. The preparation methods for different film layers of the display panel can refer to existing technologies and are not limited here.

[0068] This application also discloses a method for manufacturing a display panel, such as... Figure 8 As shown, it may include:

[0069] 81. A substrate is provided, the substrate comprising a substrate and a metal shielding layer stacked together.

[0070] 82. An independent first active layer and an etch barrier layer are prepared above a substrate, wherein the first active layer and the etch barrier layer are located in the same layer.

[0071] 83. A first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third gate layer, a first interlayer dielectric layer, a second active layer, a third insulating layer, a fourth gate layer, and a second interlayer dielectric layer are sequentially formed above the first active layer and the etch barrier layer.

[0072] 84. Perform the first etching operation to obtain the first via and the second via that are in contact with the first active layer, the third via that is in contact with the second active layer, the first sub-via that penetrates the etch barrier layer, and the third sub-via located in the bonding area.

[0073] 85. Perform secondary etching on the first sub-via and the third sub-via to obtain the first deep hole and the second deep hole. The bottom of the first deep hole is located in the metal shielding layer, and the bottom of the second deep hole is located in the substrate.

[0074] 86. Fill the first via, the second via, the third via, and the first deep hole with metal material to obtain the first source-drain layer, the second source-drain layer, and the metal layer.

[0075] 87. A first planarization layer is prepared above the first source-drain layer, the second source-drain layer, and the metal layer, and the material of the first planarization layer fills the interior and above the second deep hole.

[0076] The method for manufacturing the display panel provided in this application can produce a panel as follows: Figure 1 The display panel shown is described above, and the specific manufacturing process can be found in the aforementioned documentation. Figures 3-7 The description will not be repeated here.

[0077] This application also provides a display device, which includes a display panel as described in any of the preceding claims; the specific structure of the display panel can be referred to the foregoing content, and will not be repeated here.

[0078] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0079] In practice, each of the above units or structures can be implemented as an independent entity or can be arbitrarily combined to be implemented as the same or several entities. For the specific implementation of each of the above units or structures, please refer to the previous method embodiments, which will not be repeated here.

[0080] The above provides a detailed description of a display panel and its manufacturing method according to embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a binding area, and the display panel further includes: A substrate, the substrate comprising a substrate, a metal shielding layer, a first buffer layer and a second buffer layer stacked together; A thin-film transistor layer is disposed above the metal shielding layer, and the thin-film transistor layer includes a first thin-film transistor located in the display area and a second thin-film transistor electrically connected to the first thin-film transistor; the first thin-film transistor includes a first active layer and a first source-drain layer located above the metal shielding layer, and the first source-drain layer is connected to the first active layer through a first via. The second thin-film transistor includes a second active layer and a second source-drain layer located above the metal shielding layer. The second source-drain layer is connected to the first active layer through a second via, and the second source-drain layer is connected to the second active layer through a third via. The display panel further includes an etch barrier layer and a first deep hole disposed between the bonding area and the second thin film transistor. The etch barrier layer is located above the metal shielding layer. The first deep hole penetrates the thin film transistor layer and the etch barrier layer, and the first deep hole partially penetrates the substrate. A metal layer is formed in the first deep hole, and the metal layer is electrically connected to the metal shielding layer through the first deep hole.

2. The display panel according to claim 1, characterized in that, The etching barrier layer is located above the first buffer layer and in the same layer as the first active layer. The etching barrier layer and the first active layer are prepared simultaneously.

3. The display panel according to claim 1, characterized in that, The first deep hole has a stepped structure and includes a first sub-via and a second sub-via. The second sub-via is located below the first sub-via, and the diameter of the second sub-via is smaller than the diameter of the first sub-via.

4. The display panel according to claim 3, characterized in that, The first buffer layer is disposed above the metal shielding layer and completely covers the metal shielding layer; the second buffer layer is disposed above the first buffer layer and completely covers the first buffer layer. In this configuration, the first sub-via is transformed into the second sub-via in the second buffer layer. The bottom of the first sub-via is located in the second buffer layer, and the top of the second sub-via is located in the second buffer layer and is in direct contact with the bottom of the first sub-via.

5. The display panel according to claim 4, characterized in that, The display panel further includes a second deep hole located in the bonding area. The second deep hole has a stepped structure and includes a third sub-via and a fourth sub-via. The fourth sub-via is located below the third sub-via, and the diameter of the fourth sub-via is smaller than the diameter of the third sub-via. The third sub-via is transformed into the fourth sub-via in the second buffer layer. The bottom of the third sub-via is located in the second buffer layer, and the top of the fourth sub-via is located in the second buffer layer and is in direct contact with the bottom of the third sub-via.

6. The display panel according to claim 5, characterized in that, The distance between the bottom of the first sub-via and the side of the etch barrier layer near the substrate is less than the distance between the bottom of the third sub-via and the side of the etch barrier layer near the substrate.

7. The display panel according to claim 5, characterized in that, The bottom of the first deep hole is located in the metal shielding layer, and the bottom of the second deep hole is located in the substrate.

8. The display panel according to claim 1, characterized in that, The first via penetrates the first active layer, and the first source and drain electrodes form a side contact with the first active layer.

9. A method for manufacturing a display panel, characterized in that, The method includes: A substrate is provided, the substrate comprising a substrate, a metal shielding layer, a first buffer layer and a second buffer layer stacked together; A separate first active layer and an etch barrier layer are fabricated above the substrate, wherein the first active layer and the etch barrier layer are located in the same layer; A first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third gate layer, a first interlayer dielectric layer, a second active layer, a third insulating layer, a fourth gate layer, and a second interlayer dielectric layer are sequentially formed above the first active layer and the etch barrier layer. The first etching operation is performed to obtain a first via and a second via that are in contact with the first active layer, a third via that is in contact with the second active layer, a first sub-via that penetrates the etch barrier layer, and a third sub-via located in the bonding area. The first sub-via and the third sub-via are etched a second time to obtain a first deep hole and a second deep hole. The bottom of the first deep hole is located in the metal shielding layer, and the bottom of the second deep hole is located in the substrate.

10. The method for manufacturing a display panel according to claim 9, characterized in that, The method further includes: Metal material is filled into the first via, the second via, the third via, and the first deep hole to obtain a first source-drain layer, a second source-drain layer, and a metal layer. A first planarization layer is prepared above the first source-drain layer, the second source-drain layer, and the metal layer, and the material of the first planarization layer fills the interior and the top of the second deep hole.

Images