A chip, a method for manufacturing the chip, and an electronic device.

Abstract

This application provides a chip, a method for fabricating the chip, and an electronic device. The method for fabricating the chip includes: providing a substrate; wherein the surface of the substrate has: a plurality of active regions, a plurality of first strip-shaped regions extending along a first direction, a plurality of second strip-shaped regions extending along a second direction, and a plurality of redundant regions; each active region corresponds to at least one fin field-effect transistor to be formed, and each active region is surrounded by a region formed by the first strip-shaped regions and / or the second strip-shaped regions; forming a plurality of fins on the substrate; removing the fins from the plurality of first strip-shaped regions and the plurality of second strip-shaped regions to form a fin structure of a fin field-effect transistor in each active region and a redundant fin structure in each redundant region. By forming redundant fin structures, the uniformity of the subsequently formed isolation dielectric layer can be improved, resulting in better performance of the obtained fin field-effect transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip, a method for manufacturing the chip, and an electronic device. Background Technology

[0002] With the continuous development of electronic technology, the fin field-effect transistor (FinFET), as a new type of field-effect transistor, has been widely used in various chips. A FinFET consists of a gate and a strip-shaped fin structure. The gate surrounds the fin structure on three sides. The gate can control the channel region through the top surface and two sides of the fin structure, thereby significantly improving gate control capability and noticeably reducing leakage current. This gives FinFET advantages such as strong gate control capability, small device size, and low power consumption.

[0003] In related technologies, during the fabrication of fin field-effect transistors, after forming multiple fins on the substrate, the fins outside the active region need to be removed to form a fin structure within the active region. Since the shape of the region outside the active region is generally complex, the process precision for removing the fins is low, easily affecting the shape of the fin structure in the active region. Furthermore, the removal of the fins outside the active region leads to significant process differences between the region outside and the active region, resulting in poor uniformity of the subsequently formed isolation dielectric layer. This affects the growth of subsequent film layers and can easily cause stress unevenness, leading to defects such as bending and misalignment in the fin structure. Therefore, the performance of fin field-effect transistors fabricated using these technologies is poor. Summary of the Invention

[0004] This application provides a chip, a method for manufacturing the chip, and an electronic device to solve the problem of poor performance of fin field-effect transistors manufactured in related technologies.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a chip, which may include:

[0006] A substrate is provided; wherein the surface of the substrate has: a plurality of active regions, a plurality of first strip regions extending along a first direction, a plurality of second strip regions extending along a second direction, and a plurality of redundant regions. The redundant regions are located in areas other than the plurality of active regions, the plurality of first strip regions, and the plurality of second strip regions. The first direction and the second direction intersect each other, for example, the first direction and the second direction may be perpendicular to each other. Each active region corresponds to at least one fin field-effect transistor to be formed, and each active region is surrounded by a region formed by the first strip regions and / or the second strip regions. For example, when the active region is rectangular, the active region may be surrounded by two first strip regions and two second strip regions. In practical applications, the active regions can be set to rectangular, "L" shaped, etc., and can be configured according to the structure of the fin field-effect transistor to be formed. Furthermore, the shape and position of the first strip regions and the second strip regions can be set according to the shape and relative position of the active regions on the substrate.

[0007] Then, multiple fins are formed on the substrate. Optionally, the formed multiple fins can approximately cover the surface of the substrate, that is, fins are distributed in each active region, each first strip region, each second strip region, and each redundant region. In specific implementation, multiple fins extending along a first direction can be formed on the substrate. That is, the extension direction of each fin formed on the substrate is consistent, and the extension direction of the fins is consistent with the extension direction of the first strip region.

[0008] Subsequently, the fins in multiple first strip regions and multiple second strip regions are removed to form a fin structure of a fin field-effect transistor in each active region and a redundant fin structure in each redundant region, wherein the fin structure is a portion of the fins located in the active region and the redundant fin structure is a portion of the fins located in the redundant region.

[0009] The chip fabrication method provided in this application involves setting multiple first strip-shaped regions and multiple second strip-shaped regions. The first strip-shaped regions extend along a first direction, and the second strip-shaped regions extend along a second direction. Each active region is surrounded by a region formed by the first strip-shaped regions and / or the second strip-shaped regions. Thus, after removing the fins from the multiple first strip-shaped regions and multiple second strip-shaped regions, a fin structure of a fin-type field-effect transistor can be formed in each active region. Furthermore, redundant fin structures can be formed in redundant regions other than the active regions, the first strip-shaped regions, and the second strip-shaped regions. The redundant fin structures are separated from the fin structures in the active regions by the first strip-shaped regions and the second strip-shaped regions, thus the redundant fin structures do not affect the performance of the fin structures in the active regions. Moreover, by setting redundant fin structures, the uniformity of the subsequently formed isolation dielectric layer can be improved, thereby improving the quality of the subsequently formed film layer and preventing defects such as fin structure bending and misalignment caused by uneven stress. In addition, the shapes of the first strip-shaped regions and the second strip-shaped regions are relatively simple, reducing the difficulty of the fin removal process and not affecting the shape of the fin structures in the active regions. Therefore, the fin field-effect transistors obtained by the chip fabrication method provided in this application have better performance.

[0010] In this embodiment, each active region may include at least two first edges extending along a first direction and at least two second edges extending along a second direction. Each first strip region is adjacent to the first edge of at least one active region, and each second strip region is adjacent to the second edge of at least one active region. That is, the active region is relatively close to the first and second strip regions surrounding it. Thus, after removing the fin rays from the first and second strip regions, the resulting fin structure is essentially located within the range of each active region, resulting in high manufacturing precision. Furthermore, a certain gap may exist between the active region and the first and second strip regions surrounding it. This avoids affecting the shape of the fin structure within the active region due to process errors during the removal of fin rays from the first and second strip regions, thereby ensuring good performance of the fin structure formed within the active region.

[0011] In one possible implementation, the width of the first strip region in the second direction can be in the range of 0–2000 nm, and the width of the second strip region in the first direction can be in the range of 0–2000 nm. By appropriately setting the widths of the first and second strip regions, the size of the redundant regions outside the active region and the first and second strip regions can be controlled. Narrower widths of the first and second strip regions result in smaller areas of removed fins, leading to larger areas of the resulting redundant fin structure. This minimizes the process differences between the regions outside the active region and the active region, achieving process optimization and ensuring good performance of the formed fin field-effect transistor.

[0012] In one possible implementation, the removal of fins from the plurality of first strip regions and the plurality of second strip regions may include:

[0013] The fins in multiple first strip-shaped regions are removed using photolithography and etching processes;

[0014] The fins in multiple second strip-shaped regions are removed using photolithography and etching processes.

[0015] In the actual process, when removing the fins in the first or second strip region, the process accuracy and process window can be improved by adjusting the conditions of the photolithography process, such as the light source and exposure parameters, as well as the etching process conditions.

[0016] In this embodiment, the example shown is that the fins in the first strip regions are removed first, and then the fins in the second strip regions are removed. In the actual process, the fins in the second strip regions can be removed first, and then the fins in the first strip regions can be removed. Alternatively, the fins in the first strip regions and the second strip regions can be removed together. There is no limitation here.

[0017] In one possible implementation, forming multiple fins on the substrate as described above may include:

[0018] Multiple base axes are formed on the substrate, with the extension direction of the base axes being the same as that of the fins to be formed. Optionally, polycrystalline silicon can be used to fabricate the base axes; of course, other materials can also be used, and this is not limited here. In the actual process, a base axis film layer covering the entire surface can be formed on the substrate, and then multiple base axes located on the substrate can be obtained through an etching process.

[0019] A sidewall layer is formed over the entire surface of the base shaft. In practice, silicon nitride can be used to fabricate the sidewall layer, but other materials can also be used; this is not a limitation. Next, the sidewall layer is etched to form multiple sidewalls located at the sidewalls of the base shaft. In the actual process, the entire sidewall layer can be etched. Due to the geometric effects of the base shaft sidewalls, the material at the base shaft sidewalls will not be etched away, thus forming sidewalls at the sidewalls of the base shaft.

[0020] Multiple base shafts were removed using an etching process;

[0021] The substrate is etched using multiple sidewalls as shields to obtain a pattern of multiple fins;

[0022] Remove multiple sidewalls to obtain multiple fins.

[0023] In this embodiment of the application, the above manufacturing process is used as an example to illustrate the manufacturing process of the fins. In actual process, other methods can also be used to manufacture the fins, which are not limited here.

[0024] In some embodiments of this application, after forming the fin structure of the fin field-effect transistor, the following may also be included:

[0025] Each fin structure within the active region is doped to form a source region, a drain region, and a channel region; the channel region can be located between the source and drain regions. During the doping process of the fin structures within the active regions, redundant fin structures in the redundant regions can also be doped, thus eliminating the need to mask the redundant regions and simplifying the process.

[0026] An isolation dielectric layer is formed on the surface of the substrate and etched to make each fin structure protrude from the isolation dielectric layer. In this embodiment, the isolation dielectric layer formed on the substrate surface can be approximately formed over the entire surface. After etching the isolation dielectric layer, each redundant fin structure can also protrude from the isolation dielectric layer. Because there are redundant fin structures in the redundant regions other than the active region, the first strip region, and the second strip region, the uniformity of the formed isolation dielectric layer can be better.

[0027] A gate dielectric layer is formed on the fin structure in each active region, and the gate dielectric layer can cover the channel region of the fin structure.

[0028] A gate is formed on the gate dielectric layer in each active region to obtain at least one fin field-effect transistor. Because the isolation dielectric layer formed in this embodiment has good uniformity, the quality of the subsequently formed gate dielectric layer and gate is good, resulting in better performance of the obtained fin field-effect transistor.

[0029] In actual manufacturing processes, a gate dielectric layer and a gate can be formed on top of the redundant fin structure, thus minimizing the process differences between the active and redundant regions. Furthermore, after the doping process, a source electrically connected to the source region of the fin structure and a drain electrically connected to the drain region of the fin structure can be formed, thereby bringing out the source and drain regions of the fin structure. Since the redundant fin structure only serves to improve the uniformity of the subsequently formed isolation dielectric layer and does not need to be electrically connected to other components, the source and drain regions in the redundant fin structure do not need to be brought out.

[0030] Secondly, embodiments of this application also provide a chip, which may include: a substrate, a plurality of fin structures and a plurality of redundant fin structures located on the substrate. The surface of the substrate may have: a plurality of active regions, a plurality of first strip regions extending along a first direction, a plurality of second strip regions extending along a second direction, and a plurality of redundant regions, wherein the redundant regions may be located in regions other than the active regions, the plurality of first strip regions, and the plurality of second strip regions. The first direction and the second direction intersect each other; for example, the first direction and the second direction may be perpendicular to each other. Each active region on the substrate has at least one fin structure, and each redundant region on the substrate has at least one redundant fin structure. Each active region and the redundant region are separated by the first strip regions and / or the second strip regions.

[0031] In this embodiment, each active region corresponds to at least one fin field-effect transistor, meaning the chip includes at least one fin field-effect transistor. Each active region and redundant region are separated by a first strip region and / or a second strip region. Therefore, the fin structure in each active region is separated from the redundant fin structure in the redundant region, and thus the redundant fin structure does not affect the performance of the fin structure.

[0032] Furthermore, among the redundant regions on the substrate surface, at least one redundant region is shaped as a polygon with at least five sides; that is, the polygon may include five, six, or more sides, which can be configured according to the position and shape of the active regions on the substrate surface. The redundant region also includes at least one sub-region surrounded by at least three sides of the polygon, and the sub-region is embedded in the gap between two adjacent active regions. In one possible implementation, the sub-region may be a closed region enclosed by at least three sides of the polygon and a line segment (which may also be a polygonal line or a curve, etc.) located within the redundant region.

[0033] In this way, the space between two adjacent active regions can be fully utilized, and more redundant fin structures can be set near the active regions. This allows for a larger area of ​​redundant regions, which can significantly improve the uniformity of the subsequently formed isolation dielectric layer, thereby improving the quality of the subsequent film layer and resulting in better performance of the fin field-effect transistor.

[0034] In one possible implementation, at least one of the multiple redundant regions on the substrate surface at least partially surrounds an active region. The redundant region may partially surround one, two, or more active regions; alternatively, the redundant region may also fully surround at least one active region, without limitation. It is understood that "the redundant region at least partially surrounds an active region" means that the redundant region surrounds at least two sides of the active region.

[0035] Optionally, at least one of the multiple redundant regions on the substrate surface can be rectangular.

[0036] In a specific implementation, at least one of the multiple active regions on the substrate surface is rectangular, and this active region is separated from the redundant region by two first strip regions and two second strip regions. Of course, the active region can also be other shapes, such as an "L" shape. The number and position of the first and second strip regions surrounding the active region can be set according to the shape of the active region.

[0037] In one possible implementation, the chip may further include: an isolation dielectric layer on a substrate, with the fin structure protruding from the side of the isolation dielectric layer facing away from the substrate. Furthermore, the chip may also include: a gate dielectric layer and a gate located within an active region on the substrate. The gate is located on the side of the fin structure facing away from the substrate, and the gate dielectric layer is located between the fin structure and the gate. The fin structure includes a source region, a drain region, and a channel region, with the channel region located between the source and drain regions. The gate covers the channel region of the fin structure, and the gate surrounds the top surface and both sides of the fin structure. Therefore, the gate can control the channel region through the top surface and both sides of the fin structure, giving the fin field-effect transistor advantages such as strong gate control capability, small device size, and low power consumption.

[0038] Thirdly, embodiments of this application also provide an electronic device, which can be a smartphone, smart TV, laptop computer, or similar device. This electronic device may include any of the aforementioned chips, as well as a printed circuit board. Because the fin field-effect transistors in the aforementioned chips have good performance, the electronic device including these chips also has good performance. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of a fin field-effect transistor.

[0040] Figure 2 A flowchart illustrating a method for manufacturing a chip according to an embodiment of this application;

[0041] Figure 3 , Figure 4 , Figure 5a , Figure 5b and Figure 6 This is a schematic diagram of the structure corresponding to each step in the chip manufacturing method in the embodiments of this application;

[0042] Figures 7 to 12 This is a flowchart illustrating the manufacturing process of the fins in the embodiments of this application;

[0043] Figure 13a This is a schematic diagram of the structure of multiple fins formed on a substrate;

[0044] Figure 13b for Figure 13a A schematic diagram of the cross-section at the dashed line WW';

[0045] Figure 14a A schematic diagram of the structure during the process of removing fins from multiple first strip-shaped regions;

[0046] Figure 14b for Figure 14a A schematic diagram of the cross-section at the dashed line PP';

[0047] Figure 15a A schematic diagram of the structure after removing multiple fins from the first strip-shaped region;

[0048] Figure 15b for Figure 15a A schematic diagram of the cross-section at the dashed line PP';

[0049] Figure 16a A schematic diagram of the structure during the process of removing fins from multiple second strip-shaped regions;

[0050] Figure 16b for Figure 16a A cross-sectional diagram at the point indicated by the dashed line QQ'.

[0051] Figure 17a A schematic diagram of the structure after removing the fins from multiple second strip-shaped regions;

[0052] Figure 17b for Figure 17a A cross-sectional diagram at the point indicated by the dashed line QQ'.

[0053] Figures 18 to 20 This is a schematic diagram of the structure corresponding to each step in the chip manufacturing method in the embodiments of this application.

[0054] Figure label:

[0055] 10-Substrate; 11-Fin; 111-Fin structure; 112-Redundant fin structure; 12-Isolation dielectric layer; 13-Gate; 14-Gate dielectric layer; 15-Base axis; 16-Sidewall layer; 161-Sidewall; 17-Buffer layer; 18-Protective layer; A1~A7-Active region; T1-First strip region; T2-Second strip region; C1, C2, C3-Redundant region; a-First edge; b-Second edge. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0057] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0058] This application provides a chip, a method for manufacturing the chip, and an electronic device. The chip can be a central processing unit chip, an artificial intelligence chip, etc., and of course, it can also be other types of chips; no limitation is made here. The chip provided in this application can be applied to various types of electronic devices, such as smartphones, smart TVs, and laptops.

[0059] The chip provided in this application embodiment may include at least one fin field-effect transistor. Figure 1 This is a schematic diagram of the structure of a fin field-effect transistor, as shown below. Figure 1 As shown, a fin field-effect transistor may include: a substrate 10, at least one fin structure 111 on the substrate 10, an isolation dielectric layer 12 on the substrate 10, a gate 13 on the side of the fin structure 111 facing away from the substrate 10, and a gate dielectric layer 14 between the fin structure 111 and the gate 13. The fin structure 111 is a strip-shaped structure extending along a first direction F1, and the fin structures 111 are arranged along a second direction F2. The first direction F1 and the second direction F2 intersect each other, and the third direction F3 may be a direction perpendicular to the surface of the substrate 10. Figure 1Taking the fin field-effect transistor (FET) with three fin structures 111 as an example, in specific implementations, the FET may also include one, two, four, or more fin structures 111; the number of fin structures 111 is not limited here. The fin structure 111 protrudes from the isolation dielectric layer 12 on the side facing away from the substrate 10. The fin structure 111 includes a source region, a drain region, and a channel region. The gate 13 covers the channel region of the fin structure 11, and the gate 13 surrounds the top surface and two side surfaces of the fin structure 111. Therefore, the gate 13 can control the channel region through the top surface and two side surfaces of the fin structure 111, giving the fin field-effect transistor advantages such as strong gate control capability, small device size, and low power consumption.

[0060] The chip, chip manufacturing method, and electronic device provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0061] Figure 2 A flowchart illustrating a chip fabrication method provided in an embodiment of this application. Figure 3 , Figure 4 , Figure 5a , Figure 5b and Figure 6 This is a schematic diagram of the structure corresponding to each step in the chip fabrication method in the embodiments of this application. For example... Figure 2 As shown, the chip manufacturing method provided in this application embodiment may include:

[0062] S201, reference Figure 3 A substrate 10 is provided. The surface of the substrate 10 has a plurality of active regions (e.g., Figure 3 The substrate 10 has active regions A1 to A7 on its surface, a plurality of first strip regions T1 extending along a first direction F1, a plurality of second strip regions T2 extending along a second direction F2, and a plurality of redundant regions (e.g., Figure 3 The surface of the intermediate substrate 10 has redundant regions C1 to C3. The redundant regions C1 to C3 are located in the region excluding the plurality of active regions, the plurality of first strip regions T1, and the plurality of second strip regions T2. The first direction F1 and the second direction F2 intersect each other; for example, the first direction F1 and the second direction F2 can be perpendicular to each other. Each active region corresponds to at least one fin field-effect transistor to be formed, and each active region is surrounded by a region formed by the first strip region T1 and / or the second strip region T2, for example... Figure 3 In the diagram, the active regions A1, A2, A3, A4, A6, and A7 are surrounded by regions consisting of two first strip regions T1 and two second strip regions T2.

[0063] In practical implementation, at least two adjacent active regions can share either the first strip region T1 or the second strip region T2. ​​For example, in... Figure 3In the above, active regions A2 and A3 share the same second stripe region T2, active regions A1 and A4 share the same second stripe region T2, and active regions A5 and A6 share the same second stripe region T2. ​​Alternatively, at least two active regions with substantially aligned edges can share either the first stripe region T1 or the second stripe region T2, for example, in... Figure 3 In this context, active regions A1, A5, and A6 share the same first stripe region T1, while active regions A3 and A7 can share the same first stripe region T. It should be noted that... Figure 3 The diagram illustrates the active regions A1, A2, A3, A4, A6, and A7 as rectangles, and active region A5 as an "L" shape. In practical applications, the active regions can also be other shapes, which can be set according to the structure of the fin field-effect transistor to be formed. Furthermore, the shape and position of the first strip region T1 and the second strip region T2 can be set according to the shape and relative position of the active regions on the substrate 10.

[0064] S202, reference Figure 4 Multiple fins 11 are formed on the substrate 10. Optionally, the multiple fins 11 formed can approximately cover the surface of the substrate 10, that is, fins 11 are distributed in the active regions A1 to A7, each first strip region T1, each second strip region T2, and the redundant regions C1 to C3.

[0065] S203, reference Figure 5a The fins within multiple first strip regions T1 and multiple second strip regions T2 are removed to form a fin structure 111 of a fin field-effect transistor in each active region and a redundant fin structure 112 in each redundant region. The fin structure 111 consists of a portion of the fins located within the active region, and the redundant fin structure 112 consists of a portion of the fins located within the redundant region.

[0066] To more clearly illustrate the fin structure and redundant fin structure formed in step S203, Figure 6 Central Province Figure 5a The markings for the first and second bar regions. From Figure 6It is evident that each active region includes at least one strip-shaped fin structure 111, and multiple redundant fin structures 112 are present in the redundant regions C1 to C3 outside the active regions. Furthermore, since the fins in the first and second strip-shaped regions surrounding the active regions are removed, the formed fin structures 111 and redundant fin structures 112 are separated, thus the formed redundant fin structures 112 do not affect the performance of the fin structures 111. Moreover, in each of the formed redundant regions, at least one redundant region is a polygon with at least five sides, and the edge of the redundant region is embedded in the gap between two adjacent active regions. For example, redundant region C1 is a polygon with 16 sides, and the edge of redundant region C1 is embedded in the gap between active regions A4 and A5. This results in a larger area for the redundant region, allowing for more redundant fin structures near the active regions, significantly improving the uniformity of the subsequently formed isolation dielectric layer, and resulting in better performance of the formed fin field-effect transistor.

[0067] The chip fabrication method provided in this application involves setting multiple first strip-shaped regions and multiple second strip-shaped regions. The first strip-shaped regions extend along a first direction, and the second strip-shaped regions extend along a second direction. Each active region is surrounded by a region formed by the first strip-shaped regions and / or the second strip-shaped regions. Thus, after removing the fins from the multiple first strip-shaped regions and multiple second strip-shaped regions, a fin structure of a fin-type field-effect transistor can be formed in each active region. Furthermore, redundant fin structures can be formed in redundant regions other than the active regions, the first strip-shaped regions, and the second strip-shaped regions. The redundant fin structures are separated from the fin structures in the active regions by the first strip-shaped regions and the second strip-shaped regions, thus the redundant fin structures do not affect the performance of the fin structures in the active regions. Moreover, by setting redundant fin structures, the uniformity of the subsequently formed isolation dielectric layer can be improved, thereby improving the quality of the subsequently formed film layer and preventing defects such as fin structure bending and misalignment caused by uneven stress. In addition, the shapes of the first strip-shaped regions and the second strip-shaped regions are relatively simple, reducing the difficulty of the fin removal process and not affecting the shape of the fin structures in the active regions. Therefore, the fin field-effect transistors obtained by the chip fabrication method provided in this application have better performance.

[0068] In specific implementation, step S202 above may include: referring to Figure 4Multiple fins 11 extending along a first direction F1 are formed on the substrate 10. That is, the extension directions of all fins 11 formed on the substrate 10 are consistent, and the extension direction of the fins 11 is consistent with the extension direction of the first strip region T1. This makes it easier to remove the fins 11 in the first strip region T1 and the second strip region T2 in the subsequent step S203, resulting in higher process precision for fin removal. Therefore, the removal of the fins 11 in the first strip region T1 and the second strip region T2 does not affect the shape of the fin structure in the active region, leading to better performance of the fin field-effect transistor formed in the active region.

[0069] In the embodiments of this application, such as Figure 3 As shown, each active region (for example, referring to active region A7) may include at least two first edges a extending along a first direction F1, and at least two second edges b extending along a second direction F2. Each first strip region T1 is adjacent to the first edge a of at least one active region, and each second strip region T2 is adjacent to the second edge b of at least one active region. That is, the active region is relatively close to the first strip region T1 and the second strip region T2 surrounding it. Thus, after removing the fins within the first strip region T1 and the second strip region T2, the resulting fin structure is essentially located within the range of each active region, resulting in high manufacturing precision. Furthermore, a certain gap can exist between the active region and the first strip region T1 and the second strip region T2 surrounding it. This avoids affecting the shape of the fin structure within the active region due to process errors during the removal of the fins within the first strip region T1 and the second strip region T2, thereby ensuring good performance of the fin structure formed within the active region.

[0070] In practical applications, continue to refer to Figure 3 The width d1 of the first strip region T1 in the second direction F2 can be in the range of 0 to 2000 nm, and the width d2 of the second strip region T2 in the first direction F1 can be in the range of 0 to 2000 nm. Thus, by reasonably setting the widths of the first and second strip regions, the size of the active region and the redundant regions outside the first and second strip regions can be controlled. This allows for narrower widths of the first and second strip regions T1 and T2, resulting in a smaller area of ​​the fins removed in step S203. Consequently, the area of ​​the formed redundant fin structure can be larger, minimizing the process differences between the regions outside the active region and the active region. This achieves process optimization and ensures better performance of the formed fin field-effect transistor.

[0071] Figures 7 to 12 This is a flowchart illustrating the manufacturing process of the fins in the embodiments of this application, combined with... Figures 7 to 12Step S202 above may include:

[0072] Reference Figure 7 Multiple base shafts 15 are formed on the substrate 10, and the extending direction of the base shafts 15 is the same as the extending direction of the fins to be formed, that is... Figure 7 The direction perpendicular to the paper can be the first direction mentioned above, the horizontal direction in the figure can be the second direction F2 mentioned above, and the vertical direction in the figure can be the third direction F3, which can be a direction perpendicular to the surface of the substrate 10. Optionally, polycrystalline silicon material can be used to make the base shaft 15. Of course, other materials can also be used to make the base shaft 15, and there is no limitation here. In the actual process, a base shaft film layer covering the entire surface can be formed on the substrate 10, and then multiple base shafts 15 located on the substrate 10 can be obtained by etching process.

[0073] Reference Figure 8 A sidewall layer 16 is formed over the entire surface of the base shaft 15. In practice, silicon nitride can be used to fabricate the sidewall layer 16; however, other materials can also be used. No limitation is made here. Then, the sidewall layer 16 is etched, referring to… Figure 9 Multiple sidewalls 161 are formed at the sidewall of the base shaft 15. In the actual process, the sidewall layer can be etched in its entirety. Due to the geometric effect of the sidewall of the base shaft 15, the material at the sidewall of the base shaft 15 will not be etched away, thus forming sidewalls 161 at the sidewall of the base shaft 15.

[0074] Multiple base shafts were removed using an etching process to obtain Figure 10 The structure shown.

[0075] Reference Figure 11 Using multiple sidewalls 161 as shields, the substrate 10 is etched to obtain a pattern of multiple fins 11.

[0076] Reference Figure 12 Multiple sidewalls were removed to obtain multiple fins 11.

[0077] In the embodiments of this application, Figures 7 to 12 The following is an example of the manufacturing process for fins. In actual production, other methods can also be used to manufacture fins, and this is not a limitation here.

[0078] Figure 13a This is a schematic diagram of the structure of multiple fins formed on a substrate. Figure 13b for Figure 13a A schematic diagram of the cross-section at the dashed line WW', as shown below. Figure 13a and Figure 13bAs shown, in step S202 above, a plurality of fins 11 extending along the first direction F1 are formed on the substrate 10. After step S202 and before step S203, the process may further include: forming a buffer layer 17 on the fins 11, and forming a protective layer 18 on the buffer layer 17. By forming the buffer layer 17 and the protective layer 18 on the fins 11, the fins 11 can be protected, preventing damage to the fins 11 in subsequent processing steps.

[0079] Figure 14a This is a structural diagram illustrating the process of removing fins from multiple first strip-shaped regions. Figure 14b for Figure 14a A schematic diagram of the cross-section at the dashed line PP'. Figure 15a This is a schematic diagram of the structure after removing the fins from multiple first strip-shaped regions. Figure 15b for Figure 15a A schematic diagram of the cross-section at the dashed line PP'. Figure 16a This is a structural diagram illustrating the process of removing fins from multiple second-striped regions. Figure 16b for Figure 16a A cross-sectional diagram at the point indicated by the dashed line QQ'. Figure 17a This is a schematic diagram of the structure after removing the fins from multiple second-striped regions. Figure 17b for Figure 17a A cross-sectional view at the dashed line QQ'. The following, in conjunction with the accompanying drawings, details the process of removing the fins from the multiple first strip-shaped regions and multiple second strip-shaped regions in step S203.

[0080] Reference Figure 14a and Figure 14b The fins 11 within the multiple first strip regions T1 can be removed using photolithography and etching processes. Optionally, a photoresist layer (not shown) can be formed over the entire surface of the protective layer 18. The photoresist layer within the multiple first strip regions T1 is then removed using exposure and development processes to protect the areas outside the multiple first strip regions T1. Next, an etching process is used to remove the fins 11 within the multiple first strip regions T1, followed by the removal of the remaining photoresist layer. After removing the fins 11 within the multiple first strip regions T1, the desired result is... Figure 15a and Figure 15b The structure shown.

[0081] Reference Figure 16a and Figure 16bThe fins 11 within the multiple second strip regions T2 can be removed using photolithography and etching processes. Optionally, a photoresist layer (not shown) can be formed over the entire surface of the protective layer 18. The photoresist layer within the multiple second strip regions T2 is then removed using exposure and development processes to protect the areas outside the multiple second strip regions T2. Next, an etching process is used to remove the fins 11 within the multiple second strip regions T2, followed by the removal of the remaining photoresist layer. After removing the fins 11 within the multiple second strip regions T2, the desired result is obtained. Figure 17a and Figure 17b The structure shown is as follows: Figure 17a and Figure 17b As shown, after removing the fins 11 in multiple first strip regions T1 and multiple second strip regions T2, fin structures 111 are formed in active regions A1 to A7, and redundant fin structures 112 are formed in redundant regions C1 to C3.

[0082] In the actual process, when removing the fins in the first or second strip region, the process accuracy and process window can be improved by adjusting the conditions of the photolithography process, such as the light source and exposure parameters, as well as the etching process conditions.

[0083] In this embodiment, the example shown is that the fins in the first strip regions are removed first, and then the fins in the second strip regions are removed. In the actual process, the fins in the second strip regions can be removed first, and then the fins in the first strip regions can be removed. Alternatively, the fins in the first strip regions and the second strip regions can be removed together. There is no limitation here.

[0084] Figures 18 to 20 The diagram below shows the structural schematics corresponding to each step in the chip fabrication method in the embodiments of this application. In some embodiments of this application, after step S203, the method may further include:

[0085] Each fin structure within the active region is doped to form a source region, a drain region, and a channel region, where the channel region can be located between the source and drain regions. In practical applications, buffer and protective layers on the fin structure can be removed before doping the active region. During the doping process, redundant fin structures in redundant regions can also be doped, eliminating the need to mask these redundant regions and simplifying the process.

[0086] like Figure 18As shown, an isolation dielectric layer 12 is formed on the surface of the substrate 10, and the isolation dielectric layer 12 is etched so that each fin structure 11 protrudes from the isolation dielectric layer 12. In this embodiment, the isolation dielectric layer 12 formed on the surface of the substrate 10 can be approximately formed over the entire surface. After etching the isolation dielectric layer 12, each redundant fin structure can also protrude from the isolation dielectric layer 12. Since there are redundant fin structures in the redundant regions other than the active region, the first strip region, and the second strip region, the uniformity of the formed isolation dielectric layer 12 can be better.

[0087] like Figure 19 As shown, a gate dielectric layer 14 is formed on the fin structure 11 in each active region, and the gate dielectric layer 14 can cover the channel region of the fin structure 11.

[0088] like Figure 20 As shown, a gate 13 is formed on the gate dielectric layer 14 in each active region to obtain at least one Figure 1 The fin field-effect transistor shown is an example. Because the isolation dielectric layer 12 formed in this embodiment has good uniformity, the subsequently formed gate dielectric layer 14 and gate 13 are of good quality, resulting in a fin field-effect transistor with good performance.

[0089] In actual manufacturing processes, gate dielectric layers 14 and gate 13 can be formed on the redundant fin structure, thus minimizing the process differences between the active and redundant regions. Furthermore, after the doping process, a source electrically connected to the source region of the fin structure and a drain electrically connected to the drain region of the fin structure can be formed, thereby bringing out the source and drain regions of the fin structure. Since the redundant fin structure only serves to improve the uniformity of the subsequently formed isolation dielectric layer and does not need to be electrically connected to other components, the source and drain regions in the redundant fin structure do not need to be brought out.

[0090] Based on the same technical concept, this application also provides a chip, which can be a central processing unit chip, an artificial intelligence chip, or other types of chips. This chip can be manufactured using any of the above-described manufacturing methods.

[0091] like Figure 5a As shown, the chip may include: a substrate 10, a plurality of fin structures 111 and a plurality of redundant fin structures 112 located on the substrate 10. The surface of the substrate 10 may have: a plurality of active regions (e.g., Figure 5a The surface of the intermediate substrate 10 has source regions A1 to A7, a plurality of first strip regions T1 extending along a first direction F1, a plurality of second strip regions T2 extending along a second direction F2, and a plurality of redundant regions (e.g., Figure 5aThe surface of the substrate 10 has redundant regions C1 to C3, which can be located in areas other than the active regions, the multiple first strip regions T1, and the multiple second strip regions T2. The first direction F1 and the second direction F2 intersect each other; for example, the first direction F1 and the second direction F2 can be perpendicular to each other. Each active region on the substrate 10 has at least one fin structure 111, and each redundant region on the substrate 10 has at least one redundant fin structure 112. Each active region and redundant region is separated by the first strip region T1 and / or the second strip region T2.

[0092] In this embodiment, each active region corresponds to at least one fin field-effect transistor, meaning the chip includes at least one fin field-effect transistor. Each active region and the redundant region are separated by a first strip region T1 and / or a second strip region T2. ​​Therefore, the fin structure 111 in each active region is separated from the redundant fin structure 112 in the redundant region, and thus the redundant fin structure does not affect the performance of the fin structure.

[0093] Furthermore, among the redundant regions on the substrate surface, at least one redundant region is shaped as a polygon with at least five sides; that is, the polygon may include five, six, or more sides, which can be configured according to the position and shape of the active regions on the substrate surface. The redundant region also includes at least one sub-region surrounded by at least three sides of the polygon, and the sub-region is embedded in the gap between two adjacent active regions. In one possible implementation, the sub-region may be a closed region enclosed by at least three sides of the polygon and a line segment (which may also be a polygonal line or a curve, etc.) located within the redundant region.

[0094] Figure 5b for Figure 5a The enlarged schematic diagram is shown to clearly illustrate the sub-regions within the redundant region. Figure 5b The diagrams of the fin structure, redundant fin structure, first strip region, and second strip region have been omitted. (Combined with...) Figure 5a and Figure 5b For example, Figure 5a The redundant region C1 is a polygon with 16 sides. Redundant region C1 can include sub-regions C11 and C12. Sub-region C11 can be a closed region enclosed by edges x1, x2, and x3 of redundant region C1 and line segment y1 located within redundant region C1, and sub-region C11 is embedded in the gap between active regions A4 and A5. Sub-region C12 can be a closed region enclosed by edges x4, x5, x6, and x7 of redundant region C1 and line segment y2 located within redundant region C1, and sub-region C12 is embedded in the gap between active regions A2, A1, and A4.

[0095] In this way, the space between two adjacent active regions can be fully utilized, and more redundant fin structures can be set near the active regions. This allows for a larger area of ​​redundant regions, which can significantly improve the uniformity of the subsequently formed isolation dielectric layer, thereby improving the quality of the subsequent film layer and resulting in better performance of the fin field-effect transistor.

[0096] Continue to refer to Figure 5a At least one redundant region among multiple redundant regions on the substrate surface, at least partially surrounding an active region, for example... Figure 5a In the diagram, redundant region C1 partially surrounds active regions A4, A5, and A7. Of course, redundant region can also partially surround one, two, or more active regions, or it can completely surround at least one active region; this is not limited here. It can be understood that "redundant region partially surrounds at least one active region" means that redundant region surrounds at least two edges of the active region.

[0097] Optionally, at least one of the multiple redundant regions on the substrate surface can be rectangular, for example... Figure 5a The redundant regions C2 and C3 are rectangles.

[0098] In specific implementation, such as Figure 5a As shown, at least one of the multiple active regions on the surface of substrate 10 is rectangular (e.g., Figure 5a The active region A1 in the diagram is rectangular, and this active region and the redundant region are separated by two first strip regions T1 and two second strip regions T2. Of course, the active region can also be other shapes, for example... Figure 5a The active region A5 is "L" shaped. The number and position of the first and second strip regions surrounding the active region can be set according to the shape of the active region.

[0099] In the embodiments of this application, such as Figure 1 As shown, the chip may further include: an isolation dielectric layer 12 located on the substrate 10, with the fin structure 111 protruding from the isolation dielectric layer 12 on the side facing away from the substrate 10. Furthermore, the chip may also include: a gate dielectric layer 14 and a gate 13 located within the active region on the substrate 10, with the gate 13 located on the side of the fin structure 111 facing away from the substrate 10, and the gate dielectric layer 14 located between the fin structure 111 and the gate 13. The fin structure 111 includes a source region, a drain region, and a channel region, with the channel region located between the source and drain regions. The gate 13 covers the channel region of the fin structure 11, and the gate 13 surrounds the top surface and both sides of the fin structure 111. Therefore, the gate 13 can control the channel region through the top surface and both sides of the fin structure 111, giving the fin field-effect transistor advantages such as strong gate control capability, small device size, and low power consumption.

[0100] Based on the same technical concept, this application also provides an electronic device, which can be a smartphone, smart TV, laptop, or other similar device. This electronic device may include any of the aforementioned chips, as well as a printed circuit board. Because the fin field-effect transistors in the aforementioned chips have good performance, the electronic device including these chips also has good performance.

[0101] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0102] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A chip, characterized in that, include: A substrate, and multiple fin structures and multiple redundant fin structures located on the substrate; The surface of the substrate has: a plurality of active regions, a plurality of first strip regions extending along a first direction, a plurality of second strip regions extending along a second direction, and a plurality of redundant regions; wherein the first direction and the second direction intersect each other; At least one fin structure is provided in each of the active regions on the substrate; At least one redundant fin structure is provided in each of the redundant regions above the substrate; Each of the active regions and the redundant regions is separated by the first strip region and / or the second strip region; At least one of the multiple redundant regions is a polygon with at least five sides, and the redundant region includes at least one sub-region surrounded by at least three of the at least five sides, the sub-region being embedded in the gap between two adjacent active regions.

2. The chip as described in claim 1, characterized in that, At least one of the multiple redundant regions at least partially surrounds one of the active regions.

3. The chip as described in claim 1, characterized in that, At least one of the plurality of redundant regions is rectangular.

4. The chip as described in claim 1, characterized in that, At least one of the plurality of active regions is rectangular, and the active region and the redundant region are separated by two first strip regions and two second strip regions.

5. The chip according to any one of claims 1 to 4, characterized in that, Also includes: An isolation dielectric layer located on the substrate; The fin structure protrudes from the side of the isolation medium layer opposite to the substrate.

6. The chip as described in claim 5, characterized in that, Also includes: The gate dielectric layer and the gate located in the active region above the substrate; The gate is located on the side of the fin structure opposite to the substrate, and the gate dielectric layer is located between the fin structure and the gate. The fin structure includes a source region, a drain region, and a channel region, wherein the channel region is located between the source region and the drain region, and the gate covers the channel region of the fin structure.

7. An electronic device, characterized in that, include: The chip as described in any one of claims 1 to 6, and the printed circuit board.

8. A method for manufacturing a chip, characterized in that, include: A substrate is provided; wherein the surface of the substrate has: a plurality of active regions, a plurality of first strip regions extending along a first direction, a plurality of second strip regions extending along a second direction, and a plurality of redundant regions; the first direction and the second direction intersect each other; each active region corresponds to at least one fin field-effect transistor to be formed, each active region is surrounded by a region formed by the first strip regions and / or the second strip regions; each active region and the redundant regions are separated by the first strip regions and / or the second strip regions; at least one of the plurality of redundant regions is shaped as a polygon including at least five sides, and the redundant region includes at least one sub-region, the sub-region being surrounded by at least three of the at least five sides, the sub-region being embedded in the gap between two adjacent active regions; Multiple fins are formed on the substrate; The fins in the plurality of first strip regions and the plurality of second strip regions are removed to form a fin structure of the fin field-effect transistor in each of the active regions and a redundant fin structure in each of the redundant regions; wherein the fin structure is a portion of the fins located in the active regions and the redundant fin structure is a portion of the fins located in the redundant regions.

9. The manufacturing method as described in claim 8, characterized in that, The formation of multiple fins on the substrate includes: A plurality of fins extending along the first direction are formed on the substrate.

10. The manufacturing method as described in claim 8, characterized in that, Each of the active regions includes: at least two first edges extending along the first direction, and at least two second edges extending along the second direction; Each of the first strip regions is adjacent to the first edge of at least one of the active regions, and each of the second strip regions is adjacent to the second edge of at least one of the active regions.

11. The manufacturing method as described in claim 10, characterized in that, The width of the first strip region in the second direction is in the range of 0 to 2000 nm, and the width of the second strip region in the first direction is in the range of 0 to 2000 nm.

12. The manufacturing method as described in claim 10, characterized in that, The removal of the fins from the plurality of first strip regions and the plurality of second strip regions includes: The fins within the plurality of first strip-shaped regions are removed using photolithography and etching processes; The fins in the plurality of second strip-shaped regions are removed by photolithography and etching processes.

13. The manufacturing method as described in claim 8, characterized in that, The formation of multiple fins on the substrate includes: Multiple base shafts are formed on the substrate, and the extending direction of the base shafts is the same as the extending direction of the fins to be formed; A sidewall layer is formed over the entire surface of the base shaft, and the sidewall layer is etched to form multiple sidewalls located at the sidewalls of the base shaft. The plurality of base shafts are removed by an etching process; Using the multiple sidewalls as shields, the substrate is etched to obtain the pattern of the multiple fins; Remove the multiple sidewalls to obtain the multiple fins.

14. The manufacturing method according to any one of claims 8 to 13, characterized in that, After forming the fin structure of the fin field-effect transistor, the method further includes: The fin structure in each of the active regions is doped to form a source region, a drain region, and a channel region in the fin structure; An isolation dielectric layer is formed on the surface of the substrate, and the isolation dielectric layer is etched so that each of the fin structures protrudes from the isolation dielectric layer; A gate dielectric layer is formed on the fin structure in each of the active regions; A gate is formed on the gate dielectric layer in each of the active regions to obtain at least one fin field-effect transistor.

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