An exception handling method, apparatus, processor, and electronic device

Abstract

The present application discloses an exception handling method, apparatus, processor and electronic device, which are applied to the processor; the exception handling method includes: when a target exception is triggered during the execution of a program flow, performing exception handling on the target exception based on a target firmware; performing exception handling on the target exception again based on an exception vector table in the kernel space of the processor; after the exception handling in the kernel space is completed, returning to a target fault point to continue executing the program flow, where the target fault point is an interruption point when the target exception is triggered in the program flow. The implementation manner of the present application integrates two ways of handling exceptions, and for an actually occurring exception or a hardware interruption, respectively based on the firmware and the exception vector table in the kernel space, realizes a specific handling process, and significantly improves the superiority of exception handling in the processor.

Description

Technical Field

[0001] This application relates to the field of chips. Specifically, it relates to processor technology in the field of chips. More specifically, it relates to an exception handling method, apparatus, processor, and electronic device. Background Art

[0002] The exception handling mechanism of a processor is an important part of its architecture, which allows the processor to take appropriate actions when encountering specific exception situations. This mechanism can ensure the stable operation of the system and also improve the flexibility and reliability of the processor.

[0003] Currently, most processors implement exception handling based on the exception vector table in the kernel space. For example, after an exception is triggered in the program flow, it jumps to the exception vector table, and the exception handling function in the exception vector table is executed to implement exception handling, and finally it returns to the fault point to continue executing the program flow.

[0004] However, the exception vector table is usually stored in the kernel of the processor, and it can only perform exception handling in the kernel space. And to handle some specific exceptions, it is necessary to deploy the general code of each relevant platform, which is very difficult to implement. Eventually, the superiority of the current exception handling mechanism in the processor is very poor. Summary of the Invention

[0005] To solve the above technical problems, this application provides an exception handling method, apparatus, processor, and electronic device to achieve the purpose of enhancing the superiority of the current exception handling mechanism in the processor.

[0006] To achieve the above technical objectives, the embodiments of this application provide the following technical solutions:

[0007] In a first aspect, an embodiment of this application provides an exception handling method applied to a processor. The exception handling method includes:

[0008] When a target exception is triggered during the execution of the program flow, perform exception handling on the target exception based on the target firmware;

[0009] Perform exception handling on the target exception again based on the exception vector table in the kernel space of the processor;

[0010] After the exception handling is completed in the kernel space, return to the target fault point to continue executing the program flow, where the target fault point is the breakpoint when the target exception is triggered in the program flow.

[0011] In a second aspect, an embodiment of this application provides an exception handling apparatus applied to a processor. The exception handling apparatus includes:

[0012] The first exception handling module is used to perform exception handling on the target exception based on the target firmware when the target exception is triggered during the execution of the program flow;

[0013] The second exception handling module is used to perform exception handling on the target exception again based on the exception vector table in the kernel space of the processor;

[0014] The exception return module is used to return to the target fault point to continue executing the program flow after the exception handling in the kernel space is completed, where the target fault point is the interruption point when the target exception is triggered in the program flow.

[0015] In a third aspect, an embodiment of the present application provides a processor configured to execute the exception handling method as described in the first aspect.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, including: the processor as described in the third aspect.

[0017] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, the exception handling method as described in the first aspect is implemented.

[0018] In a sixth aspect, an embodiment of the present application provides a computer program product or a computer program. The computer program product includes a computer program stored in a computer-readable storage medium; a processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, the steps of the exception handling method as described in the first aspect are implemented.

[0019] For the exception handling method provided by the present application, when the target exception is triggered during the execution of the program flow, first, initial exception handling is performed in the form of firmware. Compared with operating in the kernel space, exception handling at the firmware level is safer, and the firmware has higher operability and can flexibly adjust the exception handling logic. Then, the target exception is handled again based on the exception vector table in the kernel space of the processor. By reusing the exception vector table in the kernel space, secondary processing of the exception is realized. While ensuring security and flexibility, the final effect of the entire exception handling process can be improved. Finally, after the exception handling in the kernel space is completed, it returns to the interruption point when the target exception is triggered to continue executing the program flow, completing the exception handling process. The embodiments of the present application integrate two ways of handling exceptions, and for an actual occurrence of a single exception or a single hardware interruption, specific handling processes are realized respectively based on the firmware and the exception vector table in the kernel space, significantly improving the superiority of exception handling in the processor. Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0021] Figure 1 A flowchart of an exception handling method provided for an embodiment of the present application;

[0022] Figure 2 A flowchart for calculating the offset provided for an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the processing process for a target exception triggered in user space provided for an embodiment of the present application;

[0024] Figure 4 A schematic diagram of the processing process for a target exception triggered in kernel space provided for an embodiment of the present application;

[0025] Figure 5 A structural block diagram of an exception handling device provided for an embodiment of the present application;

[0026] Figure 6 A schematic diagram of the structure of an electronic device provided for an embodiment of the present application. Specific Embodiments

[0027] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meaning understood by those of ordinary skill in the art to which the present application belongs. The "first", "second" and similar terms used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to avoid confusion of components.

[0028] Unless otherwise required by the context, throughout the specification, "a plurality" means "at least two", and "including" is interpreted as an open and inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0030] Overview

[0031] As described above, the exception handling mechanism of the processor usually relies on the exception vector table in the kernel space. This exception vector table can be understood as a fixed memory address space. After an exception occurs, it will jump into this exception vector table, and then the exception will be handled with the help of the exception vector table.

[0032] At present, the exception vector table has been relatively mature and stable, and it is relatively simple to implement exception handling using the exception vector table. However, the exception vector table is subject to some restrictions in the kernel space, making the superiority of the exception handling mechanism using the exception vector table not obvious. For example, limited by the restrictions of the kernel space in terms of operating system security, its flexibility and operability are relatively poor.

[0033] To solve the above problems discovered by the inventors through research, the inventors proposed that when an exception occurs, the firmware is preferentially used for an exception handling once, and then the exception vector table in the kernel space is reused for exception handling again. Integrating the two ways of handling exceptions can significantly improve the superiority of exception handling in the processor.

[0034] Based on the above concept, the inventors provided an exception handling method. Below, the exception handling method provided in the embodiments of the present application will be described exemplarily in conjunction with the accompanying drawings.

[0035] Exemplary Method

[0036] Taking the application to a processor as an example, the embodiments of the present application provide an exception handling method, and this exception handling method includes:

[0037] Step S101: When a target exception is triggered during the execution of the program flow, perform exception handling on the target exception based on the target firmware.

[0038] In this step, the program flow refers to the control flow when the program is executed in the processor. It describes the execution order of instructions and conditional branches, determines the running path and logic of the program. It can also be called the program execution flow. During the execution of the program flow, a fault will trigger a corresponding exception, thus interrupting the execution of the program flow. The target exception can be an exception triggered by certain specified faults. These faults can be illegal instructions, misaligned instruction accesses, UCE (Uncorrectable Error) in memory faults, etc., but are not limited to this. Correspondingly, the target exceptions triggered by these faults can be Synchronous External Abort (SEA), System Error Interrupt (SEI), etc.

[0039] The target firmware is a functional module in the processor that performs exception handling in the form of firmware. It should be noted that this target firmware is different from the exception vector table in the kernel space. It has the characteristics of firmware, higher operability, and can flexibly adjust the exception handling logic. When the processor executes the program flow and an exception is triggered, the pre-stored target firmware is preferentially used for exception handling, and this exception handling includes fault diagnosis, fault repair, execution of panic, etc. It can be understood that when a fault occurs or an exception is triggered in the processor, the hardware is used to record the fault information. During the process of using the target firmware to handle the exception, the fault information in the hardware can be read to implement exception handling.

[0040] Step S102: Based on the exception vector table in the kernel space of the processor, perform exception handling on the target exception again.

[0041] In this step, the target exception is handled using the exception vector table in the kernel space. Regarding the kernel space of the processor and the exception vector table in the kernel space, no more details will be elaborated here. Among them, this exception vector table is the exception vector table used when handling exceptions in the kernel space. Specifically, the exception vector table can be understood as a specific memory address space. When an exception occurs, it jumps to the corresponding memory address space in the exception vector table for exception handling. Here, an existing exception vector table can be used to handle the target exception, but it is not limited to this.

[0042] Step S103: After completing the exception handling in the kernel space, return to the target fault point to continue executing the program flow.

[0043] In this step, the target fault point is the breakpoint when the target exception is triggered in the program flow. It can be understood that after a fault occurs, an interruption usually takes place. After the fault is resolved, the execution continues from the breakpoint. Specifically, the breakpoint can be the next PC being executed, that is, the address of the next instruction to be executed, but it is not limited to this. In the implementation mode of this application, step S101 and step S102 are two different processing methods for the same exception. That is to say, for an exception actually triggered during the system operation or a hardware interruption, two different processing methods are used to process the exception / interruption respectively.

[0044] In the implementation mode of this application, when the target exception is triggered during the execution of the program flow, first, the initial exception handling is performed in the form of firmware. Compared with operating in the kernel space, performing exception handling at the firmware level is safer, and the firmware has higher operability, and the exception handling logic can be flexibly adjusted. Then, the target exception is processed again based on the exception vector table in the kernel space of the processor. By reusing the exception vector table in the kernel space, the secondary processing of the exception is realized. While ensuring security and flexibility, the final effect of the entire exception handling process can be improved. Finally, after the exception handling is completed in the kernel space, the execution returns to the breakpoint when the target exception is triggered to continue the program flow, and the exception handling process is completed. The implementation mode of this application integrates two ways of handling exceptions. For an actually occurring exception or a hardware interruption, the specific processing process is realized respectively based on the exception vector tables of the firmware and the kernel space, which significantly improves the superiority of exception handling in the processor.

[0045] In some implementation modes, when the target exception is triggered during the execution of the program flow, the target exception is processed based on the target firmware, including:

[0046] When the target exception is triggered during the execution of the program flow, the exception level of the target exception is switched to the target exception level; wherein, the target exception level is the exception level for which the processor performs exception handling in the form of firmware;

[0047] Based on the target firmware corresponding to the target exception level, the target exception is processed.

[0048] It should be noted that for the exceptions triggered in the processor, the exception levels (ExceptionLevel, abbreviated as EL) are usually divided to achieve the security and reliability of the processor. Among them, the exception levels define different privilege levels, and each privilege level has different access rights and capabilities. For example, in the current ARM architecture, the exception levels can be divided into four different levels, namely EL0, EL1, EL2, and EL3. Among them, EL0 is the lowest privilege level for executing ordinary applications. EL1 is a high privilege level for executing the operating system kernel. EL2 is used for virtualization support, allowing virtualization software (such as a hypervisor) to run at this level. EL3 is the highest privilege level for security monitoring and trusted execution environments. It can be understood that the processor can divide the exception levels of the triggered target exceptions according to different faults of the triggered exceptions. Then, through the switching of the exception levels, the exception level of the target exception can be switched to the target exception level. For example, during the execution of an application program in the user space, when a UCE occurs, an exception at the EL0 level will be triggered. Then, through the switching of the exception levels, the exception level of this exception can be switched to the EL3 level. Correspondingly, this exception is the target exception, and EL3 is the target exception level.

[0049] In this embodiment, the exception of the target exception level does not directly use the exception vector table in the kernel space to implement exception handling, but preferentially implements exception handling in the form of firmware. That is to say, the target firmware for implementing exception handling can be set corresponding to the target exception level in advance. When an exception of the target exception level is triggered, the target firmware is preferentially used to implement exception handling. In some embodiments, the target exception level is not EL1 / EL2, but can be EL3. To ensure a smooth switch to EL3, the EA (External Abort) bit field of the SCR (Secure Configuration Register) under EL3 can be kept as 1, that is, SCR_EL3.EA is 1. At this time, regardless of the exception level at which the current program is executed, all SEA and SEI will ultimately fall into EL3, thus ensuring that the target firmware preferentially processes the target exception. Of course, if the exception level of the target exception triggered by the fault is directly designated as the target exception level, then keep this target exception level. It can also be regarded as a switch from the target exception level to this exception level.

[0050] In this embodiment, when the exception level of the target exception is not the exception level that implements exception handling in the form of firmware, exception level switching can be used to ensure that the target firmware is preferentially used to implement exception handling.

[0051] In some embodiments, the target exception is again exception-handled based on the exception vector table in the kernel space of the processor, including:

[0052] Determine the entry address of the target exception handling function; wherein, the target exception handling function is the exception handling function in the exception vector table in the kernel space for handling the target exception;

[0053] Store the entry address of the target exception handling function into the target register at the target exception level;

[0054] Based on the entry address in the target register, execute the target exception handling function in the kernel space to perform exception handling on the target exception.

[0055] It should be noted that the exception vector table contains multiple exception handling functions that can handle different exceptions. When implementing exception handling using the exception vector table, it is usually to use the exception handling functions in the exception vector table to implement exception handling. It can be understood that different exception handling functions are used to handle different exceptions. Therefore, during the process of performing exception handling on the target exception through the exception vector table, it is necessary to first determine the exception handling function for handling the target exception, that is, the target exception handling function. Furthermore, the exception handling of the target exception is implemented by means of the target exception handling function.

[0056] In the processor, each exception handling function has an entry address, and through this entry address, it is possible to jump to the corresponding exception handling function. In this embodiment, after using the target firmware to preferentially handle the target exception, in order to implement the exception handling of the target exception using the target exception handling function. After determining the target exception handling function, its entry address needs to be stored in the target register at the target exception level, and this target register is the register used to store the function return address at the target exception level. In this embodiment, this function return address is the entry address of the target exception handling function. After using the target firmware to handle the target exception, it will jump according to the function return address in this target register, so as to jump to the target exception handling function in the kernel space to implement exception handling. Specifically, this target register can be the Exception Link Register (ELR for short).

[0057] In this embodiment, after using the target firmware to implement exception handling, it is possible to jump to the kernel space by means of the entry address in the target register, so as to use the target exception handling function to implement the exception handling of the target exception.

[0058] In order to ensure that key system states and data are not lost when handling exceptions in the kernel space and to ensure that the system can be correctly restored to the state before the exception occurs after the exception handling is completed, in some embodiments of the present application, before executing the target exception handling function in the kernel space based on the entry address in the target register to perform exception handling on the target exception, the method further includes:

[0059] Store the exception status information of the target exception into the corresponding register in the kernel space.

[0060] It should be noted that the exception status information is used to represent the information of the target exception or the fault that triggers the target exception. Specifically, the exception status information can be the error information related to the exception or fault stored in the relevant registers after the target exception is triggered.

[0061] It can be understood that when the target exception level is EL3, in order to enable the subsequent target exception to be routed to the kernel space, SCR_EL3.EA can be changed to 0. However, this method can only successfully execute an exception handling once. After the subsequent target exception is triggered, since the operating system has no permission to modify the value of SCR_EL3, only exception handling in the kernel space can be achieved. Therefore, in this embodiment, the target exception is injected into EL2 / EL1 of the operating system in a software manner, that is, the firmware can always be given priority to handle the target exception, and then it can successfully jump to the kernel space. After the exception status information is stored into the corresponding register in the kernel space, it can be regarded that a target exception has occurred in the kernel space, and at this time, the target exception can be successfully handled in the kernel space.

[0062] In this embodiment, by storing the exception status information into the corresponding register in the kernel space, it can be ensured that key system states and data will not be lost when handling exceptions in the kernel space, and it can be ensured that after the exception handling is completed, it can be correctly restored to the state before the exception occurred, and directly return from the kernel space to the fault point.

[0063] In some embodiments, storing the exception status information of the target exception into the corresponding register in the kernel space includes:

[0064] Copy the values of the registers used to record the exception status information at the target exception level into the corresponding registers in the kernel space;

[0065] Based on the exception type and exception source information of the target exception, adjust the values of the target bit fields in the corresponding registers in the kernel space.

[0066] It should be noted that the registers used in the processor to record exception status information include, but are not limited to: the Exception Syndrome Register (ESR for short), the Exception Link Register, the Saved Program Status Register (SPSR for short), the Fault Address Register (FAR for short), etc. It can be understood that the aforementioned registers are set at each exception level. For example, ESR_EL1, ELR_EL1, SPSR_EL1, and FAR_EL1 are set at EL1. ESR_EL3, ELR_EL3, SPSR_EL3, and FAR_EL3 are set at EL3. The registers with the same function at different exception levels are the corresponding registers. In some embodiments, the exception levels corresponding to the kernel space include EL1 and EL2, and the target exception level is EL3. During the process of exception handling of the target exception using the target firmware, registers such as ESR_EL3, ELR_EL3, SPSR_EL3, and FAR_EL3 will record the exception status information. When copying the exception status information to the corresponding registers in the kernel space, ESR_EL3 copies to ESR_EL1, ELR_EL3 copies to ELR_EL1, and so on.

[0067] It is worth noting that since the kernel space corresponds to both EL1 and EL2 exception levels simultaneously. When considering which exception level's register to copy the information to, it can be considered whether the ARM64 server enables the Virtualization Extension (VHE). If so, copy it to the register under EL2; otherwise, copy it to the register under EL1.

[0068] In addition, considering the differences between the corresponding registers at different exception levels, it is necessary to modify the relevant bit fields during or after the copying process. Among them, the target bit field is the bit field with differences in the corresponding register. Specifically, when considering the target bit field and how to adjust it, it is necessary to ensure that the kernel space after adjustment is like a real target exception has occurred. Therefore, it is necessary to implement specific adjustments based on the exception type and exception source information of the target exception. Among them, the exception type includes synchronous exceptions and asynchronous exceptions. The exception source information includes the initial exception level divided when the target exception is triggered, that is, the exception level before the target exception switches the exception level. For example, in the scenario of copying the values of each register at the EL3 level to the corresponding register at the EL2 level, when the error type of ESR_EL3.EC is 0x25, it indicates that the exception type is a synchronous exception. At this time, if SPSR_EL3.M[3:0] == 0x9 holds, the exception source information can indicate that the exception comes from EL1h, so set ESR_EL2.EC = 0x25. If SPSR_EL3.M[3:0] == 0x8 holds, the exception source information can indicate that the exception comes from EL1t, so set ESR_EL2.EC = 0x25. If neither SPSR_EL3.M[3:0] == 0x9 nor SPSR_EL3.M[3:0] == 0x8 holds, the exception source information can indicate that the exception comes from EL0t, so set SPSR_EL3.M[3:0] == 0x9. When the error type of ESR_EL3.EC is 0x2f, it indicates that the exception type is an asynchronous exception. At this time, if SPSR_EL3.M[3:0] == 0x9 holds, the exception source information can indicate that the exception comes from EL1h, so set SPSR_EL3.M[3:0] = 0x9. If SPSR_EL3.M[3:0] == 0x8 holds, the exception source information can indicate that the exception comes from EL1t, so set SPSR_EL3.M[3:0] = 0x9. If neither SPSR_EL3.M[3:0] == 0x9 nor SPSR_EL3.M[3:0] == 0x8 holds, the exception source information can indicate that the exception comes from EL0t, so set SPSR_EL3.M[3:0] = 0x9.

[0069] In this embodiment, when copying relevant information to the corresponding registers in the kernel space, based on the difference information between the corresponding registers, some bit fields of the relevant registers are adjusted, which can avoid errors that may be caused by only copying relevant information.

[0070] In some embodiments, determining the entry address of the target exception handling function includes:

[0071] Determine the offset of the target exception handling function based on the exception type and exception source information of the target exception;

[0072] Based on the base address and offset of the exception vector table in the kernel space, determine the entry address of the target exception handling function.

[0073] It should be noted that the exception type includes synchronous exceptions and asynchronous exceptions. The exception source information includes the initial exception level divided when the target exception is triggered, that is, the exception level before the target exception switches the exception level. It can be understood that the base address of the exception vector table is its starting address, and there are different offsets between the entry addresses of different exception handling functions in it and this base address. Therefore, to determine the entry address of the target exception handling function, the offset of the entry address of the target exception handling function relative to the base address can be determined first. When determining this offset, the exception type and exception source information of the target exception need to be used. After determining the exception type of the target exception and the initial exception level of the target exception, the offset can be obtained. As Figure 2 shown, when the target exception level is EL3, the process of determining the offset of the target exception handling function includes:

[0074] Start:

[0075] Step S201: Determine whether the target exception is a synchronous exception. If so, start the synchronous exception process; if not, start the asynchronous exception process. Specifically, determine whether the error type of ESR_EL3.EC is 0x2f. If so, it indicates an asynchronous exception, such as SEI; otherwise, it is a synchronous exception, such as SEA.

[0076] Step S202: Determine whether SPSR_EL3.M[3:0] == 0x9 holds. If so, it indicates that the exception comes from EL1h, and step S203 needs to be executed; if not, step S204 is executed.

[0077] Step S203: Set the offset of the target exception handling function to 0x200, that is, the entry address of the el1h_64_sync synchronous exception. Of course, the offset of the target exception handling function can also be regarded as the offset of the exception vector table.

[0078] Step S204: Determine whether SPSR_EL3.M[3:0] == 0x8 holds. If so, it indicates that the exception comes from EL1t, and step S205 needs to be executed; if not, step S206 is executed.

[0079] Step S205: Set the offset of the target exception handling function to 0x00, that is, the entry address of the el1t_64_sync synchronous exception. Similarly, the offset of the target exception handling function can also be regarded as the offset of the exception vector table.

[0080] Step S206: If the exception comes from EL0h, set the offset of the target exception handling function to 0x400, which is the entry address of the el0h_64_sync synchronous exception.

[0081] Step S207: Determine whether SPSR_EL3.M[3:0] == 0x9 holds. If so, it means the exception comes from EL1h and step S208 needs to be executed; otherwise, step S209 is executed.

[0082] Step S208: Set the offset of the target exception handling function to 0x380, which is the entry address of the el1h_64_error asynchronous exception. Of course, the offset of the target exception handling function can also be regarded as the offset of the exception vector table.

[0083] Step S209: Determine whether SPSR_EL3.M[3:0] == 0x8 holds. If so, it means the exception comes from EL1t and step S210 needs to be executed; otherwise, step S211 is executed.

[0084] Step S210: Set the offset of the target exception handling function to 0x180, which is the entry address of the el1t_64_error asynchronous exception. Similarly, the offset of the target exception handling function can also be regarded as the offset of the exception vector table.

[0085] Step S211: If the exception comes from EL0h, set the offset of the target exception handling function to 0x580, which is the entry address of the el0h_64_error asynchronous exception.

[0086] End.

[0087] In this embodiment, based on the exception type and exception source information of the target exception, the offset of the target exception handling function can be accurately determined, and then the entry address of the target exception handling function can be obtained by combining the base address of the exception vector table.

[0088] In some embodiments, based on the entry address in the target register, the target exception handling function is executed in the kernel space to handle the target exception, including:

[0089] Execute the exception return instruction, jump to the kernel space and execute the target exception handling function according to the entry address;

[0090] Notify the kernel thread of the exception event;

[0091] Use the kernel thread to read the exception record information in the shared memory, and based on the repair situation of the target exception, handle the target exception;

[0092] Among them, the exception record information in the shared memory is the record information generated during the exception handling process of the target firmware for the target exception.

[0093] It should be noted that the exception return instruction is the ERET instruction in the processor, which will not be elaborated here. Since the entry address of the target exception handling function has been stored in the target register at the target exception level. Therefore, by executing the ERET instruction, it is possible to jump to the kernel space based on the entry address of the target exception handling function in the target register and execute the target exception handling function.

[0094] It can be understood that when performing exception handling in the kernel space, the specific exception handling process will be implemented using a kernel thread. In this embodiment, to wake up the kernel thread, it is necessary to notify it of the exception event first. Since the target exception has been processed once by the target firmware, at this time, the target exception may have been repaired or other situations. To simplify the exception handling process in the kernel thread. During the process of using the kernel thread to handle the target exception, the record information generated during the exception handling process of the target firmware for the target exception can be read first. Then, based on this information, the repair situation of the target exception can be determined. Finally, based on the repair situation of the target exception, targeted exception handling can be performed on the target exception. For example, if the repair situation indicates that the target exception has been repaired. At this time, when performing exception handling on the target exception in the kernel thread, it is only necessary to notify the operating system of the relevant logs. If the repair situation indicates that the target exception has not been repaired, but it belongs to the type that can be repaired in the kernel space. At this time, when performing exception handling on the target exception in the kernel thread, methods such as isolation and page remapping can be used to repair the target exception. If the repair situation indicates that the target exception has not been repaired and belongs to the type that cannot be repaired. At this time, when performing exception handling on the target exception in the kernel thread, the kernel can be directly panicked.

[0095] In this embodiment, during the process of using the kernel thread to perform exception handling on the target exception, the record information generated during the exception handling process of the target firmware for the target exception can be referred to, and based on this, targeted processing of the target exception can be performed, which can simplify the exception handling process in the kernel thread.

[0096] To avoid the impact caused by the exception level switch, before switching the exception level of the target exception to the target exception level, the method further includes:

[0097] Performing an operation to save the context.

[0098] Before executing the exception return instruction, jumping to the kernel space and executing the target exception handling function according to the entry address, the method further includes:

[0099] Performing an operation to restore the context.

[0100] It should be noted that the switching of the exception level will cause the values of some registers in the processor to change. To ensure that the state before the exception level switching can be restored and the impact caused by the exception level switching can be avoided, it is necessary to perform the operation of protecting the scene before the exception level switching and store the values of the registers that may be affected. After the relevant operations are processed, the operation of restoring the scene is performed to restore the values of the registers. Among them, the registers that may be affected include but are not limited to the general-purpose registers X0 - X29, the LR (Link Register) register, and the SP (Stack Pointer) register.

[0101] In this embodiment, the operation of protecting the scene and the operation of restoring the scene are respectively performed before and after the exception level switching, which can avoid the impact caused by the exception level switching.

[0102] To ensure that after the exception handling is completed, the program flow can continue smoothly, before executing the target exception handling function according to the entry address, the method further includes:

[0103] Performing the operation of protecting the scene;

[0104] After performing the exception handling on the target exception based on the repair situation of the target exception, the method further includes:

[0105] Performing the operation of restoring the scene.

[0106] It should be noted that the operation of protecting the scene and the operation of restoring the scene in this embodiment are similar to those in the previous embodiment. The difference is that this embodiment avoids the impact caused by the exception handling process. It can be understood that the exception handling program needs to save the relevant state information of the currently executing thread or process, including the program counter, register values, stack pointer, etc. The purpose of doing this is to prevent the exception handling process from damaging the scene and ensure that the execution scene can be correctly restored after the exception handling is completed. Protecting the scene can also prevent errors or exceptions during the exception handling process from spreading to other parts and maintain the stability of the system. Through the operation of restoring the scene, the operating system can restore the saved thread state information to the state before the exception occurred, enabling the program to continue executing from the place where the exception occurred. Specifically, in this embodiment, performing the operation of protecting the scene can realize the switching and stack protection process of the application program user-mode stack SP_EL0 and the kernel-mode stack SP_EL1. Performing the operation of restoring the scene can restore the user-mode stack SP_EL0 from the kernel-mode stack.

[0107] In this embodiment, the operation of protecting the scene and the operation of restoring the scene are respectively performed before and after the exception handling, which can avoid the impact caused by the exception handling process.

[0108] In some implementations, the target exception is an exception triggered in a user space or an exception triggered in a kernel space of a processor.

[0109] It should be noted that the kernel space and user space in the processor are not described in detail here. In this embodiment, no matter which space of the kernel space and the user space the exception is triggered in, the triggered exception can be processed respectively using two exception processing methods to improve the superiority of exception processing in the processor.

[0110] The following is a specific example to illustrate the exception handling method provided by the present application. Assume that a UCE in a memory failure occurs in the user space, the target exception triggered is an exception at the EL0 level, and the target exception level is EL3. Figure 3 As shown, when a UCE fault address is accessed at time t1, if the attribute of the address is a Normal memory attribute, it will trigger the hardware to generate a synchronous exception, which may be SEA; if the address is a device attribute, it will trigger the hardware to generate an asynchronous exception, which may be SEI.

[0111] Since the firmware configures the EA bit field of SCR_EL3 to 1, the program will fall into EL3 regardless of the exception level it is currently executing in. Here, it falls from EL0 to EL3. Since the exception level switch occurs, it is necessary to save the values ​​of the general registers X0-X29, LR, and SP_EL0 registers for subsequent fault recovery.

[0112] After completing the scene protection before the exception level switching, enter the exception handling function provided by the target firmware, and perform fault diagnosis by querying the information of the fault record register and the exception / interrupt information provided by the hardware. If the fault address can be repaired, the fault address is repaired and the fault is recorded in a shared memory to facilitate the subsequent kernel thread to query the fault record.

[0113] When an exception level switch occurs, the error status of the fault / exception is recorded in the SPSR_EL3, ELR_EL3, ESR_EL3 and FAR_EL3 registers. Therefore, when the fault is reported to the operating system / kernel space, these fault record information needs to be passed to the operating system to ensure that the exception can be returned normally, and follow the fault hierarchical processing and step-by-step reporting mechanism adopted by the firmware priority. Specifically, the values ​​of the SPSR_EL3, ELR_EL3, ESR_EL3 and FAR_EL3 registers are copied to SPSR_EL2 / 1, ELR_EL2 / 1, ESR_EL2 / 1 and FAR_EL2 / 1, and the contents of some bit fields need to be appropriately modified. Please refer to the adjustment of the target bit field in the above implementation method, which will not be repeated here.

[0114] Configure the EL2 / 1 exception vector table. Read the Vector Base Address Register (VBAR) under EL2, i.e., VBAR_EL2. Calculate the entry address (absolute address) of the target exception handling function by adding the base address to the offset of the exception vector table, and then assign it to ELR_EL3. Among them, the target exception handling function is the exception handling function in the exception vector table that can handle the above exceptions. Regarding the offset of the exception vector table, it can be obtained in the manner shown in Figure 2 and will not be elaborated here.

[0115] Restore the values of the general-purpose registers X0 - X29, LR, and the SP_EL0 register. Then execute ERET, and the program will jump to the kernel exception vector table specified by ELR_EL3 to execute the target exception handling function. That is, the handling function of SEA or SEI. Here, it is necessary to perform the operation of protecting the scene, Figure 3 which shows the switching and stack protection process of the application user-mode stack SP_EL0 and the kernel-mode stack SP_EL1. It will not be elaborated here. It can be understood that when performing exception handling in the kernel space, other kernel threads can be notified of the sea_notify event or the sei_notify event. Then read the fault record generated by the firmware repair to implement specific fault handling / exception handling. Specifically, the kernel thread for fault handling will read the type and severity level of the exception from the fault record. If it is a Fatal type, the kernel will directly Panic. If it is a Recoverable type, the kernel repair mechanism (such as isolation and page remapping) will be called for repair. If it is a Corrected type, no repair is required, and only the operating system will be notified by logging. After the exception handling is completed, it is necessary to restore the scene, that is, the user-mode stack SP_EL0 will be restored from the kernel-mode stack. It should be noted that for Recoverable and Corrected type errors, after the user-mode stack SP_EL0 is restored, it will return to the breakpoint of the program flow according to the address recorded in ELR_EL2 / 1 and continue to execute.

[0116] It can be understood that, Figure 3 the serial numbers and arrows in Figure 3 represent the execution order of the exception handling method, but implementing the exception handling method provided by this application is not limited to

[0117] In this embodiment, during the process where the firmware gives priority to exception handling, exceptions are injected into the operating system / kernel space through software, making full use of the existing exception vector table of the operating system for reporting, recovery, and handling of faults. Its security, reliability, flexibility in implementation, and the idea of hierarchical processing are fully guaranteed.

[0118] In the case of triggering an exception in the kernel space, the specific implementation of the exception handling method provided by this application is as Figure 4 shown. The entire process is basically similar to the Figure 3 processing process shown, except that the process of switching between the user-mode stack and the kernel-mode stack is missing, and the processing functions corresponding to the exception vector table are inconsistent. There are no essential differences in other aspects. For the similarities, refer to Figure 3 the relevant description, which will not be elaborated here.

[0119] Exemplary Apparatus

[0120] Some embodiments of this application also provide an exception handling device, which is applied to a processor, as Figure 5 shown. The exception handling device includes:

[0121] A first exception handling module 51, configured to perform exception handling on a target exception based on a target firmware when the target exception is triggered during the execution of a program flow;

[0122] A second exception handling module 52, configured to perform exception handling on the target exception again based on the exception vector table in the kernel space of the processor;

[0123] An exception return module 53, configured to return to the target fault point to continue executing the program flow after the exception handling in the kernel space is completed, where the target fault point is the breakpoint when the target exception is triggered in the program flow.

[0124] In some embodiments, the first exception handling module 51 includes:

[0125] An exception level switching unit, configured to switch the exception level of the target exception to the target exception level when the target exception is triggered during the execution of the program flow; where the target exception level is the exception level for exception handling in the form of firmware in the processor;

[0126] A first exception handling unit, configured to perform exception handling on the target exception based on the target firmware corresponding to the target exception level.

[0127] In some embodiments, the second exception handling module 52 includes:

[0128] An entry address determination unit for determining the entry address of a target exception handling function; wherein, the target exception handling function is an exception handling function in the exception vector table in the kernel space for handling a target exception.

[0129] An entry address storage unit for storing the entry address of the target exception handling function into a target register at a target exception level.

[0130] A second exception handling unit for executing the target exception handling function in the kernel space based on the entry address in the target register to handle the target exception.

[0131] In some embodiments, the apparatus further includes:

[0132] An exception information storage module for storing the exception status information of the target exception into a corresponding register in the kernel space.

[0133] In some embodiments, the exception information storage module is specifically configured to:

[0134] Copy the values of the registers for recording exception status information at the target exception level to the corresponding registers in the kernel space;

[0135] Adjust the values of the target bit fields in the corresponding registers in the kernel space based on the exception type and exception source information of the target exception.

[0136] In some embodiments, the entry address determination unit is specifically configured to:

[0137] Determine the offset of the target exception handling function based on the exception type and exception source information of the target exception;

[0138] Determine the entry address of the target exception handling function based on the base address and offset of the exception vector table in the kernel space.

[0139] In some embodiments, the second exception handling unit is specifically configured to:

[0140] Execute an exception return instruction, jump to the kernel space and execute the target exception handling function according to the entry address;

[0141] Notify the kernel thread of the exception event;

[0142] Use the kernel thread to read the exception record information in the shared memory and handle the target exception based on the repair condition of the target exception;

[0143] Wherein, the exception record information in the shared memory is the record information generated during the process of the target firmware handling the target exception.

[0144] In some embodiments, the device further includes:

[0145] A first on-site protection module, configured to perform an on-site protection operation before switching the exception level of the target exception to the target exception level;

[0146] A first on-site restoration module, configured to perform an on-site restoration operation before executing an exception return instruction, jumping to the kernel space and executing a target exception handling function according to the entry address.

[0147] In some embodiments, the device further includes:

[0148] A second on-site protection module, configured to perform an on-site protection operation before executing a target exception handling function according to the entry address;

[0149] A second on-site restoration module, configured to perform an on-site restoration operation after performing exception handling on the target exception based on the repair situation of the target exception.

[0150] In some embodiments, the target exception is an exception triggered in the user space of the processor or an exception triggered in the kernel space.

[0151] The exception handling device provided by the embodiments of the present application belongs to the same inventive concept as the exception handling method provided by the above embodiments of the present application. For technical details not described in detail in this embodiment, reference may be made to the specific processing content of the exception handling method provided by the above embodiments of the present application, which will not be elaborated herein.

[0152] Exemplary Processor and Electronic Device

[0153] Another embodiment of the present application also proposes a processor, which is configured to execute the steps in the exception handling method according to various embodiments of the present application described in the above embodiments of the present application.

[0154] Another embodiment of the present application also proposes an electronic device, including the processor in the above embodiment. Refer to Figure 6 As shown, an exemplary embodiment of the present application also provides an electronic device, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the steps in the exception handling method according to various embodiments of the present application described in the above embodiments of the present application.

[0155] The internal structure of the electronic device can be as Figure 6As shown in the figure, the electronic device includes a processor, a memory, a network interface, and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it performs the steps in the exception handling method according to various embodiments of the present application described in the above embodiments of the present application.

[0156] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0157] The memory stores a program for implementing the technical solution of the present invention and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, and so on.

[0158] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0159] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, etc.

[0160] The output device may include a device for allowing information to be output to a user, such as a display screen, a printer, a speaker, etc.

[0161] The communication interface may include any device such as a transceiver for communicating with other devices or communication networks, such as an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0162] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any of the abnormal handling methods provided in the above embodiments of the present application.

[0163] The electronic device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the electronic device may be a touch layer covering the display component, or a button, a trackball or a touchpad provided on the housing of the electronic device, or an external keyboard, touchpad or mouse, etc.

[0164] Those skilled in the art can understand that Figure 6 the structure shown in

[0165] Exemplary Computer Program Product and Storage Medium

[0166] In addition to the above methods and devices, the abnormal handling method provided by the embodiments of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor executes the steps in the abnormal handling methods according to various embodiments of the present application described in the "Exemplary Method" section above of the present application.

[0167] The computer program product can be written in any combination of one or more programming languages to execute the program code for the operations of the embodiments of the present application. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed completely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or completely on a remote computing device or server.

[0168] In addition, the embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored. The computer program is executed by a processor to execute the steps in the abnormal handling methods according to various embodiments of the present application described in the "Exemplary Method" section above of the present application.

[0169] Those of ordinary skill in the art can understand that implementing all or part of the processes in the above embodiments can be accomplished by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above various methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0170] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope recorded in this application.

[0171] The above-described embodiments merely represent several embodiments of this application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the solutions provided by the embodiments of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.

Claims

1. An exception handling method, characterized in that, Applied to a processor, the exception handling method includes: When a target exception is triggered during the execution of a program flow, perform exception handling on the target exception based on target firmware; the exception handling includes fault repair; Store the exception status information of the target exception in the corresponding register in the kernel space, and trigger the target exception again in the kernel space; Perform exception handling on the target exception again based on the exception vector table in the kernel space of the processor; After the exception handling is completed in the kernel space, return to the target fault point to continue executing the program flow, where the target fault point is the breakpoint when the target exception is triggered in the program flow.

2. The method according to claim 1, characterized in that, When a target exception is triggered during the execution of a program flow, performing exception handling on the target exception based on target firmware includes: When a target exception is triggered during the execution of a program flow, switch the exception level of the target exception to the target exception level; where the target exception level is the exception level for which the processor performs exception handling in firmware mode; Perform exception handling on the target exception based on the target firmware corresponding to the target exception level.

3. The method according to claim 2, characterized in that, Performing exception handling on the target exception again based on the exception vector table in the kernel space of the processor includes: Determine the entry address of the target exception handling function; where the target exception handling function is the exception handling function in the exception vector table in the kernel space for handling the target exception; Store the entry address of the target exception handling function in the target register at the target exception level; Based on the entry address in the target register, execute the target exception handling function in the kernel space to perform exception handling on the target exception.

4. The method according to claim 3, characterized in that, Storing the exception status information of the target exception in the corresponding register in the kernel space includes: Copy the values of the registers for recording exception status information at the target exception level to the corresponding registers in the kernel space; Adjust the values of the target bit fields in the corresponding registers in the kernel space based on the exception type and exception source information of the target exception.

5. The method according to claim 3, characterized in that, Determining the entry address of the target exception handling function includes: Determine the offset of the target exception handling function based on the exception type and exception source information of the target exception; Based on the base address of the exception vector table in the kernel space and the offset, determine the entry address of the target exception handling function.

6. The method according to claim 3, characterized in that, Based on the entry address in the target register, executing the target exception handling function in the kernel space to perform exception handling on the target exception includes: Execute an exception return instruction, jump to the kernel space and execute the target exception handling function according to the entry address; Notify the kernel thread of the exception event; Use the kernel thread to read the exception record information in the shared memory, and perform exception handling on the target exception based on the repair situation of the target exception; Where the exception record information in the shared memory is the record information generated during the exception handling of the target exception by the target firmware.

7. The method according to claim 6, characterized in that, Before switching the exception level of the target exception to the target exception level, the method further includes: Performing an operation to protect the scene; Before executing an exception return instruction and jumping to the kernel space and executing the target exception handling function according to the entry address, the method further includes: Performing an operation to restore the scene.

8. The method according to claim 6, characterized in that, Before executing the target exception handling function according to the entry address, the method further includes: Performing an operation to protect the scene; After performing exception handling on the target exception based on the repair situation of the target exception, the method further includes: Performing an operation to restore the scene.

9. The method according to claim 1, characterized in that,The target exception is an exception triggered in the user space or the kernel space of the processor.

10. An exception handling device, characterized in that, Applied to a processor, the exception handling device includes: A first exception handling module, configured to perform exception handling on the target exception based on a target firmware when a target exception is triggered during the execution of a program flow; the exception handling includes fault repair; An exception information storage module, configured to store the exception status information of the target exception in corresponding registers in the kernel space and trigger the target exception again in the kernel space; A second exception handling module, configured to perform exception handling on the target exception again based on the exception vector table in the kernel space of the processor; An exception return module, configured to return to the target fault point to continue executing the program flow after exception handling is completed in the kernel space, where the target fault point is the interruption point when the target exception is triggered in the program flow.

11. The device according to claim 10, characterized in that, The first exception handling module includes: An exception level switching unit, configured to switch the exception level of the target exception to the target exception level when a target exception is triggered during the execution of a program flow; where the target exception level is the exception level for performing exception handling in the form of firmware in the processor; A first exception handling unit, configured to perform exception handling on the target exception based on the target firmware corresponding to the target exception level.

12. The device according to claim 11, characterized in that, The second exception handling module includes: An entry address determination unit, configured to determine the entry address of the target exception handling function; where the target exception handling function is the exception handling function in the exception vector table in the kernel space for handling the target exception; An entry address storage unit, configured to store the entry address of the target exception handling function in the target register at the target exception level; A second exception handling unit, configured to execute the target exception handling function in the kernel space based on the entry address in the target register and perform exception handling on the target exception.

13. The device according to claim 12, characterized in that, The exception information storage module is specifically configured to: Copy the values of the registers for recording exception status information at the target exception level to the corresponding registers in the kernel space; Adjust the values of the target bit fields in the corresponding registers in the kernel space based on the exception type and exception source information of the target exception.

14. The device according to claim 12, characterized in that, The entry address determination unit is specifically configured to: Determine the offset of the target exception handling function based on the exception type and exception source information of the target exception; Determine the entry address of the target exception handling function based on the base address of the exception vector table in the kernel space and the offset.

15. A processor, characterized in that, The processor is configured to execute the exception handling method according to any one of claims 1 to 9.

16. An electronic device, characterized in that, Comprising: The processor according to claim 15.

17. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the exception handling method according to any one of claims 1 to 9 is implemented.

Images