Semiconductor module

Abstract

A semiconductor module includes: a first conductive portion; a second conductive portion spaced apart from the first conductive portion in a first direction; a plurality of first semiconductor elements electrically joined to the first conductive portion and spaced apart from each other in a second direction orthogonal to the first direction; and a plurality of second semiconductor elements electrically joined to the second conductive portion and spaced apart from each other in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal having a polarity opposite to that of the first input terminal; and an output terminal located on an opposite side to the two input terminals in the first direction and electrically connected to the second conductive portion. The semiconductor module further includes: a first conduction member connected to the plurality of first semiconductor elements and the second conductive portion; and a second conduction member connected to the plurality of second semiconductor elements and the second input terminal.

Description

[0001] This application is a divisional application; the parent application of this application has application number "2021800647359" and the title of the invention is "Semiconductor Module". TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor module. BACKGROUND

[0003] In the past, a semiconductor module provided with a power switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is known. Such a semiconductor module is mounted on various electronic devices from industrial equipment to home appliances, information terminals, and automotive equipment. In Patent Literature 1, a conventional semiconductor module (power module) is disclosed. The semiconductor module described in Patent Literature 1 is provided with a semiconductor element and a support substrate (ceramic substrate). The semiconductor element is, for example, an IGBT made of Si (silicon). The support substrate supports the semiconductor element. The support substrate includes an insulating base material and a conductor layer laminated on both surfaces of the base material. The base material is composed of, for example, ceramic. Each conductor layer is composed of, for example, Cu (copper), and the semiconductor element is bonded to one of the conductor layers.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2015-220382 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] In recent years, energy saving, high performance, and miniaturization of electronic devices are required. Therefore, improvement in performance and miniaturization of semiconductor modules mounted on electronic devices are required.

[0009] In view of the above, an object of the present disclosure is to provide a semiconductor module having a preferred module configuration in terms of equalization of parasitic inductance components in a path of a main circuit current and equalization of the amount of current flowing to a semiconductor element.

[0010] MEANS FOR SOLVING THE PROBLEMS

[0011] The semiconductor module provided by the present disclosure has: an electrically conductive substrate having a main surface and a back surface separated from each other by a distance in a thickness direction; at least one semiconductor element electrically joined to the main surface and having a switching function; a conduction member that constitutes a path of a main circuit current switched by the semiconductor element; a first input terminal and a second input terminal disposed on one side in a first direction orthogonal to the thickness direction with respect to the electrically conductive substrate; and at least one output terminal disposed on the other side in the first direction with respect to the electrically conductive substrate. The electrically conductive substrate includes a first electrically conductive portion and a second electrically conductive portion disposed at a distance from each other in the first direction. The at least one semiconductor element includes a plurality of first semiconductor elements electrically joined to the first electrically conductive portion and a plurality of second semiconductor elements electrically joined to the second electrically conductive portion. The plurality of first semiconductor elements are disposed at a distance from each other in a second direction that is orthogonal to both the thickness direction and the first direction. The plurality of second semiconductor elements are disposed at a distance from each other in the second direction. The first input terminal is electrically connected to the first electrically conductive portion. The second input terminal is opposite in polarity to the first input terminal. The output terminal is electrically connected to the second electrically conductive portion. The conduction member includes a first conduction member connected to the plurality of first semiconductor elements and the second electrically conductive portion, and a second conduction member connected to the plurality of second semiconductor elements and the second input terminal.

[0012] Inventive Effects

[0013] According to the above-described structure, a module configuration that is preferable in terms of equalizing parasitic inductance components in the path of the main circuit current and equalizing the amount of current flowing to the semiconductor elements can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a perspective view of the semiconductor module of the first embodiment.

[0015] Figure 2 is a perspective view in which the sealing resin, the resin portion, and the resin filling portion are omitted from Figure 1 .

[0016] Figure 3 is a perspective view in which the conduction member is omitted from Figure 2 .

[0017] Figure 4 is a plan view showing the semiconductor module of the first embodiment.

[0018] Figure 5 is a plan view in which the sealing resin, the resin portion, and the resin filling portion are shown by imaginary lines in the plan view of Figure 4 .

[0019] Figure 6 is a partial enlarged view of a portion of Figure 5 , omitting the sealing resin, the resin portion, and the imaginary line of the resin filling portion.

[0020] Figure 7 is a partial enlarged view of a portion of Figure 6 .

[0021] Figure 8 is a view in which a portion of the conduction member is shown with an imaginary line in a plan view of Figure 5 .

[0022] Figure 9 is a front view showing the semiconductor module of the first embodiment.

[0023] Figure 10 is a bottom view showing the semiconductor module of the first embodiment.

[0024] Figure 11 is a left side view showing the semiconductor module of the first embodiment.

[0025] Figure 12 is a right side view showing the semiconductor module of the first embodiment.

[0026] Figure 13 is a sectional view along the XIII-XIII line of Figure 5 .

[0027] Figure 14 is a sectional view along the XIV-XIV line of Figure 5 .

[0028] Figure 15 is a partial enlarged view of a portion of Figure 14 .

[0029] Figure 16 is a sectional view along the XVI-XVI line of Figure 5 .

[0030] Figure 17 is a sectional view along the XVII-XVII line of Figure 5 .

[0031] Figure 18 is a sectional view along the XVIII-XVIII line of Figure 5 .

[0032] Figure 19 is a sectional view along the XIX-XIX line of Figure 5 .

[0033] Figure 20 is an example of a circuit configuration of the semiconductor module of the first embodiment.

[0034] Figure 21 is a plan view showing one step of the manufacturing method of the semiconductor module of the first embodiment.

[0035] Figure 22 is a cross-sectional schematic view showing one step of the manufacturing method of the semiconductor module of the first embodiment.

[0036] Figure 23 is a plan view showing one step of the manufacturing method of the semiconductor module of the first embodiment.

[0037] Figure 24 is a cross-sectional view of a part of the manufacturing method of the first embodiment, corresponding to the cross-section shown in Figure 13 .

[0038] Figure 25 is a main part enlarged cross-sectional view showing one step of the manufacturing method of the semiconductor module of the first embodiment, corresponding to a view in which a part of the cross-section shown in Figure 13 is enlarged.

[0039] Figure 26 is a main part enlarged cross-sectional view showing one step of the manufacturing method of the semiconductor module of the first embodiment, corresponding to a view in which a part of the cross-section shown in Figure 14 is enlarged.

[0040] Figure 27 is a main part enlarged cross-sectional view showing one step of the manufacturing method of the semiconductor module of the first embodiment, corresponding to a view in which a part of the cross-section shown in Figure 14 is enlarged.

[0041] Figure 28 is a main part enlarged cross-sectional view showing one step of the manufacturing method of the semiconductor module of the first embodiment, corresponding to a view in which a part of the cross-section shown in Figure 13 is enlarged.

[0042] Figure 29 is a main part enlarged cross-sectional view showing one step of the manufacturing method of the semiconductor module of the first embodiment, corresponding to a view in which a part of the cross-section shown in Figure 14 is enlarged.

[0043] Figure 30 is a plan view showing the semiconductor module of the second embodiment, which is the same as Figure 5 .

[0044] Figure 31 is a partial enlarged view of a part of Figure 30 , in which the imaginary lines of the sealing resin, the resin part, and the resin filling part are omitted.

[0045] Figure 32 is a partial enlarged view of a portion of Figure 31 .

[0046] Figure 33 is a plan view of the semiconductor module of the third embodiment, and is the same as Figure 5 .

[0047] Figure 34 is a sectional view along line XXXIV-XXXIV of Figure 33 . DETAILED DESCRIPTION

[0048] A preferred embodiment of the semiconductor module of the present disclosure will be described below with reference to the accompanying drawings. In the following description, the same symbols are affixed to identical or similar constituent elements, and repeated description is omitted.

[0049] Figures 1-20 is a plan view of the semiconductor module A1 of the first embodiment. The semiconductor module A1 is provided with a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal support 5, a conductive member 6, a first conductive joining material 71, a second conductive joining material 72, a plurality of metal wires 731 to 735, an encapsulating resin 8, a resin portion 87, and a resin filling portion 88.

[0050] Figure 1 is a perspective view of the semiconductor module A1. Figure 2 is a view in which the encapsulating resin 8, the resin portion 87, and the resin filling portion 88 are omitted in the perspective view of Figure 1 . Figure 3 is a view in which the conductive member 6 is omitted in the perspective view of Figure 2 . Figure 4 is a plan view of the semiconductor module A1. Figure 5 is a view in which the encapsulating resin 8, the resin portion 87, and the resin filling portion 88 are shown by imaginary lines in the plan view of Figure 4 . Figure 6 is a partial enlarged view of a portion of Figure 5 . In Figure 6 , the imaginary lines of the encapsulating resin 8, the resin portion 87, and the resin filling portion 88 are omitted. Figure 7 is a partial enlarged view of a portion of Figure 6 . Figure 8 is a view in which a portion (a second conductive member 62 described later) of the conductive member 6 is shown by imaginary lines in the plan view of Figure 5 . Figure 9 is a front view of the semiconductor module A1. Figure 10 is a bottom view of the semiconductor module A1.Figure 11 is a left side view of the semiconductor module Al. Figure 12 is a right side view of the semiconductor module Al. Figure 13 is a sectional view along the XIII-XIII line of Figure 5 . Figure 14 is a sectional view along the XIV-XIV line of Figure 5 . Figure 15 is an enlarged view of a part of Figure 14 . Figure 16 is a sectional view along the XVI-XVI line of Figure 5 . Figure 17 is a sectional view along the XVII-XVII line of Figure 5 . Figure 18 is a sectional view along the XVIII-XVIII line of Figure 5 . Figure 19 is a sectional view along the XIX-XIX line of Figure 5 . Further, in Figure 2 , Figure 3 , Figure 7 , Figure 14 , Figure 18 , a plurality of wires 731 to 735 are omitted. Figure 20 is an example of a circuit configuration of the semiconductor module Al. In the circuit diagram of Figure 20 , only one of a plurality of first semiconductor elements 10A (described later) and a plurality of second semiconductor elements 10B (described later) are described, and the other first semiconductor elements 10A and the other second semiconductor elements 10B are omitted.

[0051] For convenience of explanation, three directions, that is, an x direction, a y direction, and a z direction, which are orthogonal to each other, are referred to. The z direction is a thickness direction of the semiconductor module Al. The x direction is a left-right direction in a plan view (refer to Figure 4 ) of the semiconductor module Al. The y direction is an up-down direction in the plan view (refer to Figure 4 ) of the semiconductor module Al. One of the x directions is set to an xl direction, and the other of the x directions is set to an x2 direction. The same applies to the y direction and the z direction. In the following description, it can be said that "plan view" when viewed in the z direction. The x direction is an example of a "first direction", and the y direction is an example of a "second direction".

[0052] Multiple semiconductor elements 10 serve as the functional hubs of the semiconductor module A1. The constituent material of each semiconductor element 10 is, for example, a semiconductor material primarily composed of SiC (silicon carbide). This semiconductor material is not limited to SiC; it can also be Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride), etc. Each semiconductor element 10, for example, has a switching function Q1 (see reference MOSFET) composed of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Figure 20 The switching function Q1 is not limited to a MOSFET; it can also be other transistors, such as a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a bipolar transistor like an IGBT. All semiconductor elements 10 are the same element. Each semiconductor element 10 is, for example, an n-channel MOSFET, but it can also be a p-channel MOSFET.

[0053] like Figure 15 As shown, each semiconductor element 10 has a main surface 101 and a back surface 102. In each semiconductor element 10, the main surface 101 and the back surface 102 are spaced apart in the z-direction. The main surface 101 faces the z2 direction, and the back surface 102 faces the z1 direction.

[0054] The plurality of semiconductor elements 10 includes a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. In this embodiment, semiconductor module A1 has three first semiconductor elements 10A and three second semiconductor elements 10B. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited to this structure and can be appropriately changed according to the performance requirements of semiconductor module A1. Figure 8 In this example, three of each of the first semiconductor element 10A and the second semiconductor element 10B are configured. The number of first semiconductor elements 10A and second semiconductor elements 10B can be one, two, or more than four each. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B can be the same or different. The number of first semiconductor elements 10A and second semiconductor elements 10B is determined by the current processing capacity of semiconductor module A1.

[0055] like Figure 20As shown, semiconductor module A1 is configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A constitute the upper arm circuit of semiconductor module A1, and a plurality of second semiconductor elements 10B constitute the lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. Each first semiconductor element 10A and each second semiconductor element 10B are connected in series to form a bridging layer.

[0056] like Figure 8 as well as Figure 16 As shown, multiple first semiconductor elements 10A are respectively mounted on the conductive substrate 2. Figure 8 In the example shown, a plurality of first semiconductor elements 10A are arranged, for example, in the y-direction and spaced apart from each other. Each first semiconductor element 10A is electrically bonded to the conductive substrate 2 (the first conductive portion 2A described later) via a second conductive bonding material 72. When each first semiconductor element 10A is bonded to the first conductive portion 2A, the back surface 102 of the element is opposite to the first conductive portion 2A.

[0057] like Figure 8 as well as Figure 17 As shown, multiple second semiconductor elements 10B are respectively mounted on the conductive substrate 2. Figure 8 In the example shown, a plurality of second semiconductor elements 10B are arranged, for example, in the y-direction, spaced apart from each other. Each second semiconductor element 10B is electrically bonded to the conductive substrate 2 (the second conductive portion 2B described later) via a second conductive bonding material 72. When each second semiconductor element 10B is bonded to the second conductive portion 2B, the back surface 102 of the element faces the second conductive portion 2B. Figure 8 As is understood, when viewed in the x-direction, a plurality of first semiconductor elements 10A overlap with a plurality of second semiconductor elements 10B, but this disclosure is not limited thereto.

[0058] Multiple semiconductor elements 10 (multiple first semiconductor elements 10A and multiple second semiconductor elements 10B) each have a first main surface electrode 11, a second main surface electrode 12, and a back electrode 15. The structures of the first main surface electrode 11, the second main surface electrode 12, and the back electrode 15, as described below, are common in each semiconductor element 10. The first main surface electrode 11 and the second main surface electrode 12 are disposed on the main surface 101 of the element. The first main surface electrode 11 and the second main surface electrode 12 are insulated by an insulating film (not shown). The back electrode 15 is disposed on the back surface 102 of the element.

[0059] The first main surface electrode 11 is, for example, a gate electrode, into which a drive signal (e.g., gate voltage) is input to drive the semiconductor element 10. In each semiconductor element 10, the second main surface electrode 12 is, for example, a source electrode, through which source current flows. The back electrode 15 is, for example, a drain electrode, through which drain current flows. The back electrode 15 covers substantially the entire area of ​​the back surface 102 of the element. The back electrode 15 is, for example, made of Ag plating.

[0060] If a drive signal (gate voltage) is input to the first main surface electrode 11 (gate electrode) via the aforementioned switching function Q1, each semiconductor element 10 switches between an on state and an off state according to the drive signal. The action of switching between these on and off states is called a switching operation. In the on state, current flows from the back electrode 15 (drain electrode) to the second main surface electrode 12 (source electrode); in the off state, no current flows. That is, each semiconductor element 10 performs a switching operation via the switching function Q1. The semiconductor module A1, through the switching function Q1 of the multiple semiconductor elements 10, converts, for example, a first power supply voltage (DC voltage) input between one input terminal 41 and two input terminals 42 and 43 into a second power supply voltage (AC voltage), and outputs the second power supply voltage from the output terminal 44. Input terminals 41-43 and output terminal 44 are both power supply terminals for processing power supply voltages. Input terminals 41-43 are the first power supply terminals for inputting the first power supply voltage. Output terminal 44 is the second power supply terminal for outputting the second power supply voltage.

[0061] Several of the multiple semiconductor elements 10 (in) Figure 8 The example shown has two units (Q1 and D1), which, in addition to the aforementioned switching function unit Q1, also have a diode function unit D1 (see reference). Figure 20 In semiconductor module A1, one of a plurality of first semiconductor elements 10A (configured in...) Figure 8 The first semiconductor element 10A (located on the side closest to the y2 direction) and one of the plurality of second semiconductor elements 10B (configured in Figure 8 The second semiconductor element 10B, located on the side closest to the y1 direction, includes a switching function unit Q1 and a diode function unit D1. The function and role of the diode function unit D1 are not particularly limited; for example, a temperature sensing diode can be used. Furthermore, Figure 20 The diode D2 shown is, for example, a parasitic diode component of the switching function unit Q1.

[0062] like Figure 8As shown, the semiconductor device 10 with diode function section D1, in addition to having a first main surface electrode 11, a second main surface electrode 12, and a back electrode 15, also has a third main surface electrode 13, a fourth main surface electrode 14, and a fifth main surface electrode 16. The structures of the third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16, as described below, are common in all semiconductor devices 10 with diode function section D1. The third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16 are formed on the main surface 101 of the device. In the semiconductor device 10 with diode function section D1, the third main surface electrode 13 and the fourth main surface electrode 14 are connected to the diode function section D1. The fifth main surface electrode 16 is, for example, a source sensing electrode, representing the source current in the current switching function section Q1.

[0063] like Figure 7 As shown, each of the first semiconductor elements 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 when viewed from above. Figure 7 The diagram shows a first semiconductor element 10A arranged in the y-direction, with the one positioned at the center. The other first semiconductor elements 10A also have a first side 191, a second side 192, a third side 193, and a fourth side 194. The first side 191 and the second side 192 extend in the y-direction. The first side 191 is the edge on the x2 direction side when viewed from above, and the second side 192 is the edge on the x1 direction side when viewed from above. The third side 193 and the fourth side 194 extend in the x-direction. The third side 193 is the edge on the y2 direction side when viewed from above, and the fourth side 194 is the edge on the y1 direction side when viewed from above. Each first semiconductor element 10A is rectangular in shape when viewed from above, therefore the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are approximately right angles when viewed from above. Figure 7 As shown, the four corners do not overlap with the conductive components 6 (the first conductive component 61 and the second conductive component 62 described later) when viewed from above. The lengths of the third side 193 and the fourth side 194 are greater than the lengths of the first side 191 and the second side 192.

[0064] The conductive substrate 2 is also called a lead frame. The conductive substrate 2 supports multiple semiconductor elements 10. The conductive substrate 2 is bonded to the support substrate 3 via a first conductive bonding material 71. The conductive substrate 2 is, for example, rectangular in shape when viewed from above. The conductive substrate 2, together with the conducting member 6, forms the path of the main circuit current switched by the multiple semiconductor elements 10.

[0065] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each a plate-shaped member made of metal. The metal is, for example, Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B constitute, together with a plurality of input terminals 41 to 43 and a plurality of output terminals 44, a conduction path to the plurality of semiconductor elements 10. As shown in Figures 13-18 , the first conductive portion 2A and the second conductive portion 2B are each joined to the support substrate 3 via a first conductive joining material 71. In the first conductive portion 2A, a plurality of first semiconductor elements 10A are each joined via a second conductive joining material 72. In the second conductive portion 2B, a plurality of second semiconductor elements 10B are each joined via the second conductive joining material 72. As shown in Figure 3 , Figure 8 , Figure 13 and Figure 14 , the first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction. In the example shown in the above-described drawing, the first conductive portion 2A is located closer to the x2 direction than the second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each, for example, rectangular in plan view. The first conductive portion 2A and the second conductive portion 2B overlap in the x direction. The first conductive portion 2A and the second conductive portion 2B each have, for example, a dimension of 15 mm to 25 mm (preferably about 20 mm) in the x direction, a dimension of 30 mm to 40 mm (preferably about 35 mm) in the y direction, and a dimension of 1.5 mm to 3.0 mm (preferably about 2.0 mm) in the z direction.

[0066] The conductive substrate 2 has a main surface 201 and a back surface 202. As shown in Figure 13 , Figure 14 and Figures 16-18 , the main surface 201 and the back surface 202 are spaced apart in the z direction. The main surface 201 faces the z2 direction, and the back surface 202 faces the z1 direction. The main surface 201 is a surface in which the upper surface of the first conductive portion 2A and the upper surface of the second conductive portion 2B are brought together. The back surface 202 is a surface in which the lower surface of the first conductive portion 2A and the lower surface of the second conductive portion 2B are brought together. The back surface 202 is joined to the support substrate 3 in such a manner as to face the support substrate 3. As shown in Figure 5 , Figure 8 and Figure 13As shown, a plurality of recessed portions 201a are formed in the main surface 201. Each of the recessed portions 201a is a portion recessed in the z direction from the main surface 201. The degree of recess (depth) of each of the recessed portions 201a is, for example, more than 0 μm and 100 μm or less. Each of the recessed portions 201a is formed, for example, at the time of the mold forming described later. The plurality of recessed portions 201a include a recessed portion of the main surface 201 formed in the first conductive portion 2A and a recessed portion of the main surface 201 formed in the second conductive portion 2B. The two recessed portions 201a of the main surface 201 formed in the first conductive portion 2A are spaced apart in the y direction and overlap when viewed in the y direction. The two recessed portions 201a of the main surface 201 formed in the second conductive portion 2B are spaced apart in the y direction and overlap when viewed in the y direction.

[0067] The conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B) includes a base material 21, a main surface bonding layer 22, and a back surface bonding layer 23 stacked one on another. The base material 21 is a plate-shaped member made of metal. The metal is Cu or a Cu alloy. The main surface bonding layer 22 is formed on the upper surface of the base material 21. The main surface bonding layer 22 is a surface layer on the z2 direction side of the conductive substrate 2. The upper surface of the main surface bonding layer 22 corresponds to the main surface 201 of the conductive substrate 2. The main surface bonding layer 22 is, for example, plated Ag. The back surface bonding layer 23 is formed on the lower surface of the base material 21. The back surface bonding layer 23 is a surface layer on the z1 direction side of the conductive substrate 2. The lower surface of the back surface bonding layer 23 corresponds to the back surface 202 of the conductive substrate 2. The back surface bonding layer 23 is, like the main surface bonding layer 22, for example, plated Ag.

[0068] The support substrate 3 supports the conductive substrate 2. The support substrate 3 is, for example, composed of a DBC (Direct Bonded Copper) substrate. The support substrate 3 includes an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.

[0069] The insulating layer 31 is, for example, a ceramic excellent in thermal conductivity. As such a ceramic, for example, there is AlN (aluminum nitride). The insulating layer 31 is not limited to a ceramic and can be an insulating resin sheet or the like. The insulating layer 31 is, for example, rectangular in plan view.

[0070] The first metal layer 32 is formed on the upper surface (the surface facing the z2 direction) of the insulating layer 31. The constituent material of the first metal layer 32 includes, for example, Cu. The constituent material can include Al instead of Cu. The first metal layer 32 includes a first portion 32A and a second portion 32B. The first portion 32A and the second portion 32B are spaced apart in the x direction. The first portion 32A is located on the x2 direction side of the second portion 32B. The first portion 32A is bonded to the first conductive portion 2A and supports the first conductive portion 2A. The second portion 32B is bonded to the second conductive portion 2B and supports the second conductive portion 2B. The first portion 32A and the second portion 32B are, for example, rectangular in plan view, respectively.

[0071] The first joining layer 321 is formed on the upper surface of the first metal layer 32 (each of the first portion 32A and the second portion 32B). The first joining layer 321 is, for example, plated Ag. The first joining layer 321 is provided in order to make the joining with the solid-phase diffusion formed by the first conductive joining material 71 good.

[0072] The second metal layer 33 is formed on the lower surface (the surface facing the zl direction) of the insulating layer 31. The constituent material of the second metal layer 33 is the same as that of the first metal layer 32. In Figure 10 In the example shown, the lower surface (the bottom surface 302 described later) of the second metal layer 33 is exposed from the sealing resin 8, for example. The lower surface can also be covered with the sealing resin 8 without being exposed from the sealing resin 8. The second metal layer 33 overlaps both the first portion 32A and the second portion 32B when viewed from above.

[0073] As Figures 13-18 shown, the support substrate 3 has a support surface 301 and a bottom surface 302. The support surface 301 and the bottom surface 302 are spaced apart in the z direction. The support surface 301 faces the z2 direction, and the bottom surface 302 faces the zl direction. As Figure 10 shown, the bottom surface 302 is exposed from the sealing resin 8. The support surface 301 is the upper surface of the first joining layer 321, and is a surface in which the upper surface of the first portion 32A and the upper surface of the second portion 32B are brought together. The support surface 301 opposes the conductive substrate 2 and is joined to the conductive substrate 2. The bottom surface 302 is the lower surface of the second metal layer 33. On the bottom surface 302, a heat dissipation member (for example, a heat sink) or the like, not shown, can be mounted. The dimension of the support substrate 3 in the z direction (the distance in the z direction from the support surface 301 to the bottom surface 302) is, for example, 0.7 mm to 2.0 mm.

[0074] The plurality of input terminals 41 to 43 and the plurality of output terminals 44 are each composed of a plate-shaped metal plate. The constituent material of the metal plate is, for example, Cu or a Cu alloy. In Figures 1-5 , Figure 8 and Figure 10 In the example shown, the semiconductor module Al has three input terminals 41 to 43 and two output terminals 44.

[0075] A power supply voltage is applied between the three input terminals 41 to 43. In this embodiment, input terminal 41 is the positive terminal (P terminal), and the two input terminals 42 and 43 are the negative terminals (N terminals). Alternatively, input terminal 41 can be the negative terminal (N terminal), and the two input terminals 42 and 43 can be the positive terminals (P terminals). In this case, the wiring inside the package can be appropriately modified by changing the polarity of the terminals to make them consistent. The three input terminals 41 to 43 and the two output terminals 44 each include a portion covered by the encapsulating resin 8 and a portion exposed from the resin side of the encapsulating resin 8.

[0076] like Figure 14 As shown, the input terminal 41 is integrally formed with the first conductive portion 2A. Unlike this structure, the input terminal 41 is separate from the first conductive portion 2A, but can also be electrically connected to the first conductive portion 2A. Figure 8 As shown, the input terminal 41 is located on the x2 direction side relative to the plurality of first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). The input terminal 41 is conductive to the first conductive portion 2A, and is also conductive to the back electrode 15 (drain electrode) of each first semiconductor element 10A via the first conductive portion 2A. The input terminal 41 is an example of a "first input terminal".

[0077] The input terminal 41 has an input-side mating surface 411 and an input-side side surface 412. The input-side mating surface 411 faces the z2 direction and extends towards the x2 direction. The input-side side surface 412, when viewed in the z-direction, is located at the periphery of the input-side mating surface 411 and faces the direction intersecting the input-side mating surface 411. In this embodiment, the input-side side surface 412 includes a front end surface 413 and a pair of side surfaces 414. The front end surface 413 is located at the x2 direction side end of the input terminal 41 and faces the x2 direction. The pair of side surfaces 414 are located at both ends of the input terminal 41 in the y-direction and face the y1 and y2 directions, respectively. At least one of the front end surface 413 and the pair of side surfaces 414 has an input-side machining mark on the input-side side surface 412. This input-side machining mark is formed by the cutting process of the lead frame, which will be described later.

[0078] like Figure 8 As shown, the two input terminals 42 and 43 are spaced apart from the first conductive part 2A. The two input terminals 42 and 43 are respectively connected to the second conductive member 62. Figure 8As shown in FIG. 1, the two input terminals 42, 43 are located on the x2 direction side with respect to the plurality of first semiconductor elements 10A and the first conductive portion 2A (the conductive substrate 2). The two input terminals 42, 43 are in conduction with the second conductive member 62, and are in conduction with the second main surface electrode 12 (the source electrode) of each of the second semiconductor elements 10B via the second conductive member 62. The input terminal 42 is an example of a "second input terminal", and the input terminal 43 is an example of a "third input terminal".

[0079] The input terminals 42, 43 have input-side bonding surfaces 421, 431 and input-side side surfaces 422, 432. The input-side bonding surfaces 421, 431 face the z2 direction and extend toward the x2 direction side. The input-side side surfaces 422, 432 are located at the periphery of the input-side bonding surfaces 421, 431 when viewed in the z direction and face a direction that intersects the input-side bonding surfaces 421, 431. In the present embodiment, the input-side side surface 422 includes a front end surface 423 and a pair of side surfaces 424. The front end surface 423 is located at the x2 direction side end of the input terminal 42 and faces the x2 direction. The pair of side surfaces 424 are located at both ends in the y direction of the input terminal 42 and face the y1 direction and the y2 direction. In the input-side side surface 422, at least one of the front end surface 423 and the pair of side surfaces 424 has an input-side processed mark. The input-side processed mark is formed by the cutting processing of the lead frame described later. The input-side side surface 432 includes a front end surface 433 and a pair of side surfaces 434. The front end surface 433 is located at the x2 direction side end of the input terminal 43 and faces the x2 direction. The pair of side surfaces 434 are located at both ends in the y direction of the input terminal 43 and face the y1 direction and the y2 direction. In the input-side side surface 432, at least one of the front end surface 433 and the pair of side surfaces 434 has an input-side processed mark. The input-side processed mark is formed by the cutting processing of the lead frame described later.

[0080] As shown in FIG. 1, Figures 1-5 , Figure 8 and Figure 10 , the three input terminals 41 to 43 each protrude from the sealing resin 8 toward the x2 direction in the semiconductor module Al. The three input terminals 41 to 43 are spaced apart from each other. The two input terminals 42, 43 are located on opposite sides of the input terminal 41 in the y direction. The input terminal 42 is located on the y2 direction side of the input terminal 41, and the input terminal 43 is located on the y1 direction side of the input terminal 41. The three input terminals 41 to 43 overlap each other when viewed in the y direction.

[0081] As understood from Figure 8 and Figure 14 , the two output terminals 44 are each formed integrally with the second conductive portion 2B. Unlike the present structure, the output terminals 44 can be separate from the second conductive portion 2B and can be in conduction with the second conductive portion 2B. As shown in FIG. 1,Figure 8 As shown, the two output terminals 44 are located on the x1 direction side relative to the plurality of second semiconductor elements 10B and the second conductive portion 2B (conductive substrate 2), respectively. Each output terminal 44 is conductive to the second conductive portion 2B, and is also conductive to the back electrode 15 (drain electrode) of each second semiconductor element 10B via the second conductive portion 2B. The two output terminals 44 are examples of a "first output terminal" and a "second output terminal".

[0082] The output terminal 44 has an output-side mating surface 441 and an output-side side surface 442. The output-side mating surface 441 faces the z2 direction and extends towards the x1 direction. When viewed in the z direction, the output-side side surface 442 is located at the periphery of the output-side mating surface 441 and faces the direction intersecting the output-side mating surface 441. In this embodiment, the output-side side surface 442 includes a front end surface 443 and a pair of side surfaces 444. The front end surface 443 is located at the x1 direction side end of the output terminal 44 and faces the x1 direction. The pair of side surfaces 444 are located at both ends of the output terminal 44 in the y direction and face the y1 and y2 directions, respectively. At least one of the front end surface 443 and the pair of side surfaces 444 has an output-side machining mark. This output-side machining mark is formed by the cutting process of the lead frame described later. Furthermore, the number of output terminals 44 is not limited to two; for example, it can be one or more. For example, if there is only one output terminal 44, it is desirable to connect it to the central portion in the y direction of the second conductive part 2B.

[0083] The plurality of control terminals 45 are pin-shaped terminals used to control each semiconductor element 10. The plurality of control terminals 45 include a plurality of first control terminals 46A-46E and a plurality of second control terminals 47A-47D. The plurality of first control terminals 46A-46E are used to control each first semiconductor element 10A. The plurality of second control terminals 47A-47D are used to control each second semiconductor element 10B.

[0084] Multiple first control terminals 46A to 46E are arranged at intervals in the y-direction. For example... Figure 8 as well as Figure 14 As shown, each of the first control terminals 46A to 46E is supported on the first conductive portion 2A via the control terminal support 5 (the first support portion 5A described later). Figure 5 as well as Figure 8 As shown, in the x-direction, each of the first control terminals 46A to 46E is located between the plurality of first semiconductor elements 10A and the three input terminals 41 to 43.

[0085] The first control terminal 46A is a terminal (gate terminal) for inputting a drive signal to the plurality of first semiconductor elements 10A. A drive signal (for example, a gate voltage is applied) for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A.

[0086] The first control terminal 46B is a terminal (source sensing terminal) for detecting a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the plurality of first semiconductor elements 10A. The voltage applied to each second main surface electrode 12 (source electrode) of the plurality of first semiconductor elements 10A is detected by the first control terminal 46B.

[0087] The first control terminal 46C and the first control terminal 46D are terminals that are turned on with the diode function portion D1. The first control terminal 46C is turned on with the third main surface electrode 13 of the first semiconductor element 10A having the diode function portion D1, and the first control terminal 46D is turned on with the fourth main surface electrode 14 of the first semiconductor element 10A having the diode function portion D1.

[0088] The first control terminal 46E is a terminal (drain sensing terminal) for detecting a voltage (a voltage corresponding to a drain current) applied to each back surface electrode 15 (drain electrode) of the plurality of first semiconductor elements 10A. The voltage applied to each back surface electrode 15 (drain electrode) of the plurality of first semiconductor elements 10A is detected by the first control terminal 46E.

[0089] The plurality of second control terminals 47A to 47D are arranged at intervals in the y direction. As shown in FIG. 1, FIG. 2, and the like, each second control terminal 47A to 47D is supported to the second conductive portion 2B via the control terminal support body 5 (the second support portion 5B described later). As shown in FIG. 1, FIG. 2, and the like, in the x direction, each second control terminal 47A to 47D is positioned between the plurality of second semiconductor elements 10B and the two output terminals 44. Figure 5 Figure 18 Figure 5 Figure 8

[0090] The plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) each include a bracket 451 and a metal pin 452.

[0091] The bracket 451 is composed of an electrically conductive material. As shown in FIG. 1, FIG. 2, and the like, the bracket 451 is formed in a rectangular shape. Figure 15 ​​​​As shown, the bracket 451 is joined with the control terminal support 5 (the first metal layer 52 described later) via the electrically conductive joining material 459. The bracket 451 includes a cylindrical portion, an upper end flange portion, and a lower end flange portion. The upper end flange portion is connected to the upper side of the cylindrical portion, and the lower end flange portion is connected to the lower side of the cylindrical portion. The metal pin 452 is inserted through at least the upper end flange portion and the cylindrical portion of the bracket 451. The upper surface of the upper end flange portion is exposed from the sealing resin 8 (the second protruding portion 852 described later) and is covered by the resin portion 87.

[0092] The metal pin 452 is a rod-shaped member extending in the z direction. The metal pin 452 is supported by being press-fitted into the bracket 451. The metal pin 452 is in conduction with the control terminal support 5 (the first metal layer 52 described later) at least via the bracket 451. As shown in the example, in a case where the lower end (the end portion on the z1 direction side) of the metal pin 452 is in contact with the electrically conductive joining material 459 within the insertion hole of the bracket 451, the metal pin 452 is in conduction with the control terminal support 5 via the electrically conductive joining material 459. Figure 15

[0093] The control terminal support 5 supports a plurality of control terminals 45. The control terminal support 5 is interposed between the main surface 201 (the conductive substrate 2) and the plurality of control terminals 45.

[0094] The control terminal support 5 includes a first support portion 5A and a second support portion 5B. The first support portion 5A is disposed on the first conductive portion 2A of the conductive substrate 2 and supports a plurality of first control terminals 46A to 46E among the plurality of control terminals 45. As shown, the first support portion 5A is joined with the first conductive portion 2A via a joining material 59. The joining material 59 can be either electrically conductive or insulating, and, for example, solder is used. The second support portion 5B is disposed on the second conductive portion 2B of the conductive substrate 2 and supports a plurality of second control terminals 47A to 47D among the plurality of control terminals 45. The second support portion 5B is joined with the second conductive portion 2B via the joining material 59. Figure 15

[0095] The control terminal support 5 (each of the first support portion 5A and the second support portion 5B) is composed of, for example, a DBC substrate. The control terminal support 5 has an insulating layer 51, a first metal layer 52, and a second metal layer 53 laminated with each other.

[0096] The insulating layer 51 is composed of, for example, ceramic. The insulating layer 51 is, for example, rectangular in plan view.

[0097] As shown, the first metal layer 52 is formed on the upper surface of the insulating layer 51. Each of the control terminals 45 is erected on the first metal layer 52. The first metal layer 52 is, for example, Cu or a Cu alloy. As shown, the second metal layer 53 is formed on the lower surface of the insulating layer 51. The second metal layer 53 is, for example, Cu or a Cu alloy. Figure 15 Figure 8 ​​​As shown, the first metal layer 52 includes a first part 521, a second part 522, a third part 523, a fourth part 524, and a fifth part 525. The first part 521, the second part 522, the third part 523, the fourth part 524, and the fifth part 525 are spaced apart from each other and insulated from each other.

[0098] The first part 521 is connected to a plurality of metal wires 731, and is connected to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 via each metal wire 731. Figure 8 As shown, the first control terminal 46A is engaged with the first part 521 of the first support part 5A, and the second control terminal 47A is engaged with the first part 521 of the second support part 5B.

[0099] The second part 522 is connected to a plurality of metal wires 732, and is connected to the second main surface electrode 12 (source electrode) of each semiconductor element 10 via each metal wire 732. Figure 8 As shown, the first control terminal 46B is engaged with the second part 522 of the first support part 5A, and the second control terminal 47B is engaged with the second part 522 of the second support part 5B.

[0100] The third part 523 is connected to the metal wire 733, and is connected to the third main electrode 13 of the semiconductor element 10 having the diode function part D1 via the metal wire 733. Figure 8 As shown, the first control terminal 46C is engaged with the third part 523 of the first support part 5A, and the second control terminal 47C is engaged with the third part 523 of the second support part 5B.

[0101] The fourth part 524 is connected to the metal wire 734, and is connected to the fourth main electrode 14 of the semiconductor element 10 having the diode function part D1 via the metal wire 734. For example... Figure 8 As shown, the first control terminal 46D is engaged with the fourth part 524 of the first support part 5A, and the second control terminal 47D is engaged with the fourth part 524 of the second support part 5B.

[0102] The fifth part 525 of the first support part 5A is joined to the metal wire 735, and is connected to the first conductive part 2A via the metal wire 735. The fifth part 525 of the second support part 5B is not connected to other structural parts. Figure 8 As shown, the first control terminal 46E is engaged with the fifth part 525 of the first support part 5A.

[0103] like Figure 15 As shown, a second metal layer 53 is formed on the lower surface of the insulating layer 51. Figure 15 As shown, the second metal layer 53 of the first support portion 5A is bonded to the first conductive portion 2A via a bonding material 59.

[0104] The second metal layer 53 of the second support portion 5B is bonded to the second conductive portion 2B via a bonding material 59.

[0105] The conductive component 6, together with the conductive substrate 2, forms the path of the main circuit current switched by the plurality of semiconductor elements 10. The conductive component 6 is spaced apart from the main surface 201 (conductive substrate 2) in the z2 direction and overlaps with the main surface 201 when viewed from above. In this embodiment, the conductive component 6 is made of a metal sheet. This metal is, for example, Cu or a Cu alloy. Specifically, the conductive component 6 is a bent metal sheet. It is not limited to this; the conductive component 6 may also be made of metal foil. In this embodiment, the conductive component 6 includes a plurality of first conductive components 61 and second conductive components 62. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current is the current that forms a path between the input terminal 41 and the output terminal 44. The second main circuit current is the current that forms a path between the output terminal 44 and the input terminals 42 and 43.

[0106] Multiple first conductive components 61 are respectively coupled to the second main surface electrode 12 (source electrode) and the second conductive portion 2B of each first semiconductor element 10A, thereby making the second main surface electrode 12 and the second conductive portion 2B of each first semiconductor element 10A conductive. Each first conductive component 61 and the second main surface electrode 12 of each first semiconductor element 10A (see reference 2B) Figure 8 The first conductive component 61 and the second conductive part 2B are respectively bonded by a conductive bonding material 69. The conductive bonding material 69 is, for example, solder, metal paste, or sintered metal. Figure 8 As shown, each of the first conductive components 61 is a strip-shaped structure extending along the x-direction when viewed from above.

[0107] In this embodiment, such as Figure 6 As shown, in each of the first conductive members 61, an opening 61h is formed in the rectangular portion connecting each first semiconductor element 10A and the second conductive portion 2B. The opening 61h is preferably formed in the center of the rectangle when viewed from above, for example, as a through hole extending in the z-direction. When a fluid resin material is injected to form a sealing resin, an opening 61h is formed near each of the first conductive members 61 to facilitate the flow of the resin material between the upper side (z2 direction side) and the lower side (z1 direction side). The planar shape of the opening 61h can be a perfect circle, an ellipse, a rectangle, or other shapes. The shape of the first conductive member 61 is not limited to this structure; for example, the opening 61h may not be formed.

[0108] In the present embodiment, three first conduction members 61 are provided corresponding to the number of the first semiconductor elements 10A. As a modification, one first conduction member 61 common to the plurality of first semiconductor elements 10A can be used regardless of the number of the first semiconductor elements 10A.

[0109] The second conduction member 62 conduction-connects the second main surface electrode 12 of each second semiconductor element 10B with each input terminal 42, 43. The maximum dimension of the second conduction member 62 in the x direction is, for example, 25 mm to 40 mm (preferably, about 32 mm), and the maximum dimension in the y direction is, for example, 30 mm to 45 mm (preferably, about 38 mm). As shown in FIG. 6, the second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. Figure 6

[0110] The first wiring portion 621 is connected with the input terminal 42. The first wiring portion 621 is joined with the input terminal 42 by the conductive joining material 69. The first wiring portion 621 is a band-like portion extending in the x direction in plan view.

[0111] The second wiring portion 622 is connected with the input terminal 43. The second wiring portion 622 is joined with the input terminal 43 by the conductive joining material 69. The second wiring portion 622 is a band-like portion extending in the x direction in plan view. The first wiring portion 621 and the second wiring portion 622 are arranged apart in the y direction and substantially in parallel. The second wiring portion 622 is located in the yl direction with respect to the first wiring portion 621.

[0112] The third wiring portion 623 is connected with both the first wiring portion 621 and the second wiring portion 622. The third wiring portion 623 is a band-like portion extending in the y direction in plan view. As understood from FIG. 6, the third wiring portion 623 overlaps the plurality of second semiconductor elements 10B in plan view. Figure 6 As shown in FIG. 6, the third wiring portion 623 is connected with each second semiconductor element 10B. The third wiring portion 623 has a plurality of concave regions 623a. As shown in FIG. 6, each concave region 623a protrudes more toward the zl direction than other portions of the third wiring portion 623. Each concave region 623a in the third wiring portion 623 is joined with each second semiconductor element 10B. Each concave region 623a of the third wiring portion 623 is joined with the second main surface electrode 12 (see FIG. 4) of each second semiconductor element 10B via the conductive joining material 69. Figure 17 Figure 17 Figure 8

[0113] ​​​​The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. In addition, the fourth wiring portion 624 is connected to the third wiring portion 623. The fourth wiring portion 624 is located on the x2 direction side than the third wiring portion 623. As Figure 6 As understood, the fourth wiring portion 624 overlaps the plurality of first semiconductor elements 10A when viewed from above. The fourth wiring portion 624 includes a first strip portion 625 and a plurality of second strip portions 626.

[0114] The first strip portion 625 is spaced apart from the third wiring portion 623 in the x direction, and is a portion of the fourth wiring portion 624 that is strip-shaped when viewed from above. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622. The first strip portion 625 overlaps the plurality of first semiconductor elements 10A when viewed from above. The first strip portion 625 has a plurality of convex regions 625a. As Figure 16 As shown, each convex region 625a protrudes more toward the z2 direction than other portions of the first strip portion 625. As Figure 6 As shown, each convex region 625a overlaps each first semiconductor element 10A when viewed from above. As Figure 16 As shown, the first strip portion 625 has a plurality of convex regions 625a, and thus regions for bonding each first conduction member 61 are provided on each first semiconductor element 10A. Thus, the first strip portion 625 is prevented from contacting each first conduction member 61.

[0115] The plurality of second strip portions 626 are respectively connected to the first strip portion 625 and the third wiring portion 623. Each second strip portion 626 is a strip-shaped portion that extends in the x direction when viewed from above. The plurality of second strip portions 626 are spaced apart in the y direction and are arranged substantially in parallel. When viewed from above, one end of each of the plurality of second strip portions 626 is connected to between two first semiconductor elements 10A adjacent in the y direction among the first strip portion 625, and the other end is connected to between two second semiconductor elements 10B adjacent in the y direction among the third wiring portion 623.

[0116] The first strip portion 625 has a first end edge 627 and a second end edge 628. As Figure 7 As shown, the first end edge 627 is located on the x1 direction side than the first side 191 when viewed from above, and extends in the y direction at least from the third side 193 to the fourth side 194. Thus, when viewed from above, two corners 171, 172 on the x2 direction side of each first semiconductor element 10A do not overlap the second conduction member 62, respectively. The two corners are a corner 171 between the first side 191 and the third side 193, and a corner 172 between the first side 191 and the fourth side 194. Thus, in each first semiconductor element 10A, when viewed from above (in detail, when viewed from above in the direction of the arrow A1 in FIG. 1, for example), the second conduction member 62 does not overlap the first semiconductor element 10A. Figure 7Under the conditions shown (and so on), a portion of each of the two sides sandwiching angles 171 and 172 can be seen. Figure 7 As shown, the second edge 628, when viewed from above, is located further in the x2 direction than the second side 192, and extends at least from the third side 193 to 194 in the y direction. Therefore, when viewed from above, the two corners 173 and 174 on the x1 direction side of each first semiconductor element 10A do not overlap with the second conductive member 62. These two corners are the angle 173 formed by the second side 192 and the third side 193, and the angle 174 formed by the second side 192 and the fourth side 194. Therefore, in each first semiconductor element 10A, when viewed from above, a portion of each of the two sides sandwiching each corner 173 and 174 can be seen.

[0117] Of the aforementioned angles 171, 172, 173, and 174, the length of the portion sandwiching each angle 171, 172, 173, and 174 that is visible when viewed from above should be greater than 0 μm and less than 200 μm. Furthermore, when viewed from above, the length of the portion visible on each side sandwiching each angle 171, 172, 173, and 174 is preferably 5 μm or more and less than 150 μm. When the length of the portion visible on each side sandwiching each angle 171, 172, 173, and 174 is 2 μm or more, the angle of the first semiconductor element 10A can be detected; when the length of the portion visible on each side is 5 μm or more, the angle of the first semiconductor element 10A can be reliably detected. However, when the length of the portion visible on each side exceeds 200 μm, the bonding area between the first conducting member 61 and the first semiconductor element 10A becomes smaller than required, which is therefore not preferred. As long as the upper limit of the length of the visible portion on both sides is less than 150 μm, the junction area between the first conductive component 61 and the first semiconductor element 10A can be avoided from becoming too small, which is therefore preferable.

[0118] like Figure 6 As shown, the conducting member 6 (first conducting member 61 and second conducting member 62) has a first portion 601. The first portion 601 is the area that overlaps with the semiconductor element 10 (any one of the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B) when viewed from above. In the second conducting member 62, a portion of the fourth wiring portion 624 (the area that overlaps with the plurality of first semiconductor elements 10A when viewed from above) and a portion of the third wiring portion 623 (the area that overlaps with the plurality of second semiconductor elements 10B when viewed from above) constitute the first portion 601.

[0119] like Figure 6 , Figure 8As shown, the main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A (the first semiconductor element 10A having a diode functional section D1) are arranged along the y-direction at the end of the first semiconductor element 10A on the x2 direction side. In a top view, the first conducting member 61 and the second conducting member 62 do not overlap with any of the main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A, or any of the corners 171 and 172 on the x2 direction side. Furthermore, in a top view, the first conducting member 61 and the second conducting member 62 do not overlap with at least one of the corners 173 and 174 on the x1 direction side of the first semiconductor element 10A (the side opposite to the side where the main surface electrodes are disposed). Therefore, in a top view, at least three of the four corners 171, 172, 173, and 174 of the semiconductor element 10A can be seen. Therefore, with the semiconductor element 10A, the first conductive component 61, and the second conductive component 62 assembled on the conductive substrate 2, the correct assembly of the semiconductor element 10A can be checked by automatic visual inspection. When viewed from above, all four corners 171, 172, 173, and 174 of the semiconductor element 10A are also visible. Furthermore, the aforementioned main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A are an example of a "one-sided main surface electrode".

[0120] In addition, such as Figure 6 As shown, each of the second semiconductor elements 10B, when viewed from above, is also rectangular in shape, similar to the first semiconductor element 10A, and has four corners 181, 182, 183, and 184 corresponding to the four corners 171, 172, 173, and 174 of the first semiconductor element 10A. The top-view relationship between the four corners 171, 172, 173, and 174 of each of the first semiconductor elements 10A and the first conducting member 61 and the second conducting member 62 is also the same as the top-view relationship between the four corners 181, 182, 183, and 184 of each of the second semiconductor elements 10B and the second conducting member 62.

[0121] like Figure 5 As shown, the second conductive member 62 includes a first portion 62A and a second portion 62B. The first portion 62A overlaps with the main surface 201 of the conductive substrate 2 (the main surface 201 of either the first conductive portion 2A or the second conductive portion 2B) when viewed from above, and does not overlap with any of the plurality of semiconductor elements 10 when viewed from above. The second portion 62B overlaps with the main surface 201 when viewed from above, and also overlaps with any of the plurality of semiconductor elements 10 when viewed from above. Figure 5 In the diagram, the first part 62A is marked with a rightward rising shadow line, and the second part 62B is marked with a rightward falling shadow line. The first part 62A has an opening 63. (As shown...) Figure 5 as well as Figure 13As shown in FIG. 1, the opening 63 is a portion that is partially cut away when viewed from above. In the present embodiment, the opening 63 overlaps the main surface 201 of the first conductive substrate 2 (the conductive substrate 2) when viewed from above, and is positioned so as not to overlap the plurality of semiconductor elements 10 when viewed from above. The opening 63 is, for example, a through-hole that penetrates in the z direction. The opening 63 has a portion formed in the first wiring portion 621 and a portion formed in the second wiring portion 622. The opening 63 is provided near at least two of the corners of the conductive substrate 2 when viewed from above, and is provided on the x2 direction side in each of the first wiring portion 621 and the second wiring portion 622, for example. Furthermore, the planar shape of the opening 63 is not limited, and can be a hole as in the present embodiment, or a cutout different from the present embodiment. The opening 63 can also be produced by electroforming or the like, for example. In this case, the second through member 62 has the opening 63 composed of a portion where metal is not deposited, rather than a portion that has been removed.

[0122] In the second through member 62, a rectangular portion that overlaps each first semiconductor element 10A when viewed from above is formed with an opening 625h. In the present embodiment, the opening 625h is preferably formed so as to overlap the central portion of each first semiconductor element 10A when viewed from above. The opening 625h is, for example, a through-hole formed in each convex region 625a of the above-described first band-shaped portion 625 (the fourth wiring portion 624) (see FIG. 1). Figure 6 The opening 625h is used when the first through member 61 is joined to the first semiconductor element 10A, in order to optically confirm the state of the joining from above.

[0123] In the second through member 62, a rectangular portion that overlaps each second semiconductor element 10B when viewed from above is formed with an opening 623h. In the present embodiment, the opening 623h is preferably formed so as to overlap the central portion of the second semiconductor element 10B when viewed from above. The opening 623h is, for example, a through-hole formed in each concave region 623a of the above-described third wiring portion 623. The opening 623h is used when the second through member 62 is positioned with respect to the conductive substrate 2. The planar shape of the above-described two openings 623h, 625h can be a perfect circle, or an elliptical shape, a rectangular shape, or another shape.

[0124] The shape of the second through member 62 is not limited to the present structure, and can not include the fourth wiring portion 624, for example. However, in terms of reducing the inductance value generated by current flowing in the second through member 62, it is preferable that the fourth wiring portion 624 be provided in the second through member 62.

[0125] The first conductive joining material 71 is interposed between the conductive substrate 2 and the support substrate 3, and electrically conducts and joins the conductive substrate 2 and the support substrate 3. The first conductive joining material 71 has a portion that electrically conducts and joins the first conductive portion 2A and the first portion 32A, and a portion that electrically conducts and joins the second conductive portion 2B and the second portion 32B. As shown in FIG. 7, the first conductive joining material 71 has a first base layer 711, a first layer 712, and a second layer 713 that are layered one on another. Figure 15

[0126] As shown in FIG. 7, the side surface of the first conductive joining material 71 and the side surface of the first metal layer 32, which is the uppermost layer of the support substrate 3, are most preferably the same surface. It is preferable that the side surface of the first metal layer 32 be located slightly inward of the side surface of the first conductive joining material 71 when viewed from above. That is, the side surface of the first metal layer 32 is joined so as not to extend more outward than the side surface of the first conductive joining material 71 when viewed from above. In the case where the side surface of the first metal layer 32 extends more outward than the side surface of the first conductive joining material 71 when viewed from above, the along-surface distance between the first metal layer 32 and the second metal layer 33 becomes small, and thus is not preferable. Furthermore, the side surface of the first metal layer 32 is disposed more outward than the side surface of the base material 21 of the conductive substrate 2 when viewed from above. Figure 15

[0127] The first base layer 711 is a metal, and the metal is, for example, Al (aluminum) or an Al alloy. The first base layer 711 is a sheet. The Young's modulus of Al as a material constituting the first base layer 711 is 70.3 GPa.

[0128] The first layer 712 is formed on the upper surface of the first base layer 711. The first layer 712 is interposed between the first base layer 711 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The first layer 712 is, for example, Ag plating. The first layer 712 is joined to the respective back surface joining layer 23 of the first conductive portion 2A and the second conductive portion 2B, for example, by solid-phase diffusion of the metal. That is, the first layer 712 and the respective back surface joining layer 23 of the first conductive portion 2A and the second conductive portion 2B are joined by solid-phase diffusion joining. Thereby, the first layer 712 and the respective back surface joining layer 23 are joined in a state of directly contacting each other at the joining interface. Furthermore, in the present disclosure, "A and B are joined by solid-phase diffusion joining" means that, as a result of performing solid-phase diffusion joining, A and B are fixed to each other in a state of directly contacting each other at the joining interface, and it can be said that a solid-phase diffusion joining layer is constituted by A and B. In the case where solid-phase diffusion joining is performed under ideal conditions, there is a case where the joining interface does not exist significantly due to diffusion of metal elements. On the other hand, in the case where an intermediate such as an oxide film exists on the surface of A and B, or a gap exists between A and B, there is a case where these intermediates or gaps exist at the joining interface.

[0129] ​​The second layer 713 is formed on the lower surface of the first base layer 711. The second layer 713 is interposed between the first base layer 711 and the support substrate 3 (each of the first portion 32A and the second portion 32B). The second layer 713 is, for example, plated Ag. The second layer 713 is joined to the first joining layer 321 formed on the first portion 32A and the second portion 32B, respectively, by solid-phase diffusion of the metal. That is, the second layer 713 is joined to the first joining layer 321 by solid-phase diffusion joining to be joined in a state of directly contacting each other at the joining interface. The Young's modulus of the plated Ag (silver) as the constituent material of the first layer 712 and the second layer 713 is 82.7 GPa.

[0130] In the first conductive joining material 71, the constituent material of the first base layer 711 and each of the constituent materials of the first layer 712 and the second layer 713 are the above-described materials, and thus the Young's modulus of the first base layer 711 is smaller than the Young's modulus of the first layer 712 and the second layer 713. The thickness (z-direction dimension) of the first base layer 711 is larger than each of the thicknesses of the first layer 712 and the second layer 713.

[0131] In the first conductive joining material 71, plated Ag is not formed on the end surface of the first base layer 711 that is Al or an Al alloy, and the end surface of the first base layer 711 is exposed. However, plated Ag can be formed on the end surface of the first base layer 711. From the viewpoint of reducing the manufacturing cost of the first conductive joining material 71, it is preferable to form plated Ag on both surfaces of a large-area sheet, and then to produce the first conductive joining material 71 by cutting the sheet with plated Ag. From this viewpoint, it is preferable that plated Ag is not formed on the end surface of the first base layer 711.

[0132] The second conductive joining material 72 is interposed between the conductive substrate 2 and each of the semiconductor elements 10 to join the conductive substrate 2 and each of the semiconductor elements 10 in conduction. The second conductive joining material 72 has a portion that joins each of the first semiconductor elements 10A and the first conductive portion 2A in conduction and a portion that joins each of the second semiconductor elements 10B and the second conductive portion 2B in conduction. As shown in FIG. 2, the second conductive joining material 72 includes a second base layer 721, a third layer 722, and a fourth layer 723 that are stacked on each other. Figure 15

[0133] The second base layer 721 is a metal, for example, Al or an Al alloy. The second base layer 721 is a sheet.

[0134] ​A third layer 722 is formed on the upper surface of the second base layer 721. The third layer 722 is located between the second base layer 721 and each semiconductor element 10. The third layer 722 is, for example, Ag plating. The third layer 722 is bonded to the back electrode 15 of each semiconductor element 10, for example, by solid-phase diffusion of the metal. That is, the third layer 722 and the back electrode 15 are bonded by solid-phase diffusion bonding, so that they are bonded in a state where they are directly in contact with each other at the bonding interface.

[0135] A fourth layer 723 is formed on the lower surface of the second base layer 721. The fourth layer 723 is located between the second base layer 721 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The fourth layer 723 is, for example, plated with Ag. The fourth layer 723 is bonded to the main surface bonding layers 22 of the first conductive portion 2A and the second conductive portion 2B, for example, by solid-phase diffusion of the metal. That is, the fourth layer 723 is bonded to each main surface bonding layer 22 by solid-phase diffusion bonding, so that they are bonded in a state where they are directly in contact with each other at the bonding interface.

[0136] In the second conductive bonding material 72, the constituent materials of the second base layer 721 and the constituent materials of the third layer 722 and the fourth layer 723 are the same as those described above. Therefore, the Young's modulus of the second base layer 721 is smaller than that of the third layer 722 and the fourth layer 723. The thickness (z-direction dimension) of the second base layer 721 is larger than that of the third layer 722 and the fourth layer 723.

[0137] In the second conductive bonding material 72, no Ag plating is formed on the end face of the second base layer 721, which is Al or an Al alloy, and the end face of the second base layer 721 is exposed. However, Ag plating may also be formed on the end face of the second base layer 721. From the viewpoint of reducing the manufacturing cost of the second conductive bonding material 72, it is preferable to form Ag plating on both sides of a sheet of area, and then manufacture the second conductive bonding material 72 by cutting the sheet with Ag plating. According to this viewpoint, it is preferable not to form Ag plating on the end face of the second base layer 721.

[0138] Multiple metal wires 731-735 respectively conduct electricity between two spaced-apart portions. The multiple metal wires 731-735 are, for example, bonding leads. The constituent materials of the multiple metal wires 731-735 include, for example, any one of Au (gold), Al, or Cu.

[0139] like Figure 8 As shown, multiple metal wires 731 are respectively connected to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 and the first part 521 (first metal layer 52) of each control terminal support 5, making them conductive. Figure 8As shown, the plurality of metal wires 731 includes a plurality of first metal wires 731a and a plurality of second metal wires 731b. The plurality of first metal wires 731a are respectively connected to the first main surface electrodes 11 (gate electrodes) of the respective first semiconductor elements 10A and the first portions 521 (first metal layers 52) of the first support portions 5A. Thus, the first control terminals 46A are connected to the first main surface electrodes 11 (gate electrodes) of the respective first semiconductor elements 10A via the respective first metal wires 731a. The plurality of second metal wires 731b are respectively connected to the first main surface electrodes 11 (gate electrodes) of the respective second semiconductor elements 10B and the first portions 521 (first metal layers 52) of the second support portions 5B. Thus, the second control terminals 47A are connected to the first main surface electrodes 11 (gate electrodes) of the respective second semiconductor elements 10B via the respective second metal wires 731b.

[0140] As shown, the plurality of metal wires 732 are respectively connected to the second main surface electrodes 12 (source electrodes) of the respective semiconductor elements 10 and the second portions 522 (first metal layers 52) of the respective control terminal support bodies 5, so as to connect them. However, in the respective semiconductor elements 10 having the diode function portions Dl, the respective metal wires 732 are connected to the fifth main surface electrodes 16 (source sensing electrodes) instead of the second main surface electrodes 12 (source electrodes). Figure 8 As shown, the plurality of metal wires 733 are respectively connected to the third main surface electrodes 13 of the respective semiconductor elements 10 having the diode function portions Dl and the third portions 523 (first metal layers 52) of the respective control terminal support bodies 5, so as to connect them.

[0141] Figure 8 As shown, the plurality of metal wires 734 are respectively connected to the fourth main surface electrodes 14 of the respective semiconductor elements 10 having the diode function portions Dl and the fourth portions 524 (first metal layers 52) of the respective control terminal support bodies 5, so as to connect them.

[0142] As shown, the metal wire 735 is connected to the main surface 201 in the first conductive portion 2A (conductive substrate 2) and the fifth portion 525 (first metal layer 52) of the first support portion 5A (control terminal support body 5), so as to connect them. Figure 8 As shown, the metal wire 735 is connected to the main surface 201 in the first conductive portion 2A (conductive substrate 2) and the fifth portion 525 (first metal layer 52) of the first support portion 5A (control terminal support body 5), so as to connect them.

[0143] Figure 8 As shown, the metal wire 735 is connected to the main surface 201 in the first conductive portion 2A (conductive substrate 2) and the fifth portion 525 (first metal layer 52) of the first support portion 5A (control terminal support body 5), so as to connect them.

[0144] ​​The sealing resin 8 covers a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3 (except for the bottom surface 302), a portion of each of a plurality of input terminals 41-43, a portion of each of a plurality of output terminals 44, a portion of each of a plurality of control terminals 45, a control terminal support 5, a conductive component 6, and a plurality of metal wires 731-735. The sealing resin 8 is, for example, made of black epoxy resin. The sealing resin 8 is formed, for example, by molding as described later. The sealing resin 8 has a dimension of approximately 35 mm to 60 mm in the x-direction, approximately 35 mm to 50 mm in the y-direction, and approximately 4 mm to 15 mm in the z-direction. The above dimensions are the size of the largest portion in each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831-834.

[0145] like Figure 9 , Figure 11 as well as Figure 12 As shown, the resin main surface 81 and the resin back surface 82 are spaced apart in the z-direction. The resin main surface 81 faces the z2 direction, and the resin back surface 82 faces the z1 direction. Multiple control terminals 45 (multiple first control terminals 46A-46E and multiple second control terminals 47A-47D) protrude from the resin main surface 81. Figure 10 As shown, the resin back surface 82 is a frame-like structure that surrounds the bottom surface 302 (lower surface of the second metal layer 33) of the support substrate 3 when viewed from above. The bottom surface 302 of the support substrate 3 protrudes from the resin back surface 82, for example, being the same surface as the resin back surface 82. Multiple resin side surfaces 831-834 are respectively connected to both the resin main surface 81 and the resin back surface 82, and are sandwiched between them in the z-direction. Figure 4 As shown, resin side 831 and resin side 832 are spaced apart in the x-direction. Resin side 831 faces the x1 direction, and resin side 832 faces the x2 direction. Two output terminals 44 protrude from resin side 831, and three input terminals 41-43 protrude from resin side 832. Figure 4 As shown, resin side surface 833 and resin side surface 834 are spaced apart in the y-direction. Resin side surface 833 faces the y1 direction, and resin side surface 834 faces the y2 direction.

[0146] like Figure 4 As shown, a plurality of recesses 832a are formed on the resin side surface 832. Each recess 832a is a portion that is recessed in the x-direction when viewed from above. The plurality of recesses 832a have portions formed between input terminals 41 and 42 and between input terminals 41 and 43 when viewed from above. The plurality of recesses 832a are provided to increase the surface distances along the resin side surface 832 between input terminals 41 and 42, and between input terminals 41 and 43.

[0147] As shown in FIG. 1, the sealing resin 8 has a plurality of first protruding portions 851, a plurality of second protruding portions 852, and a resin gap portion 86. Figure 13 Figure 14 As shown in FIG. 1, the sealing resin 8 has a plurality of first protruding portions 851, a plurality of second protruding portions 852, and a resin gap portion 86.

[0148] The plurality of first protruding portions 851 protrude in the z direction from the resin main surface 81, respectively. The plurality of first protruding portions 851 are arranged near the four corners of the sealing resin 8 in plan view. At the front end (end portion in the z2 direction) of each first protruding portion 851, a first protruding end surface 851a is formed. Each first protruding end surface 851a in the plurality of first protruding portions 851 is substantially parallel to the resin main surface 81 and is on the same plane (x-y plane). Each first protruding portion 851 is, for example, a hollow frustoconical shape. The plurality of first protruding portions 851 are used as spacers when the semiconductor module Al is mounted on a circuit board or the like for control possessed by an apparatus using a power supply generated by the semiconductor module Al. The plurality of first protruding portions 851 each have a recessed portion 851b and an inner wall surface 851c formed on the inner wall surface 851c of the recessed portion 851b. The shape of each first protruding portion 851 can be a columnar shape, and is preferably a cylindrical shape. The shape of the recessed portion 851b is preferably a cylindrical shape, and the inner wall surface 851c is a single circular shape in plan view.

[0149] There is a case where the semiconductor module Al is mechanically fixed by a method such as screwing with respect to a circuit board or the like for control. In this case, a screw thread can be formed on the inner wall surface 851c of the recessed portion 851b in the plurality of first protruding portions 851. It is also possible to embed a nut in the recessed portion 851b in the plurality of first protruding portions 851.

[0150] As shown in FIG. 1, the sealing resin 8 has a plurality of first protruding portions 851, a plurality of second protruding portions 852, and a resin gap portion 86. Figure 14 As shown in FIG. 1, the sealing resin 8 has a plurality of first protruding portions 851, a plurality of second protruding portions 852, and a resin gap portion 86.

[0151] As shown in FIG. 1, the sealing resin 8 has a plurality of first protruding portions 851, a plurality of second protruding portions 852, and a resin gap portion 86. Figure 13 ​As shown, the resin gap portion 86 passes from the resin main surface 81 through the recessed portion 201a formed in the main surface 201 of the conductive substrate 2 in the z direction. The resin gap portion 86 is formed in a tapered shape in which the cross-sectional area becomes smaller as it goes toward the z direction from the recessed portion 201a. The resin gap portion end edge 861 of the resin gap portion 86, which is in contact with the main surface 201, and the recessed portion end edge 201b of the recessed portion 201a, which is in contact with the main surface 201, coincide with each other. The resin gap portion 86 is formed at the time of the mold forming described later, and is a portion in which the sealing resin 8 is not formed at the time of the mold forming.

[0152] The resin portion 87 is provided on the second protruding portion 852 of the sealing resin 8. The resin portion 87 covers a portion (upper surface of the upper end flange portion) of the bracket 451 and a portion of the metal pin 452 that are exposed from the sealing resin 8 in each control terminal 45. The resin portion 87 is composed of, for example, the same epoxy resin as the sealing resin 8, but can be a different material from the sealing resin 8.

[0153] The resin filling portion 88 is filled in the resin gap portion 86 so as to bury the resin gap portion 86. The resin filling portion 88 is composed of, for example, the same epoxy resin as the sealing resin 8, but can be a different material from the sealing resin 8.

[0154] Hereinafter, the manufacturing method of the semiconductor module Al will be described with reference to Figures 21-29 The manufacturing method of the semiconductor module Al will be described. Figure 21 is a plan view showing one step of the manufacturing method of the semiconductor module Al. Figure 22 is a cross-sectional view showing one step of the manufacturing method of the semiconductor module Al. Figure 23 is a plan view showing one step of the manufacturing method of the semiconductor module Al. Figure 24 is a cross-sectional view showing one step of the manufacturing method of the semiconductor module Al. Figure 24 corresponds to the cross section shown in Figure 13 Figure 25 and Figure 28 are main part enlarged cross-sectional views showing one step of the manufacturing method of the semiconductor module Al, and correspond to views in which a portion of the cross section shown in Figure 13 is enlarged. Figure 26 , Figure 27 and Figure 29 are main part enlarged cross-sectional views showing one step of the manufacturing method of the semiconductor module Al, and correspond to views in which a portion of the cross section shown in Figure 14 is enlarged.

[0155] ​First, multiple semiconductor elements 10, conductive substrate 2, support substrate 3, multiple input terminals 41-43, and multiple output terminals 44 are prepared. The structures of the multiple semiconductor elements 10, conductive substrate 2, and support substrate 3 are as described above. During the preparation of these components, the multiple semiconductor elements 10, conductive substrate 2, and support substrate 3 are prepared separately and are not connected to each other. Furthermore, as... Figure 21 As shown, the conductive substrate 2, multiple input terminals 41-43, and multiple output terminals 44 are interconnected, for example, formed by the same lead frame. Furthermore, as... Figure 21 As shown, no recess 201a is formed on the main surface 201 of the conductive substrate 2.

[0156] Next, as Figure 22 As shown, a conductive substrate 2 is placed on a support substrate 3 with a first conductive bonding material 71 as a gap, and each semiconductor element 10 is placed on the conductive substrate 2 with a second conductive bonding material 72 as a gap. Then, while clamping the lower surface of the support substrate 3 and the upper surface of each semiconductor element 10 (see reference 1), Figure 22 (The thick arrow indicates the direction of the bonding) While heating, each semiconductor element 10 is bonded to the conductive substrate 2 via solid-state diffusion, and the conductive substrate 2 is bonded to the support substrate 3 via solid-state diffusion. Specifically, the first bonding layer 321 (support substrate 3) on the first metal layer 32 is bonded to the second layer 713 (first conductive bonding material 71), the first layer 712 (first conductive bonding material 71) is bonded to the back bonding layer 23 (conductive substrate 2), the fourth layer 723 (second conductive bonding material 72) is bonded to the main bonding layer 22 (conductive substrate 2), and the third layer 722 (second conductive bonding material 72) is bonded to the back electrode 15 of each semiconductor element 10 via solid-state diffusion. Under solid-state diffusion conditions, the heating temperature during bonding only needs to be in the range of 200°C to 350°C, and the pressure applied during bonding (the clamping force mentioned above) only needs to be in the range of 1 MPa to 100 MPa. Solid-state diffusion is assumed to be carried out in the atmosphere, but it can also be carried out in a vacuum. Thus, the conductive substrate 2 is bonded to the support substrate 3 via the first conductive bonding material 71, and each semiconductor element 10 is bonded to the conductive substrate 2 via the second conductive bonding material 72. Furthermore, the bonding of the conductive substrate 2 to the support substrate 3 and the bonding of the conductive substrate 2 to each semiconductor element 10 can be processed separately rather than together. However, for the purpose of improving manufacturing efficiency, it is preferable to process them together.

[0157] like Figure 16 as well as Figure 17 As shown, when each semiconductor element 10 is mounted on the conductive substrate 2 with a second conductive bonding material 72 between them, a separate second conductive bonding material 72 is disposed corresponding to each semiconductor element 10. However, this is not a limitation; alternatively, materials may be disposed with...Figure 16 The three semiconductor elements 10 shown are common to one second conductive bonding material 72.

[0158] Next, as shown in Figure 23 Fig. 6, the bonding of the control terminal support 5, the bonding of each of the holders 451 of the plurality of control terminals 45, the wire bonding of the plurality of wires 731 to 735, the bonding of the plurality of first conductive members 61, and the bonding of the second conductive member 62 are performed. The above-mentioned processing order is not limited.

[0159] Next, the sealing resin 8 is formed. The formation of the sealing resin 8 is performed, for example, by molding. As shown in Figure 24 Fig. 7, a metal mold 91 used in the molding is provided with a press pin 911 as a pressing member. The front end of the press pin 911 is in contact with the main surface 201 of the conductive substrate 2. At this time, a recess 201a is formed in the main surface 201 by the pressing force of the press pin 911 to the main surface 201. The degree of recess (depth) of the recess 201a is changed by the magnitude of the pressing force and the like. In addition, the press pin 911 in contact with the main surface 201 in the first conductive portion 2A is inserted in the opening 63 of the second conductive member 62. Then, a flowable resin material is injected into a cavity space 919 of the metal mold 91 in order through a resin flow path and a resin injection port (both not shown). The sealing resin 8 is formed by curing the flowable resin material after the injection. As shown in Figure 25 and Figure 26 Fig. 8, the formed sealing resin 8 has the above-mentioned first protruding portion 851, the above-mentioned second protruding portion 852, and the above-mentioned resin gap portion 86. As shown in Figure 25 Fig. 9, the resin gap portion end edge 861 in the resin gap portion 86 in contact with the main surface 201 and the recess end edge 201b in the recess 201a in contact with the main surface 201 coincide with each other. As shown in Figure 26 Fig. 10, the upper surface of the holder 451 is exposed from the second protruding portion 852 and is the same surface as the upper surface of the second protruding portion 852. In addition, as understood from Figure 24 and Figure 25 the resin gap portion 86 is formed by not filling the flowable resin material by the press pin 911. In addition, the press pin 911 can be a movable pin. In this case, the press pin 911 is preferably provided in a hole portion formed in the metal mold 91 and is elastically supported. The pressing member is not limited to a pin shape, but a block-shaped pressing member can be used.

[0160] Next, the mold 91 is opened, and the lead frame including the conductive substrate 2 and the molded body including the sealing resin 8 are taken out. Then, the sealing resin 8 is separated from the resin cured in the resin flow path and the resin injection port. In this process, the resin separation marks are formed in at least one of the two positions in the resin side surface 831 on the x1 direction side in the sealing resin 8, or the two positions near the y direction ends, or the corner portions of the y direction ends. In the case where the resin separation marks are formed in the corner portions of the y direction ends, the resin separation marks are formed in the surfaces formed in the corner portions (the portions in which the chamfering is performed in the C shape when viewed from above). The above-described bevels are included in the resin side surface 831 on the x1 direction side in the sealing resin 8. The second position is between the two output terminals 44 in the resin side surface 831 shown in Figure 1 . These resin separation marks are formed by separating the sealing resin 8 from the resin cured in the resin injection port of the mold 91. In order to suppress the bias of the spread of the resin, it is preferable to inject the resin from the central position in the y direction. In this case, the resin separation marks are formed between the two output terminals 44.

[0161] Next, as shown in Figure 27 , each metal pin 452 of the plurality of control terminals 45 is pressed into each support 451. Specifically, each metal pin 452 having a cross-sectional dimension slightly larger than the inner diameter of the cylindrical portion (see Figure 26 ) of each support 451 is inserted while an insertion pressure is applied. Thereby, each support 451 and each metal pin 452 are mechanically fixed and electrically connected. It is also possible to electrically connect each support 451 and each metal pin 452 using, for example, soldering. Then, as shown in Figure 28 and Figure 29 , the resin portion 87 and the resin filling portion 88 are formed. The formation of the resin portion 87 and the resin filling portion 88 is performed, for example, by potting.

[0162] Next, the plurality of input terminals 41 to 43 and the output terminal 44 are separated by appropriately cutting the above-described lead frame. In the input terminals 41 to 43 and the output terminal 44 shown in Figure 21 , it is sufficient to cut the vicinity of the connection portion of each terminal and the outer frame portion of the lead frame using a mold or the like (the portions shown by the broken lines in Figure 21 ). Here, the front end surfaces 413, 423, and 433 are formed as input side processing marks in the input terminals 41 to 43, respectively. The front end surface 443 is formed as an output side processing mark in the output terminal 44. In the lead frame, in the case where a drawbar connecting the terminals adjacent in the y direction in the y direction is provided, the drawbar can be cut using a mold or the like. In this case, processing marks are formed in the two side surfaces in the y direction on each terminal. By going through the above processes, the lead frame 1 shown in Figures 1-20 is manufactured.Figures 1-20 The semiconductor module Al is shown.

[0163] The semiconductor module Al is mounted to a circuit board or the like for control. Here, each metal pin 452 is inserted into a pin hole of a circuit board on which the semiconductor module Al is mounted, and connected to a terminal around the pin hole. The input terminals 41, 42, 43 each have an input-side bonding surface 411, 421, 431 toward one side (z2 direction) in the z direction. Each output terminal 44 has an output-side bonding surface 441 toward one side (z2 direction side) in the z direction. The input-side bonding surfaces 411, 421, 431 and the output-side bonding surface 441 are connected to terminals of a circuit board on which the semiconductor module Al is mounted, for example, using solder.

[0164] The paths of the currents from the input terminal 41 to the output terminal 44 in the semiconductor module Al of the present embodiment will be described below. In the path called the input terminal 41, the first conductive portion 2A, each first semiconductor element 10A, the first conduction member 61, the second conductive portion 2B, and each output terminal 44, a first main circuit current flows. Between the second main surface electrode 12 of each first semiconductor element 10A and the second conductive portion 2B, the first main circuit current flows in the x direction via each first conduction member 61. In the second conductive portion 2B, between the portion bonded to each first conduction member 61 and each output terminal 44, the first main circuit current flows in the x direction and in a direction slightly inclined from the x direction.

[0165] The paths of the currents from the output terminal 44 to the input terminal 42 and the input terminal 43 will be described below. In the path called the output terminal 44, the second conductive portion 2B, each second semiconductor element 10B, the second conduction member 62, the input terminal 42, and the input terminal 43, a second main circuit current flows. The path of the second main circuit current has the second conduction member 62, and the second main circuit current flows in both the third wiring portion 623 extending in the y direction and the first wiring portion 621 and the second wiring portion 622 connected to both ends of the third wiring portion 623 and extending in the x2 direction. Also, the two second strip portions 626 disposed between the first wiring portion 621 and the second wiring portion 622 and extending in the x direction, and the first strip portion 625 disposed between the first wiring portion 621 and the second wiring portion 622 and extending in the y direction are provided as paths, and the second main circuit current flows in the first wiring portion 621 and the second wiring portion 622.

[0166] The second main circuit current flows between the input terminal 42 and the input terminal 43 and the second main surface electrode 12 of each of the second semiconductor elements 10B, via the first wiring portion 621 and the second wiring portion 622 and the third wiring portion 623, the two second strip-shaped portions 626, and the first strip-shaped portion 625 included in each of the second conduction members 62. In the first wiring portion 621, the second wiring portion 622, and the two second strip-shaped portions 626, the second main circuit current flows in the x direction. The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows.

[0167] In the first conduction member 61, the direction in which the first main circuit current flows is the x direction, as is the direction in which the second main circuit current flows in the first wiring portion 621 and the second wiring portion 622 and the two second strip-shaped portions 626 included in the second conduction member 62.

[0168] The effects of the semiconductor module Al are as follows.

[0169] The semiconductor module Al includes the conductive substrate 2, the plurality of input terminals 41 to 43, the output terminal 44, and the conduction member 6. The conductive substrate 2 includes the first conductive portion 2A to which the plurality of first semiconductor elements 10A are bonded and the second conductive portion 2B to which the plurality of second semiconductor elements 10B are bonded. The input terminal 41 is connected to the first conductive portion 2A and is conducted with the plurality of first semiconductor elements 10A via the first conductive portion 2A. The input terminal 42 and the input terminal 43 are conducted with the plurality of second semiconductor elements 10B via the second conduction member 62 (the conduction member 6). The output terminal 44 is connected to the second conductive portion 2B and is conducted with the plurality of second semiconductor elements 10B via the second conductive portion 2B. The conduction member 6 includes the first conduction member 61 that conducts each first semiconductor element 10A with the second conductive portion 2B and the second conduction member 62 that conducts each second semiconductor element 10B with each input terminal 42, 43. The plurality of input terminals 41 to 43 are arranged on the x2 direction side with respect to the conductive substrate 2, and the output terminal 44 is arranged on the x1 direction with respect to the conductive substrate 2. Also, the two input terminals 42, 43 are arranged on opposite sides from each other in the y direction with the input terminal 41 interposed therebetween. In a semiconductor module having a different structure from the semiconductor module Al, in a case where the input terminal 43 is not provided and the input terminal 41 and the input terminal 42 are arranged side by side in the y direction, there is a possibility that a deviation occurs in a path of current flowing from the input terminal 41 to the output terminal 44 via each first semiconductor element 10A and a deviation occurs in a path of current flowing from the output terminal 44 to each input terminal 42 via each second semiconductor element 10B. Therefore, in the semiconductor module Al, the two input terminals 42, 43 are provided, and by sandwiching the input terminal 41 with the two input terminals 42, 43, it is possible to reduce the deviation in the path of current flowing from the input terminal 41 to the output terminal 44 via each first semiconductor element 10A and to reduce the deviation in the path of current flowing from the output terminal 44 to each input terminal 42, 43 via each second semiconductor element 10B. Thus, it is possible to reduce the parasitic inductance component of the semiconductor module Al. That is, the semiconductor module Al constitutes a preferred package configuration in terms of reducing the parasitic inductance component.

[0170] In the semiconductor module Al, the upper arm current path and the lower arm current path overlap when viewed from above. The upper arm current path is a path of current flowing from the input terminal 41 to each output terminal 44 via the first conductive portion 2A, each first semiconductor element 10A, each first conduction member 61, and the second conductive portion 2B, and in the present embodiment, as understood from Figure 5 the x2 direction side to the x1 direction side. The lower arm current path is a path of current flowing from the output terminal 44 to the input terminal 42 via each second semiconductor element 10B and the second conduction member 62, and in the present embodiment, as understood from Figure 5As understood, from the x1 direction side to the x2 direction side. According to this structure, the magnetic field generated by the current along the upper arm current path and the magnetic field generated by the current along the lower arm current path cancel each other out, and thus the parasitic inductance component can be reduced. In particular, in the semiconductor module Al, by the through members 6 (each of the plurality of first through members 61 and the second through members 62) being composed of a metal plate, the region in which the upper arm current path and the lower arm current path overlap when viewed from above can be appropriately ensured. That is, the semiconductor module Al constitutes a preferred package structure in terms of reducing the parasitic inductance component.

[0171] In the semiconductor module Al, the second through member 62 that constitutes the lower arm current path includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to the input terminals 42, 43 disposed on opposite sides of each other in the y direction with the input terminal 41 interposed therebetween, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to the plurality of second semiconductor elements 10B, respectively. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps the plurality of first semiconductor elements 10A when viewed from above. The second through member 62 composed of the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 is disposed apart from the main surface 201 (the conductive substrate 2) in the z direction, and overlaps a wide range of the main surface 201 when viewed from above. According to this structure, the deviation of the path of the current flowing from the output terminal 44 to each of the input terminals 42, 43 via each of the second semiconductor elements 10B can be appropriately reduced, and it is suitable for reducing the parasitic inductance component.

[0172] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x direction. According to this structure, the size of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) in which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are disposed can be suppressed from becoming large in the y direction, and the semiconductor module Al can be made small.

[0173] The fourth wiring portion 624 of the second conduction member 62 has a first strip portion 625 and a plurality of second strip portions 626. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is a portion that overlaps the plurality of first semiconductor elements 10A in plan view. The plurality of second strip portions 626 are each connected to the first strip portion 625 and the third wiring portion 623, and are strips that extend in the x direction in plan view. The plurality of second strip portions 626 are spaced apart in the y direction and are arranged substantially in parallel. In plan view, one end of each of the plurality of second strip portions 626 is connected between two first semiconductor elements 10A adjacent in the y direction among the first strip portion 625, and the other end is connected between two second semiconductor elements 10B adjacent in the y direction among the third wiring portion 623. According to this structure, the size of the fourth wiring portion 624 (the second conduction member 62) in plan view can be ensured more greatly. This is more preferable in terms of reducing the parasitic inductance component.

[0174] The first strip portion 625 has a plurality of convex regions 625a that protrude more in the z2 direction than other portions. Each of the convex regions 625a overlaps each of the first semiconductor elements 10A in plan view. According to the structure in which the first strip portion 625 has the plurality of convex regions 625a, the first strip portion 625 can be prevented from coming into undesired contact with the first conduction member 61 bonded to the first semiconductor elements 10A.

[0175] The third wiring portion 623 has a plurality of concave regions 623a that protrude more in the z1 direction than other portions. Each of the concave regions 623a is bonded to any one of the plurality of second semiconductor elements 10B. According to this structure, the third wiring portion 623 (the second conduction member 62) can be brought into appropriate conduction with the plurality of second semiconductor elements 10B, and the size of the third wiring portion 623 (the second conduction member 62) in plan view can be ensured more greatly.

[0176] In the semiconductor module Al, in addition to the conduction member 6 (the first conduction member 61 and the second conduction member 62) having the above-described structure, a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D for controlling the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are provided. The plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are each arranged to extend in the z direction on the main surface 201 of the conductive substrate 2. The semiconductor module Al of this structure can achieve a reduction in size in plan view, and is thus suitable for achieving a reduction in the parasitic inductance component while achieving a reduction in size in plan view.

[0177] The plurality of first control terminals 46A to 46E are supported by the first conductive portion 2A and are arranged on the x2 direction side than the plurality of first semiconductor elements 10A. The plurality of second control terminals 47A to 47D are supported by the second conductive portion 2B and are arranged on the x1 direction side than the plurality of second semiconductor elements 10B. The plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are arranged at intervals in the y direction, respectively. Thus, the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are appropriately arranged in regions corresponding to the plurality of first semiconductor elements 10A configuring the upper arm circuit and the plurality of second semiconductor elements 10B configuring the lower arm circuit, respectively. The semiconductor module Al of this structure is more preferable in terms of achieving reduction of parasitic inductance components while achieving miniaturization.

[0178] The first semiconductor elements 10A and the second semiconductor elements 10B each have a first main surface electrode 11 (gate electrode) toward the z2 direction. The first control terminal 46A is connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first metal wire 731a. The second control terminal 47A is connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second metal wire 731b. Thus, a drive signal for driving the first semiconductor element 10A (second semiconductor element 10B) having a switching function can be appropriately input to the first main surface electrode 11 via the first control terminal 46A (second control terminal 47A), the first metal wire 731a (second metal wire 731b).

[0179] When the semiconductor module Al is mounted to the circuit board, each metal pin 452 is inserted into a pin hole of the circuit board on which the semiconductor module Al is mounted and is connected to a terminal around the pin hole. The input terminals 41, 42, and 43 each have an input side bonding surface 411, 421, and 431 toward one side (z2 direction) of the z direction. Each output terminal 44 has an output side bonding surface 441 toward one side (z2 direction side) of the z direction. The input side bonding surfaces 411, 421, and 431 and the output side bonding surface 441 are connected to the terminals of the circuit board on which the semiconductor module Al is mounted, for example, using solder. With the above-described structure, it is possible to arrange the power system circuit board to which the input terminals 41 to 43 and the output terminal 44 are connected and the control system circuit board to which each metal pin 452 is connected separately in the z direction. Thus, first, the degree of freedom of arrangement with respect to the signal terminals in the semiconductor module Al is improved. Second, the degree of freedom of layout and length of signal wiring in the semiconductor module Al is improved. Third, when the semiconductor module Al is used, the degree of freedom of arrangement of the circuit board with respect to the user is improved.

[0180] In the semiconductor module Al, each control terminal 45 protrudes from the resin main surface 81 and extends in the z direction. In a structure different from the semiconductor module Al, there is a case where each control terminal 45 is arranged so as to extend in a plane (x-y plane) orthogonal to the z direction. In this structure, the reduction in size in plan view is limited. Therefore, as in the semiconductor module Al, by arranging each control terminal 45 so as to extend in the z direction, the reduction in size in plan view of the semiconductor module Al can be achieved. That is, the semiconductor module Al is a preferred package structure in terms of achieving the reduction in size in plan view.

[0181] In the semiconductor module Al of the present embodiment, the control terminal support body 5 is interposed between each control terminal 45 and the main surface 201 (conductive substrate 2). The control terminal support body 5 has an insulating layer 51, and each control terminal 45 is supported to the conductive substrate 2 via the control terminal support body 5. According to this structure provided with the control terminal support body 5, insulation between the conductive substrate 2 can be ensured, and each control terminal 45 can be appropriately supported on the conductive substrate 2.

[0182] The control terminal support body 5 is a layered structure body having the insulating layer 51, the first metal layer 52, and the second metal layer 53 laminated with each other. The control terminal 45 is joined to the first metal layer 52 formed on the upper surface of the control terminal support body 5 via the conductive joining material 459. According to this structure, the control terminal support body 5 can be formed using a ready-made layered structure body (for example, a DBC substrate or the like), and the control terminal 45 can be conductively joined to the control terminal support body 5 (first metal layer 52).

[0183] The semiconductor element 10 has an element main surface 101 facing the z2 direction, and an element back surface 102 facing the zl direction. The first main surface electrode 11 (gate electrode) is arranged on the element main surface 101. The first main surface electrode 11 of each semiconductor element 10 is connected to the first metal layer 52 (first portion 521) by the conductive metal wire 731. Thus, a drive signal for driving the semiconductor element 10 having a switching function can be appropriately input to the first main surface electrode 11 via the control terminal 45, the first metal layer 52, and the metal wire 731.

[0184] Each control terminal 45 includes a holder 451 and a metal pin 452. The holder 451 is composed of an electrically conductive material and is configured to include a cylindrical portion. The metal pin 452 is a rod-shaped member extending in the z-direction and is pressed into the holder 451. In addition, a portion (upper surface of the upper end flange portion) of the holder 451 is exposed from the sealing resin 8. According to this structure, the holder 451 is covered with the sealing resin 8 except for a portion (upper end surface) and the upper end surface of the holder 451 is exposed from the sealing resin 8 by the formation (molding) of the sealing resin 8. Thus, it is possible to insert the metal pin 452 into the holder 451 after the sealing resin 8 is formed. Therefore, according to the structure in which the control terminal 45 includes the holder 451 and the metal pin 452 described above, it is possible to avoid the metal mold 91 used in the molding from becoming complicated and to be suitable for efficiently manufacturing the semiconductor module Al.

[0185] The semiconductor module Al of the present embodiment is provided with the resin portion 87 bonded to the sealing resin 8. The resin portion 87 covers a portion (upper surface of the upper end flange portion) of the holder 451 and a portion of the metal pin 452 exposed from the sealing resin 8. According to this structure, it is possible to prevent the intrusion of foreign matter into the connection portion of the holder 451 and the metal pin 452. The semiconductor module Al of the structure described above is preferable in terms of improving durability and reliability.

[0186] The sealing resin 8 has a plurality of second protruding portions 852 protruding from the resin main surface 81. The plurality of second protruding portions 852 surround the plurality of control terminals 45 when viewed from above. Each metal pin 452 of the plurality of control terminals 45 protrudes from each second protruding portion 852. The resin portion 87 is disposed on each second protruding portion 852. According to this structure, it is possible to increase the along-surface distance of the control terminals 45 adjacent to each other along the resin main surface 81. It is preferable in terms of improving the withstand voltage of the control terminals 45 adjacent to each other.

[0187] The conductive substrate 2 includes first conductive portions 2A and second conductive portions 2B which are spaced apart from each other in the x direction. The first conductive portions 2A are located closer to the x2 direction than the second conductive portions 2B. The plurality of semiconductor elements 10 includes first semiconductor elements 10A which are bonded to the first conductive portions 2A, and second semiconductor elements 10B which are bonded to the second conductive portions 2B. The plurality of control terminals 45 includes first control terminals 46A to 46E and second control terminals 47A to 47D. The first control terminals 46A to 46E are supported on the first conductive portions 2A, and are located between the first semiconductor elements 10A and the input terminals 41, 42, and the like in the x direction. The second control terminals 47A to 47D are located between the second semiconductor elements 10B and the output terminal 44 in the x direction. According to this structure, the plurality of control terminals 45 (the first control terminals 46A to 46E and the second control terminals 47A to 47D) are appropriately arranged in regions corresponding to the first semiconductor elements 10A which constitute the upper arm circuit and the second semiconductor elements 10B which constitute the lower arm circuit, respectively. This structure is more preferable in terms of achieving miniaturization of the semiconductor module Al.

[0188] The sealing resin 8 has a plurality of first protruding portions 851 which protrude from the resin main surface 81. A first protruding end surface 851a is formed at a front end of each of the first protruding portions 851. Each of the first protruding end surfaces 851a in the plurality of first protruding portions 851 is substantially parallel to the resin main surface 81, and is on the same plane (x-y plane). According to this structure, in a device which uses the power supply generated by the semiconductor module Al, a predetermined gap can be ensured between a surface of a circuit substrate for control on which the semiconductor module Al is mounted and the resin main surface 81. Thus, even in the case where various functional components are mounted in the above-mentioned circuit substrate for control in opposition to the semiconductor module Al, the functional components can be prevented from being improperly contacted with the sealing resin 8.

[0189] In the semiconductor module Al, the conductive substrate 2 to which each of the semiconductor elements 10 is bonded is provided. According to this structure, heat generated by energization of each of the semiconductor elements 10 is transferred to the conductive substrate 2, and the heat transferred from each of the semiconductor elements 10 is diffused in the conductive substrate 2. Thus, the semiconductor module Al is configured as a preferable package structure in terms of improving heat dissipation of the heat of each of the semiconductor elements 10.

[0190] In the semiconductor module Al, the conductive substrate 2 and the support substrate 3 are joined via the first conductive joining material 71. The first conductive joining material 71 includes a first layer 712 and a second layer 713. The first layer 712 is joined to the conductive substrate 2 by solid-phase diffusion of a metal to be joined in a state where the joining interfaces directly contact each other. The second layer 713 is joined to the support substrate 3 by solid-phase diffusion of a metal to be joined in a state where the joining interfaces directly contact each other. According to this structure, the joining strength of the conductive substrate 2 and the support substrate 3 can be improved compared to a case where the conductive substrate 2 and the support substrate 3 are joined by a joining material such as solder. Thus, the semiconductor module Al is a preferable package structure in terms of suppressing peeling of the conductive substrate 2 and the support substrate 3.

[0191] In the semiconductor module Al, each semiconductor element 10 and the conductive substrate 2 are joined via the second conductive joining material 72. The second conductive joining material 72 includes a third layer 722 and a fourth layer 723. The third layer 722 is joined to each semiconductor element 10 (back surface electrode 15) by solid-phase diffusion of a metal to be joined in a state where the joining interfaces directly contact each other. The fourth layer 723 is joined to the conductive substrate 2 by solid-phase diffusion of a metal to be joined in a state where the joining interfaces directly contact each other. According to this structure, the joining strength of each semiconductor element 10 and the conductive substrate 2 can be improved compared to a case where each semiconductor element 10 and the conductive substrate 2 are joined by a joining material such as solder. Thus, the semiconductor module Al is a preferable package structure in terms of suppressing peeling of each semiconductor element 10 and the conductive substrate 2.

[0192] In the semiconductor module Al of the present embodiment, the Young's modulus of the first base layer 711 in the first conductive joining material 71 is smaller than the Young's modulus of each of the materials constituting the first layer 712 and the second layer 713. According to this structure, when the first conductive joining material 71 is joined to the conductive substrate 2 and the support substrate 3 by solid-phase diffusion, stress can be alleviated by the relatively soft first base layer 711, and smoothing of the joining boundary portions can be achieved. Thus, the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3 are more firmly joined by solid-phase diffusion.

[0193] In addition, in the present embodiment, the thickness of the first base layer 711 is larger than the thickness of each of the first layer 712 and the second layer 713. Thus, when joining by solid-phase diffusion is used, the pressing force applied to each of the boundary portions of the first layer 712 and the conductive substrate 2 (back surface joining layer 23), and the boundary portions of the second layer 713 and the support substrate 3 (first joining layer 321) becomes more uniform. Thus, the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3 can be brought into a more firm conductive joining state, respectively.

[0194] The first layer 712 and the second layer 713 are each composed of silver. According to this structure, when solid-phase diffusion bonding is used with the first conductive bonding material 71, oxidation of the first layer 712 and the second layer 713 can be suppressed, achieving good solid-phase diffusion bonding. Furthermore, the back bonding layer 23 and the first bonding layer 321, which are bonded to the first layer 712 and the second layer 713, also contain silver, thus achieving even better solid-phase diffusion bonding.

[0195] In this embodiment, the Young's modulus of the second base layer 721 in the second conductive bonding material 72 is smaller than that of the constituent materials of the third layer 722 and the fourth layer 723. According to this structure, when the second conductive bonding material 72 is bonded to the semiconductor element 10 (back electrode 15) and the conductive substrate 2 by solid-phase diffusion, stress can be mitigated by the relatively soft second base layer 721, achieving smoothing of the bonding boundary. Thus, the third layer 722 is more firmly bonded to the semiconductor element 10 (back electrode 15), and the fourth layer 723 is more firmly bonded to the conductive substrate 2 by solid-phase diffusion.

[0196] Furthermore, in this embodiment, the thickness of the second base layer 721 is greater than the thicknesses of the third layer 722 and the fourth layer 723. Therefore, during solid-phase diffusion bonding, the pressing pressure acting on the boundary between the third layer 722 and the semiconductor element 10 (back electrode 15), and on the boundary between the fourth layer 723 and the conductive substrate 2 (main surface bonding layer 22), becomes more uniform. Consequently, the third layer 722 and the semiconductor element 10 (back electrode 15), and the fourth layer 723 and the conductive substrate 2, can achieve a more robust conductive bonding state.

[0197] The third layer 722 and the fourth layer 723 are each composed of silver. According to this structure, when solid-state diffusion bonding is used with the second conductive bonding material 72, oxidation of the third layer 722 and the fourth layer 723 can be suppressed, achieving good solid-state diffusion bonding. Furthermore, the back electrode 15 and the main bonding layer 22, which are bonded to the third layer 722 and the fourth layer 723, also contain silver, thus achieving even better solid-state diffusion bonding.

[0198] The first conductive bonding material 71 has a structure in which a first layer 712 and a second layer 713, serving as Ag plating layers, are laminated on both sides of a first base layer 711 made of an Al-containing sheet. Similarly, the second conductive bonding material 72 has a structure in which a third layer 722 and a fourth layer 723, serving as Ag plating layers, are laminated on both sides of a second base layer 721 made of an Al-containing sheet. With this structure, the first conductive bonding material 71 and the second conductive bonding material 72 can be easily prepared.

[0199] In the semiconductor module Al, the second conduction member 62 is formed with an opening 63. The opening 63 overlaps the main surface 201 (the conductive substrate 2) in plan view, and does not overlap each semiconductor element 10 in plan view. According to this structure, in the molding (a process of forming the sealing resin 8) in the manufacturing process of the semiconductor module Al, the pressing pin 911 provided to the metal mold 91 can be inserted through the opening 63. Thus, without interfering with the second conduction member 62, the conductive substrate 2 can be pressed by the pressing pin 911, and therefore the warping of the support substrate 3 to which the conductive substrate 2 is joined can be suppressed. The warping occurs, for example, in such a manner that both outer sides in the y direction of the support substrate 3 are located higher than the central side in the y direction. If the warping occurs in the support substrate 3, there is a concern that the joining strength of the conductive substrate 2 to the support substrate 3 decreases. In addition, at the time of molding, sometimes the sealing resin 8 is formed on the bottom surface 302 due to resin leakage, and this is a cause of poor joining of a heat dissipation member (for example, a heat sink) to the bottom surface 302. Thus, the semiconductor module Al is a preferable packaging structure in terms of achieving an increase in the joining strength of the conductive substrate 2 to the support substrate 3 by suppressing the warping of the support substrate 3, and is a preferable packaging structure in terms of suppressing resin leakage of the sealing resin 8 to an undesirable position.

[0200] The conductive substrate 2 includes a first conductive portion 2A joined to the plurality of first semiconductor elements 10A and a second conductive portion 2B joined to the plurality of second semiconductor elements 10B. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction, and the first conductive portion 2A is located closer to the x2 direction than the second conductive portion 2B. The second conduction member 62 is connected to the plurality of second semiconductor elements 10B and the input terminals 42, 43, and the opening 63 provided to the second conduction member 62 overlaps the main surface 201 of the first conductive portion 2A in plan view. According to this structure, in a case where the size of the second conduction member 62 in plan view is ensured to be large, at the time of forming the sealing resin 8 (at the time of molding), interference with the second conduction member 62 can be avoided, and the conductive substrate 2 can be pressed by the pressing pin 911 provided to the metal mold 91. Further, by increasing the size of the second conduction member 62 in plan view, the parasitic resistance component of the second conduction member 62 (the conduction member 6) that constitutes a path of a main circuit current can be suppressed.

[0201] The second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are connected to the input terminals 42 and 43, respectively, which are disposed on opposite sides of each other in the y direction with the input terminal 41 interposed therebetween, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to the plurality of second semiconductor elements 10B, respectively. An opening 63 is formed in each of the first wiring portion 621 and the second wiring portion 622 at a position in the x2 direction. Thus, the opening 63 is disposed in the vicinity of both corners on the outer sides in the y direction of the conductive substrate 2 (the first conductive portion 2A) in plan view. Therefore, the opening 63 is disposed in the vicinity of both corners on the outer sides in the y direction of the support substrate 3 that supports the conductive substrate 2 (the first conductive portion 2A) in plan view. According to this structure, the size of the second conduction member 62 in plan view is ensured to be relatively large, and when the sealing resin 8 is formed (molded), the press pins 911 provided in the metal mold 91 can be inserted through the openings 63 to press the vicinity of the corners on the outer sides in the y direction of the conductive substrate 2 (the first conductive portion 2A). As described above, the warping of the support substrate 3 to which the conductive substrate 2 is joined occurs such that the outer sides in the y direction of the support substrate 3 are positioned higher than the central side in the y direction, and according to the above structure, the warping of the support substrate 3 at the time of molding can be effectively suppressed.

[0202] In the present embodiment, the conduction members 6 (the first conduction member 61 and the second conduction member 62) are composed of metal plates. Thus, the openings 63 can be easily formed in the second conduction member 62. In addition, the conduction members 6 (the first conduction member 61 and the second conduction member 62) composed of metal plates are easily adaptable to various shapes and sizes, and the reliability of the joint portions to other portions can be improved by ensuring the joint area to other portions.

[0203] In the main surface 201 of the conductive substrate 2 (the first conductive portion 2A), at a position overlapping each opening 63 in plan view, a recess 201a is formed. Each recess 201a is a trace of a pressing force imparted to the main surface 201 by the press pin 911 at the time of molding. In the present embodiment, by studying the arrangement of the second conduction member 62 and the openings 63 formed therein, it is possible to avoid interference with functional elements such as the semiconductor elements 10 at the time of molding, and to press appropriate portions of the conductive substrate 2 (the first conductive portion 2A) by the press pin 911.

[0204] The resin void portion 86 is tapered, and the cross-sectional area thereof decreases as it goes from the resin main surface 81 toward the recessed portion 201a. Such a resin void portion 86 is formed at the time of molding (at the time of formation of the sealing resin 8). After the molding, the surface of the recessed portion 201a in the main surface 201 of the conductive substrate 2 is exposed from the sealing resin 8. In addition, in the present embodiment, the resin void portion 86 is filled with a resin filling portion 88 in such a manner that the resin void portion 86 is buried. According to such a structure, it is possible to prevent the intrusion of foreign matter (including moisture) into the recessed portion 201a exposed from the sealing resin 8. The semiconductor module Al of the above-described structure is preferable in terms of improving durability and reliability.

[0205] In the present embodiment, each opening 63 formed in the second conductive member 62 (conductive member 6) is a through-hole that penetrates in the z direction. According to such a structure, in the second conductive member 62 (conductive member 6) that constitutes the path of the main circuit current, it is possible to suppress the skew of the current path caused by the formation of the opening 63.

[0206] The semiconductor module Al is provided with the conductive member 6. The conductive member 6 constitutes the path of the main circuit current switched by each semiconductor element 10. The conductive member 6 includes each first conductive member 61 connected to each first semiconductor element 10A and a second conductive member 62 connected to each second semiconductor element 10B. The conductive member 6 (each of the first conductive member 61 and the second conductive member 62) is constituted by a metal plate. The above-described main circuit current is sometimes a relatively large value. In this case, it is preferable to suppress the parasitic resistance component in the conductive member 6 that is the path of the main circuit current in terms of reducing the reduction in power consumption of the semiconductor module Al. Therefore, in the semiconductor module Al, as described above, the conductive member 6 is constituted not by a bonding wire but by a metal plate, and the parasitic resistance component in the conductive member 6 is suppressed. That is, the semiconductor module Al is constituted as a preferable package structure in terms of achieving suppression of the parasitic resistance component.

[0207] In the semiconductor module Al, each first semiconductor element 10A is rectangular in plan view, and the four corners of the first semiconductor element 10A in plan view do not overlap the second conductive member 62. According to this structure, in the manufacturing process of the semiconductor module Al, before the process of forming the sealing resin 8, it is possible to perform appearance inspection of whether each first semiconductor element 10A is properly bonded. That is, the semiconductor module Al can perform appearance inspection of whether each first semiconductor element 10A is properly bonded in the middle of the manufacturing process (for example, before the process of forming the sealing resin 8). Figure 23The appearance inspection of the bonding state of each first semiconductor element 10A is performed (in the state shown in the drawing), and thus it is possible to determine whether each first semiconductor element 10A is properly bonded. For example, the distance of the four corners of the first semiconductor element 10A is measured by a laser distance measuring method, and if the difference in the measured distance of the four corners is small, it is determined that the first semiconductor element 10A is properly bonded. Thus, the semiconductor module Al can perform the appearance inspection during the manufacturing process, and thus is a preferable package configuration in terms of achieving an improvement in reliability. Further, when the appearance inspection is performed, it is sufficient to confirm at least three corner portions of the four corners of the first semiconductor element 10A in plan view, and thus it is sufficient that the three corner portions do not overlap the second conduction member 62. In addition, as shown in the drawing, in each second semiconductor element 10B as well, the four corners of each second semiconductor element 10B in plan view do not overlap the second conduction member 62, and thus it is possible to perform the appearance inspection of whether each second semiconductor element 10B is properly bonded before the process of forming the sealing resin 8 in the manufacturing process of the semiconductor module Al. The appearance inspection can also be an automatic appearance inspection using photographing and image processing. Figure 5

[0208] The second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are connected to the input terminals 42 and 43, respectively, which are disposed on opposite sides of each other in the y direction with the input terminal 41 interposed therebetween, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to the plurality of second semiconductor elements 10B, respectively. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. The fourth wiring portion 624 is located on the x2 direction side with respect to the third wiring portion 623, and overlaps the plurality of first semiconductor elements 10A in plan view. The second conduction member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 is configured to overlap a wide range of the main surface 201 in plan view, and the size in plan view is large. Thus, increasing the size of the second conduction member 62 in plan view is more preferable in terms of suppressing the parasitic resistance component of the second conduction member 62 (the conduction member 6) that constitutes the path of the main circuit current.

[0209] ​Each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 when viewed from above. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is an end edge on the x2 direction side when viewed from above, and the second side 192 is an end edge on the x1 direction side when viewed from above. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is an end edge on the y2 direction side when viewed from above, and the fourth side 194 is an end edge on the y1 direction side when viewed from above. Each first semiconductor element 10A is rectangular in shape when viewed from above, and thus the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are substantially right-angled when viewed from above. On the other hand, the fourth wiring portion 624 (first belt-shaped portion 625) of the second conduction member 62 has a first end edge 627 and a second end edge 628. The first end edge 627 is an end edge in the x2 direction in the fourth wiring portion 624, and is located further in the x1 direction than the first side 191 when viewed from above. The first end edge 627 further extends in the y direction at least from the third side 193 to the fourth side 194. Thus, the two corners 171, 172 on the x2 direction side of each first semiconductor element 10A do not overlap the second conduction member 62 when viewed from above. The second end edge 628 is an end edge in the x1 direction in the fourth wiring portion 624 (first belt-shaped portion 625), and is located further in the x2 direction than the second side 192 when viewed from above. The second end edge 628 further extends in the y direction at least from the third side 193 to the fourth side 194. Thus, the two corners 173, 174 on the x1 direction side of each first semiconductor element 10A do not overlap the second conduction member 62 when viewed from above. In this structure, the size of the second conduction member 62 when viewed from above is increased by ensuring that the region of the fourth wiring portion 624 that overlaps each first semiconductor element 10A when viewed from above, and the four corners of the first semiconductor element 10A when viewed from above do not overlap the second conduction member 62. Thus, the parasitic resistance component of the second conduction member 62 (conduction member 6) can be effectively suppressed, and the appearance of the bonding state of each first semiconductor element 10A can be inspected during the manufacture of the semiconductor module A1.

[0210] The fourth wiring portion 624 (first belt-shaped portion 625) has a plurality of convex regions 625a that protrude further in the z2 direction than other portions. Each convex region 625a overlaps each first semiconductor element 10A when viewed from above. According to the structure in which the fourth wiring portion 624 has a plurality of convex regions 625a, the fourth wiring portion 624 can be prevented from coming into undesirable contact with the first conduction member 61 that is bonded to the first semiconductor element 10A.

[0211] The third wiring portion 623 has a plurality of concave regions 623a that protrude more toward the zl direction than other portions. Each of the concave regions 623a is joined to any one of the plurality of second semiconductor elements 10B. According to this structure, the third wiring portion 623 (the second conduction member 62) can be appropriately connected to the plurality of second semiconductor elements 10B, and the size of the third wiring portion 623 (the second conduction member 62) in plan view can be ensured to be large.

[0212] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other in the x direction in plan view. According to this structure, the size of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) in which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged can be prevented from being large in the y direction, and the semiconductor module Al can be made small.

[0213] The semiconductor module Al includes the conductive substrate 2, the two input terminals 41, 42 (or the two input terminals 41, 43), the output terminal 44, and the conduction member 6. The conductive substrate 2 includes the first conductive portion 2A and the second conductive portion 2B arranged in the x direction in plan view. The plurality of first semiconductor elements 10A are electrically joined to the first conductive portion 2A. In addition, the plurality of second semiconductor elements 10B are electrically joined to the second conductive portion 2B. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged at intervals in the y direction, respectively. The two input terminals 41, 42 (or the two input terminals 41, 43) are located in the x2 direction with respect to the first conductive portion 2A. The input terminal 41 is a positive electrode and is connected to the first conductive portion 2A. The input terminal 42 (or the input terminal 43) is a negative electrode. The output terminal 44 is located in the xl direction with respect to the second conductive portion 2B. The conduction member 6 includes the first conduction member 61 connected to the plurality of first semiconductor elements 10A and the second conductive portion 2B, and the second conduction member 62 connected to the plurality of second semiconductor elements 10B and the input terminal 42 (or the input terminal 43). According to this structure, the path of the main circuit current switched by the plurality of semiconductor elements 10 (the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B) is in the x direction in plan view, and the semiconductor module Al is configured to have a symmetry axis in the planar configuration (see FIG. 1) in the y direction. Figure 5The auxiliary line L1) is in the y direction in plan view. That is, the above-mentioned axis of symmetry is orthogonal to the path of the above-mentioned main circuit current. Due to this, in the main circuit current that is input from the two input terminals 41, 42 (or the two input terminals 41, 43) and output from the output terminal 44, the difference in the current paths to the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B can be reduced. That is, the deviation in the parasitic inductance component and the current deviation in the semiconductor module Al can be suppressed. Therefore, the semiconductor module Al is a preferable package configuration in terms of achieving equalization of the parasitic inductance component in the path of the main circuit current and equalization of the current amount to each semiconductor element 10.

[0214] The first semiconductor elements 10A and the second semiconductor elements 10B are spaced apart in the x direction. The first semiconductor elements 10A and the second semiconductor elements 10B are arranged in the y direction, respectively. Therefore, the direction in which the semiconductor elements 10 are arranged is orthogonal to the direction in which the first main circuit current or the second main circuit current flows. Due to this, in the case where a plurality of switching elements are connected in parallel and used as in the present embodiment, the difference in the length of the current path of the first main circuit current between the three first semiconductor elements 10A can be suppressed. Due to this, the parasitic resistance component in the conduction member 6 that is the path of the main circuit current can be suppressed.

[0215] The region in which the first main circuit current flows and the region in which the second main circuit current flows are configured to overlap in plan view. That is, in order to make the second main circuit current flow, the second conduction member 62 that connects the output terminal 44 and the first input terminal 42 and the second input terminal 43 that are negative terminals is arranged above the region in which the first main circuit current flows (the first conductive portion 2A, the first conduction member 61, the second conductive portion 2B). The direction in which the first main circuit current flows and the direction in which the second main circuit current flows are opposite. Therefore, by the above-mentioned arrangement, the magnetic field generated by the first main circuit current and the magnetic field generated by the second main circuit current can be canceled, and thus the inductance can be reduced.

[0216] The semiconductor module Al of the present embodiment has two input terminals 42, 43. These input terminals 42, 43 are both negative, and are spaced apart from the input terminal 41 in the y direction. In addition, the second conduction member 62 is connected to the two input terminals 42, 43. According to this structure, the deviation in the path of the current that flows from the output terminal 44 to each of the input terminals 42, 43 via each of the second semiconductor elements 10B and the second conduction member 62 can be further reduced.

[0217] In the semiconductor module Al, the second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are connected to the input terminals 42 and 43, respectively, which are disposed on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to the plurality of second semiconductor elements 10B, respectively. In the fourth wiring portion 624, the fourth wiring portion 624 is located on the x2 direction side with respect to the third wiring portion 623, and is connected to any one of the first wiring portion 621, the second wiring portion 622, and the third wiring portion 623. The second conduction member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 overlaps a wide range of the main surface 201 when viewed from above, and the size when viewed from above can be ensured to be large. According to this structure, the deviation of the path of the current flowing from the output terminal 44 to each of the input terminals 42 and 43 via each of the second semiconductor elements 10B and the second conduction member 62 can be appropriately reduced. Therefore, the semiconductor module Al of the present embodiment is more preferable in terms of achieving equalization of the parasitic inductance component in the path of the main circuit current (the second conduction member 62) and equalization of the amount of current flowing to each of the second semiconductor elements 10B.

[0218] The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps the plurality of first semiconductor elements 10A when viewed from above. In addition, the fourth wiring portion 624 (the first belt-shaped portion 625) has a plurality of convex regions 625a that protrude more toward the z2 direction than other portions. Each of the convex regions 625a overlaps each of the first semiconductor elements 10A when viewed from above. According to this structure, the size of the fourth wiring portion 624 (the second conduction member 62) when viewed from above can be ensured to be large, and the fourth wiring portion 624 can be prevented from being improperly in contact with the first conduction member 61 bonded to the first semiconductor elements 10A.

[0219] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x direction. According to this structure, the size of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) in which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are disposed can be suppressed from being large in the y direction, and the semiconductor module Al can be made small.

[0220] Figures 30-32 A semiconductor module of a second embodiment is shown. In the semiconductor module A2 of the present embodiment, the structure of the second conduction member 62 is different from that of the semiconductor module Al of the above-described embodiment.

[0221] In the present embodiment, the area occupied by the fourth wiring portion 624 of the second conduction member 62 is different from that of the above-described embodiment. Specifically, the dimension of the first band-shaped portion 625 in the x direction is larger than that of the above-described semiconductor module Al. As shown in FIG. 6B, the position of the second end edge 628 of the first band-shaped portion 625 is located on the xl direction side as compared with the above-described semiconductor module Al. As shown in FIG. 6C, the second end edge 628 is located further on the xl direction side than the second edge 192 of the first semiconductor element 10A in plan view. Thus, the two corners on the xl direction side of each first semiconductor element 10A respectively overlap with the second conduction member 62 (the first band-shaped portion 625) in plan view. Figure 31 、 Figure 32 Figure 32

[0222] The semiconductor module A2 according to the present embodiment also functions to achieve the same effects as the semiconductor module Al of the above-described embodiment. In the semiconductor module A2, the dimension of the first band-shaped portion 625 (the second conduction member 62) of the fourth wiring portion 624 in plan view can be more ensured. This is more preferable in terms of reducing the parasitic inductance component.

[0223] Figure 33 Figure 34 A semiconductor module according to a third embodiment will be described. In the semiconductor module A3 according to the present embodiment, the structure of the second conduction member 62 is mainly different from that of the semiconductor module Al of the above-described embodiment.

[0224] In the semiconductor module A3, the second conduction member 62 does not have the opening 63 unlike the above-described embodiment. In manufacturing the semiconductor module A3, the metal mold 91 used for forming (mold forming) the sealing resin 8 does not have the press pin 911. Thus, as shown in FIG. 7B, the resin void portion 86 is not formed in the sealing resin 8, and the recess portion 201a is not formed in the main surface 201 of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B). Further, since the resin void portion 86 is not formed in the sealing resin 8, the semiconductor module A3 according to the present embodiment does not have the resin filling portion 88 used for filling the resin void portion 86 in the above-described embodiment. Figure 34

[0225] In the semiconductor module A3 according to the present embodiment, the same effects as the semiconductor module Al of the above-described embodiment are achieved.

[0226] The semiconductor module of the present disclosure is not limited to the above-described embodiments. The specific structure of each portion of the semiconductor module of the present disclosure is freely designed variously.

[0227] ​​​​In the above embodiment, a structure having two input terminals 42, 43 (N terminals) and a second conductive member 62 connected to these input terminals 42, 43 has been described, but it is not limited to this. A structure having only one input terminal 42 (N terminal) and a second conductive member 62 connected to this input terminal 42 may also be used.

[0228] In the above embodiments, the plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) are configured such that each control terminal 45 extends along the z-direction, but this is not a limitation. For example, it may also be a structure in which each control terminal 45 extends along a plane orthogonal to the z-direction (x-y plane).

[0229] The above embodiment shows an example where the second conducting member 62 has two second strip portions 626 and a first strip portion 625, but it may not have two second strip portions 626 and a first strip portion 625. However, by providing two second strip portions 626 and a first strip portion 625, compared with a structure without two second strip portions 626 and a first strip portion 625, the offset between multiple semiconductor elements 10 can be suppressed, and the inductance can be further reduced.

[0230] This disclosure includes the structure described in the following notes.

[0231] Postscript 1.

[0232] A semiconductor module, comprising:

[0233] A conductive substrate having a front surface and a back surface spaced apart from each other in the thickness direction;

[0234] At least one semiconductor element is electrically connected to the aforementioned main surface and has a switching function;

[0235] The conducting component forms the path of the main circuit current switched by the aforementioned semiconductor element;

[0236] The first input terminal and the second input terminal are disposed on one side of a first direction orthogonal to the thickness direction relative to the conductive substrate; and

[0237] At least one output terminal is disposed on the opposite side of the first direction relative to the conductive substrate.

[0238] The conductive substrate includes a first conductive portion and a second conductive portion that are spaced apart from each other in the first direction.

[0239] The at least one semiconductor element includes a plurality of first semiconductor elements and a plurality of second semiconductor elements, the plurality of first semiconductor elements are electrically connected to the first conductive portion, and are arranged at intervals from each other in a second direction that is orthogonal to both the thickness direction and the first direction, the plurality of second semiconductor elements are electrically connected to the second conductive portion, and are arranged at intervals from each other in the second direction,

[0240] The first input terminal is electrically connected to the first conductive portion,

[0241] The second input terminal is opposite in polarity to the first input terminal,

[0242] The output terminal is electrically connected to the second conductive portion,

[0243] The conduction member includes a first conduction member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conduction member connected to the plurality of second semiconductor elements and the second input terminal.

[0244] Addendum 2.

[0245] The semiconductor module according to Addendum 1,

[0246] The path of the main circuit current includes a first main circuit current path between the first input terminal and the output terminal, and a second main circuit current path between the output terminal and the second input terminal,

[0247] The direction of the first main circuit current is opposite to the direction of the second main circuit current.

[0248] Addendum 3.

[0249] The semiconductor module according to Addendum 1 or 2,

[0250] The path of the main circuit current switched by the plurality of first semiconductor elements and the plurality of second semiconductor elements is configured to be along the first direction when viewed in the thickness direction.

[0251] Addendum 4.

[0252] The semiconductor module according to any one of Addenda 1 to 3,

[0253] The first conduction member includes a plurality of conduction portions corresponding to the plurality of first semiconductor elements, respectively.

[0254] Addendum 5.

[0255] The semiconductor module according to any one of Addenda 1 to 4,

[0256] The semiconductor module further includes a third input terminal disposed on one side of the first direction with respect to the first semiconductor element and connected to the second conduction member.

[0257] The first input terminal is disposed between the second input terminal and the third input terminal in the second direction.

[0258] Clause 6.

[0259] The semiconductor module according to Clause 5,

[0260] The second conduction member includes a first wiring portion connected to the second input terminal and extending in the first direction, a second wiring portion connected to the third input terminal and extending in the first direction, a third wiring portion connected to both the first wiring portion and the second wiring portion and extending in the second direction and connected to the plurality of second semiconductor elements, respectively, and a fourth wiring portion disposed on one side of the first direction with respect to the third wiring portion and connected to any one of the first wiring portion, the second wiring portion, and the third wiring portion.

[0261] Clause 7.

[0262] The semiconductor module according to Clause 6,

[0263] The fourth wiring portion overlaps the plurality of first semiconductor elements when viewed in the thickness direction.

[0264] Clause 8.

[0265] The semiconductor module according to Clause 7,

[0266] The fourth wiring portion has a plurality of convex regions protruding more in the thickness direction than other regions of the fourth wiring portion, each convex region overlapping a corresponding one of the plurality of first semiconductor elements when viewed in the thickness direction.

[0267] Clause 9.

[0268] The semiconductor module according to any one of Clauses 6 to 8,

[0269] The plurality of first semiconductor elements and the plurality of second semiconductor elements each have a source electrode and a drain electrode disposed at a distance from each other in the thickness direction,

[0270] The first conduction member is connected to the source electrode of each first semiconductor element,

[0271] The first conductive portion is connected to the drain electrode of each first semiconductor element,

[0272] The third wiring portion is connected to the source electrode of each second semiconductor element,

[0273] The second conductive portion is connected to the drain electrode of each second semiconductor element.

[0274] Note 10

[0275] The semiconductor module according to Note 9,

[0276] The plurality of first semiconductor elements and the plurality of second semiconductor elements overlap with each other when viewed in the first direction.

[0277] Note 11

[0278] The semiconductor module according to any one of Notes 5 to 10,

[0279] The first input terminal, the second input terminal, and the third input terminal overlap with each other when viewed in the second direction.

[0280] Note 12

[0281] The semiconductor module according to any one of Notes 1 to 11,

[0282] The first conductive member and the second conductive member are each formed of a metal plate.

[0283] Note 13

[0284] The semiconductor module according to Note 1,

[0285] Further, a control terminal is connected to one of the plurality of first semiconductor elements and the plurality of second semiconductor elements,

[0286] The control terminal is provided on the main surface and extends in the thickness direction.

[0287] Note 14

[0288] The semiconductor module according to any one of Notes 1 to 13,

[0289] The first input terminal and the second input terminal each include an input-side bonding surface that extends toward one side of the first direction and toward one side of the thickness direction.

[0290] The output terminal includes an output-side bonding surface that extends toward the other side of the first direction and toward one side of the thickness direction.

[0291] Note 15

[0292] The semiconductor module according to any one of the above 14,

[0293] The first input terminal and the second input terminal each have an input-side side surface located at a periphery of the input-side bonding surface and facing a direction intersecting a normal line of the input-side bonding surface when viewed in the thickness direction, and an input-side processing mark formed on the input-side side surface,

[0294] The output terminal has an output-side side surface located at a periphery of the output-side bonding surface and facing a direction intersecting a normal line of the output-side bonding surface when viewed in the thickness direction, and an output-side processing mark formed on the output-side side surface.

[0295] The semiconductor module according to any one of the above 14,

[0296] The semiconductor module according to any one of the above 14,

[0297] Further, a sealing resin is provided, which covers at least a part of each of the first and second conductive portions, the plurality of first semiconductor elements, the plurality of second semiconductor elements, the first conduction member, and the second conduction member.

[0298] The semiconductor module according to any one of the above 14,

[0299] The semiconductor module according to any one of the above 14,

[0300] The sealing resin has a first resin side surface and a second resin side surface spaced apart from each other in the first direction, the second resin side surface being located closer to the second conductive portion than the first resin side surface, the second resin side surface having two end portions spaced apart from each other in the second direction, and a resin separation mark being formed at at least one of the end portions.

[0301] The semiconductor module according to any one of the above 14,

[0302] The semiconductor module according to any one of the above 14,

[0303] The at least one output terminal includes a first output terminal and a second output terminal,

[0304] The sealing resin has a resin side surface having a resin separation mark formed thereon between the first output terminal and the second output terminal.

[0305] The semiconductor module according to any one of the above 14,

[0306] A semiconductor module includes:

[0307] A conductive substrate has a main surface and a back surface spaced apart from each other in a thickness direction;

[0308] at least one semiconductor element electrically connected to the main surface and having a switching function;

[0309] a conduction member that configures a path of a main circuit current switched by the semiconductor element and is spaced apart from the main surface in the thickness direction;

[0310] a first input terminal and a second input terminal disposed on one side in a first direction orthogonal to the thickness direction with respect to the conductive substrate; and

[0311] an output terminal disposed on the other side in the first direction with respect to the conductive substrate,

[0312] the conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other in the first direction orthogonal to the thickness direction,

[0313] the at least one semiconductor element includes a plurality of first semiconductor elements electrically connected to the first conductive portion and a plurality of second semiconductor elements electrically connected to the second conductive portion,

[0314] the plurality of first semiconductor elements are disposed spaced apart from each other in a second direction that is orthogonal to both the thickness direction and the first direction,

[0315] the plurality of second semiconductor elements are disposed spaced apart from each other in the second direction,

[0316] the first input terminal is a positive electrode connected to the first conductive portion,

[0317] the second input terminal is a negative electrode,

[0318] the output terminal is connected to the second conductive portion,

[0319] the conduction member includes a first conduction member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conduction member connected to the plurality of second semiconductor elements and the second input terminal.

[0320] Paragraph 20.

[0321] the semiconductor module according to Paragraph 19,

[0322] the path of the main circuit current switched by the plurality of first semiconductor elements and the plurality of second semiconductor elements is configured to be along the first direction when viewed in the thickness direction,

[0323] when viewed in the thickness direction, the plurality of first semiconductor elements and the plurality of second semiconductor elements are disposed symmetrically with respect to an axis orthogonal to the first direction.

[0324] Paragraph 21

[0325] The semiconductor module according to any one of Paragraphs 19 or 20,

[0326] The third input terminal is located on one side of the first direction with respect to the plurality of first semiconductor elements, and is a negative electrode connected to the second conduction member.

[0327] The second input terminal and the third input terminal are respectively arranged on one side and the other side of the second direction via the first input terminal.

[0328] Paragraph 22

[0329] The semiconductor module according to Paragraph 21,

[0330] The second conduction member includes: a first wiring portion connected to the second input terminal and extending in the first direction; a second wiring portion connected to the third input terminal and extending in the first direction; a third wiring portion connected to both the first wiring portion and the second wiring portion and extending in the second direction, and connected to the plurality of second semiconductor elements, respectively; and a fourth wiring portion located on one side of the first direction with respect to the third wiring portion, and connected to any one of the first wiring portion, the second wiring portion, and the third wiring portion.

[0331] Paragraph 23

[0332] The semiconductor module according to Paragraph 22,

[0333] The fourth wiring portion overlaps the plurality of first semiconductor elements when viewed in the thickness direction.

[0334] Paragraph 24

[0335] The semiconductor module according to Paragraph 23,

[0336] The fourth wiring portion has a plurality of convex regions protruding more in the thickness direction than other portions of the fourth wiring portion, each convex region overlapping a corresponding one of the plurality of first semiconductor elements when viewed in the thickness direction.

[0337] Paragraph 25

[0338] The semiconductor module according to any one of Paragraphs 22 to 24,

[0339] The plurality of first semiconductor elements and the plurality of second semiconductor elements each have a source electrode and a drain electrode spaced apart from each other in the thickness direction,

[0340] the first conductive portion is connected to the source electrode of each of the first semiconductor elements,

[0341] the first conductive portion is connected to the source electrode of each of the first semiconductor elements,

[0342] the third wiring portion is connected to the source electrode of each of the second semiconductor elements,

[0343] the second conductive portion is connected to the drain electrode of each of the second semiconductor elements.

[0344] Addendum 26.

[0345] the semiconductor module according to any one of Addenda 25,

[0346] the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap each other when viewed in the first direction.

[0347] Addendum 27.

[0348] the semiconductor module according to any one of Addenda 21 to 26,

[0349] the first input terminal, the second input terminal, and the third input terminal overlap each other when viewed in the second direction.

[0350] Addendum 28.

[0351] the semiconductor module according to any one of Addenda 19 to 27,

[0352] the first conductive portion and the second conductive portion are made of a metal plate.

[0353] Explanation of Symbols

[0354] A1, A2, A3 — semiconductor module, 10 — semiconductor element, 10A — first semiconductor element, 10B — second semiconductor element, 101 — element front surface, 102 — element back surface, 11 — first main surface electrode (gate electrode), 12 — second main surface electrode (source electrode), 13 — third main surface electrode, 14 — fourth main surface electrode, 15 — back surface electrode (drain electrode), 16 — fifth main surface electrode, 171, 172, 173, 174 — corner, 181, 182, 183, 184 — corner, 191 — first side, 192 — second side, 193 — third side, 194 — fourth side, 2 — conductive substrate, 2A — first conductive portion, 2B — second conductive portion, 201 — front surface, 201a — recess, 201b — recess end edge, 202 — back surface, 21 — base material, 22 — front surface bonding layer, 23 — back surface bonding layer, 3 — support substrate, 301 — support surface, 302 — bottom surface, 31 — insulating layer, 32 — first metal layer, 32A — first portion, 32B — second portion, 321 — first bonding layer, 33 — second metal layer, 41 — first input terminal, 411 — input-side bonding surface, 412 — input-side side surface, 413 — front end surface, 414 — side surface, 42 — second input terminal, 421 — input-side bonding surface, 422 — input-side side surface, 423 — front end surface, 424 — side surface, 43 — third input terminal, 431 — input-side bonding surface, 432 — input-side side surface, 433 — front end surface, 434 — side surface, 44 — output terminal, 441 — output-side bonding surface, 442 — output-side side surface, 443 — front end surface, 444 — side surface, 45 — control terminal, 451 — holder, 452 — metal pin, 459 — electrically conductive bonding material, 46A, 46B, 46C, 46D, 46E — first control terminal, 47A, 47B, 47C, 47D — second control terminal, 5 — control terminal support, 51 — insulating layer, 52 — first metal layer, 521 — first portion, 522 — second portion, 523 — third portion, 524 — fourth portion, 525 — fifth portion, 53 — second metal layer, 59 — bonding material, 6 — conduction member, 601 — first portion, 61 — first conduction member, 61h — opening, 62 — second conduction member, 62A — first portion, 62B — second portion, 621 — first wiring portion, 622 — second wiring portion, 623 — third wiring portion, 623a — recessed region, 623h — opening, 624 — fourth wiring portion, 625 — first belt portion, 625a — convex region, 625h — opening, 626 — second belt portion, 627 — first end edge, 628 — second end edge, 63 — opening, 69 — electrically conductive bonding material, 71 — first electrically conductive bonding material, 711 — first base layer, 712 — first layer, 713 — second layer, 72 — second electrically conductive bonding material, 721 — second base layer, 722 — third layer, 723 — fourth layer, 731 — metal wire,731a - first wire, 731b - second wire, 732, 733, 734, 735 - wire, 8 - sealing resin, 81 - resin front face, 82 - resin back face, 831, 832 - resin side face, 832a - recess, 833, 834 - resin side face, 851 - first protruding portion, 851a - first protruding end face, 851b - recess, 851c - inner wall face, 852 - second protruding portion, 86 - resin gap portion, 861 - resin gap portion end edge, 87 - resin portion, 88 - resin filling portion, 91 - metal mold, 911 - press pin.

Claims

1. A semiconductor module characterized by comprising: a conductive substrate having a main surface and a back surface which are spaced apart from each other in a thickness direction; at least one semiconductor element electrically joined to the main surface and having a switching function; a conduction member which constitutes a path of a main circuit current switched by the at least one semiconductor element; a first input terminal, a second input terminal, and a third input terminal which are arranged on one side in a first direction orthogonal to the thickness direction with respect to the conductive substrate; at least one output terminal which is arranged on the other side in the first direction with respect to the conductive substrate; at least one control terminal which is connected to the at least one semiconductor element; and an encapsulating resin which covers at least a part of the conductive substrate, a part of the at least one semiconductor element, a part of the first input terminal, a part of the second input terminal, a part of the third input terminal, and a part of the at least one output terminal, and a part of the at least one control terminal, wherein the conductive substrate includes a first conductive portion and a second conductive portion which are arranged spaced apart from each other, wherein the at least one semiconductor element includes a plurality of first semiconductor elements electrically joined to the first conductive portion and a plurality of second semiconductor elements electrically joined to the second conductive portion, wherein the first input terminal is electrically connected to either of the plurality of first semiconductor elements and the plurality of second semiconductor elements, wherein the second input terminal and the third input terminal are arranged on one side and the other side in a second direction orthogonal to the thickness direction and the first direction with respect to the first input terminal, respectively, and are electrically connected to the other of the plurality of first semiconductor elements and the plurality of second semiconductor elements, wherein the at least one output terminal is electrically connected to the second conductive portion, wherein the encapsulating resin has a first recessed portion recessed toward the other side in the first direction between the first input terminal and the second input terminal when viewed in the thickness direction, and a second recessed portion recessed toward the other side in the first direction between the first input terminal and the third input terminal when viewed in the thickness direction, wherein the encapsulating resin includes a first protruding portion, a second protruding portion, and a third protruding portion which protrude toward the one side in the first direction at positions where the first input terminal, the second input terminal, and the third input terminal are arranged when viewed in the thickness direction, and a resin back surface which faces in the same direction as the back surface, wherein a step is provided between a back surface of each of the first protruding portion, the second protruding portion, and the third protruding portion and the resin back surface, wherein the at least one control terminal is arranged on the main surface and extends in the thickness direction, wherein a first main circuit current path is constituted between the first input terminal and the output terminal via either of the plurality of first semiconductor elements and the plurality of second semiconductor elements, and wherein a second main circuit current path is constituted between the output terminal and the second input terminal and the third input terminal via the other of the plurality of first semiconductor elements and the plurality of second semiconductor elements. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first main circuit current path is symmetrically arranged with respect to a center line passing through the center of the first input terminal and extending in the first direction, and the second main circuit current path is symmetrically arranged with respect to the center line passing through the center of the first input terminal and extending in the first direction when viewed in the thickness direction, The first conductive portion, the second conductive portion, the plurality of first semiconductor elements, the plurality of second semiconductor elements, the output terminal, the control terminal, the first input terminal, the second input terminal, and the third input terminal constitute one half-bridge type switching circuit.

2. The semiconductor module according to claim 1, wherein The at least one control terminal includes a plurality of first control terminals that control the plurality of first semiconductor elements and a plurality of second control terminals that control the plurality of second semiconductor elements, The plurality of first control terminals are supported by the first conductive portion and arranged between the plurality of first semiconductor elements and the first input terminal and the second input terminal in the first direction, The plurality of second control terminals are supported by the second conductive portion and arranged between the plurality of second semiconductor elements and the at least one output terminal in the first direction.

3. The semiconductor module according to claim 1, wherein The plurality of first semiconductor elements and the plurality of second semiconductor elements overlap each other when viewed in the first direction.

4. The semiconductor module according to claim 1, wherein The first input terminal, the second input terminal, and the third input terminal overlap each other when viewed in the second direction.

5. The semiconductor module according to claim 1, wherein The first input terminal and the second input terminal each include an input-side bonding surface that extends toward one side of the first direction and toward one side of the thickness direction, The at least one output terminal includes an output-side bonding surface that extends toward the other side of the first direction and toward one side of the thickness direction.

6. The semiconductor module according to claim 5, wherein The first input terminal and the second input terminal each have an input-side side surface that is located at a periphery of the input-side bonding surface when viewed in the thickness direction and that faces a direction intersecting a normal line of the input-side bonding surface, and an input-side processing mark formed on the input-side side surface, The at least one output terminal has an output-side side surface that is located at a periphery of the output-side bonding surface when viewed in the thickness direction and that faces a direction intersecting a normal line of the output-side bonding surface, and an output-side processing mark formed on the output-side side surface.

7. The semiconductor module according to claim 1, wherein The resin side surface has a first resin side surface and a second resin side surface spaced apart from each other in the first direction, the second resin side surface being located closer to the second conductive portion than the first resin side surface, the second resin side surface having two end portions spaced apart from each other in the second direction, and at least one of the end portions having a resin separation mark formed therein.

8. The semiconductor module according to claim 1, wherein the at least one output terminal includes a first output terminal and a second output terminal, the sealing resin has a resin side surface having a resin separation mark formed therebetween the first output terminal and the second output terminal.

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