A logarithmic conversion circuit and chip

Abstract

The disclosed embodiment provides a logarithmic conversion circuit and chip, in which the chopper circuit receives a DC input signal, performs a DC-to-AC process on the DC input signal, and generates an AC input signal; the conversion circuit receives an AC input signal, and performs amplification and AC-to-DC process on the AC input signal, and generates a DC output signal; the conversion circuit includes N cascaded amplifier circuits, and the first-stage amplifier circuit receives an AC input signal; the feedback circuit is connected between the output end of the j-stage amplifier circuit and the input end of the i-stage amplifier circuit, and is used to input a feedback signal to the input end of the i-stage amplifier circuit, wherein the feedback signal includes a DC portion and / or a low-frequency portion in the output signal of the j-stage amplifier circuit. The disclosed embodiment can suppress the offset voltage generated inside the amplifier circuit, which is beneficial for the circuit to achieve a large dynamic range.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a logarithmic conversion circuit and chip. Background Art

[0002] In the field of communications, some wireless signals have a very wide dynamic range, which can be as high as 100 decibels (dB) or more. In order to accurately measure signals with such a wide dynamic range, a common method is to first convert the AC signal into a DC signal and then detect the DC signal. Since the converted DC signal has a very high dynamic range, direct measurement requires the use of a very high-precision analog-to-digital converter, which greatly increases the measurement cost. Therefore, the "logarithmic compression" technology is widely used. By first compressing the DC signal, the compressed output DC signal and the input signal present a "logarithmic linear" characteristic, and then only a medium-resolution analog-to-digital converter is needed to achieve accurate digital representation. This "logarithmic compression" technology usually uses a logarithmic conversion circuit, which is widely used in communications, radar, electronic countermeasures, and electronic measurement. In order to further expand the dynamic range of logarithmic conversion, the logarithmic conversion circuit needs to use multi-stage cascade amplification. However, due to the offset voltage in the cascade amplifier, the output voltage and dynamic range of the logarithmic conversion circuit will be greatly affected. Summary of the invention

[0003] The embodiments of the present disclosure provide a logarithmic conversion circuit and chip, which can reduce offset voltage and measurement errors.

[0004] In a first aspect, an embodiment of the present disclosure provides a logarithmic conversion circuit, which includes a chopper circuit, N cascaded amplifier circuits, a multi-stage rectifier and a feedback circuit, wherein: the input end of the chopper circuit receives a DC input signal, the chopper circuit performs DC-to-AC processing on the DC input signal to generate an AC input signal, and the output end of the chopper circuit outputs the AC input signal; the input end of the first-stage amplifier circuit is connected to the output end of the chopper circuit to receive the AC input signal; the output end of each of the amplifier circuits is connected to the input end of one of the rectifiers, and the output ends of all the rectifiers are connected together to output a DC output signal; the feedback circuit is connected between the output end of the j-th stage amplifier circuit and the input end of the i-th stage amplifier circuit, and is used to input a feedback signal to the input end of the i-th stage amplifier circuit, wherein the feedback signal includes a DC part and / or a low-frequency part in the output signal of the j-th stage amplifier circuit, i and j are both integers greater than or equal to 1 and less than or equal to N, and j is greater than or equal to i.

[0005] In a second aspect, an embodiment of the present disclosure provides a chip, comprising the logarithmic conversion circuit as described in the first aspect.

[0006] The disclosed embodiment provides a logarithmic conversion circuit and chip, firstly, a chopper circuit is used to convert a DC input signal into an AC input signal, thereby distinguishing the frequencies of the DC input signal and the DC offset signal, and then the amplifier circuit amplifies both the AC input signal and the DC offset voltage generated by the amplifier circuit itself, and the feedback circuit generates a feedback signal according to the DC part and / or the low-frequency part in the j-th amplifier circuit, and the feedback signal returns and acts on the amplifier circuit, and the feedback signal and the DC offset signal generated by the amplifier circuit are offset, thereby realizing the suppression of the DC offset voltage; at the same time, the feedback signal includes the DC part and / or the low-frequency part in the output signal of the j-th amplifier circuit, and the frequency of the feedback signal is different from the frequency of the AC input signal, which will not affect the normal amplification of the AC input signal, and the conversion circuit also converts the AC amplified signals of each level into DC, and integrates them into DC output signals for output. Finally, while not adversely affecting the normal amplification of the circuit, the offset voltage is reduced, the measurement error is reduced, and it is beneficial for the circuit to achieve a large dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of the structure of a traditional logarithmic conversion circuit Figure 1 ;

[0008] Figure 2 A schematic diagram of the structure of a traditional logarithmic conversion circuit Figure 2 ;

[0009] Figure 3 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 1 ;

[0010] Figure 4 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 2 ;

[0011] Figure 5 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 3 ;

[0012] Figure 6 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 4 ;

[0013] Figure 7 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 5 ;

[0014] Figure 8 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 6 ;

[0015] Fig. 9 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 7 ;

[0016] Fig.10 The structure diagram of the logarithmic conversion circuit provided in the embodiment of the present disclosure is as follows: Figure 8 ;

[0017] Fig.11 A schematic diagram for describing the functions of a chopper circuit provided in an embodiment of the present disclosure;

[0018] Fig.12 The structure diagram of the chopper circuit provided in the embodiment of the present disclosure is as follows: Figure 1 ;

[0019] Fig.13 The structure diagram of the chopper circuit provided in the embodiment of the present disclosure is as follows: Figure 2 ;

[0020] Fig.14 The structure diagram of the chopper circuit provided in the embodiment of the present disclosure is as follows: Figure 3 ;

[0021] Fig.15 The structure diagram of the chopper circuit provided in the embodiment of the present disclosure is as follows: Figure 4 ;

[0022] Fig.16 The structure diagram of the chopper circuit provided in the embodiment of the present disclosure is as follows: Figure 5 ;

[0023] Fig.17 The structure diagram of the filter circuit provided in the embodiment of the present disclosure is as follows: Figure 1 ;

[0024] Fig.18 The structure diagram of the filter circuit provided in the embodiment of the present disclosure is as follows: Figure 2 ;

[0025] Fig.19 A schematic diagram of the structure of the feedback amplifier provided in the embodiment of the present disclosure Figure 1 ;

[0026] Fig. 20 A schematic diagram of the structure of the feedback amplifier provided in the embodiment of the present disclosure Figure 2 ;

[0027] Fig.21 The structure diagram of the amplifier circuit provided in the embodiment of the present disclosure is as follows Figure 1 ;

[0028] Fig. 22 The structure diagram of the amplifier circuit provided in the embodiment of the present disclosure is as follows Figure 2;

[0029] Fig.23 The structure diagram of the rectifier provided in the embodiment of the present disclosure is as follows: Figure 1 ;

[0030] Fig.24 The structure diagram of the rectifier provided in the embodiment of the present disclosure is as follows: Figure 2 ;

[0031] Fig.25 A schematic diagram of the composition structure of the chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. It will be understood that the specific embodiments described herein are only used to explain the relevant disclosure and are not intended to limit the disclosure. It should also be noted that, for ease of description, only the parts related to the relevant disclosure are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0033] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects, and do not represent a specific ordering of the objects. It is understood that "first\second\third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.

[0034] The logarithmic conversion circuit can be implemented by a feedback amplifier composed of a diode or a transistor, but this method is generally used to process single-ended input signals. Logarithmic conversion of dual-ended input signals is usually implemented using the architecture of "cascade limiting amplifier + transconductance unit" or "cascade limiting amplifier + rectifier unit". Among them, the structure of "cascade limiting amplifier + rectifier unit" can achieve better "linear dB" characteristics. The cascade limiting amplifier amplifies the input signal step by step, and then converts it into output current through a rectifier, and adds the multi-stage output current into the load resistor, and finally obtains a logarithmic output voltage that can indicate the input voltage. At the same time, by increasing the number of cascade limiting amplifiers, the dynamic range of the measurement can be expanded accordingly.

[0035] Figure 1It is a logarithmic conversion circuit for double-ended signals. Figure 1 As shown in FIG. 1 , the logarithmic conversion circuit includes m cascaded limiting amplifiers (limiting amplifier 1, limiting amplifier 2, ... limiting amplifier m) and m+1 rectifiers (rectifier 1, rectifier 2, ... rectifier m+1), where m is an integer greater than 0. The limiting amplifier amplifies the input signal and limits the amplitude of the output signal to a fixed value, so it is called a limiting amplifier.

[0036] like Figure 1 As shown in the figure, in this logarithmic conversion circuit, the limiting amplifier (also called the limiting amplifier stage) is mainly used to amplify the input signal step by step, and when the signal reaches a certain level, the output signal of the limiting amplifier will reach the limiting value step by step. The main function of the rectifier is to convert the step-by-step output signal of the limiting amplifier into a DC current, and the rectifier in the logarithmic conversion circuit has the characteristic that the output current and its own input voltage amplitude are in a logarithmic relationship. Figure 1 As shown, the logarithmic conversion circuit may further include a load resistor connected between the output voltage and the ground terminal.

[0037] For the overall logarithmic conversion circuit, a multi-stage limiting amplifier and rectifier cascade is usually required to achieve a large dynamic range. As the amplifier is gradually amplified, the output signal of the limiting amplifier will reach a fixed limiting value step by step, and the rectifier will also convert it into the corresponding current step by step according to the output voltage of the limiting amplifier. Finally, the overall output current (the sum of the current of each rectifier stage) / output voltage presents a logarithmic relationship with the input voltage.

[0038] In order to further expand the dynamic range of logarithmic conversion, the logarithmic conversion circuit needs to use multi-stage cascade amplification. However, there is an offset voltage in the cascaded limiting amplifier, among which, the amplifier based on triode and the amplifier based on metal oxide semiconductor field effect transistor (MOS tube) have an offset voltage, and the offset voltage of the amplifier based on MOS tube is more serious, which will greatly affect the output voltage and dynamic range of the logarithmic conversion circuit.

[0039] For ease of understanding, the offset voltage of each cascaded limiting amplifier can be equivalent to the input terminal of the limiting amplifier. Figure 1 The figure shows the relationship between the voltage difference ΔV between the positive input terminal (+) and the negative input terminal (-) of each level of limiting amplifier and the time t, and the relationship between the output current I of each level of rectifier and the time t when there is no signal input. Figure 1 As shown, between the non-inverting input and the inverting input of the limiting amplifier 1, the corresponding voltage difference ; Between the non-inverting input and the inverting input of the limiting amplifier 2, the corresponding voltage difference ,in, represents the gain of the limiting amplifier, Represents the equivalent offset voltage of the limiting amplifier, and the same applies to the following; between the positive input terminal and the negative input terminal of the limiting amplifier 3, the corresponding voltage difference ; ...; Between the positive input and the negative input of the limiting amplifier m, the corresponding voltage difference ; Between the positive and negative output terminals of the limiting amplifier m, the corresponding voltage difference ; It can be seen that after the offset voltage is amplified step by step, a large voltage difference is finally introduced; it can also be seen from the current relationship diagram that the current I output from rectifier 1 to rectifier m+1 1 To current I m+1 It's also getting bigger.

[0040] That is to say, even if there is no DC input signal in the logarithmic conversion circuit, the equivalent offset voltage at the input of each limiting amplifier will be amplified step by step and superimposed, causing the static operating point of each limiting amplifier to shift and form a larger offset voltage output. The offset voltage output of each stage will form an offset current through the rectifier, affecting the final voltage output.

[0041] Furthermore, since the offset voltage changes with temperature, even in the absence of an input signal, the logarithmic conversion circuit will form different and larger DC voltage deviations at different temperatures. For this reason, even if the offset voltage is calibrated during circuit initialization, the problem of offset voltage will reappear due to temperature changes during circuit operation.

[0042] further, Figure 2 The figure shows the voltage difference between the input signal at the positive input and the negative input of each level of the limiting amplifier when there is a signal input. The relationship between the voltage difference ΔV caused by the offset voltage (indicated by the dotted line, generated by the two-terminal input signal) and the time t, as well as the relationship between the output current I of each rectifier and the time t, in the voltage-time diagram, the ordinate is represented by voltage V. Figure 2 As shown, the double-ended input signal includes the non-inverting input signal: , and the inverting input signal: , that is, the voltage difference of the two-terminal input signal is ; Between the non-inverting input and the inverting input of limiting amplifier 1, the actual voltage difference is ; Between the non-inverting input and the inverting input of limiting amplifier 2, the actual voltage difference ; Between the non-inverting input and the inverting input of the limiting amplifier 3, the actual voltage difference ; ...; Between the non-inverting input and the inverting input of the limiting amplifier m, the actual voltage difference ; Between the positive and negative output terminals of the limiting amplifier m, the actual voltage difference ; Combined with the current relationship diagram, it can be seen that when a DC signal is input to the logarithmic conversion circuit, the DC signal is amplified step by step, and the offset voltage of the limiting amplifier will form an offset current through the rectifier and be added to the output voltage of the logarithmic conversion circuit, causing a large measurement error and affecting the dynamic range.

[0043] In addition, since the offset voltage is gradually amplified to a value close to the limiting voltage in the multi-stage cascaded limiting amplifier, the amplification range of the limiting amplifier for the input valid signal is greatly reduced, and the dynamic range of the valid signal is finally compressed. In extreme cases, if many limiting amplifiers are cascaded, the offset voltage of the limiting amplifier will cause its output to be directly saturated, and it will be unable to amplify small DC input signals, making the logarithmic conversion circuit function ineffective.

[0044] Based on this, the embodiment of the present disclosure provides a logarithmic conversion circuit, which first uses a chopper circuit to convert a DC input signal into an AC input signal, and then the conversion circuit amplifies it step by step. The feedback circuit performs feedback compensation on the i-th to j-th amplifier circuits according to the DC part or low-frequency part of the amplified signal output by the j-th amplifier circuit, offsetting and suppressing the DC offset voltage generated inside the amplifier circuit; at the same time, since the signal to be amplified (effective DC input signal) is converted into AC, the feedback circuit will not produce unnecessary suppression on this part of the signal. Finally, the offset voltage in the amplifier circuit is suppressed, and the DC input signal is converted into an AC input signal and amplified in an AC manner, and finally converted into a DC output signal and output, which reduces the measurement error and is beneficial for the circuit to achieve a large dynamic range.

[0045] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0046] In one embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of the composition structure of a logarithmic conversion circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 3 As shown, the logarithmic conversion circuit 10 may include a chopping circuit 11, a conversion circuit 12 and a feedback circuit 13, wherein:

[0047] The input end of the chopper circuit 11 receives a DC input signal, and the chopper circuit 11 converts the DC input signal into an AC input signal, and the output end of the chopper circuit 11 outputs the AC input signal;

[0048] The input end of the conversion circuit 12 is connected to the output end of the chopper circuit 11. The conversion circuit 12 is used to receive an AC input signal, and amplify and convert the AC input signal to generate a DC output signal. The conversion circuit 12 includes N cascaded amplifier circuits 121. The first-stage amplifier circuit 121 receives an AC input signal.

[0049] The feedback circuit 13 is connected between the output end of the j-th stage amplifier circuit 121 and the input end of the i-th stage amplifier circuit 121, and is used to generate a feedback signal according to the DC part or the low-frequency part in the j-th amplified signal output by the j-th stage amplifier circuit 121, and feed the feedback signal back to the input end of the i-th stage amplifier circuit 121, wherein N is an integer greater than 0, i and j are both integers greater than or equal to 1 and less than or equal to N, and j is greater than or equal to i.

[0050] It should be noted that the amplifier circuit 121 can be specifically an amplifier, such as the aforementioned limiting amplifier, for amplifying the signal input therein. In this embodiment, it is necessary to suppress the offset voltage of the cascaded limiting amplifier. In addition, since the input signal and the offset voltage to be amplified are both DC signals, when suppressing the offset voltage of the limiting amplifier, it is also necessary to ensure that the valid input signal is not lost.

[0051] Therefore, in order to avoid adverse effects on the input voltage, the embodiment of the present disclosure utilizes a chopper circuit 11 to convert the input DC signal into an AC signal so as to distinguish the AC voltage from the DC offset voltage. The feedback circuit 13 is mainly used to suppress this part of the DC offset voltage. Finally, the conversion circuit 12 is used to implement logarithmic conversion so that the overall DC output signal is in a logarithmic relationship with the DC input signal.

[0052] like Figure 3 As shown, the input end of the chopper circuit 11 receives a DC input signal, and the output end of the chopper circuit 11 is connected to the first-stage amplifier circuit 121 in the conversion circuit 12. In this embodiment, the chopper circuit 11 converts the DC input signal into an AC input signal, and transmits it to the first-stage amplifier circuit 121. In this way, the amplifier circuit 121 amplifies the AC input signal and the DC offset voltage generated by the amplifier circuit 121 itself step by step, and the feedback circuit 13 generates a DC feedback signal to suppress the DC offset signal, and does not suppress the AC signal, so as to ensure that the offset voltage is suppressed while not affecting the normally amplified signal.

[0053] It should also be noted that if Figure 3As shown, in the conversion circuit 12, the output ends of the N amplifier circuits 121 and the output end of the chopper circuit 11 are coupled together, serving as the output end of the conversion circuit 12, and also the output end of the logarithmic conversion circuit 10, for outputting a DC output signal. The N amplifier circuits 121 amplify the AC input signal step by step, and the conversion circuit 12 also converts the AC input signal and the N amplified signals (all AC signals) output by the N amplifier circuits 121 into DC, and finally merges them to obtain a DC output signal. Figure 3 In the figure, the wavy lines indicate other circuits that may exist in the conversion circuit 12 and are omitted.

[0054] In this embodiment, “coupling” includes an indirect connection through other circuits, or, if possible, may also include a direct connection achieved only through wires or the like.

[0055] As an example, in Figure 3 In the embodiment, the feedback circuit 13 is connected between the output end of the last stage (Nth stage) amplifier circuit 121 and the input end of the second stage amplifier circuit 121, that is, i=2, j=N, so that the feedback circuit 13 receives the Nth amplified signal after being amplified by the Nth stage amplifier circuit 121, and the feedback circuit 13 filters out the AC part in the Nth amplified signal, and only allows the DC part or the low-frequency part to pass through, so as to obtain the feedback signal. Here, the feedback signal can be the DC part or the low-frequency part obtained directly after filtering out the AC part, and an amplification coefficient can be set according to actual conditions, and the DC part or the low-frequency part obtained can be amplified to a certain extent to obtain the feedback signal, and then the feedback signal acts on the input end of the second stage amplifier circuit 121 to suppress the offset voltage inside the second stage amplifier circuit 121 to the Nth stage amplifier circuit 121.

[0056] It should also be noted that the feedback circuit 13 only allows the DC part of the j-th amplified signal to pass, or the feedback circuit 13 only allows the low-frequency part of the j-th amplified signal to pass; it can be understood that the DC signal is a special case of the low-frequency signal, and if the low-frequency part is passed, the DC part thereof will also pass; in this case, even if a small amount of AC signal passes, causing the AC input signal to be slightly suppressed, the effect of such suppression can be ignored after step-by-step amplification. Here, the low-frequency part can be the common definition of low frequency in the fields of amplifiers, etc., or it can be combined with the circuit and the signal frequency environment in use, and a frequency threshold is set, and the part of the signal with a frequency less than the frequency threshold is called the low-frequency part, and no specific limitation is made to this.

[0057] In addition, in other examples, the feedback circuit 13 can be connected between the output terminal of any post-stage amplifier circuit 121 and the input terminal of any pre-stage amplifier circuit 121 as needed. When the loop gain formed by the i-th stage amplifier circuit 121 and the j-th stage amplifier circuit 121 and the feedback circuit 13 is larger, the offset voltage is suppressed more comprehensively.

[0058] The chopper circuit 11 may be a chopper. That is to say, in view of the problems existing in the traditional logarithmic conversion circuit, the present solution proposes a structure of a "logarithmic conversion circuit of a single chopper (i.e., chopper circuit 11) + a DC offset suppression feedback loop (i.e., feedback circuit 13)", which is used to suppress the DC offset voltage of the logarithmic conversion circuit, thereby reducing the measurement error and improving the dynamic range of the measurement.

[0059] First, since the input signal and the offset voltage of the cascade limiting amplifier are both DC signals, in order to suppress the offset voltage without losing the effective input signal, a chopper is first used at the input end to modulate the effective signal into AC and distinguish the frequency from the DC offset signal.

[0060] Then, the feedback circuit 13 is used in the subsequent stage to form a negative feedback loop with the forward path of the amplifier circuit itself, so as to suppress the DC offset voltage of the amplifier circuit to a very low value, while not suppressing the useful signal in AC. Therefore, the final output current includes a complete useful signal and a very low offset current, thereby forming an accurate output voltage.

[0061] In this way, after the DC-to-AC processing by the chopper circuit 11, the DC offset voltage is distinguished from the AC input signal (AC voltage), and then the feedback circuit 13 suppresses the DC offset voltage. This solution reduces the offset voltage and the measurement error, which is beneficial for the circuit to achieve a large dynamic range.

[0062] It should also be noted that the feedback circuit 13 is configured to utilize the output signal of the preceding circuit of the i-th stage amplifier circuit 121 minus the feedback signal to form an input signal of the i-th stage amplifier circuit 121; wherein, when i is equal to 1, the preceding circuit of the i-th stage amplifier circuit 121 is the chopper circuit 11; when i is greater than 1, the preceding circuit of the i-th stage amplifier circuit 121 is the i-1-th stage amplifier circuit 121.

[0063] Here, the output signal of the previous stage circuit may be subtracted from the feedback signal to form an input signal of a feedback loop (i-th stage amplifier circuit 121 to j-th stage amplifier circuit 121 + feedback circuit 13), thereby achieving the suppression of the offset voltage.

[0064] See also Figure 4 , which shows a schematic diagram of the composition structure of a logarithmic conversion circuit provided by an embodiment of the present disclosure Figure 2 .like Figure 4 As shown, in some embodiments, the conversion circuit 12 also includes N+1-level rectifiers 122, wherein: the input end of the 1st-level rectifier 122 is connected to the output end of the chopper circuit 11; the input end of the s-th-level rectifier 122 is connected to the output end of the s-1-th-level amplifier circuit 121, where s is an integer greater than 1 and less than or equal to N+1; the output ends of the N+1 rectifiers 122 are connected as the output end of the conversion circuit 12, for outputting a DC output signal.

[0065] In some embodiments, the conversion circuit 12 also includes N-stage rectifiers 122, for example, the input end of each stage rectifier 122 is connected to the output end of an amplifier circuit 121, and the output ends of all rectifiers 122 are connected to output a DC output signal; or, the input end of each stage rectifier 122 is connected to the input end of an amplifier circuit 121, and the output ends of all rectifiers 122 are connected to output a DC output signal.

[0066] It should be noted that if Figure 4 As shown, the first-stage rectifier 122 is connected to the output end of the chopper circuit 11, and is used to convert the AC input signal into DC. Each stage of the second to N+1-stage rectifiers 122 is connected to the output end of an amplifier circuit 121, and the amplified AC signal is converted into a DC signal step by step. The DC signals of each stage are added as the final DC output signal, and finally logarithmic conversion is achieved.

[0067] For the feedback circuit 13, in some embodiments, as Figure 4 As shown, the feedback circuit 13 may include a filter circuit 131, and the filter circuit 131 is connected between the output end of the j-th stage amplifier circuit 121 and the input end of the i-th stage amplifier circuit 121; wherein:

[0068] The filter circuit 131 is used for receiving the j-th amplified signal and filtering the j-th amplified signal to allow the DC part or the low-frequency part of the j-th amplified signal to pass through and generate a feedback signal.

[0069] It should be noted that the DC part represents the DC offset voltage of multiple amplifier circuits 121, and the j-th amplified signal includes the AC input voltage and the DC offset voltage after N-stage amplification; the purpose of the filtering process performed by the filter circuit 131 is to distinguish the AC voltage from the DC offset voltage, and only allow the DC part or the low-frequency part to pass, and not allow the AC part or the high-frequency part to pass (the high-frequency part here is relative to the low-frequency part). Here, the filter circuit 131 can be a low-pass filter, which allows the DC part or the low-frequency part in the j-th amplified signal to pass, forming a feedback signal to be transmitted to the input end of the i-th amplifier circuit 121, acting on the i-th amplifier circuit 121 to the j-th amplifier circuit 121, and suppressing the offset voltage.

[0070] For the feedback circuit 13, in some other embodiments, see Figure 5 , which shows a schematic diagram of the composition structure of a logarithmic conversion circuit provided by an embodiment of the present disclosure Figure 3 .like Figure 5 As shown, the feedback circuit 13 may further include a feedback amplifier 132, the input end of the feedback amplifier 132 is connected to the output end of the filter circuit 131, and the output end of the feedback amplifier 132 is connected to the input end of the i-th stage amplifier circuit 121; wherein:

[0071] The feedback amplifier 132 is used to amplify the feedback signal. The feedback amplifier 132 may be a voltage amplifier, which is used to provide voltage gain.

[0072] It should be noted that in Figure 4 On the basis of Figure 5 As shown, a feedback amplifier 132 may be provided in the feedback circuit 13. The function of the feedback amplifier 132 is to amplify the signal input therein. Since it is located in the feedback circuit 13 and plays a feedback role, it is called a feedback amplifier. The gain of the feedback amplifier 132 may be greater than or equal to 1. The greater the gain, the stronger the suppression effect on the offset voltage. If the gain of the feedback amplifier 132 is equal to 1, it means that the feedback amplifier 132 does not work, which is equivalent to Figure 4 The feedback amplifier 132 amplifies the feedback signal, and the amplified feedback signal has a stronger suppressive effect on the offset voltage in the amplifier circuit 121 .

[0073] Furthermore, in the embodiment of the present disclosure, the logarithmic conversion circuit 10 can be a dual-end input, then correspondingly, the DC input signal can include a positive-phase DC input signal and a negative-phase DC input signal, the AC input signal can include a positive-phase AC input signal and a negative-phase AC input signal, the j-th amplified signal can include a j-th positive-phase amplified signal and a j-th negative-phase amplified signal, and the feedback signal can include a positive-phase feedback signal and a negative-phase feedback signal.

[0074] See also Figure 6 , which shows a schematic diagram of the composition structure of a logarithmic conversion circuit provided by an embodiment of the present disclosure Figure 4 .like Figure 6As shown, the positive-phase DC input signal can be represented by "DCIN+", the negative-phase DC input signal can be represented by "DCIN-", the positive-phase AC input signal can be represented by "ACIN+", the negative-phase AC input signal can be represented by "ACIN-", the nth stage positive-phase amplified signal can be represented by "An+", the nth negative-phase amplified signal can be represented by "An-", n is an integer greater than 0 and less than or equal to N, the DC output signal can be represented by "OUT", the positive-phase feedback signal can be represented by "F+", the negative-phase feedback signal can be represented by "F-", the amplified positive-phase feedback signal can be represented by "F`+", and the amplified negative-phase feedback signal can be represented by "F`-".

[0075] like Figure 6 As shown, in some embodiments, each amplifier circuit 121 includes a non-phase input terminal (+), an inverting input terminal (-), a non-phase output terminal (+) and an inverting output terminal (-), each rectifier 122 includes a first input terminal, a second input terminal and an output terminal, the filter circuit 131 includes a first input terminal, a second input terminal, a first output terminal and a second output terminal, and the feedback amplifier 132 includes a non-phase input terminal (+), an inverting input terminal (-), a non-phase output terminal (+) and an inverting output terminal (-); wherein:

[0076] The first input end of the first-stage rectifier 122 and the non-inverting input end of the first-stage amplifier circuit 121 are both connected to the first output end of the chopper circuit 11, and the second input end of the first-stage rectifier 122 and the inverting input end of the first-stage amplifier circuit 121 are both connected to the second output end of the chopper circuit 11;

[0077] The first input terminal of the s-th stage rectifier 122 and the non-inverting input terminal of the s-th stage amplifier circuit 121 are both connected to the non-inverting output terminal of the s-1-th stage amplifier circuit 121, and the second input terminal of the s-th stage rectifier 122 and the inverting input terminal of the s-th stage amplifier circuit 121 are both connected to the inverting output terminal of the s-1-th stage amplifier circuit 121;

[0078] The non-inverting output terminal of the j-th stage amplifier circuit 121 is connected to the first input terminal of the filter circuit 131, and the inverting input terminal of the j-th stage amplifier circuit 121 is connected to the second input terminal of the filter circuit 131; the non-inverting input terminal of the feedback amplifier 132 is connected to the first output terminal of the filter circuit 131, and the inverting input terminal of the feedback amplifier 132 is connected to the second output terminal of the filter circuit 131;

[0079] The non-inverting input terminal of the i-th stage amplifier circuit 121 is connected to the inverting output terminal of the feedback amplifier 132 , and the inverting input terminal of the i-th stage amplifier circuit 121 is connected to the non-inverting output terminal of the feedback amplifier 132 .

[0080] It should be noted that if Figure 4As shown, i=2, j=N is still taken as an example, that is, the feedback circuit 13 is connected between the output end of the N-th stage amplifier circuit 121 and the input end of the second stage amplifier circuit 121. Here, since the amplifier circuit 121 can be a limiting amplifier (limiting amplifier stage), the N amplifier circuits 121 are respectively represented as limiting amplifier 1, limiting amplifier 2, limiting amplifier 3, ... limiting amplifier N; and the N+1 rectifiers 122 are respectively represented as rectifier 1, rectifier 2, ... rectifier N+1.

[0081] The first-stage rectifier rectifies the positive-phase AC input signal ACIN+ and the negative-phase AC input signal ACIN- to obtain the corresponding DC signal; the second to N+1-stage rectifiers respectively rectify the positive-phase amplified signal An+ and the negative-phase amplified signal An- output by the first to N-stage amplifier circuits to obtain the corresponding DC signal, and the N+1 DC signals are integrated into the DC output signal OUT. Here, as Figure 6 As shown, the load resistor is connected between the output terminal of the conversion circuit 12 and the ground terminal to convert the current signal into a voltage signal.

[0082] It should also be noted that the positive phase output terminal of the feedback amplifier 132 may be inverted and connected to the positive phase input terminal of the i-th stage amplifier circuit 121, and the negative phase output terminal of the feedback amplifier 132 may be inverted and connected to the negative phase input terminal of the i-th stage amplifier circuit 121.

[0083] If the feedback circuit 13 does not include the feedback amplifier 132, the positive feedback signal output from the first output terminal of the filter circuit 131 is inverted and connected to the positive input terminal of the i-th stage amplifier circuit 121; the negative feedback signal output from the second output terminal of the filter circuit 131 is inverted and connected to the negative input terminal of the i-th stage amplifier circuit 121.

[0084] exist Figure 6 On this basis, for ease of understanding, the offset voltage of each cascaded limiting amplifier can be equivalent to the input terminal, Figure 7 The figure shows the relationship between the voltage difference ΔV between the positive phase input terminal and the negative phase input terminal of each level of the limiting amplifier and the relationship between the output current I of each level of the rectifier 122 and the time t when there is no signal input. Figure 7 As shown, between the positive-phase input terminal and the negative-phase input terminal of the limiting amplifier 1 to the limiting amplifier N, and between the positive-phase output terminal and the negative-phase output terminal of the limiting amplifier N, the corresponding voltage difference , ,……, , Approximately equal to ; The current I output from rectifier 1 to rectifier N+1 1 ,I 2 ,……,IN+1 Also extremely low.

[0085] It can be seen that when the logarithmic conversion circuit 10 has no DC input signal, due to the existence of the feedback circuit 13, it and the cascaded limiting amplifier form a negative feedback loop, so that the equivalent offset voltage at the input end of each stage of the limiting amplifier will not be amplified step by step and superimposed, but each stage of the output end is suppressed to be approximately equal to the equivalent input offset voltage value of the next stage. Therefore, the output voltage of each stage of the limiting amplifier is very small, and the offset current formed by the rectifier 122 is also very small, so that the output voltage (i.e., the DC output signal, written as output voltage in the subsequent figures) is basically not affected by the offset voltage. Although the offset voltage will change with the change of temperature, due to the suppression effect of the negative feedback loop formed by the DC offset feedback loop and the cascaded limiting amplifier, and the absolute value of the equivalent input offset voltage of each stage is very small, the logarithmic conversion circuit 10 has only a small DC voltage deviation at different temperatures.

[0086] Further, such as Figure 8 As shown, when a DC signal is input to the logarithmic conversion circuit 10, the DC signal is first chopped into AC. Figure 8 The figure shows the relationship between the voltage difference ΔV' (AC signal, represented by a solid line) of the input signal at the positive input and the negative input of each level of the limiting amplifier and the voltage difference ΔV caused by the offset voltage (DC signal, represented by a dotted line) with time t, and the relationship between the output current I of each level of the rectifier with time t. Figure 2 The same, no further description. Figure 8 As shown, since the chopper circuit 11 converts the DC input signal into an AC input signal, the voltage difference of the converted AC input signal is expressed as It means that the actual voltage difference between the non-inverting input and the inverting input of the limiting amplifier 1 is ; Between the non-inverting input and the inverting input of limiting amplifier 2, the actual voltage difference ; Between the non-inverting input and the inverting input of the limiting amplifier 3, the actual voltage difference ; ...; Between the non-inverting input and the inverting input of the limiting amplifier N, the actual voltage difference ; Between the positive and negative output terminals of the limiting amplifier N, the actual voltage difference ; Combined with the current relationship diagram, it can be seen that the effective signal (AC) and the offset voltage (DC) are distinguished in frequency. Since the DC offset voltage of the cascade limiting amplifier has been suppressed by the loop formed by the feedback circuit 13 and the cascade limiting amplifier, the output of each stage of the limiting amplifier mainly outputs the effective signal modulated to AC. The rectifier 122 has the ability to convert AC to DC and can produce accurate output for the modulated AC effective signal. The offset current formed by the offset voltage through the rectifier 122 is very small, and the measurement error is greatly reduced.

[0087] In addition, since the offset voltage is greatly suppressed, the voltage margin available for the limiting amplifier to input a valid signal is greatly increased, effectively expanding the dynamic range of the valid signal.

[0088] In another specific implementation, Fig. 9 As shown, the feedback circuit 13 is connected between the output end of the Nth stage amplifier circuit 121 and the input end of the first stage amplifier circuit 121. The technical principle is the same as that of the above Figure 6 In addition, the access point of the feedback circuit 13 can be changed according to the specific DC offset voltage suppression effect requirements, and the number of feedback circuits 13 can also be changed to produce different implementation methods and DC offset voltage suppression effects.

[0089] like Fig.10 , the number of feedback circuits 13 is multiple, and one feedback circuit 13 corresponds to one amplifier circuit group;

[0090] A plurality of adjacent amplifier circuits 121 form an amplifier circuit group, the output end of the amplifier circuit group is the output end of the last amplifier circuit 121 in the amplifier circuit group, and the input end of the amplifier circuit group is the input end of the first amplifier circuit 121 in the amplifier circuit group; or, one amplifier circuit 121 forms an amplifier circuit group, the output end of the amplifier circuit group is the output end of one amplifier circuit 121, and the input end of the amplifier circuit group is the input end of one amplifier circuit 121;

[0091] For each feedback circuit 13, the feedback circuit 13 is respectively connected to the output end of the amplifier circuit group and the input end of the amplifier circuit group. The feedback circuit 13 is used to generate a feedback signal according to the DC signal in the signal at the output end of the amplifier circuit group, and feed the feedback signal back to the input end of the amplifier circuit group.

[0092] It should be noted that Fig.10 As shown in the figure, for example, two feedback circuits are included, namely feedback circuit 13-1 and feedback circuit 13-2, and each feedback circuit only includes a filter circuit 131. It can be understood that each feedback circuit may also include a feedback amplifier 132, or some may include the feedback amplifier 132 and some may not include the feedback amplifier 132, and no specific limitation is made to this.

[0093] Among them, the limiting amplifier 1 forms an amplifier circuit group, and forms a feedback loop with the feedback circuit 13-1. The feedback circuit 13-1 generates a feedback signal for suppressing the offset voltage of the limiting amplifier 1; the limiting amplifiers 3 to the limiting amplifier N form an amplifier circuit group, and form a feedback loop with the feedback circuit 13-2. The feedback circuit 13-2 generates a feedback signal for suppressing the offset voltage of the limiting amplifier 3 to the limiting amplifier N.

[0094] It should also be noted that Fig.10 The example shown is only an example of a case where multiple feedback circuits 13 are included. The number and access points of the feedback circuits 13 can be flexibly set according to actual conditions.

[0095] Below, the specific circuit implementation of each component structure is exemplarily described in detail in conjunction with the accompanying drawings.

[0096] In this embodiment, the chopper circuit 11 may be a chopper, which is used to convert a DC input signal into an AC input signal. Fig.11 As shown, the first input terminal of the chopper circuit 11 (chopper) is denoted as V IN+ (positive input terminal), the second input terminal is denoted as V IN- (negative input terminal), the first output terminal is denoted as V OUT+ (positive output terminal), the second output terminal is denoted as V OUT- (Negative output terminal). Fig.11 The waveforms of the voltage (V) of the DC signal and the AC signal changing with time t before and after the processing by the chopper circuit 11 are also shown. It can be seen that the voltage value of the DC signal is a constant value, and the voltage value of the AC signal changes periodically.

[0097] Several specific implementations of the chopper circuit 11 are described below by way of example, but are not limited thereto.

[0098] In some embodiments, see Fig.12 , which shows a schematic diagram of the composition structure of a chopper circuit provided by an embodiment of the present disclosure Figure 1 .like Fig.12 As shown, the chopper circuit 11 may include a first switch circuit 111, a second switch circuit 112, a third switch circuit 113 and a fourth switch circuit 114, wherein:

[0099] A first end of the first switch circuit 111 and a first end of the second switch circuit 112 are connected as a first input end of the chopping point 11 for receiving a positive-phase DC input signal; a first end of the third switch circuit 113 and a first end of the fourth switch circuit 114 are connected as a second input end of the chopping circuit 11 for receiving a negative-phase DC input signal; a second end of the first switch circuit 111 and a second end of the third switch circuit 113 are connected as a first output end of the chopping circuit 11 for outputting a positive-phase AC input signal; a second end of the second switch circuit 112 and a second end of the fourth switch circuit 114 are connected as a second output end of the chopping circuit for outputting a negative-phase AC input signal.

[0100] It should be noted that the main function of the chopper circuit 11 is to modulate the DC voltage to AC. During the operation of the chopper circuit 11, the control clock can be used to control the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114. Its working mechanism is to connect the positive input terminal and the negative input terminal to the positive output terminal and the negative output terminal respectively through four-way switches. By controlling the control clock of the four-way switch, the positive output terminal can be connected to the positive input terminal in a time period, and the negative output terminal can be connected to the negative input terminal at the same time, and the positive output terminal can be connected to the negative input terminal in another time period, and the negative output terminal can be connected to the positive input terminal, thereby realizing the process of converting the signal from DC to an AC square wave signal.

[0101] For example, when the first switch circuit 111 and the fourth switch circuit 114 are turned on at the same time, the second switch circuit 112 and the third switch circuit 113 are turned off at the same time; or, when the second switch circuit 112 and the third switch circuit 113 are turned on at the same time, the first switch circuit 111 and the fourth switch circuit 114 are turned off at the same time, thereby realizing the conversion of the input DC signal into an AC signal.

[0102] Here, each switch circuit can be specifically implemented by a combination of NMOS and PMOS tubes or by separately implementing the four-way switch of the chopper, or can be implemented by NPN or PNP transistors. A pair of first clock signals and second clock signals, which are mutually inverted signals, can be used to control the opening and closing of each switch circuit. In some embodiments, at least some of the switches in the first switch circuit 111, the second switch circuit 112, the third switch circuit 113, and the fourth switch circuit 114 can be different types of switches.

[0103] In the first implementation, see Fig.13 , which shows a detailed structural diagram of a chopper circuit provided by an embodiment of the present disclosure Figure 1 .like Fig.13As shown, if the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all transmission gates, the first control end of the first switch circuit 111, the second control end of the second switch circuit 112, the second control end of the third switch circuit 113 and the first control end of the fourth switch circuit 114 are all used to receive the first clock signal CLK+; the second control end of the first switch circuit 111, the first control end of the second switch circuit 112, the first control end of the third switch circuit 113 and the second control end of the fourth switch circuit 114 are all used to receive the second clock signal CLK-.

[0104] It should be noted that the transmission gate is composed of a PMOS tube and an NMOS tube, wherein the control end (gate) of the NMOS tube serves as the first control end of the transmission gate, and the control end (gate) of the PMOS tube serves as the second control end of the transmission gate. The first end of the PMOS tube and the first end of the NMOS tube are connected as the first end of the transmission gate, that is, the first end of the corresponding switch circuit; the second end of the PMOS tube and the second end of the NMOS tube are connected as the second end of the transmission gate, that is, the second end of the corresponding switch circuit. The two control ends of the transmission gate receive a pair of inverted first clock signals and second clock signals, respectively, so as to realize the opening and closing of the four transmission gates as required.

[0105] In the second implementation, see Fig.14 , which shows a detailed structural diagram of a chopper circuit provided by an embodiment of the present disclosure Figure 2 If the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all single-pole single-throw switches, the control end of the first switch circuit 111 and the control end of the fourth switch circuit 114 are both used to receive the first clock signal CLK+, and the control end of the second switch circuit 112 and the control end of the third switch circuit 113 are both used to receive the second clock signal CLK-.

[0106] In the third implementation, see Fig.15 , which shows a detailed structural diagram of a chopper circuit provided by an embodiment of the present disclosure Figure 3 If the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all NMOS transistors, the control end of the first switch circuit 111 and the control end of the fourth switch circuit 114 are both used to receive the first clock signal CLK+, and the control end of the second switch circuit 112 and the control end of the third switch circuit 113 are both used to receive the second clock signal CLK-.

[0107] In the fourth implementation, see Fig.16 , which shows a detailed structural diagram of a chopper circuit provided by an embodiment of the present disclosure Figure 4 If the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all PMOS tubes, the control end of the first switch circuit 111 and the control end of the fourth switch circuit 114 are both used to receive the second clock signal CLK-, and the control end of the second switch circuit 112 and the control end of the third switch circuit 113 are both used to receive the first clock signal CLK+.

[0108] It should be noted that if the switching circuit is an NMOS tube or a PMOS tube, then the first end and the second end of the switching circuit can be the drain and source of the NMOS tube or the PMOS tube respectively, and the control end can be a gate. According to the signal received by the gate, the conduction and cutoff of the MOS tube are controlled to realize the conduction and cutoff of the switching circuit.

[0109] It should also be noted that chopping technology is often used in pairs in low-offset amplifiers. The conventional method of use is to chop the low-frequency signal into an AC high-frequency signal, and then after entering the amplifier, chop the signal back to a low frequency, and chop the DC offset voltage to an AC high frequency. Finally, the signal is retained through a low-pass filter, and the offset voltage modulated to the AC high frequency is filtered out. Therefore, chopping technology is usually used in pairs of two choppers. In this solution, only one chopper is used to modulate the signal to a high frequency to distinguish the effective signal from the offset voltage of the cascade amplifier. Since the rectifier has the ability to process both high-frequency AC signals and DC signals, there is no need to use an additional chopper to modulate the signal back to a low frequency, and the energy loss caused by the signal being modulated again is avoided.

[0110] For the feedback circuit 13 (DC offset suppression feedback loop), its main function is to suppress the DC offset voltage by forming a negative feedback loop with the cascaded limiting amplifier, while not suppressing the AC signal. The working mechanism is to use the filter circuit 131 (low-pass filter), the DC offset voltage will pass through the low-pass filter smoothly and be amplified by the feedback amplifier 132 (if the feedback amplifier 132 is included), forming a feedback coefficient greater than 1, and finally being suppressed by the negative feedback loop formed by the feedback circuit 13 and the cascaded limiting amplifier. However, for AC signals, due to the existence of the low-pass filter, its DC offset suppression feedback loop is equivalent to an open circuit, that is, the negative feedback loop does not work, so the AC signal will still be amplified step by step as if there is no feedback loop.

[0111] The filter circuit 131 in the feedback circuit 13 can be implemented by passive resistors and capacitors, or by passive resistors and capacitors combined with active amplifiers, which are described below with examples, but are not limited thereto.

[0112] For the filter circuit 131, in the accompanying drawings, the first input terminal of the filter circuit 131 is denoted as V IN+(positive input terminal), the second input terminal is denoted as V IN- (negative input terminal), the first output terminal is denoted as V OUT+ (positive output terminal), the second output terminal is denoted as V OUT- (negative output terminal). In the first implementation, see Fig.17 , which shows a schematic diagram of the composition structure of the filter circuit provided by the embodiment of the present disclosure Figure 1 .like Fig.17 As shown, the filter circuit 131 may include a first filter resistor R LPF1 , the second filter resistor R LPF2 , the first filter capacitor C LPF1 and the second filter capacitor C LPF2 ;in:

[0113] The first filter resistor R LPF1 The first end of the first filter resistor R LPF1 The second end and the first filter capacitor C LPF1 The first end of the first filter capacitor C is connected as the first output end of the filter circuit 131, for outputting a positive phase feedback signal; LPF1 The second end is connected to the ground terminal;

[0114] The second filter resistor R LPF2 The first end of the second filter resistor R LPF2 The second end of the second filter capacitor C LPF2 The first end of the second filter capacitor C is connected as the second output end of the filter circuit 131, for outputting an inverted feedback signal; LPF2 The second end of is connected to the ground end.

[0115] In the second implementation, see Fig.18 , which shows a schematic diagram of the composition structure of the filter circuit provided by the embodiment of the present disclosure Figure 2 .like Fig.18 As shown, the filter circuit 131 may include: a third filter resistor R LPF3 , the fourth filter resistor R LPF4 , the third filter capacitor C LPF3 , the fourth filter capacitor C LPF4 and filter amplifier A LPF ;in:

[0116] The third filter resistor R LPF3 The first end of the third filter resistor R LPF3 The second end of the third filter capacitor C LPF3The first end of the filter amplifier A LPF The third filter capacitor C LPF3 The second end of the filter amplifier A LPF The inverting output terminal of the filter circuit 131 is connected as the first output terminal of the filter circuit 131, and is used to output an inverting feedback signal;

[0117] The fourth filter resistor R LPF4 The first end of the fourth filter resistor R LPF4 The second end of the fourth filter capacitor C LPF4 The first end of the filter amplifier A LPF The inverting input terminal is connected to the fourth filter capacitor C LPF4 The second end of the filter amplifier A LPF is connected to the inverting output terminal of the filter circuit 131 as the second output terminal of the filter circuit 131, for outputting a positive phase feedback signal.

[0118] It should be noted that the filter amplifier A LPF It is used to amplify the signal input thereto, and because it functions in the filter circuit 131, it is called a filter amplifier.

[0119] As for the feedback amplifier 132, the feedback amplifier 132 in the feedback circuit 13 can be implemented by a single-stage amplifier structure, which can be a simple common-source amplifier or a more complex common-source common-gate amplifier structure. In addition, it can also be implemented by a multi-stage amplifier structure, such as a two-stage cascade amplifier.

[0120] For the feedback amplifier 132, the non-inverting input terminal of the feedback amplifier 132 is denoted as V IN+ , the inverting input terminal is denoted as V IN- , the positive phase output terminal is denoted as V OUT+ , the inverting output terminal is denoted as V OUT- In the first implementation, see Fig.19 , which shows a schematic diagram of the composition structure of the feedback amplifier provided in the embodiment of the present disclosure Figure 1 The feedback amplifier 132 may include a first transistor M1, a second transistor M2, a first feedback resistor R L1 , the second feedback resistor R L2 and the first wake source I-1, where:

[0121] The control terminal of the first transistor M1 is used as the inverting input terminal of the feedback amplifier 132 for receiving the inverted feedback signal; the first feedback resistor R L1 The first end of the first feedback resistor R L1The second end of the first transistor M1 is connected to the first end of the first transistor M1 as an inverting output end of the feedback amplifier 132, for outputting the amplified inverted feedback signal;

[0122] The control terminal of the second transistor M2 is used as the non-inverting input terminal of the feedback amplifier 132 for receiving the non-inverting feedback signal; the second feedback resistor R L2 The first end of the second feedback resistor R L2 The second end of the second transistor M2 is connected to the first end of the second transistor M2 as an inverting output end of the feedback amplifier 132, for outputting the amplified positive feedback signal;

[0123] The second end of the first transistor M1 and the second end of the second transistor M2 are both connected to the first end of the first tail current source I- 1 , and the second end of the first tail current source I- 1 is connected to the ground end.

[0124] In the second implementation, see Fig. 20 , which shows a schematic diagram of the composition structure of the feedback amplifier provided in the embodiment of the present disclosure Figure 2 The feedback amplifier may include a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a third feedback resistor R L3 , the fourth feedback resistor R L4 and the second wake source I-2, where:

[0125] The first end of the third transistor M3, the first end of the fifth transistor M5, the control end of the fifth transistor M5 and the control end of the eighth transistor M8 are connected; the control end of the third transistor M3 serves as an inverting input end of the feedback amplifier 132 for receiving an inverted feedback signal; the second end of the fifth transistor M5 is connected to a power supply;

[0126] The first end of the fourth transistor M4, the first end of the sixth transistor M6, the control end of the sixth transistor M6 and the control end of the seventh transistor M7 are connected; the control end of the fourth transistor M4 serves as a positive phase input end of the feedback amplifier 132 for receiving a positive phase feedback signal; the second end of the sixth transistor M6 is connected to a power supply;

[0127] The second end of the third transistor M3 and the second end of the fourth transistor M4 are both connected to the first end of the second tail current source I-2, and the second end of the second tail current source I-2 is connected to the ground end;

[0128] The first terminal of the seventh transistor M7 and the third feedback resistor R L3 The first end of the third feedback resistor R is connected as the positive phase output end of the feedback amplifier 132, and is used to output the amplified positive phase feedback signal; L3 The second end of the seventh transistor M7 is connected to the power supply;

[0129] The first terminal of the eighth transistor M8 and the fourth feedback resistor R L4 The first end of the fourth feedback resistor R is connected to the inverting output end of the feedback amplifier 132, and is used to output the amplified inverting feedback signal; L4 The second end of the eighth transistor M8 is connected to the power supply.

[0130] The amplifier circuit 121 may be implemented in the following ways, but is not limited thereto. The positive-phase input terminal of the amplifier circuit 121 (limiting amplifier, limiting amplifier stage) is denoted as V IN+ , the inverting input terminal is denoted as V IN- , the positive phase output terminal is denoted as V OUT+ , the inverting output terminal is denoted as V OUT- In the first implementation, see Fig.21 , which shows a schematic diagram of the composition structure of the amplifier circuit provided by the embodiment of the present disclosure Figure 1 .like Fig.21 As shown, the amplifier circuit 121 may include a ninth transistor M9, a tenth transistor M10, a first amplifier resistor R S1 , the second amplifying resistor R S2 , the third amplifying resistor R S3 , the fourth amplifying resistor R S4 and the third wake source I-3, where:

[0131] The control terminal of the ninth transistor M9 serves as the non-inverting input terminal of the amplifier circuit 121;

[0132] The control terminal of the tenth transistor M10 serves as the inverting input terminal of the amplifier circuit 121;

[0133] The first end of the ninth transistor M9 and the first amplifying resistor R S1 The first end is connected as the inverting output end of the amplifier circuit 121;

[0134] The first terminal of the tenth transistor M10 is connected to the second amplifying resistor R S2 The first end is connected as the positive phase output end of the amplifier circuit 121;

[0135] The first amplifying resistor R S1 The second end of the ninth transistor M9 is connected to the ground end; the second end of the ninth transistor M9 is connected to the third amplifying resistor R S3 The first end of the second amplifying resistor R S2 The second end of the tenth transistor M10 is connected to the ground end; the second end of the tenth transistor M10 is connected to the fourth amplifying resistor R S4 The first end of the fourth amplifying resistor R S4 The second end and the third amplifying resistor R S3The second ends of the two tail current sources 1-1 and 1-2 are connected to the second end of the third tail current source 1-3, and the first end of the third tail current source 1-3 is connected to the power supply.

[0136] In the second implementation, see Fig. 22 , which shows a schematic diagram of the composition structure of the amplifier circuit provided by the embodiment of the present disclosure Figure 2 .like Fig. 22 As shown, the amplifier circuit 121 may include an eleventh transistor M11, a twelfth transistor M12, a fifth amplifying resistor R S5 , the sixth amplifying resistor R S6 , the seventh amplifying resistor R S7 , the eighth amplifying resistor R S8 and the fourth wake source I-4, where:

[0137] The control terminal of the eleventh transistor M11 serves as a non-inverting input terminal of the amplifier circuit 121;

[0138] The control terminal of the twelfth transistor M12 serves as the inverting input terminal of the amplifier circuit 121;

[0139] The first terminal of the eleventh transistor M11 and the fifth amplifying resistor R S5 The second end is connected as the inverting output end of the amplifier circuit 121;

[0140] The first end of the twelfth transistor M12 and the sixth amplifying resistor R S6 The second end is connected as the positive phase output end of the amplifier circuit 121;

[0141] The fifth amplifying resistor R S5 The first end of the eleventh transistor M11 is connected to the power supply, the second end of the eleventh transistor M11 is connected to the seventh amplifying resistor R S7 The first end of the sixth amplifying resistor R S6 The first end of the twelfth transistor M12 is connected to the power supply, the second end of the twelfth transistor M12 is connected to the eighth amplifying resistor R S8 The first end of the eighth amplifying resistor R S8 The second end and the seventh amplifying resistor R S7 The second ends of the fourth tail current source I-4 are connected to the first end of the fourth tail current source I-4, and the second end of the fourth tail current source I-4 is connected to the ground end.

[0142] The rectifier 122 may be implemented in the following ways, but is not limited thereto. The first input terminal of the rectifier 122 is denoted as V IN+ , the second input terminal is denoted as V IN- , the output terminal is denoted as I OUT In the first implementation, see Fig.23 , which shows a schematic diagram of the composition structure of the rectifier provided in the embodiment of the present disclosure Figure 1 .like Fig.23 As shown, the rectifier 122 may include: a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a first rectifier resistor R CM1 , the second rectifier resistor R CM2 and the fifth wake source I-5; among which:

[0143] The first rectifier resistor R CM1 The first end of the second rectifier resistor R CM2 The second end of the first rectifier resistor R CM1 The second end and the second rectifier resistor R CM2 and a control terminal of a fourteenth transistor M14;

[0144] The second end of the thirteenth transistor M13, the second end of the fourteenth transistor M14, and the second end of the fifteenth transistor M15 are all connected to the first end of the fifth tail current source I-5, and the second end of the fifth tail current source I-5 is connected to the ground end;

[0145] The first end of the thirteenth transistor M13, the first end of the fifteenth transistor M15, the first end of the seventeenth transistor M17, and the control end of the eighteenth transistor M18 are all connected to the control end of the seventeenth transistor M17; the first end of the fourteenth transistor M14 is connected to the first end of the sixteenth transistor M16; the second end of the sixteenth transistor M16, the second end of the seventeenth transistor M17, and the second end of the eighteenth transistor M18 are all connected to the power supply; the second end of the eighteenth transistor M18 is connected to the power supply; the first end of the eighteenth transistor M18 serves as the output end of the rectifier 122.

[0146] In the second implementation, see Fig.24 , which shows a schematic diagram of the composition structure of the rectifier provided in the embodiment of the present disclosure Figure 2 .like Fig. 22 As shown, the rectifier 122 may include a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a third rectifier resistor R CM3 , the fourth rectifier resistor R CM4 and the sixth wake source I-6; among which:

[0147] The third rectifier resistor R CM3 The first end of the fourth rectifier resistor R CM4The second end of the third rectifier resistor R CM3 The second end and the fourth rectifier resistor R CM4 The first end of the sixth tail current source I-6 is connected to the first end of the sixth tail current source I-6 and the control end of the twentieth transistor M20; the second end of the nineteenth transistor M19, the second end of the twentieth transistor M20, and the second end of the twenty-first transistor M21 are all connected to the second end of the sixth tail current source I-6, and the first end of the sixth tail current source I-6 is connected to the power supply;

[0148] The first end of the nineteenth transistor M19, the first end of the twenty-first transistor M21, the first end of the twenty-third transistor M23, and the control end of the twenty-fourth transistor M24 are all connected to the control end of the twenty-third transistor M23; the first end of the twentieth transistor M20, the first end of the twenty-second transistor M22, and the control end of the twenty-second transistor M22 are connected; the second end of the twenty-second transistor M22, the second end of the twenty-third transistor M23, and the second end of the twenty-fourth transistor M24 are all connected to the ground end; the first end of the twenty-fourth transistor M24 serves as the output end of the rectifier 122.

[0149] It should be noted that, for the first transistor M1 to the twenty-fourth transistor 24 involved in the embodiment of the present disclosure, the control end may be a gate, the first end may be a drain, and the second end may be a source.

[0150] In the above examples, the rectifier 122 and the limiting amplifier are both implemented based on MOSFETs. Alternatively, they can also be implemented by transistors.

[0151] In short, the embodiment of the present disclosure aims at the problem of offset voltage of the logarithmic conversion circuit based on the multi-stage cascade limiting amplifier, and proposes a logarithmic conversion circuit architecture based on a single chopper and a DC offset suppression feedback loop, which effectively suppresses the offset voltage, reduces the detection error, and expands the dynamic range of the detection. The main technical principle is to first use a chopper at the input end to modulate the effective signal to AC and distinguish the frequency of the DC offset signal. Then, a DC offset feedback loop (feedback circuit 13 and i-th stage amplifier circuit 121 to j-th stage amplifier circuit 121) is used in the later stage. Through the DC offset feedback loop, the DC offset voltage of each stage of the limiting amplifier is suppressed to an extremely low value, so the offset DC in the output DC current after passing through the rectifier is extremely low. And because the rectifier also has the ability to process AC signals, accompanied by extremely low output DC current offset, the effective signal chopped to AC can be converted into an accurate linear output voltage. At the same time, because the offset voltage of the cascade limiting amplifier is suppressed, the effective signal obtains a larger voltage margin, so that the circuit achieves a larger dynamic range. Moreover, the offset voltage of the cascaded limiting amplifier will generally vary greatly at different temperatures (generally, the change is greater than 20% from -40 degrees to 125 degrees). Therefore, even if the offset voltage is first calibrated using a calibration technique, the offset voltage will be affected again due to temperature changes after the circuit is put into operation, and will be amplified step by step. However, using the circuit architecture provided in the embodiment of the present disclosure, the offset voltage can be suppressed to an extremely low value at different temperatures.

[0152] In another embodiment of the present disclosure, see Fig.25 , which shows a schematic diagram of the composition structure of a chip provided by an embodiment of the present disclosure. Fig.25 As shown, the chip 20 includes the logarithmic conversion circuit 10 described in any one of the aforementioned embodiments.

[0153] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0154] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0155] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above is only a specific implementation method of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field of the present disclosure can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A logarithmic conversion circuit, characterized in that: The logarithmic conversion circuit includes a chopper circuit, N cascaded amplifier circuits, a multi-stage rectifier and a feedback circuit, wherein: The input end of the chopper circuit receives a DC input signal, the chopper circuit performs DC-to-AC processing on the DC input signal to generate an AC input signal, and the output end of the chopper circuit outputs the AC input signal; the DC input signal is a valid signal; The input end of the first-stage amplifier circuit is connected to the output end of the chopper circuit to receive the AC input signal; the output end of each amplifier circuit is connected to the input end of one of the rectifiers, and the output ends of all the rectifiers are connected together to output a DC output signal; The feedback circuit is connected between the output end of the j-th stage amplifier circuit and the input end of the i-th stage amplifier circuit, and is used to input a feedback signal to the input end of the i-th stage amplifier circuit, wherein the feedback signal includes a DC part and / or a low-frequency part in the output signal of the j-th stage amplifier circuit, i and j are both integers greater than or equal to 1 and less than or equal to N, and j is greater than or equal to i; The feedback circuit comprises a filter circuit, wherein the first input terminal and the second input terminal of the filter circuit are respectively connected to the positive phase output terminal and the negative phase output terminal of the j-th stage amplifier circuit, and the first output terminal and the second output terminal of the filter circuit are respectively connected to the negative phase output terminal and the positive phase output terminal of the i-th stage amplifier circuit; The filter circuit comprises a first filter capacitor and a second filter capacitor, the first filter capacitor is connected to a first output end of the filter circuit, and the second filter capacitor is connected to a second output end of the filter circuit; The first output end of the chopper circuit is connected to the non-phase input end of the first-stage amplifier circuit for outputting a non-phase DC input signal; the second output end of the chopper circuit is connected to the non-phase input end of the first-stage amplifier circuit for outputting a non-phase DC input signal.

2. The logarithmic conversion circuit according to claim 1, characterized in that: The filter circuit is connected between the output end of the j-th stage amplifier circuit and the input end of the i-th stage amplifier circuit; wherein: The filtering circuit is used to receive the output signal of the j-th stage amplifier circuit and filter the output signal of the j-th stage amplifier circuit to allow the DC part and / or low-frequency part of the output signal of the j-th stage amplifier circuit to pass through and generate the feedback signal.

3. The logarithmic conversion circuit according to claim 2, characterized in that: The feedback circuit further includes a feedback amplifier, the input end of the feedback amplifier is connected to the output end of the filter circuit, and the output end of the feedback amplifier is connected to the input end of the i-th stage amplifier circuit; wherein: The feedback amplifier is used to amplify the feedback signal.

4. The logarithmic conversion circuit according to claim 3, characterized in that: The positive phase input terminal and the negative phase input terminal of each amplifier circuit are respectively connected to the positive phase output terminal and the negative phase output terminal of the amplifier circuit of the previous stage; The first input terminal and the second input terminal of each of the rectifiers are respectively connected to the positive phase output terminal and the negative phase output terminal of one of the amplifier circuits; The first input terminal and the second input terminal of the filter circuit are respectively connected to the positive phase output terminal and the negative phase output terminal of the j-th stage amplifier circuit; The positive-phase input terminal and the negative-phase input terminal of the feedback amplifier are connected to the first output terminal and the second output terminal of the filter circuit respectively; The positive phase output terminal and the negative phase output terminal of the feedback amplifier are respectively connected to the negative phase output terminal and the positive phase output terminal of the i-th stage amplifier circuit.

5. The logarithmic conversion circuit according to claim 4, characterized in that: The DC input signal includes a positive phase DC input signal and a negative phase DC input signal, the AC input signal includes a positive phase AC input signal and a negative phase AC input signal, and the chopper circuit includes a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit, wherein: The first end of the first switch circuit and the first end of the second switch circuit are connected to receive the positive-phase DC input signal; the first end of the third switch circuit and the first end of the fourth switch circuit are connected to receive the negative-phase DC input signal; the second end of the first switch circuit and the second end of the third switch circuit are connected to output the positive-phase AC input signal; the second end of the second switch circuit and the second end of the fourth switch circuit are connected to output the negative-phase AC input signal.

6. The logarithmic conversion circuit according to claim 5, characterized in that: The first switch circuit, the second switch circuit, the third switch circuit or the fourth switch circuit is one or more of a transmission gate, an NMOS tube, a single-pole single-throw switch or a PMOS tube.

7. The logarithmic conversion circuit according to claim 2, characterized in that: The filtering circuit is a low-pass filter.

8. The logarithmic conversion circuit according to claim 3, characterized in that: The feedback amplifier is a voltage amplifier.

9. The logarithmic conversion circuit according to claim 1, characterized in that: The amplifier circuit is a limiting amplifier.

10. The logarithmic conversion circuit according to any one of claims 1 to 9, characterized in that: There are multiple feedback circuits, and one feedback circuit corresponds to one amplifier circuit group; A plurality of adjacent amplifier circuits form an amplifier circuit group, the output end of the amplifier circuit group is the output end of the last amplifier circuit in the amplifier circuit group, and the input end of the amplifier circuit group is the input end of the first amplifier circuit in the amplifier circuit group; or, one amplifier circuit forms an amplifier circuit group, the output end of the amplifier circuit group is the output end of one amplifier circuit, and the input end of the amplifier circuit group is the input end of one amplifier circuit; For each of the feedback circuits, the feedback circuit is respectively connected to the output end of the amplifier circuit group and the input end of the amplifier circuit group, and the feedback circuit is used to generate a feedback signal based on a DC signal in the signal at the output end of the amplifier circuit group, and feed the feedback signal back to the input end of the amplifier circuit group.

11. A chip, characterized in that: The chip comprises the logarithmic conversion circuit according to any one of claims 1 to 10.

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