A display panel

Abstract

The present application provides a display panel, which at least includes an active layer, a gate electrode, and a gate auxiliary structure. The active layer is disposed along a first direction and includes a channel layer. The gate electrode is located above the channel layer, and the width of the gate electrode along the first direction is equal to the length of the channel layer along the first direction. The gate auxiliary structure is disposed adjacent to the gate electrode. Among them, the width of the gate electrode along the first direction is less than 1 micron, so the length of the channel layer along the first direction is also less than 1 micron. The present application can achieve a gate electrode with an extremely small width, and thus achieve a channel layer with an extremely small length. It can not only improve the mobility, reduce the area of the device, and increase the aperture ratio of the panel, but also facilitate the development of products with high resolution and high refresh rate.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel. Background Art

[0002] With the development of display technologies, flat panel display devices such as LCDs and OLEDs have been widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptop computers, and desktop computers due to their advantages of high picture quality, power saving, thin body, and wide application range, and have become the mainstream in display devices.

[0003] With the continuous development of the panel industry, higher requirements have been put forward for parameters such as narrow borders, high aperture ratios, high brightness, and high resolution of display panels, and the manufacturing of panels also faces new challenges. Especially in emerging display technology fields, such as VR / AR displays and panel system integration fields, the array substrate is required to have ultra-high PPI and device sizes at the sub-micron level. To meet these requirements, it is necessary to minimize the size and occupied area of array devices.

[0004] Among them, how to reduce the length of the channel layer in array devices is an important research direction.

[0005] Application Content

[0006] The purpose of this application is to provide a display panel, aiming to reduce the length of the channel layer in the active layer to less than 1 micron.

[0007] On the one hand, this application provides a display panel, which at least includes:

[0008] An active layer, arranged along a first direction and including a channel layer;

[0009] A gate, corresponding to the upper side of the channel layer, and the width of the gate along the first direction is equal to the length of the channel layer along the first direction;

[0010] A gate auxiliary structure, which is arranged adjacent to the gate;

[0011] Wherein, the width of the gate along the first direction is less than 1 micron.

[0012] In some embodiments, the active layer further includes:

[0013] A first ohmic contact layer and a second ohmic contact layer, the first ohmic contact layer and the second ohmic contact layer are respectively located at two ends of the active layer, and the channel layer is located between the first ohmic contact layer and the second ohmic contact layer;

[0014] A first transition layer, which is located between the first ohmic contact layer and the channel layer.

[0015] In some embodiments, the gate auxiliary structure is located on the sidewall of the gate along the first direction, and the positive projection of the first transition layer on the gate auxiliary structure is located within the gate auxiliary structure.

[0016] In some embodiments, the gate auxiliary structure is located on the sidewall of the gate along the first direction, and the positive projection of the first ohmic contact layer on the gate auxiliary structure is located within the gate auxiliary structure.

[0017] In some embodiments, the display panel further includes a source electrode and a drain electrode, the source electrode and the drain electrode are respectively connected to the first ohmic contact layer and the second ohmic contact layer, and the source electrode penetrates through the gate auxiliary structure.

[0018] In some embodiments, the active layer further includes a second transition layer, and the second transition layer is located between the second ohmic contact layer and the channel layer.

[0019] In some embodiments, the gate auxiliary structure is located on the gate, and the width of the gate auxiliary structure along the first direction is equal to the width of the gate along the first direction.

[0020] In some embodiments, the gate auxiliary structure is further located above the second ohmic contact layer and on the sidewalls of the gate trace along the first direction.

[0021] In some embodiments, the first ohmic contact layer and the second ohmic contact layer are doped with an N-type semiconductor material, and the first transition layer is doped with a P-type semiconductor material; the doping concentrations of the first ohmic contact layer and the second ohmic contact layer are greater than the doping concentration of the first transition layer.

[0022] In some embodiments, the second ohmic contact layer includes a first concentration region close to the channel layer and a second concentration region far from the channel layer, and the doping concentration of the first concentration region is less than the doping concentration of the second concentration region.

[0023] The beneficial effects of the present application are as follows: A display panel is provided. The display panel at least includes an active layer, a gate, and a gate auxiliary structure. The active layer is arranged along a first direction and includes a channel layer. The gate corresponds to the upper side of the channel layer, and the width of the gate along the first direction is equal to the length of the channel layer along the first direction. The gate auxiliary structure is arranged adjacent to the gate. Among them, the width of the gate along the first direction is less than 1 micrometer, so the length of the channel layer along the first direction is also less than 1 micrometer. The present application can achieve a gate with an extremely small width, and thus achieve a channel layer with an extremely small length, which can not only improve the mobility, reduce the area of the device, improve the aperture ratio of the panel, but also facilitate the development of products with high resolution and high refresh rate. Description of the Drawings

[0024] Combined with the accompanying drawings below, through a detailed description of the specific embodiments of the present application, the technical solutions and other beneficial effects of the present application will become obvious.

[0025] Figure 1 It is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application;

[0026] Figure 2 It is provided by some embodiments of the present application Figure 1 A schematic top view structure diagram of the display panel in

[0027] Figure 3 It is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application;

[0028] Figure 4 It is provided by some embodiments of the present application Figure 3 A schematic top view structure diagram of the display panel in

[0029] Figure 5 It is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application;

[0030] Figure 6 It is a schematic flowchart of a method for manufacturing a display panel provided by some embodiments of the present application;

[0031] Figures 7a-7e It is a schematic structure diagram of a display panel during the manufacturing process provided by some embodiments of the present application;

[0032] Figures 8a-8g It is a schematic structure diagram of a display panel during the manufacturing process provided by some embodiments of the present application. Specific Embodiments

[0033] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0034] In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0035] In this application, unless otherwise clearly defined or limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the contact between the first and second features through additional features therebetween without direct contact. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.

[0036] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0037] Please refer to Figure 1 , Figure 1 which is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application. The display panel 100 may include thin film transistors, such as low temperature polysilicon transistors, metal oxide transistors, etc. The display panel 100 may be applied to various electronic devices, such as wearable devices such as smart bracelets, smart watches, VR (Virtual Reality) devices, mobile phones, e-books and e-newspapers, televisions, personal portable computers, foldable and rollable flexible display and lighting devices.

[0038] The display panel 100 may include an active layer 10, a gate 20 and a gate auxiliary structure 40. The active layer 10 is arranged along a first direction (X) and includes a channel layer 11. The gate 20 corresponds to the upper side of the channel layer 11, and the width D1 of the gate 20 along the first direction (X) is equal to the length L of the channel layer 11 along the first direction (X). Therefore, the length L of the channel layer 11 is determined by the width D1 of the gate 20. Among them, the width D1 of the gate 20 along the first direction (X) is less than 1 micrometer, so the length L of the channel layer 11 along the first direction (X) is also less than 1 micrometer.

[0039] The gate auxiliary structure 40 is located above the active layer 10 and is disposed adjacent to the gate 20. The gate auxiliary structure 40 is used to assist in the formation of the gate 20 structure, and the material of the gate auxiliary structure 40 can be silicon nitride and / or silicon oxide, etc.

[0040] In some embodiments, the width D1 of the gate 20 in the first direction (X) is 0.05 to 0.5 micrometers.

[0041] In some embodiments, the active layer 10 may further include a first ohmic contact layer 121 and a second ohmic contact layer 122, and a first transition layer 131. The first ohmic contact layer 121 and the second ohmic contact layer 122 are respectively located at both ends of the active layer 10, the channel layer 11 is located between the first ohmic contact layer 121 and the second ohmic contact layer 122, and the first transition layer 131 is located between the first ohmic contact layer 121 and the channel layer 11.

[0042] In some embodiments, the active layer 10 may further include a second transition layer ( Figure 1 not shown), and the second transition layer is located between the second ohmic contact layer 122 and the channel layer 11.

[0043] Among them, the material of the active layer 10 can be low-temperature polycrystalline silicon or semiconductor oxide. The first ohmic contact layer 121 and the second ohmic contact layer 122 can be the active layer 10 doped with N-type semiconductor material. The first transition layer 131 and the second transition layer can be the active layer 10 doped with P-type semiconductor material. The channel layer 11 is the undoped active layer 10. And the first ohmic contact layer 121 and the second ohmic contact layer 122 are heavily doped, and the first transition layer 131 and the second transition layer are lightly doped, that is, the doping concentration of the first ohmic contact layer 121 and the second ohmic contact layer 122 is greater than the doping concentration of the first transition layer 131 and the second transition layer.

[0044] In some embodiments, the second ohmic contact layer 122 further includes a first concentration region 122a close to the channel layer 11 and a second concentration region 122b far from the channel layer 11. The doping concentration of the first concentration region 122a is less than the doping concentration of the second concentration region 122b. Among them, the doping concentration of the second concentration region 122b can be equal to the doping concentration of the first ohmic contact layer 121.

[0045] The display panel 100 may further include a source electrode 31 and a drain electrode 32, the source electrode 31 and the drain electrode 32 are respectively connected to the first ohmic contact layer 121 and the second ohmic contact layer 122, and the first ohmic contact layer 121 and the second ohmic contact layer 122 are used to reduce the contact resistance between the source electrode 31 and the drain electrode 32 and the active layer 10. The active layer 10, the gate electrode 20, the source electrode 31 and the drain electrode 32 may form a thin film transistor. The first transition layer 131 is located between the first ohmic contact layer 121 and the channel layer 11, and can prevent the current in the channel layer 11 from leaking into the first ohmic contact layer 121 when the thin film transistor is turned off. The second transition layer is located between the second ohmic contact layer 122 and the channel layer 11, and can prevent the current in the channel layer 11 from leaking into the second ohmic contact layer 122 when the thin film transistor is turned off.

[0046] In some embodiments, the display panel 100 may further include a substrate 51, a light-shielding layer 52, a buffer layer 53, a gate insulating layer 54 and a dielectric layer 55. The light-shielding layer 52 is located on the substrate 51, the buffer layer 53 is located on the substrate 51 and covers the light-shielding layer 52, and the gate insulating layer 54 is located on the buffer layer 53 and covers the active layer 10. The gate electrode 20 and the gate auxiliary structure 40 are located on the gate insulating layer 54, and the dielectric layer 55 is located on the gate insulating layer 54 and covers the gate electrode 20 and the gate auxiliary structure 40. The source electrode 31 and the drain electrode 32 penetrate through the dielectric layer 55 and a part of the gate insulating layer 54.

[0047] Please refer to Figure 2 , Figure 2 which is Figure 1 a top view structural schematic diagram of the display panel provided in some embodiments of the present application.

[0048] As Figure 1 and Figure 2 shown, the gate auxiliary structure 40 is located on the side wall of the gate electrode 20 along the first direction (X), and the orthographic projection of the first transition layer 131 on the gate auxiliary structure 40 is located within the gate auxiliary structure 40, that is, the gate auxiliary structure 40 and the first transition layer 131 are located on the same side of the gate electrode 20.

[0049] The display panel 100 includes a gate layer 20a located on the gate insulating layer 54. The thickness of the gate layer 20a is equal to the thickness of the gate auxiliary structure 40, and the gate layer 20a surrounds the side wall of the gate auxiliary structure 40, that is, the gate auxiliary structure 40 is embedded in the gate layer 20a. Among them, the gate layer 20a between the gate auxiliary structure 40 and the second ohmic contact layer 122 is the gate electrode 20, that is, the part of the gate layer 20a directly above the channel layer 11 is the gate electrode 20.

[0050] The display panel 100 may further include a gate trace 20b connected to the gate 20. The gate trace 20b is located on the gate insulating layer 54. Wherein, the width of the gate trace 20b in the first direction (X) is greater than the width D1 of the gate 20 in the first direction (X) to ensure the conductivity of the gate trace 20b.

[0051] Please refer to Figure 3 and Figure 4 , Figure 3 which is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application. Figure 4 which is provided by some embodiments of the present application Figure 3 and is a schematic top view structure diagram of the display panel in

[0052] The difference between this embodiment and the above embodiment is that in the display panel 200, the positive projections of the first transition layer 131 and the first ohmic contact layer 121 on the gate auxiliary structure 40 are both located within the gate auxiliary structure 40. That is to say, the gate auxiliary structure 40 extends from the first transition layer 131 to the first ohmic contact layer 121, that is, it covers all the active layers 10 on the left side of the channel layer 11. Thus, a part of the gate layer 20a opposite to the gate 20 does not cover the active layer 10. Therefore, the overlapping area between the active layer 10 and the gate layer 20a is only the gate 20, which can reduce the coupling capacitance between the gate layer 20a and the active layer 10.

[0053] Among them, what is different from Figure 1 is also that the source electrode 31 penetrates through the gate auxiliary structure 40.

[0054] Please refer to Figure 5 , Figure 5 which is a schematic cross-sectional structure diagram of a display panel provided by some embodiments of the present application. For the convenience of understanding and brief description, the same structures in this embodiment and the above embodiment use the same reference numerals, and the same structures will not be described in detail, and only the differences from the above embodiment will be described.

[0055] In this embodiment, the gate auxiliary structure 40c in the display panel 300 is located on the gate 20, and the width D2 of the gate auxiliary structure 40c in the first direction (X) is equal to the width D1 of the gate 20 in the first direction (X). The active layer 10 includes a first ohmic contact layer 121, a second ohmic contact layer 122, a first transition layer 131, a second transition layer 132, and a channel layer 11. The second transition layer 132 is located between the second ohmic contact layer 122 and the channel layer 11.

[0056] In some embodiments, the gate auxiliary structure 40c and the gate 20 overlap vertically.

[0057] In some embodiments, the gate auxiliary structure 40c is also located above the second ohmic contact layer 122 and on both sidewalls of the gate trace 20b along the first direction (X).

[0058] The display panel provided by the embodiments of the present application includes an active layer 10 and a gate 20. The active layer 10 is arranged along the first direction (X) and includes a channel layer 11. The gate 20 corresponds to the upper side of the channel layer 11, and the width D1 of the gate 20 along the first direction (X) is equal to the length L of the channel layer 11 along the first direction (X). Among them, the width D1 of the gate 20 along the first direction (X) is less than 1 micron. Therefore, the length L of the channel layer 11 along the first direction (X) is also less than 1 micron. The present application can implement a gate 20 with an extremely small width, and then implement a channel layer 11 with an extremely small length, which can not only improve the mobility, reduce the area of the device, improve the aperture ratio of the panel, but also facilitate the development of products with high resolution and high refresh rate, and even realize the functions of some chips.

[0059] Please refer to Figure 6 , Figure 6 which is a schematic flowchart of the manufacturing method of the display panel provided by some embodiments of the present application. Please also refer to Figures 7a-7e , Figures 7a-7e which is a schematic structural diagram of the display panel during the manufacturing process provided by some embodiments of the present application. In this embodiment, taking the manufacturing of the above display panel 100 as an example, the manufacturing method of the display panel 100 will be described. Therefore, please combine Figure 1 and Figure 2 The manufacturing method of the display panel 100 includes the following steps S1 - S3.

[0060] Step S1: Form an initial active layer 10a arranged along the first direction (X).

[0061] In some embodiments, as Figure 7a shown, a light-shielding layer 52 can be first formed on the substrate 51, then a buffer layer 53 covering the light-shielding layer 52 is formed on the substrate 51, and then an active material layer arranged along the first direction (X) is formed on the buffer layer 53. Then, heavy ion doping is performed on both ends of the active material layer to form the initial active layer 10a, and the initial active layer 10a includes a first ohmic contact layer 121, a second ohmic contact layer 122, and an initial channel layer 11a located between the first ohmic contact layer 121 and the second ohmic contact layer 122.

[0062] Step S2: A gate auxiliary structure 40 is formed above the initial active layer 10a, and a gate 20 is formed above the initial active layer 10a based on the gate auxiliary structure 40. The gate 20 is disposed adjacent to the gate auxiliary structure 40.

[0063] Step S2 may specifically include the following steps: 1) As shown in Figure 7b , a gate insulating layer 54 is formed on the initial active layer 10a; 2) As shown in Figure 7b , the gate auxiliary structure 40 is formed on the gate insulating layer 54. The gate auxiliary structure 40 covers a part of the initial channel layer 11a along the first direction (X), for example, covering the first ohmic contact layer 121 and a part of the initial channel layer 11a connected to the first ohmic contact layer 121; 3) As shown in Figure 7c , a gate material layer 20' covering the gate auxiliary structure 40 is formed on the gate insulating layer 54, such as Mo or Mo / Al or Mo / Cu or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO or Ni / Cu / Ni or MoTiNi / Cu / MoTiNi or NiCr / Cu / NiCr or CuNb, etc. The thickness of the gate material layer 20' is less than 1 μm, for example, 0.05 - 0.5 μm; 4) As shown in Figure 7d , the gate material layer 20' is anisotropically etched (vertically etched) to form a gate 20 on the sidewalls of the gate auxiliary structure 40 along the first direction (X). The gate 20 corresponds to the upper part of the initial channel layer 11a.

[0064] Wherein, after the anisotropic etching, a gate layer 20a is formed around the sidewalls of the gate auxiliary structure 40, and the gate layer 20a corresponding to the upper part of the initial channel layer 11a serves as the gate 20. Based on the film formation characteristics, the width D1 of the gate 20 along the first direction (X) is equal to the thickness of the gate material layer 20'. Based on the characteristics of the etching process, the thickness of the gate 20 is equal to the thickness of the gate auxiliary structure 40. Before the anisotropic etching process, a photoresist 60 is formed in the area where the gate trace 20b needs to be formed to form the gate trace 20b after etching the gate material layer 20'.

[0065] Step S3: Using the gate 20 as a blocking layer, the initial active layer 10a is doped to form a channel layer 11 corresponding to the lower part of the gate 20 in the initial active layer 10a. The width D1 of the gate 20 along the first direction (X) is equal to the length L of the channel layer 11 along the first direction (X); wherein, the width D1 of the gate 20 along the first direction (X) is less than 1 μm.

[0066] Specifically, as shown in Figure 7d and Figure 7eAs shown, the initial active layer 10a is lightly doped with light ions to form a first transition layer 131 and a channel layer 11 in the initial channel layer 11a. The first transition layer 131 is covered by the gate assist structure 40, and the channel layer 11 corresponds to the area below the gate 20.

[0067] The P-type ion light doping process can be directly carried out. Since the blocking effect of the gate 20 is better and the blocking effect of the gate assist structure 40 is weaker, the doping ions can pass through the gate assist structure 40 to reach the underlying initial channel layer 11a to form the first transition layer 131. The undoped initial channel layer 11a serves as the channel layer 11. Therefore, the width D1 of the gate 20 along the first direction (X) is equal to the length L of the channel layer 11 along the first direction (X). Since the width D1 of the gate 20 along the first direction (X) is less than 1 micron, the length L of the channel layer 11 along the first direction (X) is also less than 1 micron.

[0068] Since one end of the initial channel layer 11a in contact with the second ohmic contact layer 122 is not covered by the gate assist structure 40, the doping ions on the left side of the gate 20 pass through one more layer of the gate assist structure 40 than those on the right side. To ensure that a lightly doped first transition layer 131 is formed in the part of the initial channel layer 11a connected to the first ohmic contact layer 121, a higher doping concentration will be formed in the part of the initial channel layer 11a connected to the second ohmic contact layer 122. That is, the part of the initial channel layer 11a connected to the second ohmic contact layer 122 and the second ohmic contact layer 122 together form a new second ohmic contact layer 122. Therefore, the second ohmic contact layer 122 can include a first concentration region 122a close to the channel layer 11 and a second concentration region 122b far from the channel layer 11, and the doping concentration of the first concentration region 122a is less than that of the second concentration region 122b. As Figure 7d shown, the first ohmic contact layer 121, the first transition layer 131, the channel layer 11, and the second ohmic contact layer 122 form the active layer 10.

[0069] As Figure 1 shown, the method for manufacturing the display panel 100 may further include forming a source electrode 31 and a drain electrode 32 respectively connected to the first ohmic contact layer 121 and the second ohmic contact layer 122. Specifically, first, a dielectric layer 55 covering the gate 20 and the gate assist structure 40 is formed on the gate insulating layer 54, and then the dielectric layer 55 and part of the gate insulating layer 54 are etched to form vias connected to the first ohmic contact layer 121 and the second ohmic contact layer 122. A conductive material is formed in the vias and on the surface of the dielectric layer 55, and the source electrode 31 and the drain electrode 32 are located on the dielectric layer 55.

[0070] Since there is no other material covering the first ohmic contact layer 121 and the second ohmic contact layer 122 (such as the gate assist structure 40), the etching depth of the dielectric layer 55 is the same when forming the vias for the source electrode 31 and the drain electrode 32.

[0071] Please refer to Figure 6 and Figures 8a-8g , Figures 8a-8g which is a schematic structural diagram of a display panel provided in some embodiments of the present application during the manufacturing process. In this embodiment, taking the manufacturing of the above display panel 300 as an example, the manufacturing method of the display panel 300 will be described. Therefore, please refer to Figure 5 .

[0072] Step S1: Form an initial active layer 10a disposed along the first direction (X).

[0073] The specific steps of step S1 in the above embodiment can be referred to.

[0074] Step S2: Form a gate assist structure 40c above the initial active layer 10a, and form a gate 20 above the initial active layer 10a based on the gate assist structure 40c, and the gate 20 is disposed adjacent to the gate assist structure 40c.

[0075] Step S2 may specifically include the following steps.

[0076] 1) As Figure 8a shown, form a gate insulating layer 54 on the initial active layer 10a.

[0077] 2) As Figure 8b shown, form a patterned gate layer 20c on the gate insulating layer 54, and the patterned gate layer 20c covers the initial channel layer 11a. Among them, the patterned gate layer 20c further includes a gate trace 20b that does not cover the initial channel layer 11a.

[0078] 3) As Figure 8c shown, form a first gate assist layer 40a on the gate insulating layer 54 and the patterned gate layer 20c, and the first gate assist layer 40a covers a part of the patterned gate layer 20c along the first direction (X). The material of the first gate assist layer 40a may be silicon nitride.

[0079] 4) As Figure 8d shown, form a second gate assist layer 40b covering the patterned gate layer 20c and the first gate assist layer 40a. The material of the second gate assist layer 40b may be silicon oxide.

[0080] 5) As Figure 8eAs shown, an anisotropic etching is performed on the second gate auxiliary layer 40b to form a gate auxiliary structure 40c located on the sidewalls of the first gate auxiliary layer 40a along the first direction (X) and on the patterned gate layer 20c. Wherein, the width D3 of the gate auxiliary structure 40c along the first direction (X) is equal to the thickness of the second gate auxiliary layer 40b, and the thickness of the second gate auxiliary layer 40b is less than 1 μm, for example, 0.05 - 0.5 μm. The gate auxiliary structure 40c is also formed on the sidewalls of the patterned gate layer 20c and the sidewalls of the gate trace 20b.

[0081] 6) As Figure 8f shown, based on the gate auxiliary structure 40c, the patterned gate layer 20c is etched to form a gate 20 corresponding to the upper part of the initial channel layer 11a. The width D1 of the gate 20 along the first direction (X) is equal to the width D3 of the gate auxiliary structure 40c along the first direction (X). Since the width D3 of the gate auxiliary structure 40c along the first direction (X) is less than 1 μm, the width D1 of the gate 20 along the first direction (X) is less than 1 μm. Before etching, a photoresist 60a is first covered on the gate trace 20b to ensure that the gate trace 20b is not etched.

[0082] Step S3: Using the gate 20 as a barrier layer, the initial active layer 10a is doped to form a channel layer 11 corresponding to the lower part of the gate 20 in the initial active layer 10a. The width D1 of the gate 20 along the first direction (X) is equal to the length L of the channel layer 11 along the first direction (X); wherein, the width D1 of the gate 20 along the first direction (X) is less than 1 μm.

[0083] Specifically, as Figure 8g shown, a light ion doping is performed on the initial active layer 10a to form a first transition layer 131, a second transition layer 132 and a channel layer 11 in the initial channel layer 11a. The channel layer 11 corresponds to the lower part of the gate 20, and the first transition layer 131 and the second transition layer 132 are located on both sides of the channel layer 11 along the first direction (X).

[0084] A P-type ion light doping process can be directly performed. Due to the good blocking effect of the gate 20, the doping ions cannot penetrate through the gate 20 to reach the lower initial channel layer 11a. Therefore, the undoped initial channel layer 11a serves as the channel layer 11. Thus, the width D1 of the gate 20 along the first direction (X) is equal to the length L of the channel layer 11 along the first direction (X). Since the width D1 of the gate 20 along the first direction (X) is less than 1 μm, the length L of the channel layer 11 along the first direction (X) is also less than 1 μm.

[0085] The manufacturing method of the display panel provided by the embodiment of the present application forms a gate 20 with an extremely small width by using a gate assist structure, and then forms a channel layer 11 with an extremely small length based on the gate 20. The width D1 of the gate 20 is determined by the thickness of the film layer, thus getting rid of the limitation of the accuracy of the exposure machine. The gate trace 20b in other routing areas can still maintain the normal width D1, and its conductivity is not affected.

[0086] The embodiment of the present application further provides a display device, which at least includes the display panel provided by any one of the above embodiments. The display device has the same beneficial effects as the above display panel, which will not be elaborated here.

[0087] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The display panel at least includes: a substrate; an active layer, disposed on the substrate and arranged along a first direction and including a channel layer; a gate, corresponding to the upper side of the channel layer, and the width of the gate along the first direction is equal to the length of the channel layer along the first direction; a gate auxiliary structure, which is disposed adjacent to the gate; wherein, the width of the gate along the first direction is less than 1 micron.

2. The display panel according to claim 1, wherein The active layer further includes: a first ohmic contact layer and a second ohmic contact layer, the first ohmic contact layer and the second ohmic contact layer are respectively located at two ends of the active layer, and the channel layer is located between the first ohmic contact layer and the second ohmic contact layer; a first transition layer, which is located between the first ohmic contact layer and the channel layer.

3. The display panel according to claim 2, wherein The gate auxiliary structure is located on the sidewall of the gate along the first direction, and the orthographic projection of the first transition layer on the gate auxiliary structure is located within the gate auxiliary structure.

4. The display panel according to claim 2, wherein The gate auxiliary structure is located on the sidewall of the gate along the first direction, and the orthographic projection of the first ohmic contact layer on the gate auxiliary structure is located within the gate auxiliary structure.

5. The display panel according to claim 4, characterized in that, The display panel further includes a source electrode and a drain electrode, the source electrode and the drain electrode are respectively connected to the first ohmic contact layer and the second ohmic contact layer, and the source electrode penetrates through the gate auxiliary structure.

6. The display panel according to claim 2, characterized in that, The active layer further includes a second transition layer, which is located between the second ohmic contact layer and the channel layer.

7. The display panel according to claim 1, wherein The gate auxiliary structure is located on the gate, and the width of the gate auxiliary structure along the first direction is equal to the width of the gate along the first direction.

8. The display panel according to claim 7, wherein The gate auxiliary structure is further located above the second ohmic contact layer and on the two sidewalls of the gate trace along the first direction.

9. The display panel according to claim 2, wherein The first ohmic contact layer and the second ohmic contact layer are doped with an N-type semiconductor material, and the first transition layer is doped with a P-type semiconductor material; the doping concentrations of the first ohmic contact layer and the second ohmic contact layer are greater than the doping concentration of the first transition layer.

10. The display panel according to claim 2, characterized in that, The second ohmic contact layer includes a first concentration region close to the channel layer and a second concentration region far from the channel layer, and the doping concentration of the first concentration region is less than the doping concentration of the second concentration region.

Images