Semiconductor device and power conversion device

Abstract

To improve the performance of a semiconductor device. As a solution, a semiconductor device is formed, having: a semiconductor substrate having a drift layer of a first conductivity type, a body region of a second conductivity type, and a JFET region of the first conductivity type contacting the body region on both sides on the drift layer; a plurality of trenches formed on the upper surface of the semiconductor substrate and extending in a first direction; and a gate electrode formed in the trenches and on the upper surface of the semiconductor substrate with an insulating film. In a unit cell, a first trench group consisting of a plurality of trenches arranged in a second direction intersecting the first direction and a second trench group consisting of a plurality of trenches arranged in the second direction are arranged in the first direction, the lower surface of the source region between the trenches adjacent in the second direction has a channel region shallower than the trenches, the gate electrode has a first portion in the plurality of trenches and a second portion on the semiconductor substrate connecting the first portions arranged in the first direction and the second direction to each other, and each unit cell has a plurality of JFET regions.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a field-effect transistor having a channel formed on the side of a semiconductor layer. Background Technology

[0002] In recent years, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been proposed, which has trenches formed in a direction orthogonal to the source contact region, which is formed in a stripe pattern when viewed from above. The gate electrode is buried within these trenches, separated by an insulating film. In this MOSFET, current flows along the depth direction through the sides of the trenches. In this construction, the on-resistance can be reduced by increasing the trench density through decreasing the trench spacing.

[0003] For example, Patent Document 1 (Japanese Patent Application Publication No. 2004-207289) describes a MOSFET that has a buried gate formed in a trench on the upper surface of a semiconductor substrate and a channel formed on the side of the trench.

[0004] In addition, Patent Document 2 (Japanese Patent Application Publication No. 2021-12934) discloses a vertical MOSFET having a gate electrode that spans directly above each of two adjacent trenches in the trench extension direction.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2004-207289

[0008] Patent Document 2: Japanese Patent Application Publication No. 2021-12934 Summary of the Invention

[0009] The problem that the invention aims to solve

[0010] The MOSFET described in Patent Document 1 has multiple trenches, resulting in a large gate capacitance. Furthermore, the gate wiring extends across the trenches, leading to a large gate wiring resistance. Therefore, there is a problem of a large gate delay determined by CR (capacitance × resistance). Additionally, the length of the long side of the trench is determined by the design of the JFET region, making it difficult to lengthen the trench and thus widen the gate wiring.

[0011] In Patent Document 2, two trenches are included in the unit cell in the extension direction of the trench. On the other hand, there is only one JFET region in the unit cell, which has the problem of high on-resistance.

[0012] Other issues and new features will become clear from the description and accompanying drawings in this specification.

[0013] Solution for solving the problem

[0014] A brief summary of representative embodiments disclosed in this application is provided below.

[0015] One embodiment of a semiconductor device includes: a semiconductor substrate having a drift layer of a first conductivity type; a plurality of trenches formed on an upper surface of the semiconductor substrate and extending in a first direction along the upper surface of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, formed on the sidewalls of the trenches in the short-side direction; a source region of the first conductivity type formed on the upper surface of the semiconductor substrate and within the body region; a JFET region of the first conductivity type formed on the upper surface of the drift layer, with its sidewalls contacting the body region; a drain region of the first conductivity type formed on a lower surface of the semiconductor substrate and electrically connected to the drift layer; and a gate electrode formed in the trenches and on the upper surface of the semiconductor substrate through an insulating film, wherein a portion of the plurality of trenches is located within a unit cell. In a top view, a plurality of trenches are arranged in a second direction intersecting the first direction to form a first trench group. Another portion of the plurality of trenches is arranged in the second direction to form a second trench group. The trenches forming the first trench group and the trenches forming the second trench group are arranged in the first direction. A source region is also formed between adjacent trenches in the second direction. The lower surface of the source region formed between adjacent trenches in the second direction has a channel region formed at a depth shallower than the depth of the trenches. The gate electrode includes: a first portion which is buried in the plurality of trenches; and a second portion which is located on the upper surface of the semiconductor substrate. The first portions arranged in the first direction are connected to each other, and the first portions arranged in the second direction are connected to each other. Each unit cell has a plurality of JFET regions.

[0016] Invention Effects

[0017] The effects obtained through representative embodiments of the invention disclosed in this application are briefly described below.

[0018] According to the present invention, the performance of semiconductor devices can be improved. Attached Figure Description

[0019] Figure 1 This is a bird's-eye view showing the semiconductor device of Embodiment 1.

[0020] Figure 2 This is a cross-sectional view showing the semiconductor device of Embodiment 1.

[0021] Figure 3This is a cross-sectional view showing the semiconductor device of Embodiment 1.

[0022] Figure 4 This is a cross-sectional view showing the semiconductor device of Embodiment 1.

[0023] Figure 5 This is a cross-sectional view of a semiconductor device showing a variation of Embodiment 1.

[0024] Figure 6 This is a bird's-eye view showing the semiconductor device of Embodiment 2.

[0025] Figure 7 This is a cross-sectional view showing the semiconductor device of Embodiment 2.

[0026] Figure 8 This is a cross-sectional view showing the semiconductor device of Embodiment 2.

[0027] Figure 9 This is a cross-sectional view showing the semiconductor device of Embodiment 3.

[0028] Figure 10 This is a cross-sectional view showing the semiconductor device of Embodiment 3.

[0029] Figure 11 This is a circuit diagram showing the power conversion device in Embodiment 4.

[0030] Figure 12 This is a bird's-eye view showing the semiconductor device of Comparative Example 1.

[0031] Figure 13 This is a cross-sectional view showing the semiconductor device of Comparative Example 2. Detailed Implementation

[0032] Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings. Furthermore, in all the drawings used to describe the embodiments, components with the same function are labeled with the same reference numerals, and repeated descriptions are omitted. Additionally, in the following embodiments, descriptions of the same or identical parts are generally not repeated unless specifically required. Furthermore, in the drawings describing the embodiments, section lines are sometimes indicated in top views or perspective views, etc., for ease of understanding of the structure. And, in the drawings describing the embodiments, section lines are sometimes omitted in sectional views for ease of understanding of the structure.

[0033] in addition," - "as well as" + "" is a symbol indicating the relative concentration of impurities for conductivity types n-type or p-type. For example, the impurity concentration of n-type impurities is indicated by "n". - “n”, “n” + The order of "" becomes higher.

[0034] Details of areas for improvement

[0035] The following uses Figure 12 Provide details on the scope for improvement. Figure 12 This is a bird's-eye view showing the semiconductor device of Comparative Example 1. Figure 12 The diagrams of the gate insulating film, interlayer insulating film, silicide layer, and source electrode in the epitaxial layer structure are omitted. Additionally, in Figure 12 The diagram of the drain electrode beneath the SiC substrate is omitted.

[0036] Figure 12 The trench-type SiC power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) of Comparative Example 1 is shown. Hereinafter, this device will sometimes be referred to simply as a MOSFET.

[0037] like Figure 12 As shown, in Comparative Example 1, in n composed of SiC (silicon carbide) + On the upper surface of the SiC substrate, a layer with an impurity concentration ratio of n is formed. + The SiC substrate has an n-type epitaxial layer (semiconductor layer) composed of low-density SiC. The SiC substrate functions as the drain region 1, and the epitaxial layer functions as the drift layer 2. The SiC substrate and the epitaxial layer constitute a SiC epitaxial substrate. The thickness of the epitaxial layer is, for example, about 5 to 50 μm.

[0038] A p-type main region (well region) 3 is formed within the epitaxial layer at a predetermined depth, starting from the upper surface of the epitaxial layer (the upper surface of the SiC epitaxial substrate). The main region 3 is formed by extending n... + The source region 5 of the type is electrically connected to the source electrode (not shown). Source region 5 is in... Figure 12 The source contact region, indicated by the dashed line, is connected to the source electrode. Multiple source contact regions extend in the Y direction and are arranged in the X direction. That is, the source contact regions are formed in a stripe pattern. The X and Y directions are perpendicular to each other, running along the upper surface (main surface) of the SiC epitaxial substrate.

[0039] A JFET region 4 is formed within the epitaxial layer. The body region 3, JFET region 4, and source region 5 all extend in the Y direction. Multiple trenches 7 are formed along the Y direction on the upper surface of the epitaxial layer directly above the JFET region 4. Each trench 7 extends in the X direction to the midpoint of the body region 3. A source region 5 is formed from the upper surface of a plate-like epitaxial layer (fin) between adjacent trenches 7 in the Y direction, extending to the midpoint of the trenches. Within this plate-like epitaxial layer, below the source region 5, are formed the body regions 3 arranged in the X direction, p-type channel regions 6 between these body regions 3, and the JFET region 4 below the channel regions 6.

[0040] A gate electrode 16 is buried within the trench 7, separated by a gate insulating film (not shown). The MOSFET is composed of at least a channel region 6 including a channel forming region, a source region 5, a drain region 1 (SiC substrate), and a gate electrode 16 within the trench 7. Multiple gate electrodes 16 (trench gate electrodes) are arranged in the Y direction within the trench 7, and the portions of these gate electrodes 16 that are interconnected with each other above the trench 7 function as gate wiring.

[0041] When the gate electrode 16 is in the ON state, electrons flowing in the MOSFET from n + The source region 5 is formed by a channel in the p-type channel region 6 on the side of the trench 7 adjacent to the gate electrode. Electrons flowing in the Z-direction move sequentially to the n-type JFET region 4, the n-type drift layer 2, the drain region 1, and the drain electrode (not shown) at the bottom of the SiC substrate. Thus, current flows between the source and drain. The Z-direction is the thickness direction of the SiC epitaxial substrate. The X, Y, and Z directions are orthogonal to each other.

[0042] As with the MOSFET in Comparative Example 1, in a MOSFET where a channel is formed on the side of a SiC epitaxial substrate, the gate capacitance (gate-source capacitance) is large due to the formation of multiple trenches 7. Furthermore, the gate wiring extends across multiple trenches 7, resulting in a large gate wiring resistance. Therefore, in a MOSFET with trenches 7, the gate delay time, determined by CR (capacitance × resistance), is larger than that of a planar MOSFET without trenches. Conversely, if the side (long side) of the trench 7 in the extension direction (X direction) is lengthened to increase the gate wiring width, it is thought that the gate wiring resistance can be reduced. However, the long side of the trench 7 is determined by the design of the JFET region 4, making it difficult to lengthen the trench 7 and thus widen the gate wiring width.

[0043] Thus, in a semiconductor device having a MOSET with channels formed on the side of a SiC epitaxial substrate, as a first improvement, there is a situation where the gate delay time is large due to the large gate wiring resistance.

[0044] In contrast, such as Figure 13 As shown, consider forming gate electrodes 17 directly above each other on two trenches 7 arranged in the extension direction of the trench 7. Figure 13 This is a cross-sectional view showing the semiconductor device of Comparative Example 2.

[0045] The semiconductor device in Comparative Example 2 has a SiC epitaxial substrate. The SiC epitaxial substrate is made of n + The structure consists of a SiC substrate and an n-type epitaxial layer formed on the SiC substrate. The epitaxial layer is mainly composed of a drift layer 2, and the SiC substrate forms the drain region 1. Within the epitaxial layer, the drift layer 2, the main regions 3 and 3a, the source region 5, the current diffusion region 18, the protection region 13, the drain region 1, and the JFET region 4 are formed.

[0046] The lower surface of the drain region 1 is covered by the drain electrode 15. A source region 5 is formed on the upper surface of the epitaxial layer, and a main region 3, which is a p-type semiconductor region, is formed between the source region 5 and the drift layer 2 and in contact with the lower surface of the source region 5.

[0047] Below the main region 3, a surface is formed in contact with the lower surface of the main region 3, which serves as n. + A current diffusion region 18 is formed within the drift layer 2. Additionally, a JFET region 4 is formed directly below the region adjacent to the current diffusion region 18 in the X direction and in contact with the source electrode 19 extending in the Y direction. Here, the JFET region 4 is formed in the epitaxial layer below the main body region 3, extending from the lower surface of the main body region 3 to the upper surface of the drift layer 2. Furthermore, a p-type main body region 3a is formed in the region adjacent to the current diffusion region 18 in the X direction, sandwiched between the trench 7 and the main body region 3a, opposite to the JFET region 4. The upper surface of the main body region 3a is in contact with the main body region 3. The p-type impurity concentrations of both main body regions 3 and 3a are the same. The current diffusion region 18 is a low-resistance region used to diffuse the current flowing through the JFET region 4 within the drift layer 2 in the X direction and to allow the current to flow over a wider area.

[0048] Below the current diffusion region 18 and the main body region 3a respectively, a surface as p is formed in contact with the lower surface of the current diffusion region 18 and the main body region 3a respectively. +The protective region 13 is a type of semiconductor region. Additionally, a trench 7 is formed from the upper surface of the epitaxial layer, i.e., the upper surface of the source region 5, extending to a midway depth throughout the protective region 13. The trench 7 penetrates the main body region 3 but does not reach the lower surface (lower end) of the protective region 13. The trench 7 is surrounded by the protective region 13 when viewed from above.

[0049] Three of the four sides of the rectangular trench 7 are in contact with the current diffusion region 18. The remaining side of the trench 7, excluding the three sides mentioned above, is in contact with the main body region 3a at the same height as the current diffusion region 18. A JFET region 4 is formed in the region adjacent to the protection region 13 in the X direction and directly below the location where the source electrode 19 is connected to the source region 5. The main body regions 3 and 3a, and the protection region 13 are electrically connected to each other.

[0050] Multiple trenches 7 are arranged in the Y direction, and a gate electrode 17 is embedded in each trench 7 with an insulating film 20 between them. The gate electrodes 17 in each trench 7 are formed on the source region 5 with the insulating film 20 between them and are interconnected by the gate electrodes 17 extending in the Y direction. The lower surface, side surface, and upper surface of the gate electrode 17 extending in the Y direction on the source region 5 are covered by the insulating film 20. That is, the insulating film 20 includes a gate insulating film formed below the gate electrode 17 extending in the Y direction and an interlayer insulating film formed on top of the gate insulating film.

[0051] An active electrode 19 is formed in the connection hole of the through insulating film 20 on the semiconductor substrate and on the insulating film 20. The source electrode 19 completely embedded in the connection hole and the source electrode 19 on the insulating film 20 are integrated with each other.

[0052] Within the drift layer 2 below the current diffusion region 18, as an n-type or n - The JFET (Junction Field Effect Transistor) region 4, an n-type semiconductor region, is formed parallel to the guard region 13 in the X direction. The JFET region 4 is an n-type semiconductor region whose sides are in contact with the p-type semiconductor region, and it serves to connect the drift layer 2 to the channel region 6. Specifically, the JFET region 4 is adjacent to the guard region 13 directly below the current diffusion region 18, and a portion of the JFET region 4 is adjacent to the current diffusion region 18 in the X direction. The JFET region 4 extends in the Y direction. Figure 13 In the diagram, the lower end of JFET region 4 is shown by a dashed line.

[0053] The n-type impurity concentration in JFET region 4 is equal to or higher than that in drift layer 2. Furthermore, the n-type impurity concentration in JFET region 4 is lower than that in current diffusion region 18 and source region 5. JFET region 4 is the region between adjacent guard regions 13 in the X direction. That is, JFET region 4 is the region where, when the MOSFET is off, depletion layers extend from opposite sides of adjacent guard regions 13, and these depletion layers are in contact with each other.

[0054] Next, the operation of the MOSFET in Comparative Example 2 will be explained. The MOSFET has at least a drain region 1, a source region 5, a body region 3, and a gate electrode 17. When the MOSFET is in the ON state, a channel is formed in the body region 3 adjacent to the trench 7 and in the body region 3a. That is, the portion of the current diffusion region 18 in the channel is generated in the body region 3, and the portion adjacent to the current diffusion region 18 is generated in the body region 3a. In other words, the channel is generated in the p-type semiconductor region adjacent to the trench 7. In Comparative Example 2, all four sides of the trench 7 are in contact with the body region 3, so a channel is formed on all four sides. At this time, the current flows from the drain electrode 15 sequentially through the drain region 1, the drift layer 2, the JFET region 4, the current diffusion region 18, the channel (body regions 3 and 3a), and the source region 5 to the source electrode 19.

[0055] exist Figure 13 In the diagram, the area of ​​a unit cell (unit cell) of a MOSFET is shown using a double-dotted line.

[0056] A MOSFET unit cell (hereinafter, sometimes simply referred to as a unit cell) refers to one of the repeatedly formed structures when multiple MOSFETs of the same semiconductor device are arranged in a specific configuration. In this application, a MOSFET unit cell refers to one of multiple structures repeatedly arranged without reversal along the extension direction (X direction) of the trench 7. That is, Figure 13 The portion shown, enclosed by double-dotted lines, has a structure formed by arranging two configurations that are symmetrical about the center axis in the X direction. However, in this application, the configuration that is repeatedly arranged while being reversed is not referred to as a unit cell; therefore, these two configurations are not unit cells. Alternatively, in a top view, the two source contact regions that sandwich the gate electrode and are separated in the X direction can also be considered as unit cells between each other.

[0057] In Comparative Example 2, a unit cell has two trenches 7 arranged in the X direction, a gate electrode 17 spanning these trenches 7, a guard region 13, and a JFET region 4. Furthermore, in Figure 13As shown in the area enclosed by the double-dotted lines, there appear to be two JFET regions 4 on the left and right sides, but these JFET regions 4 are combined with the JFET regions 4 at the ends of the adjacent unit cell to form a single JFET region 4. Therefore, there is only one JFET region 4 formed per unit cell.

[0058] In Comparative Example 2, by forming a gate electrode 17 that spans between two trenches 7 in the extending direction (long side direction) of the trench 7, the gate wiring resistance can be reduced. However, in Comparative Example 2, two trenches 7 are arranged in a unit cell, while only one JFET region 4 is formed. Therefore, there is room for a second improvement, such as low JFET density and high on-resistance.

[0059] Therefore, in the embodiments of this application, the shortcomings of the first and second improvements described above are addressed. The technical concept of the embodiments implementing this improvement will be explained below.

[0060] (Implementation Method 1)

[0061] The following description uses a MOSFET (SiC power MOSFET) with a trench-shaped side surface forming the upper part of the epitaxial layer as the channel region, and illustrates the semiconductor device with accompanying drawings. Furthermore, while an example using silicon carbide (SiC) as the semiconductor substrate has been given, the example is not limited to this and can also be applied to other semiconductor substrates such as silicon (Si).

[0062] <Structure of Semiconductor Devices>

[0063] use Figures 1-4 The structure of the MOSFET, which is a semiconductor device according to this embodiment, will be described. Figure 1 This is a bird's-eye view showing the semiconductor device of this embodiment. Figure 2 It is a cross-sectional view along the extension direction (long side direction, length direction) of the trench of the semiconductor device, and a cross-sectional view of the part adjacent to the trench (excluding the part of the trench) in the short side direction of the trench. Figure 3 It is a cross-sectional view along the extension direction of the groove, and it is a cross-sectional view including the groove. Figure 4 This is a cross-sectional view showing a structure in which multiple trenches are arranged along the short side direction (short side direction). Figure 1 The diagrams of the gate insulating film, silicide layer, interlayer insulating film, source electrode, and drain electrode are omitted. Figure 1 The image shows a perspective view of the portion hidden by the gate electrode; the hidden ridgeline within the ridgeline of the gate electrode is not shown. Figure 1 , Figure 2 as well as Figure 3The image shows a unit cell of a MOSFET. However, the length of the unit cell in the Y direction can be greater than... Figure 1 Length can also be compared Figure 1 Short. Figure 2 In the diagram, the outline of the trench, which is not visible due to its location deep within the cross-section shown, is indicated by a dashed line.

[0064] The XYZ coordinate axes used in this description are defined with the directions shown in the figure. In this application, the Z direction (Z-axis direction) is perpendicular to the upper surface of the SiC substrate, and the X direction (X-axis direction) and Y direction (Y-axis direction) are along the upper surface of the SiC substrate and the upper surface of the SiC epitaxial substrate, respectively. The X and Y directions are along the upper surface (main surface) of the SiC epitaxial substrate, and the Z direction is the thickness direction (height direction, depth direction) of the SiC epitaxial substrate. The X, Y, and Z directions are mutually orthogonal. That is, the X and Y directions intersect each other when viewed from above.

[0065] The semiconductor device described here is, for example, a semiconductor chip with a rectangular planar shape. The structure of the component region at the center of the semiconductor chip will be described below. Although not shown, on the upper surface of the semiconductor chip, in the terminal region surrounding the component region, an FLR (Field Limiting Ring) or JTE (Junction Termination Extension) is formed as an end region.

[0066] like Figures 1-4 As shown, the semiconductor device of this embodiment has an n-type SiC (silicon carbide) epitaxial substrate. The SiC epitaxial substrate (semiconductor substrate) has an n-type SiC epitaxial substrate. + SiC substrate of type n and formed on n + An n-type epitaxial layer (semiconductor layer) is formed on a SiC substrate with a lower impurity concentration than the SiC substrate. The SiC substrate contains n-type epitaxial layers (semiconductor layers). + In the drain region of the n-type epitaxial layer, the n-type epitaxial layer functions as drift layer 2. The thickness of the epitaxial layer is, for example, about 10 μm. The impurity concentration of drift layer 2 is, for example, 1 × 10⁻⁶. 16 cm -3 .

[0067] like Figures 1-4 As shown, a main region (well region) 3, serving as a p-type semiconductor region, is formed within the drift layer 2 at a predetermined depth, starting from the upper surface of the drift layer 2 (the upper surface of the epitaxial layer). Within a single cell, the main region 3 extends in the Y direction and has three locations arranged in the X direction. A main region 3, serving as an n-type semiconductor region, is formed within the main region 3 at a predetermined depth, starting from the upper surface of the drift layer 2 (the upper surface of the main region 3). +The source region 5 is a semiconductor region. In addition, a trench 7 is formed from the upper surface of the drift layer 2 (the upper surface of the main body region 3) to a depth throughout the middle of the main body region 3.

[0068] Within a unit cell, when viewed from above, two source regions 5 extending along the Y direction are arranged along the X direction. Only a main body region 3 is formed between the two source regions 5. Within the unit cell, three main body regions 3 are arranged along the X direction. The two source regions 5 are respectively formed between the main body region 3 located at the center of the unit cell in the X direction and the main body region 3 located at the end of the unit cell in the X direction. In other words, the X-direction ends of the two source regions 5 contact different main body regions 3. When viewed from above, one of the two source regions 5 contacts a plurality of trenches 7 (first trench group) arranged in the Y direction, and the other source region 5 contacts another plurality of trenches 7 (second trench group) arranged in the Y direction. That is, within the unit cell, the plurality of trenches 7 (trench groups) arranged along the Y direction are arranged in two rows along the X direction.

[0069] Within a unit cell, trenches 7 are formed between the main body region 3 located at the center of the unit cell in the X direction and the main body region 3 located at the ends of the unit cell in the X direction. Source regions 5 are also formed between adjacent trenches 7 in the Y direction. Between adjacent trenches 7 in the Y direction, within the drift layer 2 directly below the source regions 5, p-type channel regions 6 are formed between adjacent main body regions 3 in the X direction. The p-type impurity concentration in channel regions 6 is lower than that in main body regions 3. Channel regions 6 are channel formation regions that form channels when the MOSFET operates. The lower end of channel regions 6 is located above the lower ends of both main body regions 3 and trenches 7.

[0070] In the Y-direction, adjacent trenches 7 are interspersed with each other, and an n-type JFET region 4 is formed within the drift layer 2 directly below the channel region 6. The n-type impurity concentration of the JFET region 4 is higher than the n-type impurity concentration of the drift layer 2 but lower than the n-type impurity concentration of the source region 5. The lower end of the JFET region 4 is lower than the lower end of the trench 7, for example, at the same height as the lower end of the main body region 3. The JFET region 4 extends in the Y-direction in a manner that overlaps with the plurality of trenches 7 when viewed from above. In the X-direction, the side surfaces of the JFET region 4 contact the main body region 3, which is a p-type semiconductor region. Figures 1-4 In the diagram, the lower end of JFET region 4 is shown by a dashed line. Thus, JFET region 4 is formed extending from the side of trench 7 to a region lower than trench 7. JFET region 4 is in contact with and electrically connected to drift layer 2.

[0071] That is, in the Y direction, adjacent trenches 7 are connected to each other, and on the side of trench 7, from the upper surface of the epitaxial layer downwards, a source region 5, a channel region 6, and a JFET region 4 are sequentially formed. The channel region 6 is in contact with the lower end of the source region 5, and the JFET region 4 is in contact with the lower end of the channel region 6. In addition, a drift layer 2 is formed below the JFET region 4 and the body region 3. In other words, the JFET region 4 is formed on the drift layer 2.

[0072] A gate electrode 9 is embedded within a trench 7, separated by a gate insulating film 8. The gate electrode 9 is, for example, made of a polysilicon film (conductive film). Gate electrodes 9, formed within each trench 7 and arranged along the Y direction, are formed on the trench 7 and the upper surface of the epitaxial layer, becoming integral with the gate electrodes 9 extending along the Y direction. That is, the gate electrode 9 comprises multiple trench gate electrodes formed within each trench 7 and gate wiring extending in the Y direction. In a cross-section along the Y direction, the gate electrode 9 has a comb-like structure (see reference). Figure 4 An insulating film 10 is located between the upper surface of the epitaxial layer and the gate electrode 9. Furthermore, the gate electrode 9 on the upper surface of the epitaxial layer is covered by the insulating film 10.

[0073] One of the key features of this embodiment is that the gate electrode 9, i.e., the gate wiring, on the upper surface of the epitaxial layer is formed directly above each of the two rows of trenches 7 arranged in the X direction within the unit cell, and extends in the Y direction. That is, the gate wiring is formed in the area directly above each of the trenches 7 arranged in the X direction within the unit cell. In other words, the gate wiring overlaps with each of the trenches 7 arranged in the X direction within the unit cell when viewed from above. Thus, since the gate electrode 9 is formed across each other across the trenches 7 arranged in the X direction within the unit cell, a wider gate wiring width can be ensured. Furthermore, within the unit cell, two rows of JFET regions 4 extending in the Y direction are formed directly below the gate electrode 9 (gate wiring) and arranged in the X direction.

[0074] That is, within a unit cell, two trench groups consisting of multiple trenches 7 arranged in the Y direction are arranged in the X direction, and a JFET region 4 extending in the Y direction is formed directly below each trench group. Adjacent trenches 7 in the Y direction have fins formed between them, which are arranged in multiple ways to form a fin group. In other words, within a unit cell, two fin groups consisting of multiple fins arranged in the Y direction are arranged in the X direction, and a JFET region 4 extending in the Y direction is formed directly below each fin group (each trench group).

[0075] Directly below the gate electrode 9 (gate wiring) formed between the two rows of trenches 7 (two trench groups) arranged in the X direction within the unit cell, no source region 5 is formed, and a main region 3 is formed on the upper surface of the epitaxial layer. That is, the region between the two rows of trenches 7 arranged in the X direction within the unit cell where no source region 5 is formed extends in the Y direction. In other words, the two source regions 5 formed within the unit cell are separated from each other between the two rows of trenches 7 arranged in the X direction.

[0076] A silicide layer 14 is formed in contact with the upper surface of the source region 5 exposed from the insulating film 10 and the gate electrode 9. The silicide layer 14 is, for example, made of NiSi (nickel silicide). The source region 5 formed on the upper surface of the epitaxial layer exposed from the insulating film 10 and the gate electrode 9, and the body region 3 adjacent to the source region 5, are electrically connected to the source electrode (not shown) via the silicide layer 14. The channel region 6 is electrically connected to the source electrode via the source region 5 and the silicide layer 14. The silicide layer 14 extends in the Y direction. The portion where the source region 5 is connected to the source electrode via the silicide layer 14 is the source contact region. That is, the source contact region extends in the Y direction and is arranged at both ends in the X direction within a unit cell. In other words, the source contact region is formed as a stripe when viewed from above.

[0077] Furthermore, in a location not shown, the gate electrode 9 is electrically connected to the gate electrode (gate pad) via a gate plug that penetrates the insulating film 10 on the gate electrode 9.

[0078] The lower surface (back side, bottom surface) of the SiC substrate is covered by a drain electrode 15 that is in contact with the lower surface of the SiC substrate. That is, the drain electrode 15 is electrically connected to the drain region 1.

[0079] The MOSFET (MOS field-effect transistor) of this embodiment is an n-channel MOSFET having a source region 5, a trench 7, a body region 3, a channel region 6, a drain region 1, and a gate electrode 9. Furthermore, the MOSFET has an n-type semiconductor region, i.e., a JFET region 4, electrically connected to the drain electrode 15, and a drift layer 2. In the p-type body region 3 and the p-type channel region 6, for example, Al (aluminum) is introduced as a p-type impurity. + 5. Source region of type n, 4. JFET region of type n, 2. Drift layer of type n, n + For example, N (nitrogen) is introduced into the drain region 1 of the n-type electrode as an n-type impurity.

[0080] like Figure 3As shown, a unit cell in this embodiment has two trenches 7 arranged in the X direction, a gate electrode 9 spanning between these trenches 7, and two JFET regions 4. Therefore, in this embodiment, each unit cell forms two JFET regions 4.

[0081] When the MOSFET is operating, electrons flowing through the MOSFET from n + The p-type source region 5 mainly flows through the p-type channel region 6 on the side of the trench 7, which is adjacent to the gate electrode 9. Then, electrons sequentially flow into the n-type JFET region 4, the n-type drift layer 2, and the n-type source region 5. + The drain region 1 and drain electrode 15 of the type move.

[0082] By forming a MOSFET with trench 7 as the channel forming region on the side and forming multiple trenches 7, the area of ​​the semiconductor device when viewed from above can be suppressed and a large gate width can be ensured, thus achieving a high-performance semiconductor device.

[0083] <Effects of this implementation method>

[0084] Next, the effects of the semiconductor device according to this embodiment will be explained.

[0085] The semiconductor device of this embodiment includes: a plurality of trenches 7, which, when viewed from above, have a long side in the X direction and a short side in the Y direction; a finned channel divided by the plurality of trenches 7; and a source contact region disposed at the end side of the trenches 7 in the long side direction, spanning the main body region 3 and the source region 5 and contacting the source electrode. Channel current flows longitudinally. Wherein, when a unit cell is defined between two source contact regions separated in the X direction, each unit cell has a first fin group arranged in the Y direction and a second fin group arranged in the Y direction but separated from the first fin groups in the X direction. Additionally, a gate electrode 9 is formed throughout the space between the first and second fin groups, has a gate wiring extending in the Y direction, and is embedded within the trenches 7. The embedded gate electrode 9 is connected to the gate wiring.

[0086] In other words, the semiconductor device of this embodiment includes: a semiconductor substrate having a drift layer (n-type) of a first conductivity type; a plurality of trenches formed on the upper surface of the semiconductor substrate and extending in a first direction (X direction) along the upper surface of the semiconductor substrate; and a main body region of a second conductivity type (p-type) different from the first conductivity type, formed on the side surface of the trench in the short side direction (Y direction). Furthermore, the semiconductor device of this embodiment includes: a source region of the first conductivity type formed on the upper surface of the semiconductor substrate, within the main body region; and a JFET region of the first conductivity type formed on the upper surface of the drift layer, with its side surfaces contacting the main body region. Additionally, the semiconductor device of this embodiment includes: a drain region of the first conductivity type formed on the lower surface of the semiconductor substrate and electrically connected to the drift layer; and a gate electrode formed in the trench and on the upper surface of the semiconductor substrate, separated by an insulating film. In this configuration, within a single cell, a portion of multiple trenches, when viewed from above, are arranged in a second direction intersecting the first direction to form a first trench group. Another portion of the multiple trenches is arranged in the second direction to form a second trench group. The trenches forming the first trench group and the trenches forming the second trench group are arranged in the first direction. Additionally, source regions are formed between adjacent trenches in the second direction. A channel region with a depth shallower than the trench depth is formed on the lower surface of the source regions formed between adjacent trenches in the second direction. Furthermore, the gate electrode includes: a first portion (trench gate electrode) which is embedded in the multiple trenches; and a second portion (gate wiring) located on the upper surface of the semiconductor substrate, where the first portions arranged in the first direction are connected to each other, and the first portions arranged in the second direction are also connected to each other. Moreover, each single cell includes multiple JFET regions.

[0087] Thus, the MOSFET in this embodiment and Figure 12 Unlike the MOSFET in Comparative Example 1, this MOSFET has a gate wiring (gate electrode 9) formed throughout the space between two adjacent trenches 7 along the long side of the trench 7. Therefore, the cross-sectional area of ​​the gate wiring can be increased, and the gate wiring resistance can be reduced. Furthermore, in the region between two adjacent trenches 7 along the long side of the trench 7, no source region 5 is formed directly below the gate wiring. In other words, within a single cell, the source region includes a source region of a first trench group and a source region of a second trench group, which are separated from each other directly below the portion of the second part of the gate electrode where the first parts of the gate electrodes arranged in the first direction are connected to each other. Therefore, even if the gate wiring width is increased as described above, the increase in gate capacitance can be prevented. Therefore, the gate delay time determined by CR (capacitance × resistance) can be shortened, thus improving the performance of the semiconductor device.

[0088] As described above, by forming gate wiring between adjacent trenches 7 along the long side direction of the trench 7, the MOSFET of this embodiment has a larger unit cell compared to Comparative Example 2. Therefore, in order to prevent a decrease in JFET density, two JFET regions 4 are formed per unit cell in this embodiment. In other words, the number of JFET regions 4 arranged in the X direction per unit cell is greater than the number of trenches arranged in the X direction per unit cell.

[0089] Thus, with Figure 13 Unlike the MOSFET in Comparative Example 2, this MOSFET prevents a decrease in JFET density by forming multiple JFET regions 4 in each unit cell, thereby preventing an increase in the on-resistance of the MOSFET. Therefore, the performance of the semiconductor device can be improved.

[0090] <Variation Example 1>

[0091] like Figure 5 As shown, a metal wiring 11 connected to the upper surface of the gate wiring can also be formed. That is, in this embodiment, a wide gate wiring is formed not only directly above a trench group consisting of a plurality of trenches 7 arranged in the Y direction, but also throughout the space between two trench groups. In other words, the gate wiring has sufficient width. Therefore, a metal wiring 11 extending in the Y direction can be connected to the upper surface of the gate wiring. The metal wiring 11 is covered by an insulating film 10. The metal wiring 11 is, for example, made of Al (aluminum).

[0092] In this configuration, a metal wiring 11 is formed directly above the main body region 3, which is not in contact with the source between adjacent trenches 7 in the X direction. By forming the metal wiring 11, the gate wiring resistance is further reduced, thereby shortening the gate delay time.

[0093] (Implementation Method 2)

[0094] The following uses Figures 6-8 The semiconductor device of this embodiment will be described.

[0095] Figure 6 This is a bird's-eye view showing the semiconductor device of this embodiment. Figure 7 It is a cross-sectional view along the extension direction of the groove, and it is a cross-sectional view including the groove. Figure 8 This is a cross-sectional view showing a structure with multiple trenches arranged along the short side of the trench. Figure 6 as well as Figure 7 The image shows the unit cell of a MOSFET. Figure 6 The image shows a portion hidden by the gate electrode in perspective, but the hidden ridgeline within the ridgeline of the gate electrode is not shown.

[0096] like Figures 6-8 As shown, unlike Embodiment 1 described above, the position of the upper surface of the gate electrode 12 (trench gate electrode) within the trench 7, except for one end in the X direction, is lower than the position of the upper surface of the epitaxial layer outside the trench 7 (the upper end of the trench 7). In other words, a portion of the height of the upper surface of the gate electrode 12 within the trench 7 is lower than the upper end of the trench 7. The gate electrodes 12 inside each of the two trenches 7 arranged in the X direction within a unit cell are connected to the upper gate wiring at the ends of the regions between the two trenches 7.

[0097] It is understood that if the trench spacing in the Y direction is reduced and the spacing between trenches 7 becomes narrower, the leading edges of the fins between trenches 7 become sharper, the electric field concentrates at these leading edges, and the gate breakdown voltage decreases. Therefore, by making the upper surface of the gate electrode 12 in the trench 7 lower than the upper end of the trench 7 (the upper end of the fin), the concentration of the electric field at the leading edge of the fin can be suppressed. Thus, the decrease in the gate breakdown voltage of the MOSFET can be suppressed. On the other hand, the gate electrode 12 in the trench 7 is connected to the gate wiring on the body region 3, which does not have source contact, so power can be supplied to the gate electrode 12 in each trench 7.

[0098] In this embodiment, the gate wiring width is smaller than that in Embodiment 1, so the effect of reducing the gate wiring resistance is smaller, but the effect of reducing the gate wiring resistance compared to Comparative Example 1 and reducing the on-resistance compared to Comparative Example 2 is still achieved.

[0099] (Implementation Method 3)

[0100] The following uses Figure 9 as well as Figure 10 The semiconductor device of this embodiment will be described. Figure 9 It is a cross-sectional view along the extension direction of the groove, and it is a cross-sectional view including the groove. Figure 10 It is a cross-sectional view showing a structure in which multiple grooves are arranged in the direction of the short side of the groove. Figure 9 The unit cell of a MOSFET is shown.

[0101] In Embodiment 1, a JFET region 4 is formed directly below the trench 7. In contrast, the MOSFET in this embodiment differs from that in Embodiment 1 in that the JFET region 4 is positioned directly below both the source contact region and the main body region 3, which does not have a source contact. Specifically, one JFET region 4 is formed directly below a first region between adjacent trenches 7 in the X direction, and another JFET region 4 is formed directly below a second region adjacent to the trench 7 in the X direction and opposite to the first region.

[0102] In this configuration, to electrically connect the channel region to the JFET region 4, an n-type semiconductor region, namely the current diffusion region 21, is formed beneath the main body region 3. The lower surface of the main body region 3 is located above the bottom surface of the trench 7. The current diffusion region 21 is formed directly below the main body region 3 within the drift layer 2 adjacent to the trench 7. The n-type impurity concentration in the current diffusion region 21 is higher than the n-type impurity concentration in both the drift layer 2 and the JFET region 4. In this embodiment, two JFET regions 4 are formed per unit cell.

[0103] Additionally, to protect trench 7 from the effects of a high electric field, p is formed below both trench 7 and current diffusion region 21. + The protective area 13 extends in the Y direction and contacts the bottom surface of each of the plurality of grooves 7 arranged in the Y direction. Figure 9 In this embodiment, the upper surface of the protection region 13 is at the same height as the bottom surface of the trench 7, but this upper surface can also be located above the bottom surface of the trench 7. The JFET region 4 in this embodiment is located directly below the source contact region and is an n-type semiconductor region between the protection regions 13 arranged in the X direction. Furthermore, in Figure 9 Within the unit cell shown, there appear to be three JFET regions 4 in the X direction, one in the center and one on the left and right. However, the left and right JFET regions 4 are combined with the JFET regions 4 at the ends of the adjacent unit cell to form a single JFET region 4. Therefore, in this embodiment, two JFET regions 4 are formed per unit cell.

[0104] In Embodiment 1, the length of the long side of the trench 7 is determined by the width of the JFET region 4, thus limiting design freedom. However, in this embodiment, the long side of the trench 7 can be lengthened regardless of the width of the JFET region 4. Therefore, channel density can be increased and on-resistance can be reduced. Furthermore, this embodiment achieves the same effects as Embodiment 1.

[0105] (Implementation Method 4)

[0106] The semiconductor device with SiC power MOSFET described in Embodiments 1 to 3 can be used in power conversion devices. Figure 11 The power conversion device of this embodiment will be described. Figure 11 This is a circuit diagram illustrating an example of the power conversion device (inverter) in this embodiment.

[0107] like Figure 11As shown, the inverter 102 includes switching elements, namely a SiC MOSFET 104 and a diode 105. The SiC MOSFET 104 is the SiC power MOSFET described in any of embodiments 1 to 3. In each single phase, the SiC MOSFET 104 and the diode 105 (upper arm) are connected in reverse parallel between the power supply voltage (Vcc) and the input potential of the load (e.g., a motor) 101. Additionally, the SiC MOSFET 104 and the diode 105 (lower arm) are also connected in reverse parallel between the input potential of the load 101 and the ground potential (GND).

[0108] That is, in the load 101, each single phase has two SiC MOSFETs 104 and two diodes 105, and the three phases have six SiC MOSFETs (switching elements) 104 and six diodes 105. Furthermore, a control circuit 103 is connected to the gate electrode of each SiC MOSFET 104, and the SiC MOSFET 104 is controlled by this control circuit 103. Therefore, by controlling the current flowing through the SiC MOSFETs 104 constituting the inverter 102 by the control circuit 103, the load 101 can be driven. The SiC MOSFETs 104 and diodes 105, which are connected in parallel in opposite directions, are, for example, different components and are not mixed within the same semiconductor chip.

[0109] The function of the SiCMOSFET 104 constituting the inverter 102 will be explained below. To control the drive load 101, such as a motor, a sinusoidal wave of a desired voltage needs to be input to the load 101. The control circuit 103 controls the SiCMOSFET 104 to perform pulse width modulation (PWM), which dynamically changes the pulse width of the rectangular wave. The output rectangular wave is smoothed by an inductor to become a simulated desired sine wave. The SiCMOSFET 104 has the function of generating the rectangular wave used for this PWM operation.

[0110] Thus, according to this embodiment, the SiCMOSFET 104 uses a semiconductor device with low on-resistance and short gate delay time as described in embodiments 1 to 3. Because of the high performance of the SiCMOSFET 104, high-performance power conversion devices such as inverters can be achieved.

[0111] In addition, the power conversion device can be used in three-phase motor systems. Figure 11 When the load 101 shown is a three-phase motor, the high performance of the three-phase motor system can be achieved by using a power conversion device equipped with a semiconductor device described in embodiments 1 to 3 in the inverter 102.

[0112] In addition, the same effects as those described in the previous embodiment can be obtained in this embodiment.

[0113] The invention made by the inventors has been specifically described above based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

[0114] For example, the materials, conductivity types, and manufacturing conditions of each component are not limited to those described in the aforementioned embodiments, and various modifications can certainly be made. Here, for ease of explanation, the conductivity types of the fixed semiconductor substrate and the semiconductor region have been described, but they are not limited to the conductivity types described in the aforementioned embodiments. That is, the MOSFET can also be a p-channel type.

[0115] Industrial availability

[0116] This invention can be widely used in semiconductor devices and power conversion devices having field-effect transistors with channels formed on the sides of the semiconductor layer.

[0117] Symbol Explanation

[0118] 1—Drain region, 2—Drift layer, 3—Main region, 4—JFET region, 5—Source region, 6—Channel region, 7—Trench, 8—Gate insulating film, 9, 12, 16, 17—Gate electrode, 13—Protective region.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate having a drift layer of a first conductivity type; Multiple trenches are formed on the upper surface of the semiconductor substrate and extend in a first direction along the upper surface of the semiconductor substrate; The main body region of the second conductivity type, which is different from the first conductivity type, is formed on the side of the trench in the short side direction; The source region of the first conductivity type is formed on the upper surface of the semiconductor substrate and within the main body region; The first conductivity type JFET region is formed on the upper surface of the drift layer, with its two sides in contact with the main body region. The drain region of the first conductivity type is formed on the lower surface of the semiconductor substrate and is electrically connected to the drift layer; as well as A gate electrode is formed, separated by an insulating film, within the trench and on the upper surface of the semiconductor substrate. Within a unit cell, a portion of the plurality of grooves, when viewed from above, are arranged in a second direction intersecting the first direction to form a first groove group; another portion of the plurality of grooves is arranged in the second direction to form a second groove group. The grooves constituting the first groove group and the grooves constituting the second groove group are arranged in the first direction. The source region is also formed between adjacent trenches in the second direction. The lower surface of the source region formed between adjacent trenches in the second direction has a channel region formed at a depth shallower than the depth of the trenches. The gate electrode includes: a first portion, which is respectively embedded in a plurality of the trenches; And a second portion, located on the upper surface of the semiconductor substrate, wherein the first portions arranged in the first direction are connected to each other, and the first portions arranged in the second direction are connected to each other. Each unit cell has multiple JFET regions.

2. The semiconductor device according to claim 1, characterized in that, One of the plurality of JFET regions extends along the second direction directly below the first trench group. Another JFET region among the plurality of JFET regions extends along the second direction directly below the second trench group.

3. The semiconductor device according to claim 1, characterized in that, One of the plurality of JFET regions is formed directly beneath a first region between adjacent trenches in the first direction. Another JFET region among the plurality of JFET regions is formed directly below a second region that is adjacent to the trench in the first direction and on the opposite side of the first region.

4. The semiconductor device according to claim 1, characterized in that, The upper surface of a portion of the first part of the gate electrode within the trench is lower than the upper end of the trench. Another portion of the first portion of the gate electrode within the trench is connected to the second portion of the gate electrode on the semiconductor substrate.

5. The semiconductor device according to claim 1, characterized in that, It also has metal wiring that is connected to the upper surface of the gate electrode on the semiconductor substrate and extends along the second direction.

6. The semiconductor device according to claim 1, characterized in that, The unit cell is one of a plurality of structures arranged repeatedly in the first direction without reversal.

7. The semiconductor device according to claim 1, characterized in that, Within the unit cell, the source region has source regions of the first trench group and source regions of the second trench group, the source regions of the first trench group and the source regions of the second trench group being separated from each other directly below the portion of the second portion of the gate electrode where the first portions of the gate electrode arranged in the first direction are connected to each other.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate is a semiconductor substrate containing silicon carbide.

9. A power conversion device, characterized in that, The semiconductor device of claim 1 was used.

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