An edge-band access method, a memory controller, a die, and a computer device

Abstract

An embodiment of the present application provides a sideband access method, a memory controller, a chiplet, and a computer device. The method is executed by the hardware logic of the memory controller and includes: obtaining sideband access information written by a memory physical layer interface, where the sideband access information is used for the memory physical layer interface to initiate sideband access to a memory module; generating a sideband access command corresponding to the sideband access information at least according to the command protocol of a communication host according to the sideband access information; where the communication host communicates with the memory module through a sideband path; and sending the sideband access command to the communication host to control the communication host to access the memory module. The embodiment of the present application can accelerate the processing of sideband access through hardware and improve the sideband access efficiency.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of chip technology, and in particular, to a sideband access method, a memory controller, a chiplet, and a computer device. Background Art

[0002] In a computer system, a chiplet can be docked with a memory module such as a DIMM (Dual Inline Memory Module) through a memory interface IP (Intellectual Property). The memory interface IP mainly consists of a memory controller and a memory physical layer (PHY) interface; among them, the memory physical layer interface, as a bridge between the memory controller and the memory module, can be used to transfer data between the memory controller and the memory module.

[0003] During the operation of a computer system, the computer system has a need to access the memory module through the memory physical layer interface. One way for the memory physical layer interface to access the memory module is to be implemented through a sideband path (Side Band), that is, to perform sideband access (abbreviated as sideband access) on the memory module. In this context, how to improve the efficiency of sideband access has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a sideband access method, a memory controller, a chiplet, and a computer device to improve the efficiency of sideband access.

[0005] To achieve the above object, embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, embodiments of the present application provide a sideband access method, which is executed by the hardware logic of a memory controller, and the method includes:

[0007] Obtain sideband access information written by the memory physical layer interface, where the sideband access information is used for the memory physical layer interface to initiate sideband access to the memory module;

[0008] According to the sideband access information, at least according to the command protocol of the communication host, generate a sideband access command corresponding to the sideband access information; wherein, the communication host communicates with the memory module through a sideband path;

[0009] Send the sideband access command to the communication host to control the communication host to access the memory module.

[0010] In a second aspect, an embodiment of the present application provides a memory controller, which is provided with a sideband communication processing module, and the sideband communication processing module is the hardware logic of the memory controller; the sideband communication processing module is configured to execute the sideband access method as described in the first aspect above.

[0011] In a third aspect, an embodiment of the present application provides a die, which includes a memory controller, a memory physical layer interface, and a communication host; the memory controller is the memory controller as described in the second aspect above.

[0012] In a fourth aspect, an embodiment of the present application provides a computer device, which includes the die as described in the third aspect above.

[0013] The sideband access provided by the embodiment of the present application can be implemented by the hardware logic in the memory controller. When the sideband access to the memory module is initiated by the memory physical layer interface, the hardware logic can obtain the sideband access information written by the memory physical layer interface; thus, the hardware logic can generate a sideband access command corresponding to the sideband access information according to the sideband access information written by the memory physical layer interface, at least in accordance with the command protocol of the communication host; furthermore, the sideband access command is sent to the communication host to control the communication host through the sideband access command, so that the communication host can access the memory module, realizing the sideband access from the memory physical layer interface to the memory module.

[0014] It can be seen that in the embodiment of the present application, after the sideband access is initiated by the memory physical layer interface, the processing of the sideband access is realized by the hardware logic in the memory controller and the communication host (the communication host is a hardware device for sideband communication), so the processing process of the sideband access is all realized by hardware and does not require the participation of system software; since the hardware processing speed is higher than that of the system software, the embodiment of the present application can reduce the processing time of the sideband access, enabling the processing of the sideband access to be accelerated by hardware and improving the sideband access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0016] Figure 1 It is a structural block diagram of a computer system.

[0017] Figure 2 It is another structural block diagram of a computer system.

[0018] Figure 3 Flow chart of the sideband access method.

[0019] Figure 4 Flow chart of generating sideband access commands.

[0020] Figure 5 Another flow chart of the sideband access method.

[0021] Figure 6 Example diagram of the state of the sideband communication processing module.

[0022] Figure 7 Block diagram of the sideband communication processing module.

[0023] Figure 8A Block diagram of the first register set.

[0024] Figure 8B Block diagram of the second register set.

[0025] Figure 9A Example diagram of the processing procedure of sideband write access.

[0026] Figure 9B Example diagram of the processing procedure of sideband read access.

[0027] Figure 10 Another block diagram of the computer system. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0029] Figure 1 An exemplary block diagram of the computer system is shown, such as Figure 1As shown in the figure, the computer system may include die 01 and memory module 02. Among them, die 01 may include devices such as memory controller 110, memory physical layer interface 120, processor core 130, communication host 140, etc. The memory controller 110 and the memory physical layer interface 120 may communicate through a physical layer interface protocol such as the DFI (DDR PHY Interface, DDR physical layer interface) protocol, and the memory controller 110 and the memory physical layer interface 120 form the memory interface IP of die 01, so that die 01 can be docked with the memory module 02 through the memory interface IP. The processor core 130 is, for example, a CPU (Central Processing Unit, central processing unit) core; the communication host 140 is, for example, a hardware device such as an I2C (Inter-Integrated Circuit, integrated circuit bus) / I3C (Improved Inter Integrated Circuit, improved integrated circuit bus) host that can be used for sideband communication. The processor core 130, the communication host 140 and the memory interface IP may communicate through the communication bus of the die.

[0030] In die 01, the memory physical layer interface 120 in the memory interface IP can serve as a bridge connecting the memory controller 110 and the memory module 02, and perform protocol conversion on the data transmitted between the memory controller 110 and the memory module 02 to ensure data transmission between die 01 and the memory module 02.

[0031] In one example, die 01 may form a chip system such as a SOC (System On Chip, system-on-chip), and the memory interface IP is, for example, a DDR (Double Data Rate, double data rate) IP; the memory controller 110 is, for example, a DDR Controller (controller) in the DDR IP, and the memory physical layer interface 120 is, for example, a DDR PHY interface (i.e., a DDR physical layer interface) in the DDR IP; the memory module 02 is, for example, a DIMM (Dual Inline Memory Module, dual in-line memory module). As the main memory device in the computer system, in order to adapt to different application scenarios, the DIMM can be divided into UDIMM (Unbuffered DIMM, unbuffered dual in-line memory module), RDIMM (Registered DIMM, registered dual in-line memory module), LRDIMM (Load Reduced DIMM, low-load dual in-line memory module), etc.

[0032] In the above example, the DDR PHY interface serves as a bridge connecting the DIMM and the DDR Controller. It can convert the data sent by the DDR Controller into data compliant with the DDR protocol and send it to the DDR chips in the DIMM for storage. Correspondingly, the DDR PHY interface can also convert the data sent by the DIMM into data compliant with the DFI protocol and send it to the DDR Controller, thus ensuring data transmission between the SOC and the DIMM.

[0033] Multiple devices are provided on the memory module. For the purposes of managing and configuring the devices provided on the memory module and querying the status of the memory module, etc., the computer system has a need to access the memory module through the memory physical layer interface. In one example, taking the memory module as a DIMM, devices such as DRAM (Dynamic Random Access Memory), RCD (Register Clock Driver, also known as register buffer), DB (Data Buffer), PMIC (Power Management IC), SPD (Serial Presence Detect) chip, and TS (Temperature Sensor) are provided on the DIMM. The working process of the computer system involves reading product information of the DIMM, performing register configuration on the devices provided on the DIMM, querying the status of the DIMM, etc. Therefore, during the working process, the computer system needs to access the DIMM through the DDR PHY interface.

[0034] Combined Figure 1 As shown, there are two ways for the memory physical layer interface 120 to access the memory module 02:

[0035] First, direct access. For example, the memory physical layer interface 120 accesses the memory module 02 through direct access methods such as the command and address bus (CA) signal, data bus (DQ) signal, and chip select (CS) signal between the memory physical layer interface 120 and the memory module 02. Among them, the command and address bus and the data bus of the memory module 02 can be regarded as the direct access path between the memory physical layer interface 120 and the memory module 02.

[0036] Second, sideband access. For example, the memory physical layer interface 120 accesses the memory module 02 through the sideband path between the communication host 140 and the memory module 02. Among them, the sideband path is based on protocols such as SMBus (System Management Bus), I2C, and I3C. The sideband path can be regarded as the access path between the communication host 140 (such as an I2C / I3C host, etc.) used for sideband communication in the computer system and the memory module 02, and does not belong to the direct access path between the memory physical layer interface and the memory module.

[0037] By means of sideband access, accessing the memory module may involve the following scenarios:

[0038] Before the memory training is completed, since the reliability of the command and address buses and chip select signals of the memory module cannot be guaranteed, the sideband access method needs to be used to access the memory module to manage the devices set on the DIMM.

[0039] After the memory training is completed, the sideband access method can be used to query the status information of the memory module. For example, the sideband access method can be used to query the temperature information of the temperature sensor set on the DIMM to monitor the DIMM temperature.

[0040] It should be noted that memory training refers to the process of delaying and adjusting signals such as DRAM signals, CS signals, CA signals, DQ signals, and DQS (data strobe) signals before the memory module performs normal data transmission, so as to compensate for the signal offset between DRAM interface signals (due to reasons such as different internal die and traces on the circuit board, there will be signal offset between DRAM interface signals). The purpose of memory training is to ensure the correct and efficient transmission of commands and data of the memory module. After the memory training is completed, signals such as CS signals and CA signals can already transmit data correctly, so the sideband access method can be used to access the memory module. That is to say, before the memory training is completed, the sideband access method can be used to access the memory module. Of course, the embodiments of the present application also support using the sideband access method to access the memory module after the memory training is completed. For example, after the memory training is completed, the sideband access method is used to query status information such as the temperature of the memory module.

[0041] It can be seen that during the operation of the computer system, the computer system has a need to access the memory module through the memory physical layer interface (such as reading and writing data from / to the memory module through the memory physical layer interface), and one of the ways for the memory physical layer interface to access the memory module is sideband access.

[0042] One implementation of sideband access is as follows: when initiating sideband access to a memory module at the memory physical layer interface, the system software is executed by the processor core to handle the sideband access and interact with the communication host to control the communication host to access the memory module. However, the time-consuming process of the system software handling sideband access results in low efficiency of sideband access.

[0043] Based on this, the embodiments of the present application provide a novel sideband access solution. By improving the hardware logic of the memory controller, when initiating sideband access to a memory module at the memory physical layer interface, the hardware logic of the memory controller is used to handle the sideband access and implement the interaction with communication hosts such as I2C / I3C hosts. As a result, the processing process of sideband access does not require software response and participation, but is handed over to hardware processing to be implemented, reducing the processing time-consuming of sideband access and thus improving the efficiency of sideband access.

[0044] Based on the above idea, the embodiments of the present application can set the hardware logic for interacting with the memory physical layer interface and the communication host in the memory controller, and the hardware logic in the memory controller executes the sideband access method provided by the embodiments of the present application. As an optional implementation, Figure 2 Exemplarily shows another structural block diagram of a computer system, in combination with Figure 1 and Figure 2 shown, in the Figure 2 shown computer system, a sideband communication processing module 200 is set in the memory controller 110. The sideband communication processing module 200 can be regarded as the hardware logic set in the memory controller for executing the sideband access method provided by the embodiments of the present application; and the sideband communication processing module 200 and the memory physical layer interface 120 are interconnected through a communication bus.

[0045] That is to say, a communication bus is set between the sideband communication processing module 200 and the memory physical layer interface 120. Thus, in addition to communicating with the memory physical layer interface 120 through physical layer interface protocols such as the DFI protocol, the memory controller 110 can also implement the communication between the sideband communication processing module 200 and the memory physical layer interface 120 through the added communication bus. In one example, the communication bus between the sideband communication processing module 200 and the memory physical layer interface 120 can be based on communication protocols such as APB (Advanced Peripheral Bus), AHB (Advanced High_performence Bus), AXI (Advanced eXtensible Interface), etc., and the embodiments of the present application are not limited thereto.

[0046] In an embodiment of the present application, the sideband communication processing module 200 needs to process the sideband access initiated by the memory physical layer interface and realize the interaction with the communication host 140 such as the I2C / I3C host. Therefore, the sideband communication processing module 200 can access the system management network of the computer system through a system management bus based on protocols such as AXI, thereby interacting with the communication host 140.

[0047] based on Figure 2 In the computer system shown, when the memory physical layer interface initiates a sideband access to the memory module, the sideband communication processing module in the memory controller can execute the sideband access method provided by the embodiment of the present application. Optionally, during the chip design phase, the embodiment of the present application can design a sideband communication processing module in the memory controller (for example, perform functional design and interface design of the sideband communication processing module in the memory controller, etc.) so that the sideband communication processing module has the ability to execute the sideband access method provided by the embodiment of the present application. As an optional implementation, Figure 3 An optional flow chart of a sideband access method is shown as an example. The method can be executed by the hardware logic of the memory controller (for example, the method is executed by the sideband communication processing module in the memory controller), referring to Figure 3 The method flow may include the following steps.

[0048] In step S310, sideband access information written by the memory physical layer interface is obtained, where the sideband access information is used by the memory physical layer interface to initiate sideband access to the memory module.

[0049] When the memory physical layer interface initiates a sideband access to the memory module, the memory physical layer interface can write the sideband access information in the sideband communication processing module. In an optional implementation, the sideband communication processing module can set a register address space accessible by the memory physical layer interface, so that when the memory physical layer interface initiates a sideband access, the sideband access information can be written in the register address space through the communication bus between the sideband communication processing module and the memory physical layer interface. For ease of explanation, the register address space set in the sideband communication processing module and accessible by the memory physical layer interface can be referred to as a first register set.

[0050] In an optional implementation, the sideband access information written by the memory physical layer interface to the sideband communication processing module may carry at least address information.

[0051] Optionally, the sideband access initiated by the memory physical layer interface to the memory module may be a sideband write access or a sideband read access; the sideband write access can be regarded as the sideband access for the write operation initiated by the memory physical layer interface to the memory module, used to write write data into the memory module; the sideband read access can be regarded as the sideband access for the read operation initiated by the memory physical layer interface to the memory module, used to read read data from the memory module. Correspondingly, when the memory physical layer interface initiates a sideband write access to the memory module, the sideband access information written by the memory physical layer interface may include the address information of the sideband write access and the write data. When the memory physical layer interface initiates a sideband read access to the memory module, the sideband access information written by the memory physical layer interface may include the address information of the sideband read access.

[0052] In step S311, according to the sideband access information, at least according to the command protocol of the communication host, generate a sideband access command corresponding to the sideband access information.

[0053] When the memory physical layer interface initiates a sideband access to the memory module, in the embodiment of the present application, the hardware logic in the memory controller (such as the sideband communication processing module) interacts with the communication host based on the sideband access information written by the memory physical layer interface, so as to control the communication host to access the memory module; therefore, the hardware logic in the memory controller (such as the sideband communication processing module) needs to generate a command to be sent to the communication host to control the communication host. To enable the communication host to access the memory module through the sideband path, the command generated by the sideband communication processing module may at least include a sideband access command for instructing the communication host to access the memory module.

[0054] In an alternative implementation, since the sideband access command needs to be sent to the communication host, the sideband access command needs to be generated according to the command protocol of the communication host. Based on this, as an alternative implementation, the sideband communication processing module may generate a sideband access command corresponding to the sideband access information at least according to the command protocol of the communication host based on the sideband access information written by the memory physical layer interface, so that the communication host can access the memory module based on the indication of the sideband access command.

[0055] In an alternative implementation, the sideband access command generated by the sideband communication processing module may at least carry access address information, and the access address information can be used for the communication host to perform address resolution when accessing the memory module. Optionally, the access address information may be generated based on the address information in the sideband access information written by the memory physical layer interface. In an alternative implementation, if the address information in the sideband access information can be directly used for address resolution when the communication host accesses the memory module, the address information in the sideband access information may be used as the access address information carried by the sideband access command.

[0056] Optionally, if the memory physical layer interface initiates a sideband write access, the sideband access command generated by the sideband communication processing module can be a sideband write access command, which is used to instruct the communication host to write write data into the memory module; correspondingly, the access address information in the sideband access command can include write access address information (that is, the sideband write access command carries write access address information). Further, the sideband write access command can also carry write data; the write access address information can be regarded as the write address of the write data in the memory module.

[0057] If the memory physical layer interface initiates a sideband read access, the sideband access command generated by the sideband communication processing module can be a sideband read access command, which is used to instruct the communication host to read read data from the memory module; correspondingly, the access address information in the sideband access command can include read access address information (that is, the sideband read access command carries read access address information), and the read access address information can be regarded as the read address for reading data from the memory module.

[0058] In step S312, the sideband access command is sent to the communication host to control the communication host to access the memory module.

[0059] The hardware logic in the memory controller (such as the sideband communication processing module) can send the sideband access command to the communication host through a system management bus based on protocols such as AXI; thus, the communication host can execute the sideband access command to access the memory module through the sideband path. In an alternative implementation, the communication host can access the memory module through the sideband path according to the indication of the access address information carried in the sideband access command.

[0060] In an alternative implementation, if the sideband access command is a sideband write access command, after obtaining the sideband write access command, the communication host can write the write data into the memory module through the sideband path according to the write access address information carried in the sideband write access command, so as to implement the memory physical layer interface writing data to the memory module.

[0061] If the sideband access command is a sideband read access command, after obtaining the sideband read access command, the communication host can read the read data from the memory module through the sideband path according to the read access address information carried in the sideband read access command. Further, the communication host can feedback the read data to the sideband communication processing module, so that the sideband communication processing can save the read data into the first register set that the memory physical layer interface can access, so that the memory physical layer interface can read the read data from the first register set, and implement the memory physical layer interface reading data from the memory module.

[0062] The sideband access provided by the embodiments of the present application can be implemented by the hardware logic in the memory controller. When the sideband access to the memory module is initiated at the memory physical layer interface, the hardware logic can obtain the sideband access information written by the memory physical layer interface. Thus, the hardware logic can generate a sideband access command corresponding to the sideband access information according to the sideband access information written by the memory physical layer interface, at least in accordance with the command protocol of the communication host. Furthermore, the sideband access command is sent to the communication host to control the communication host through the sideband access command, so that the communication host can access the memory module, realizing the sideband access from the memory physical layer interface to the memory module.

[0063] It can be seen that in the embodiments of the present application, after the sideband access is initiated by the memory physical layer interface, the processing of the sideband access is implemented by the hardware logic in the memory controller and the communication host (the communication host is a hardware device for sideband communication). Therefore, the processing process of the sideband access is all implemented by hardware and does not require the participation of system software. Since the hardware processing speed is higher than that of the system software, the embodiments of the present application can reduce the processing time of the sideband access, enabling the processing of the sideband access to be accelerated by hardware and improving the sideband access efficiency.

[0064] In an alternative implementation, performing sideband access to the memory module needs to follow the format information of the sideband access command. Based on this, in an alternative implementation, when generating the sideband access command sent to the communication host in the embodiments of the present application, in addition to following the command protocol of the communication host, the format information required by the sideband access command can be further combined. Optionally, Figure 4 An exemplary optional flowchart for generating the sideband access command is shown. Referring to Figure 4 , the method flow may include the following steps.

[0065] In step S410, determine the current protocol mode of the communication host.

[0066] The communication host may have multiple protocol modes, and the command protocols corresponding to different protocol modes of the communication host may be different. Therefore, when generating the sideband access command in the embodiments of the present application, it is necessary to determine the current protocol mode of the communication host so that the generated sideband access command is adapted to the command protocol corresponding to the current protocol mode. For example, the I2C / I3C host has an I2C mode and an I3C mode, and the command protocols corresponding to the I2C mode and the I3C mode of the I2C / I3C host are different. Therefore, when the I2C / I3C host is in the I2C mode, it is necessary to generate a command sent to the I2C / I3C host according to the command protocol corresponding to the I2C mode; when the I2C / I3C host is in the I3C mode, it is necessary to generate a command sent to the I2C / I3C host according to the command protocol corresponding to the I3C mode.

[0067] In an alternative implementation, the current protocol mode of the communication host may belong to a type of configuration information provided by the system software of the computer system. The system software may write the configuration information into the hardware logic of the memory controller (such as the sideband communication processing module) during system initialization. In an implementation example, the sideband communication processing module may set a second set of registers accessible by the system software, so that the system software can write the current protocol mode of the communication host into the second set of registers; furthermore, the sideband communication processing module may confirm the current protocol mode of the communication host from the second set of registers.

[0068] In step S411, according to the sideband access information, at least based on the current protocol mode of the communication host and the format information required by the sideband access command, a sideband access command corresponding to the sideband access information is generated.

[0069] When generating the sideband access command, the embodiments of the present application may generate the sideband access command at least based on the current protocol mode of the communication host and the format information required by the sideband access command, based on the sideband access information provided by the memory physical layer interface.

[0070] The sideband access command may carry at least access address information for the communication host to perform addressing when accessing the memory module. The access address information may be determined according to the address format requirements for sideband access to the memory module. In an alternative implementation, multiple memory modules (such as multiple DIMMs) may be provided in the computer system. Each memory module may be provided with different devices such as DRAM, RCD, DB, PMIC, SPD chips, TS, etc., and the devices of the memory module may have multiple channels, and different channels have independent registers; thus, when performing sideband access to the memory module, according to the address format requirements, the access address information in the sideband access command needs to be able to address the device to be accessed (the device to be accessed is located in the memory module to be accessed) and indicate the internal address of the device to be accessed (for example, the channel address, register address, etc. of the device to be accessed).

[0071] Based on this, when the memory physical layer interface initiates a sideband access, the sideband access information written by the memory physical layer interface can carry address information. As a result, when the sideband communication processing module generates a sideband access command, it can determine the access address information carried by the sideband access command based on the address information in the sideband access information. In an alternative implementation, the address information in the sideband access information may include: the memory module address of the memory module to be accessed (such as the DIMM address), the device address of the device to be accessed (such as the device addresses of devices such as RCD and PMIC on the DIMM, and the device to be accessed may be located in the memory module to be accessed), the register address (such as the register addresses of devices such as RCD and PMIC on the DIMM), and the channel address (for example, the channel address corresponding to the register of the device on the DIMM), etc. Among them, the register address and the channel address can be regarded as an example of the internal address of the device to be accessed, and the internal address may further include a page address, etc., which is not limited in the embodiments of the present application.

[0072] In an implementation example, when performing a sideband access to a memory module, it is necessary to generate a slave address and the internal address of the device to be accessed according to the address format requirements; thus, the access address information carried by the sideband access command may include the slave address and the internal address of the device to be accessed. Optionally, the slave address is used to address the device to be accessed (the device to be accessed is located in the memory module to be accessed), and can be determined based on the memory module address and the device address in the sideband access information provided by the memory physical layer interface; the internal address of the device to be accessed can be directly provided by the memory physical layer interface. For example, the internal addresses such as the register address and the channel address in the sideband access information provided by the memory physical layer interface are used as the internal address of the device to be accessed in the access address information.

[0073] In a further alternative implementation, the slave address may include a HID (Host identifier) and a LID (Local identification). For example, the slave address is formed by the HID and the LID; among them, the HID is used to address the memory module to be accessed and can be determined based on the memory module address in the sideband access information provided by the memory physical layer interface; the LID is used to address the device to be accessed and can be determined based on the device address of the device to be accessed (provided by the sideband access information written by the memory physical layer interface). For example, the device address in the sideband access information is used as the LID.

[0074] In an implementation example, the HID can be determined based on the HID configuration information of the memory module to be accessed and the memory module address; optionally, the memory module address of the memory module to be accessed can be provided by the sideband access information written by the memory physical layer interface, and the HID configuration information of the memory module to be accessed can be configured by the system software. For example, the HID configuration information of the memory module is used as a kind of configuration information of the system software, and the system software can write the HID configuration information of each memory module in the second register set of the sideband communication processing module, so that the sideband communication processing module can determine the HID configuration information of the memory module to be accessed from the second register set, and combine it with the memory module address of the memory module to be accessed provided by the memory physical layer interface to obtain the HID in the slave address.

[0075] Based on this, in an optional implementation, the embodiment of the present application can further combine the HID configuration information of the memory module to be accessed when generating the sideband access command. Optionally, the embodiment of the present application can generate a sideband access command corresponding to the sideband access information based on the sideband access information, the current protocol mode of the communication host, the HID configuration information of the memory module to be accessed, and the format information required by the sideband access command; wherein the HID configuration information of the memory module to be accessed is combined with the memory module address of the memory module to be accessed to obtain the HID in the slave address.

[0076] In a further optional implementation, according to the format information required by the sideband access command, the sideband access command needs to provide not only the access address information (such as the slave address and the internal address of the device to be accessed, etc.), but also the access byte information and other information (the access byte information is such as the number of bytes involved in the access data, such as the number of bytes involved in the write data, the number of bytes involved in the read data, etc.). Furthermore, if the sideband access command is a sideband write access command, the sideband write access command also needs to provide write data.

[0077] In an optional implementation, after obtaining control of the communication host, the sideband communication processing module can control the communication host to access the memory module by sending a sideband access command; and release the control of the communication host after the access data is transmitted. Figure 5 Another optional flow chart of the sideband access method is shown as an example. Figure 5 The method flow may include the following steps.

[0078] In step S510, sideband access information written by the memory physical layer interface is obtained, where the sideband access information is used by the memory physical layer interface to initiate sideband access to the memory module.

[0079] In step S511, the control right is requested from the communication host.

[0080] In an alternative implementation, the sideband communication processing module may generate a request command (the request command is used to request control of the communication host), and send the request command to the communication host to request control of the communication host. The request command may be generated according to the command protocol of the communication host (for example, the current protocol mode of the communication host).

[0081] In a further alternative implementation, the sideband communication processing module may request control of the communication host when it detects that sideband access is triggered. For example, when the sideband communication processing module detects the trigger information of the sideband access written by the memory physical layer interface, it is considered that the sideband access is triggered, and thus the sideband communication processing module requests control of the communication host. In an implementation example, after the sideband communication processing module writes the sideband access information, the memory physical layer interface may further write the trigger information of the sideband access to trigger the sideband access. That is to say, after obtaining the sideband access information written by the memory physical layer interface, the sideband communication processing module may further obtain the trigger information of the sideband access written by the memory physical layer interface, so as to request control of the communication host.

[0082] In an alternative implementation, the trigger information of the sideband access may be written by the memory physical layer interface into the first register set of the sideband communication processing module. Taking the sideband write access of the memory module initiated by the memory physical layer interface as an example, after the memory physical layer interface writes the sideband access information (such as the address information of the sideband write access and the write data) of the sideband write access into the first register set, it may write the trigger information of the sideband write access into the first register set to trigger the sideband write access, so that the sideband communication processing module may request control of the communication host. Taking the sideband read access of the memory module initiated by the memory physical layer interface as an example, after the memory physical layer interface writes the sideband access information (such as the address information of the sideband read access) of the sideband read access into the first register set, it may write the trigger information of the sideband read access into the first register set to trigger the sideband read access, so that the sideband communication processing module may request control of the communication host.

[0083] In an alternative alternative implementation, the sideband communication processing module may also consider that the sideband access is triggered when it at least detects the sideband access information written by the memory physical layer interface, rather than being limited to the need for the memory physical layer interface to further write the trigger information.

[0084] In an alternative implementation, the communication host may be shared by multiple memory channels. Among them, one memory channel has an independent memory controller, a memory physical layer interface, and a memory module. Thus, for the memory controller of any memory channel, before the sideband communication processing module in the memory controller requests control of the communication host, it can first determine whether the communication host is currently in an idle state. For example, before the sideband access is triggered and the control of the communication host needs to be requested, first determine whether the communication host is currently in an idle state.

[0085] If the communication host is in an idle state, it can request control of the communication host to utilize the communication host to access the memory module.

[0086] If the communication host is in a busy state, it is necessary to wait for the communication host to become idle and then request control of the communication host.

[0087] The communication host being in a busy state means that the sideband communication processing module of the memory controller of other memory channels is obtaining control of the communication host. To avoid conflicts at the communication host when the memory physical layer interfaces of multiple memory channels perform sideband access, the sideband channel module of the memory controller of any memory channel needs to wait for the communication host to be in an idle state before requesting to obtain control of the communication host.

[0088] It should be noted that in the case of multiple memory channels, the memory controller in each memory channel can be set with a sideband communication processing module, which is used to access the memory module of this memory channel by controlling the communication host when the memory physical layer interface of this memory channel initiates sideband access to the memory module of this memory channel, so as to implement sideband access to the memory module of this memory channel. That is to say, the memory controller of each memory channel can be set with a sideband communication processing module, and can implement sideband access from the memory physical layer interface of this memory channel to the memory module of this memory channel through the sideband access method provided by the embodiments of the present application.

[0089] In step S512, when obtaining control of the communication host, according to the sideband access information, at least in accordance with the command protocol of the communication host, generate a sideband access command corresponding to the sideband access information.

[0090] In an alternative implementation, the communication host can generate a response signal in response to the request command of the sideband communication processing module, so that the sideband communication processing module can confirm obtaining control of the communication host, thereby triggering the generation of a sideband access command. In one implementation instruction, the communication host can generate a response signal in a high level state (for example, a response signal with a value of 1), so that after the sideband communication processing module detects the high level state response signal of the communication host, it can be regarded as obtaining control of the communication host.

[0091] In step S513, a sideband access command is sent to the communication host to control the communication host to access the memory module.

[0092] In step S514, when the transfer of the accessed data is completed, the control right of the communication host is released.

[0093] After the sideband communication processing module sends the sideband access command to the communication host, the communication host can access the memory module through the sideband path according to the sideband access command. Thus, when the sideband communication processing module is waiting for the transfer of the access data corresponding to the sideband access command to be completed, the sideband communication processing module can release the control right of the communication host. Optionally, the sideband communication processing module can generate a release command (the release command is used to release the control right of the communication host) and send the release command to the communication host to release the control right of the communication host.

[0094] In an alternative implementation, the access data corresponding to the sideband access command is, for example, the write data corresponding to the sideband write access command and the read data corresponding to the sideband read access command.

[0095] If the sideband access command is a sideband write access command, after the communication host finishes writing the write data into the memory module, it is regarded that the transfer of the access data corresponding to the sideband write access command is completed, and thus the sideband communication processing module can release the control right of the communication host.

[0096] If the sideband access command is a sideband read access command, after the communication host reads the read data from the memory module and the sideband communication processing module saves the read data read by the communication host to the local storage space of the sideband communication processing module, it is regarded that the transfer of the access data corresponding to the sideband read access command is completed; thus, the sideband communication processing module can release the control right of the communication host. Optionally, a local storage space for saving the read data (such as a read data register for saving the read data) can be set in the first register set of the sideband communication processing module.

[0097] In an optional implementation, when the communication host finishes writing write data into the memory module or reading read data from the memory module, the communication host can use an interrupt signal in a high-level state to indicate to the sideband communication processing module that the access data has been completely transmitted on the communication host side. In an implementation example, the interrupt signal in the high-level state can be indicated by the high-level state of the access end status register of the communication host (for example, if the value of the access end status register is 1, it is regarded as the high-level state). Thus, the sideband communication processing module can confirm that the access data has been completely transmitted on the communication host side when detecting the high-level state of the access end status register of the communication host. The complete transmission of the access data on the communication host side can be, for example, that the communication host finishes writing write data into the memory module or finishes reading read data from the memory module; it can be determined at which node the communication host side completes the transmission of the access data depending on whether the sideband access command is for writing data or reading data.

[0098] As an optional alternative implementation, in addition to determining whether the access data has been completely transmitted on the communication host side through the access end status register of the communication host, the sideband communication processing module can also have other implementation methods. For example, an auto-clearing register can be added to the memory controller (the auto-clearing register can be set in the sideband communication processing module) to indicate the access end status of the communication host; when the access data has been completely transmitted on the communication host side (for example, the communication host finishes writing write data into the memory module or finishes reading read data from the memory module), the communication host can set the auto-clearing register added to the memory controller to 1; thus, the sideband communication processing module can detect whether the access data has been completely transmitted on the communication host side according to the write value of the communication host to the auto-clearing register; optionally, after one clock cycle, the value of the auto-clearing register will be automatically cleared.

[0099] Also, for example, a hardware signal can be added between the memory controller and the communication host to indicate that the access data has been completely transmitted on the communication host side; when the access data has been completely transmitted on the communication host side, the communication host can set the hardware signal to a high-level state or generate a corresponding signal pulse, so that the sideband communication processing module can detect whether the access data has been completely transmitted on the communication host side through the hardware signal in the high-level state or the signal pulse corresponding to the hardware signal.

[0100] It should be noted that for the sideband communication processing module, in the case of sideband write access, when the communication host finishes writing write data into the memory module, it can be regarded as the complete transmission of the access data. For the sideband communication processing module, in the case of sideband read access, when the communication host reads read data from the memory module, it does not mean that the access data has been completely transmitted (at this time, only the transmission of the read data on the communication host side is completed), and it is only when the sideband communication processing module saves the read data to the local storage space that it can be regarded as the sideband communication processing module completing the transmission of the access data.

[0101] In a further optional implementation, when the access data finishes transmission (for the sideband communication processing module), the sideband communication processing module may generate a sideband access completion flag to indicate to the memory physical layer interface that the sideband access execution is completed. In an optional implementation, the sideband communication processing module may generate a sideband access completion flag and record it in the first register set. Further, if the sideband access command is a sideband read access command, the memory physical layer interface may read the read data from the local storage space of the sideband communication processing module when detecting the sideband access completion flag.

[0102] It can be seen that in an optional implementation, the hardware logic of the memory controller (such as the sideband communication processing module) after the sideband access is triggered, realizes the sideband access method provided by the embodiments of the present application through different sideband access processing stages (such as requesting control of the communication host, generating and sending sideband access commands, waiting for access data to finish transmission, releasing control of the communication host, etc.). To facilitate the sideband communication processing to enter different sideband access processing stages, the embodiments of the present application may set multiple states for the sideband communication processing module; thus when the sideband access is triggered, the sideband communication processing module can respond to the sideband access being triggered and start to perform state jumps among multiple states to trigger entry into different sideband access processing stages, and further realize the processing of the sideband access method in different sideband access processing stages.

[0103] In an optional implementation, Figure 6 An exemplary state diagram of the sideband communication processing module is shown. As Figure 6 shown, the multiple states of the sideband communication processing module may include an idle state 61, a request host control right state 62, a transmission state 63, a wait transmission completion state 64, and a release host control right state 65.

[0104] The idle state 61 is the starting state of the sideband communication processing module. When the sideband access is triggered (for example, when detecting the trigger information of the sideband access written by the memory physical layer interface), it starts to jump from the idle state 61 to the request host control right state 62.

[0105] The request host control right state 62 is used to trigger a request for control of the communication host. For example, when entering the request host control right state 62, the sideband communication processing module generates a request command and sends it to the communication host. Further, if the communication host is shared by multiple memory channels, the request host control right state 62 may be entered when the communication host is in an idle state.

[0106] When obtaining the control right of the communication host (for example, when detecting the response signal of the high level state of the communication host), it jumps from the request host control right state 62 to the transmission state 63.

[0107] The transmission status 63 is at least used to trigger the generation of a sideband access command and send it to the communication host.

[0108] In an alternative implementation, in combination with Figure 6 As shown, when the sideband access command is a sideband write access command, the transmission status 63 may include a write transmission status 631. The write transmission status 631 is at least used to trigger the generation of a sideband write access command and send it to the communication host; so that the communication host writes the write data into the memory module according to the write access address information carried by the sideband write access command.

[0109] In an alternative implementation, if the sideband access command is a sideband read access command, then in the transmission status 63, the sideband communication processing module needs to transmit the sideband read access command to the communication host, and when the communication host reads the read data from the memory module, save the read data to the local storage space of the sideband communication processing module. In combination with Figure 6 As shown, when the sideband access command is a sideband read access command, the transmission status 63 may include a read transmission status 632 and a read data save status 633.

[0110] The read transmission status 632 is at least used to trigger the generation of a sideband read access command and send it to the communication host; so that the communication host reads the read data from the memory module according to the read access address information carried by the sideband read access command;

[0111] The read data save status 633 is at least used to trigger saving the read data read by the communication host to the local storage space of the sideband communication processing module; optionally, after entering the read transmission status 632, if it is detected that the communication host has read all the read data from the memory module (for example, detecting the high level status of the access end status register of the communication host), then the read transmission status 632 jumps to the read data save status 633.

[0112] Optionally, the next state of the transmission status 63 is the wait for transmission completion status 64. For the sideband communication processing module, when the access data is completely transmitted, it jumps from the wait for transmission completion status 64 to the release host control status 65.

[0113] In an alternative implementation, the wait for transmission completion status 64 is a state between the transmission status 63 and the release host control status 64. For the sideband communication processing module, the wait for transmission completion status 64 can be regarded as the waiting stage from the start of triggering the transmission of the access data to the completion of the transmission.

[0114] If the sideband access command is a sideband write access command, for the sideband communication processing module, when the communication host finishes writing the write data into the memory module, it can be regarded as the completion of the transmission of the accessed data. Therefore, when the sideband communication processing module sends the sideband write access command to the communication host, it is regarded as the start of the trigger for the transmission of the accessed data (i.e., under the trigger of the sideband write access command, the communication host starts to write the write data into the memory module); thus, when the sideband write access command is sent to the communication host, the sideband communication processing module can jump from the write transmission state to the waiting for transmission completion state; furthermore, when it is detected that the communication host has finished writing the write data into the memory module, it can jump from the waiting for transmission completion state to the releasing host control right state.

[0115] If the sideband access command is a sideband read access command, for the sideband communication processing module, the sideband communication processing module needs to save the read data locally before it is regarded as the completion of the transmission of the accessed data by the sideband communication processing module. Therefore, when the sideband communication processing module starts to save the read data to the local transmission space, it can be regarded as the start of the trigger for the transmission of the accessed data; thus, when the sideband communication processing module starts to save the read data to the local storage space, the sideband communication processing module can jump from the read data saving state to the waiting for transmission completion state; furthermore, when the read data is completely saved to the local storage space of the sideband communication processing module, it jumps from the waiting for transmission completion state to the releasing host control right state.

[0116] The releasing host control right state 65 is used to trigger the release of the control right of the communication host. For example, when entering the releasing host control right state 65, the sideband communication processing module generates a release command and sends it to the communication host. Further, after releasing the control right of the communication host (such as after sending a release command to the communication host), it can jump back to the idle state 61 from the releasing host control right state 65.

[0117] It can be seen that in an alternative implementation, if the sideband access command is a sideband write access command, it can jump sequentially among the idle state, the requesting host control right state, the write transmission state, the waiting for transmission completion state, and the releasing host control right state, and the releasing host control right state jumps back to the idle state. If the sideband access command is a sideband read access command, it can jump sequentially among the idle state, the requesting host control right state, the read transmission state, the read data saving state, the waiting for transmission completion state, and the releasing host control right state, and the releasing host control right state jumps back to the idle state.

[0118] In a further alternative implementation, the waiting for transmission completion state is between the transmission state and the releasing host control right state and can be regarded as an optional state. In the embodiments of the present application, the waiting for transmission completion state may not be set either. For example, after entering the transmission state, when waiting for the accessed data to complete the transmission, it directly jumps to the releasing host control right state.

[0119] In an embodiment of the present application, when the memory physical layer interface initiates sideband access to the memory module, the processing of the sideband access is implemented by the hardware logic in the memory controller and the communication host hardware, and does not require the participation of system software. It can be accelerated by hardware to reduce the processing time of the sideband access and improve the efficiency of the sideband access.

[0120] As an optional implementation example, the optional hardware architecture of the sideband communication processing module is introduced below. It should be noted that based on the functions of the sideband communication processing module described above, the architecture design of the sideband communication processing module to implement the functions can be diverse, depending on the design of the designer, and the embodiment of the present application is not limited. The hardware architecture of the sideband communication processing module described below is only shown as an optional method. Optional, Figure 7 An optional block diagram of a sideband communication processing module is shown in an exemplary manner, in combination with Figure 2 and Figure 7 As shown, the sideband communication processing module may include: a first register set 710 , a command sequence module 720 , and a command sending module 730 .

[0121] The first register set 710 is at least used to store the sideband access information written by the memory physical layer interface.

[0122] The command sequence module 720 is at least used to generate a command sent to the communication host. Based on the need to generate a sideband access command by the sideband communication processing module, the command generated by the command sequence module 720 and sent to the communication host may include a sideband access command corresponding to the sideband access information. As an optional implementation, when generating the sideband access command, the command sequence module 720 may be used to generate the sideband access command according to the sideband access information, at least according to the command protocol of the communication host.

[0123] The command sending module 730 is used to send the command generated by the command sequence module 720 to the communication host.

[0124] As an alternative implementation, the first register set 710 can be a register address space formed by multiple registers. On the one hand, the first register set is a register address space set in the sideband communication processing module that can be accessed by the memory physical layer interface. The memory physical layer interface can access the first register set through the communication bus to write sideband access information in the first register set. Further, after writing the sideband access information in the first register set, the memory physical layer interface can also write the trigger information for sideband access in the first register set to trigger sideband access. In one example, the memory physical layer interface can access the first register set through a communication bus based on protocols such as APB, AHB, AXI, etc. to write sideband access information and trigger information in the first register set. On the other hand, the sideband communication processing module can write the sideband access completion flag in the first register set when the data access is completed.

[0125] As an alternative implementation, the first register set can save different information through different registers. Figure 8A An exemplary optional block diagram of the first register set is shown, as Figure 8A shown, the first register set can include an address register 810, a data register 820, a trigger register 830, and an access completion flag register 840.

[0126] Among them, the address register 810 can be used to save the address information of the sideband access information written by the memory physical layer interface. For example, the address information of the sideband access information corresponding to the sideband write access; or for another example, the address information of the sideband access information corresponding to the sideband read access.

[0127] As an alternative implementation, the address information can include the memory module address of the memory module to be accessed, the device address of the device to be accessed, and the internal address of the device to be accessed; the internal address such as register address, channel address, etc. As an alternative implementation, as shown in Figure 8A shown, the address register 810 can include a memory module address register 811, a device address register 812, a register address register 813, and a channel address register 814. When the memory physical layer interface initiates sideband access, it can write the corresponding address information in the memory module address register 811, the device address register 812, the register address register 813, and the channel address register 814 respectively.

[0128] Optionally, the memory module address register 811 can be used to store the memory module address written by the memory physical layer interface to indicate the memory module to be accessed. The device address register 812 can be used to store the device address written by the memory physical layer interface to indicate the device to be accessed. The register address register 813 can be used to store the register address written by the memory physical layer interface to indicate the register of the device to be accessed. The channel address register 814 can be used to store the channel address written by the memory physical layer interface to indicate the channel address corresponding to the register of the device to be accessed. It should be noted that the register address register and the channel address register are optional forms of the internal address register, and the internal address register can be used to store the internal address of the device to be accessed; based on the possible forms of the internal address, the specific registers set in the internal address register can be adjusted accordingly, and the embodiments of the present application do not limit this.

[0129] The data register 820 can be used to store the access data. Optionally, the access data is, for example, the write data corresponding to the sideband write access, or the read data corresponding to the sideband read access. As an optional implementation, in combination with Figure 8A as shown, the data register 820 can include a write data register 821 and a read data register 822. Among them, the write data register 821 is used to store the write data, and when the memory physical layer interface initiates a sideband write access, it can write the write data into the write data register. The read data register 822 is used to store the read data, and the read data register can be the local storage space in the sideband communication processing module for storing the read data.

[0130] The trigger register 830 can be used to store the trigger information of the sideband access written by the memory physical layer interface. Optionally, in combination with Figure 8A as shown, based on the sideband access being divided into sideband write access and sideband read access, the trigger register 830 can include a write trigger register 831 and a read trigger register 832.

[0131] Among them, the write trigger register 831 is used to store the trigger information of the sideband write access; optionally, after the memory physical layer interface writes the sideband access information (address information and write data) corresponding to the sideband write access, it can write the trigger information of the sideband write access into the write trigger register to trigger the sideband communication processing module to start the subsequent sideband write access processing. The read trigger register 832 is used to store the trigger information of the sideband read access; optionally, after the memory physical layer interface writes the sideband access information (address information) corresponding to the sideband read access, the memory physical layer interface can write the trigger information of the sideband read access into the read trigger register to trigger the sideband communication processing module to start the subsequent sideband read access processing.

[0132] In an alternative implementation, the trigger information may be a first value (e.g., 1), so that the memory physical layer interface can write the first value in the trigger register 830 to trigger a sideband access. Further, the trigger information written in the trigger register 830 may be automatically cleared after one clock cycle. For example, the first value written in the trigger register 830 may be automatically cleared after one clock cycle. Of course, the embodiments of the present application also support the memory physical layer interface writing a zero value (e.g., 0) in the trigger register 830 to clear the trigger information. The above method of writing trigger information by the first value and clearing the trigger information by the zero value is applicable to both sideband write access and sideband read access cases.

[0133] It should be noted that in the embodiments of the present application, the trigger register may be an optional device of the sideband communication processing module. That is to say, it is not necessarily required that the memory physical layer interface writes trigger information in the trigger register to trigger sideband access, and other triggering methods may also be available. In an alternative implementation, the sideband communication processing module may consider that the sideband access is triggered when at least new address information is detected in the address register.

[0134] The access completion flag register 840 can be used to save the sideband access completion flag to indicate to the memory physical layer interface that the sideband access has been completed. Optionally, the memory physical layer interface can periodically read whether there is a sideband access completion flag in the access completion flag register 840 to confirm whether the sideband access has been completed. Optionally, the sideband access completion flag may be a first value (e.g., 1). For example, when the sideband communication processing module has completed the data transmission, it can write the first value in the access completion flag register 840, so that the memory physical layer interface can periodically read whether the first value is written in the access completion flag register 840 to confirm whether the sideband access has been completed. In the case of sideband read access, if the memory physical layer interface confirms that the sideband read access has been completed through the access completion flag register, it can read the read data from the read data register.

[0135] In a further alternative implementation, returning to Figure 7 As shown, the sideband communication processing module may further include a second register set 740; the second register set 740 can be used to save the configuration information provided by the system software. Optionally, the configuration information may include the current protocol mode of the communication host. Thus, when generating a sideband access command, the command sequence module can be used to generate a sideband access command according to the sideband access information saved in the first register set, at least in accordance with the current protocol mode of the communication host indicated by the second register set and the format information required by the sideband access command.

[0136] In an alternative implementation, the second register set 740 can save different configuration information by setting different registers. Optionally,Figure 8B An exemplary optional block diagram of the second register set is shown, such as Figure 8B shown, the second register set may at least include a protocol configuration register 851, and the protocol configuration register 851 may store the current protocol mode of the communication host. Thus, when generating a sideband access command, the command sequence module may be used to generate a sideband access command corresponding to the sideband access information according to the sideband access information, at least in accordance with the current protocol mode of the communication host indicated by the protocol configuration register 851 and the format information required by the sideband access command.

[0137] In a further optional implementation, in combination with Figure 8B shown, the second register set may further include a HID configuration register 852, and the HID configuration register 852 may store the HID configuration information of each memory module. In one implementation example, there may be multiple HID configuration registers, and one HID configuration register stores the HID configuration information of one memory module. Thus, when generating a sideband access command, the command sequence module may be used to generate a sideband access command according to the sideband access information, in accordance with the current protocol mode of the communication host indicated by the protocol configuration register 851, the HID configuration information of the memory module to be accessed indicated by the HID configuration register 852, and the format information required by the sideband access command.

[0138] Optionally, the format information required by the sideband access command may be preset in the corresponding register. For example, a format register may be preset in the second register set to store the format information required by the sideband access command.

[0139] As an optional implementation, when generating a sideband access command according to the format information required by the sideband access command, the access address information in the sideband access command includes a slave address and the internal address of the device to be accessed; wherein, the slave address includes HID and LID; the HID may be determined according to the HID configuration information of the memory module to be accessed indicated by the HID configuration register 852 and the memory module address written in the memory module address register 811.

[0140] In a further optional implementation, returning to Figure 7 shown, the sideband communication processing module may further include a sideband communication processing state machine 750 and a host state parsing module 760.

[0141] As an optional implementation, the sideband communication processing state machine 750 may be used for state jumps of the sideband communication processing module. For example, the sideband communication processing state machine 750 may be used to start state jumps among multiple states in response to the triggering of sideband access, so as to trigger entry into different sideband access processing stages.

[0142] The host status parsing module 760 can be used to parse the information of communication hosts such as I2C / I3C hosts, and trigger the sideband communication processing state machine 750 to perform a partial state jump by feeding back the information of the communication host to the sideband communication processing state machine 750.

[0143] Combined with Figure 6 Taking the state example of the sideband communication processing module shown, in an optional implementation, when the sideband communication processing state machine detects that the trigger register has the trigger information for sideband access written in it (such as being written with 1), it can jump the state from the idle state to the state of requesting host control. For example, in the case of sideband write access, when 1 is written in the write trigger register, the state jumps from the idle state to the state of requesting host control. Another example, in the case of sideband read access, when 1 is written in the read trigger register, the state jumps from the idle state to the state of requesting host control. In an optional implementation, the host status parsing module can detect whether the communication host is in the idle state, so that when the communication host is in the idle state, based on the trigger information of sideband access, it can trigger the sideband communication processing state machine to jump to the state of requesting host control.

[0144] The state of requesting host control can trigger the command sequence module to generate a request command, so that the command sending module can send the request command to the communication host to request control of the communication host.

[0145] When the host status parsing module detects a high-level response signal (such as a response signal with a value of 1) from the communication host, it can trigger the sideband communication processing state machine to jump the state from the state of requesting host control to the transmission state.

[0146] The transmission state can be at least used to trigger the command sequence module to generate a sideband access command, so that the command sending module can send the sideband access command to the communication host to control the communication host to access the memory module.

[0147] It should be noted that in an optional implementation, if the sideband access command is a sideband write access command, the transmission state is the write transmission state; the write transmission state is at least used to trigger the command sequence module to generate a sideband write access command, so that the command sending module can send the sideband write access command to the communication host to control the communication host to write the write data into the memory module through the sideband path according to the write access address information.

[0148] In an alternative implementation, if the sideband access command is a sideband read access command, the transfer state may include a read transfer state and a read data save state; the read transfer state is at least used to trigger the command sequence module to generate a sideband read access command, so that the command sending module sends the sideband read access command to the communication host, to control the communication host to read read data from the memory module through the sideband path according to the read access address information; the read data save state is at least used to trigger the sideband communication processing module to save the read data read by the communication host to the read data register.

[0149] Wherein, when the communication host has completely read the read data from the memory module, the access end status register of the communication host may be set to a high level state (for example, writing a first value in the access end status register), so that the host status parsing module can detect the high level state of the access end status register of the communication host, and then trigger the sideband communication processing state machine to jump the read transfer state to the read data save state.

[0150] The next state of the transfer state is the wait for transfer completion state (optional state). In the case of sideband write access, when the sideband write access command is sent to the communication host, the sideband communication processing state machine jumps to the wait for transfer completion state; and when the host status parsing module detects the high level state of the access end status register of the communication host, it can confirm that the communication host has completed writing the write data to the memory module, so that the host status parsing module can trigger the sideband communication processing state machine to jump from the wait for transfer completion state to the release host control state.

[0151] In the case of sideband read access, when entering the read data save state and starting to save the read data to the read data register, the sideband communication processing state machine jumps from the read data save state to the wait for transfer completion state; further, when the read data is completely saved to the read data register, the sideband communication processing state machine jumps from the wait for transfer completion state to the release host control state.

[0152] It can be seen that when the data access is completed for transmission, the sideband communication processing state machine jumps from the wait for transfer completion state to the release host control state. The release host control state is used to trigger the command sequence module to generate a release command, so that the command sending module can send the release command to the communication host to release the control right of the communication host. After releasing the control right of the communication host, the sideband communication processing state machine jumps back to the idle state from the release host control state.

[0153] In an implementation example, taking the sideband write access initiated by the DDR PHY interface to the DIMM as an example, Figure 9A an exemplary process diagram of the sideband write access is shown, as Figure 9A shown, and the process may include the following steps.

[0154] In step S910, the DDR PHY interface writes the DIMM address, device address, register address, channel address, and write data of the sideband write access into the corresponding registers in the first register set respectively.

[0155] Among them, the DIMM address can be written into the DIMM address register (an example of a memory module address register) to indicate the DIMM corresponding to the sideband write access, so as to identify the DIMM to be accessed among multiple DIMMs; the device address can be written into the device address register to indicate the device on the DIMM corresponding to the sideband write access. There are various different devices set on the sideband bus of the DIMM, and the device on the DIMM to be accessed needs to be identified through the device address; the register address can be written into the register address register for register addressing within the device; the channel address can be written into the channel address register to indicate the channel of the register within the device (some devices are divided into multiple channels, and different channels have independent registers. For example, some registers inside the RCD need to distinguish between channel zero and channel one). At the same time, the DDR PHY interface writes the write data into the write data register.

[0156] In step S911, the DDR PHY interface writes 1 into the write trigger register in the first register set to trigger the sideband write access.

[0157] After the DDR PHY interface finishes writing the address information and write data of the sideband write access, the sideband access information corresponding to the sideband write access can be regarded as written successfully. Thus, the DDR PHY interface can write 1 into the write trigger register in the first register set to trigger the sideband write access; the write trigger register can be implemented in a self-clearing manner. For example, the DDR PHY interface writes 1 into the write trigger register to trigger a sideband write access, and after one clock cycle, the value in the write trigger register is automatically cleared; of course, the DDR PHY interface can also write 0 into the write trigger register to clear the value in the write trigger register. After the DDR PHY interface triggers the sideband access (for example, after writing 1 into the write trigger register to trigger the sideband write access), it can periodically read whether the access completion flag register is written with 1 to confirm whether the sideband access is completed.

[0158] In step S912, the sideband communication processing module generates a sideband write access command.

[0159] As an optional implementation, after the sideband communication processing module detects that the write trigger register is written with 1, it can determine the HID of the DIMM to be accessed corresponding to the sideband write access based on the DIMM address written through the DDR PHY interface and in combination with the HID configuration information in the first register set. It should be noted that the HID of each DIMM on the motherboard is unique. For DDR5 memory, an HID can be specified for each DIMM; during system initialization, the system software can write the HID configuration information (such as the HID value) of each DIMM into the HID configuration register corresponding to the DIMM, and the HID configuration register is set in the second register set, so as to define the HID configuration information for each DIMM in the HID configuration register of the sideband communication processing module.

[0160] Furthermore, the sideband communication processing module can determine the LID of the device to be accessed based on the device address written through the DDR PHY interface, so as to obtain the slave address by combining the HID of the DIMM to be accessed and the LID of the device to be accessed; furthermore, the sideband communication processing module can generate a sideband write access command carrying slave address, access byte information, internal address (such as register address, channel address, etc.), write data, etc. according to the format information required for the sideband write access to the DIMM and in accordance with the current protocol mode of the I2C / I3C host (indicated by the protocol configuration register in the second register set).

[0161] In step S913, the sideband communication processing module sends the sideband write access command to the I2C / I3C host.

[0162] Optionally, the sideband communication processing module can send the sideband write access command to the transmit FIFO (First In First Out) of the I2C / I3C host through the system management bus.

[0163] In step S914, the I2C / I3C host writes the write data into the corresponding DIMM through the sideband path according to the sideband write access command.

[0164] After obtaining the sideband write access command, the I2C / I3C host can write the write data into the corresponding DIMM through the sideband path according to the slave address and internal address of the sideband write access command. For example, the I2C / I3C host can serially send the information related to the sideband write access command in the transmit FIFO to the DIMM sideband interface to implement writing the write data into the DIMM storage space corresponding to the slave address and internal address.

[0165] In step S915, the I2C / I3C host writes 1 into the internal access end status register.

[0166] When the I2C / I3C host has written all the write data to the corresponding DIMM (for example, when the I2C / I3C host writes all the write data in the transmit FIFO to the corresponding DIMM through the DIMM sideband interface), the I2C / I3C host can write 1 to the internal access end status register to set the access end status register to a high level.

[0167] In step S916, the sideband communication processing module writes 1 to the access completion flag register in the first register set.

[0168] Optionally, after the sideband communication processing module sends the sideband write access command to the communication host, it can periodically read the access end status register of the I2C / I3C host to determine whether the I2C / I3C host has completed writing the write data to the corresponding DIMM by judging whether 1 is written to the access end status register. Thus, when the sideband communication processing module detects that 1 is written to the access end status register of the I2C / I3C host, it can write 1 to the access completion flag register in the first register set (an example of the sideband access completion flag), thereby indicating to the DDR PHY interface that the sideband write access has been completed (for example, when the DDR PHY interface reads that 1 is written to the access completion flag register, it confirms that the sideband write access to the memory module has been completed).

[0169] It should be noted that the sideband communication processing module can enter different sideband access processing stages through state jumps, thereby implementing Figure 9A the relevant processes therein; the content of the state jump can refer to the corresponding description in the previous text and will not be elaborated here.

[0170] In one implementation example, taking the DDR PHY interface initiating a sideband read access to the DIMM as an example, Figure 9B an exemplary processing process diagram of the sideband read access is shown, as Figure 9B shown, and this process can include the following steps.

[0171] In step S920, the DDR PHY interface writes the DIMM address, device address, register address, and channel address of the sideband read access to the corresponding registers in the first register set.

[0172] In step S921, the DDR PHY interface writes 1 to the read trigger register in the first register set to trigger the sideband read access.

[0173] In step S922, the sideband communication processing module generates a sideband write access command.

[0174] As an alternative implementation, the sideband communication processing module may generate a sideband read access command carrying information such as the slave address, access byte information, internal address (e.g., register address, channel address, etc.) according to the format information required for a sideband read access to the DIMM and in accordance with the current protocol mode of the I2C / I3C host (by the protocol configuration register in the second register set).

[0175] In step S923, the sideband communication processing module sends the sideband read access command to the I2C / I3C host.

[0176] Optionally, the sideband communication processing module may send the sideband read access command to the transmit FIFO of the I2C / I3C host via the system management bus.

[0177] In step S924, the I2C / I3C host reads read data from the corresponding DIMM via the sideband path according to the sideband read access command.

[0178] Optionally, after obtaining the sideband read access command, the I2C / I3C host may read read data from the corresponding DIMM via the sideband channel according to the slave address and internal address of the sideband read access command. For example, the I2C / I3C host may serially send the information related to the sideband read access command in the transmit FIFO to the DIMM sideband interface, so as to receive the read data returned by the corresponding DIMM via the DIMM sideband interface; the read data returned by the DIMM may be saved in the receive FIFO of the I2C / I3C host.

[0179] In step S925, the I2C / I3C host writes 1 to the internal access end status register.

[0180] When the I2C / I3C host has read all the read data (e.g., when a stop flag appears on the signal of the DIMM sideband interface, indicating that the DIMM has finished returning the read data and the I2C / I3C host has read all the read data), the I2C / I3C host may write 1 to the internal access end status register to set the access end status register to a high level.

[0181] In step S926, the sideband communication processing module saves the read data read by the I2C / I3C host to the read data register in the first register set.

[0182] In an alternative implementation, when the sideband communication processing module detects that the access end status register of the I2C / I3C host has been written with 1, the sideband communication processing module may read the read data from the receive FIFO of the I2C / I3C host via the system management bus and save the read data to the read data register in the first register set.

[0183] Optionally, after the sideband communication processing module sends the sideband read access command to the communication host, it can periodically read the access end status register of the I2C / I3C host to determine whether the I2C / I3C host has completely read the read data by judging whether the access end status register is written with 1.

[0184] In step S927, the sideband communication processing module writes 1 to the access completion flag register in the first register set.

[0185] After the sideband communication processing module completely saves the read data to the read data register, it can write 1 to the access completion flag register in the first register set, thereby indicating to the DDR PHY interface that the sideband read access is completed.

[0186] In step S928, the DDR PHY interface reads the read data from the read data register.

[0187] Optionally, when the DDR PHY interface detects that the access completion flag register is written with 1, it can read the read data returned from the DIMM from the read data register, so that the DDR PHY interface obtains the read data required for the sideband read access.

[0188] It should be noted that the sideband communication processing module can enter different sideband access processing stages through state jumps, so as to implement Figure 9B the related processes in; the content of the state jump can refer to the corresponding description in the previous text and will not be elaborated here.

[0189] The embodiment of the present application also provides a chiplet, which may include a memory controller, a memory physical layer interface, and a communication host; the memory controller may be the memory controller with the hardware logic of the sideband communication processing module provided in the embodiment of the present application, and is configured to execute the sideband access method provided in the embodiment of the present application.

[0190] In a further optional implementation, the chiplet may have multiple memory channels, and one memory channel includes a memory controller and a memory physical layer interface. Among them, the memory controller and the memory physical layer interface of one memory channel are connected to the memory module corresponding to this memory channel; and, the memory modules of multiple memory channels share the communication host. In one implementation example, Figure 10 Exemplarily shows another structural block diagram of a computer system, as Figure 2 and Figure 10 shown, in Figure 10In the computer system shown, the chiplet has multiple memory channels, which are divided into memory channel 1 to memory channel n, and the value of n, which is the number of memory channels, can be determined according to the actual situation. Among them, 1 memory channel has an independent memory controller, a memory physical layer interface, and a memory module, and the memory modules of multiple memory channels share the same communication host.

[0191] When multiple memory channels share the same communication host, the method of performing sideband access by the sideband communication processing module in the memory controller of each memory channel is the same. Further, for any memory channel, the sideband communication processing module in the memory controller of this memory channel needs to interact with the communication host when the communication host is in an idle state to avoid conflicts of sideband access of multiple memory channels at the communication host.

[0192] The embodiment of the present application also provides a computer device, such as a terminal device or a server device, and this computer device may include the chiplet provided by the embodiment of the present application.

[0193] The above text describes multiple embodiment solutions provided by the embodiments of the present application. The various optional ways introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, so as to extend multiple possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the embodiments of the present application.

[0194] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A sideband access method, characterized in that, The method is executed by the hardware logic of a memory controller, and the method includes: Obtaining sideband access information written by a memory physical layer interface, where the sideband access information is used for the memory physical layer interface to initiate sideband access to a memory module; Generating a sideband access command corresponding to the sideband access information according to the sideband access information, at least in accordance with the command protocol of a communication host; wherein, the communication host communicates with the memory module through a sideband path; Sending the sideband access command to the communication host to control the communication host to access the memory module.

2. The method according to claim 1, wherein The sideband access information carries address information written by the memory physical layer interface; the sideband access command carries access address information, and the access address information is determined according to the address information.

3. The method according to claim 2, characterized in that, The generating a sideband access command corresponding to the sideband access information according to the sideband access information, at least in accordance with the command protocol of a communication host includes: Generating a sideband access command corresponding to the sideband access information according to the sideband access information, at least in accordance with the current protocol mode of the communication host and the format information required by the sideband access command.

4. The method according to claim 3, characterized in that The generating a sideband access command corresponding to the sideband access information according to the sideband access information, at least in accordance with the current protocol mode of the communication host and the format information required by the sideband access command includes: Generating a sideband access command corresponding to the sideband access information according to the sideband access information, in accordance with the current protocol mode of the communication host, the host identifier configuration information of the memory module to be accessed, and the format information required by the sideband access command.

5. The method according to claim 4, wherein The address information includes the memory module address of the memory module to be accessed, the device address of the device to be accessed, and the internal address of the device to be accessed; wherein, the device to be accessed is located in the memory module to be accessed; The access address information includes a slave address and the internal address of the device to be accessed; Wherein, the slave address includes a host identifier and a local identifier; the host identifier is used to address the memory module to be accessed, and the host identifier is determined according to the host identifier configuration information of the memory module to be accessed and the memory module address; the local identifier is used to address the device to be accessed, and the local identifier is determined according to the device address of the device to be accessed.

6. The method according to claim 1, characterized in that Before executing the step of generating a sideband access command corresponding to the sideband access information, the method further includes: Requesting control rights from the communication host; When obtaining the control rights of the communication host, triggering the execution of the step of generating a sideband access command corresponding to the sideband access information; Releasing the control rights of the communication host when the access data transmission is completed.

7. The method according to claim 6, wherein Before executing the step of requesting control rights from the communication host, the method further includes: After obtaining the sideband access information written by the memory physical layer interface, obtaining the trigger information of the sideband access written by the memory physical layer interface.

8. The method according to claim 2 or 5, characterized in that, The method further includes: In response to the sideband access being triggered, starting to perform state jumps among multiple states to trigger entry into different sideband access processing stages.

9. The method according to claim 8, wherein The multiple states include an idle state, a state of requesting host control, a transmission state, and a state of releasing host control.

10. The method according to claim 9, wherein In response to the triggering of sideband access, starting to perform state transitions among the multiple states to trigger entry into different sideband access processing phases includes: In response to the triggering of sideband access, starting to transition from the idle state to the state of requesting host control; the state of requesting host control is used to trigger a request for control from the communication host. When obtaining control of the communication host, transitioning from the state of requesting host control to the transmission state; the transmission state is at least used for: triggering the generation of the sideband access command and sending the sideband access command to the communication host. When the access data is completely transmitted, transitioning to the state of releasing host control; the state of releasing host control is used to trigger the release of control of the communication host. After releasing the control of the communication host, transitioning back from the state of releasing host control to the idle state.

11. The method according to claim 10, wherein The multiple states further include: a waiting-for-transmission-completion state between the transmission state and the state of releasing host control; the transitioning to the state of releasing host control when the access data is completely transmitted includes: When the access data is completely transmitted, transitioning from the waiting-for-transmission-completion state to the state of releasing host control.

12. The method according to claim 11, wherein, The sideband access command includes a sideband write access command, the access address information includes write access address information, and the sideband write access command also carries write data. The transmission state includes: a write transmission state; the write transmission state is at least used for: triggering the generation of the sideband write access command and sending the sideband write access command to the communication host, so that the communication host writes the write data into the memory module according to the write access address information.

13. The method according to claim 12, characterized in that In response to the triggering of sideband access, starting to perform state transitions among the multiple states to trigger entry into different sideband access processing phases further includes: When sending the sideband write access command to the communication host, transitioning to the waiting-for-transmission-completion state. The transitioning to the state of releasing host control when the access data is completely transmitted includes: When detecting that the communication host has completed writing the write data into the memory module, transitioning from the waiting-for-transmission-completion state to the state of releasing host control; wherein, when the communication host has completed writing the write data into the memory module, the access data corresponding to the sideband write access command is completely transmitted.

14. The method according to claim 11, wherein The sideband access command includes a sideband read access command, and the access address information includes read access address information. The transmission state includes: a read transmission state and a read data saving state. The read transmission state is at least used for: triggering the generation of the sideband read access command and sending the sideband read access command to the communication host, so that the communication host reads read data from the memory module according to the read access address information. The read data saving state is at least used for: triggering the saving of the read data read by the communication host to the local storage space of the hardware logic; wherein, when detecting that the communication host has completely read the read data from the memory module, the read transmission state transitions to the read data saving state.

15. The method according to claim 14, wherein In response to the triggering of the sideband access, starting to perform state jumps among multiple states to trigger entry into different sideband access processing phases further includes: When starting to save the read data to the local storage space of the hardware logic, jumping to the waiting-for-transfer-completion state; The process of jumping from the waiting-for-transfer-completion state to the releasing-host-control state when the access data completes transmission includes: When the read data is completely saved to the local storage space of the hardware logic, jumping from the waiting-for-transfer-completion state to the releasing-host-control state; wherein, when the read data is completely saved to the local storage space of the hardware logic, the access data corresponding to the sideband read access command completes transmission.

16. The method according to claim 6, characterized in that, Before performing the step of requesting control right from the communication host, the method further includes: Judging whether the communication host is currently in an idle state; wherein, the communication host is shared by multiple memory channels, and one memory channel has an independent memory controller, a memory physical layer interface, and a memory module; If the communication host is in an idle state, then enter the step of requesting control right from the communication host; If the communication host is in a busy state, then wait for the communication host to become idle; the communication host being in a busy state means that the hardware logic of the memory controller of other memory channels is obtaining the control right of the communication host.

17. The method according to claim 13 or 15, characterized in that The method further includes: When the access data completes transmission, generating a sideband access completion flag to indicate to the memory physical layer interface that the sideband access has been executed.

18. A memory controller, characterized in that, The memory controller is provided with a sideband communication processing module, and the sideband communication processing module is the hardware logic of the memory controller; the sideband communication processing module is configured to execute the sideband access method according to any one of claims 1-17.

19. The memory controller according to claim 18, wherein The sideband communication processing module communicates with the memory physical layer interface through a communication bus added by the memory controller, and the sideband communication processing module communicates with the communication host through the system management bus; the communication host communicates with the memory module through the sideband path.

20. The memory controller according to claim 19, wherein The sideband communication processing module includes: a first register set, a command sequence module, and a command sending module; Among them, the first register set is at least used to save the sideband access information written by the memory physical layer interface; The command sequence module is at least used to generate commands sent to the communication host; the commands sent to the communication host include sideband access commands corresponding to the sideband access information; when generating the sideband access commands, the command sequence module is used to generate the sideband access commands according to the sideband access information and at least in accordance with the command protocol of the communication host; The command sending module is used to send the commands generated by the command sequence module to the communication host.

21. The memory controller according to claim 20, wherein The sideband access information carries the address information written by the memory physical layer interface; the first register set includes: an address register for saving the address information; wherein, the sideband access commands carry access address information, and the access address information is determined according to the address information.

22. The memory controller according to claim 21, wherein The sideband communication processing module further includes: a second register set, and the second register set saves the configuration information provided by the system software.

23. The memory controller according to claim 22, wherein The second register set at least includes a protocol configuration register that stores the current protocol mode of the communication host; When generating the sideband access command, the command sequence module is configured to generate a sideband access command corresponding to the sideband access information according to the sideband access information, at least in accordance with the current protocol mode of the communication host indicated by the protocol configuration register and the format information required by the sideband access command.

24. The memory controller according to claim 23, wherein, The second register set further includes a host identifier configuration register that stores the host identifier configuration information of each memory module; When generating the sideband access command, the command sequence module is configured to generate a sideband access command corresponding to the sideband access information according to the sideband access information, in accordance with the current protocol mode of the communication host indicated by the protocol configuration register, the host identifier configuration information of the memory module to be accessed indicated by the host identifier configuration register, and the format information required by the sideband access command.

25. The memory controller according to claim 21, wherein The address information includes the memory module address of the memory module to be accessed, the device address of the device to be accessed, and the internal address of the device to be accessed; The address register includes: a memory module address register, a device address register, and an internal address register; wherein, the memory module address register is used to store the memory module address, the device address register is used to store the device address, and the internal address register is used to store the internal address; The access address information includes the slave address and the internal address of the device to be accessed; wherein, the slave address includes a host identifier and a local identifier; the host identifier is used to address the memory module to be accessed, determined according to the host identifier configuration information of the memory module to be accessed and the memory module address; the local identifier is used to address the device to be accessed, determined according to the device address of the device to be accessed.

26. The memory controller according to claim 25, characterized in that, The internal address includes the register address of the register to be accessed and the channel address of the channel corresponding to the register to be accessed; wherein, the register to be accessed is located in the device to be accessed; The internal address register at least includes a register address register and a channel address register; the register address register is used to store the register address, and the channel address register is used to store the channel address.

27. The memory controller according to claim 21, wherein The first register set further includes at least one of the following: a data register, a trigger register, and an access completion flag register; The data register is used to store access data; The trigger register is used to store the trigger information of the sideband access written by the memory physical layer interface; The access completion flag register is used to store the sideband access completion flag, wherein, when the sideband communication processing module completes the transmission of access data, the sideband access completion flag is written into the access completion flag register.

28. The memory controller according to claim 27, wherein The data register includes a write data register and a read data register; the write data register is used to save the write data written by the memory physical layer interface when the memory physical layer interface initiates a sideband write access to the memory module; the read data register is used to save the read data read from the memory module when the memory physical layer interface initiates a sideband read access to the memory module; The trigger register includes a write trigger register and a read trigger register; The write trigger register is used to save the trigger information of the sideband write access written by the memory physical layer interface; The read trigger register is used to save the trigger information of the sideband read access written by the memory physical layer interface.

29. The memory controller according to claim 21 or 25, characterized in that, The sideband communication processing module further includes: a sideband communication processing state machine and a host state parsing module; The sideband communication processing state machine is used to start state jumps among multiple states in response to the triggering of a sideband access, so as to trigger the entry into different sideband access processing stages; The host state parsing module is used to parse the information of the communication host and feedback the information of the communication host to the sideband communication processing state machine, so as to trigger the sideband communication processing state machine to perform state jumps in part.

30. The memory controller according to claim 29, wherein The multiple states include an idle state, a request host control right state, a transmission state, and a release host control right state.

31. The memory controller according to claim 30, wherein, The sideband communication processing state machine is used for: In response to the triggering of a sideband access, start jumping from the idle state to the request host control right state; the request host control right state is used to trigger the command sequence module to generate a request command, and the request command is used to request the control right of the communication host; Based on the response signal of the communication host to the request command detected by the host state parsing module, jump from the request host control right state to the transmission state; The transmission state is at least used to trigger the command sequence module to generate the sideband access command; When the access data is completely transmitted, jump to the release host control right state; The release host control right state is used to trigger the command sequence module to generate a release command, and the release command is used to release the control right of the communication host; After releasing the control right of the communication host, jump back from the release host control right state to the idle state.

32. The memory controller according to claim 31, wherein The multiple states further include: a waiting for transmission completion state between the transmission state and the release host control right state; when the access data is completely transmitted, the sideband communication processing state machine jumps the waiting for transmission completion state to the release host control right state.

33. The memory controller according to claim 32, wherein The sideband access command includes a sideband write access command, the access address information includes write access address information, and the sideband write access command also carries write data; The transmission state includes: a write transmission state; the write transmission state is at least used for: triggering the command sequence module to generate the sideband write access command, so that the command sending module sends the sideband write access command to the communication host, so as to control the communication host to write the write data into the memory module according to the write access address information.

34. The memory controller according to claim 33, wherein, When the sideband write access command is sent to the communication host, the sideband communication processing state machine jumps to the waiting for transmission completion state; and based on the high-level state of the access end status register of the communication host detected by the host status parsing module, the sideband communication processing state machine confirms that the communication host has completed writing the write data into the memory module, so as to jump the waiting for transmission completion state to the releasing host control right state; wherein, when the communication host has completed writing the write data into the memory module, the access data corresponding to the sideband write access command has completed transmission.

35. The memory controller according to claim 32, wherein The sideband access command includes a sideband read access command, and the access address information includes read access address information; The transmission state includes: a read transmission state and a read data saving state; the read transmission state is at least used for: triggering the command sequence module to generate the sideband read access command, so that the command sending module sends the sideband read access command to the communication host, to control the communication host to read read data from the memory module according to the read access address information; The read data saving state is at least used for: triggering the sideband communication processing module to save the read data read by the communication host into the read data register; Wherein, based on the high-level state of the access end status register of the communication host detected by the host status parsing module, the sideband communication processing state machine confirms that the communication host has completely read the read data from the memory module, so as to jump the read transmission state to the read data saving state; When starting to save the read data into the read data register, it jumps to the waiting for transmission completion state; and when the read data is completely saved into the read data register, it jumps from the waiting for transmission completion state to the releasing host control right state; when the read data is completely saved into the read data register, the access data corresponding to the sideband read access command has completed transmission.

36. A die, characterized in that, It includes a memory controller, a memory physical layer interface and a communication host; the memory controller is the memory controller according to any one of claims 18-35.

37. The chiplet according to claim 36, wherein The die has multiple memory channels, one memory channel includes a memory controller and a memory physical layer interface, the memory controller and the memory physical layer interface of one memory channel are connected to the memory module corresponding to this memory channel; and, multiple memory channels share the communication host.

38. A computer device, characterized in that, It includes the die according to any one of claims 36-37.

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