Chip particle, chip particle interconnection method, chip particle system and computer device

Abstract

The embodiments of the present application provide a chiplet, a chiplet interconnection method, a chiplet system, and a computer device, wherein the chiplet includes: a link layer and a physical layer; the physical layer includes a data path, and the information transmission mode of the data path includes a bypass mode and a normal mode, and the transmission rate of the bypass mode is lower than that of the normal mode; wherein the normal mode is the information transmission mode corresponding to the link between the data path and the chiplet at the opposite end after the chiplet establishes a link with the chiplet at the opposite end; the link layer is used to generate at least a bypass control signal before establishing the link, and transmit the bypass control signal to the data path; the data path is used to transmit control information with the chiplet at the opposite end using the bypass mode based on the bypass control signal before establishing the link. Before establishing the link, the embodiments of the present application can use the bypass mode of the data path to multiplex the data path to transmit control information, avoid using the sideband path to transmit control information, and provide the possibility of reducing the resources occupied by the chiplet interconnection.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and specifically to a chiplet, a chiplet interconnection method, a chiplet system, and a computer device. Background Art

[0002] A chiplet is a unit chip that can realize certain functions and contains a chiplet interconnection interface (interconnection interface for short). Multiple chiplets can be interconnected through the interconnection interface to form a chiplet system, which can form chips such as SOC (System On Chip).

[0003] Chip-particle interconnection refers to the use of protocols to coordinate and schedule the communication between two chiplets based on the physical connection of the interconnection interface of the two chiplets, so as to achieve interconnection and intercommunication between the two chiplets. In this context, how to provide a technical solution to reduce the resources occupied by chip-particle interconnection has become a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] In view of this, the embodiments of the present application provide an information transmission method, a chiplet, and a computer device, so as to provide a possibility for reducing the resources occupied by the chiplet interconnection.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a core particle, including: a link layer and a physical layer;

[0007] The physical layer includes a data path, and the information transmission mode of the data path includes a bypass mode and a normal mode, and the transmission rate of the bypass mode is lower than that of the normal mode; wherein the normal mode is an information transmission mode corresponding to the link of the data path after the core particle establishes a link with the opposite core particle;

[0008] The link layer is used to, before establishing a link, at least generate a bypass control signal and transmit the bypass control signal to the data path;

[0009] The data path is used to transmit control information to the opposite end chiplet using a bypass mode based on the bypass control signal before establishing a link.

[0010] In a second aspect, an embodiment of the present application provides a chiplet interconnection method, the method being applied to a chiplet, the method comprising:

[0011] Before the core particle establishes a link with the opposite end core particle, at least a bypass control signal is generated;

[0012] Based on the bypass control signal, control the data path of the core particle to be in bypass mode, so that the core particle transmits control information with the opposite end core particle through the bypass mode of the data path;

[0013] The information transmission mode of the data path includes a bypass mode and a normal mode. The transmission rate of the bypass mode is lower than that of the normal mode. The normal mode is the information transmission mode corresponding to the data path and the link after the link is established.

[0014] In a third aspect, an embodiment of the present application provides a core particle system, comprising a plurality of core particles, wherein the core particles are the core particles described in the first aspect above.

[0015] In a fourth aspect, an embodiment of the present application provides a computer device, comprising the core particle system as described in the third aspect above.

[0016] The core particle provided by the embodiment of the present application includes a link layer and a physical layer, the physical layer includes a data path, and the information transmission mode of the data path includes a bypass mode and a normal mode, the transmission rate of the bypass mode is lower than the normal mode, and the normal mode is the information transmission mode corresponding to the link between the data path and the core particle at the opposite end after the core particle establishes a link with the core particle at the opposite end; thus, before the link is established, the link layer of the core particle can generate a bypass control signal, and transmit the bypass control signal to the data path, so that the data path can use the bypass mode to transmit control information with the core particle at the opposite end based on the bypass control signal before the link is established. It can be seen that before the link is established, the embodiment of the present application can use the bypass mode of the data path to multiplex the data path to transmit control information, avoid using the sideband path to transmit control information, so that the sideband path can be used as an optional configuration in the core particle, and provide a solution to the problem that the sideband path occupies more hardware resources, thereby providing a possibility for reducing the resources occupied by the core particle interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0018] Figure 1 This is an example diagram of the structure of the core particle system.

[0019] Figure 2 The following is an example diagram of the layering of the interconnection protocol.

[0020] Figure 3 This is an example diagram of the physical layer.

[0021] Figure 4 The following is an example of the content transmitted between core particles through the sideband path.

[0022] Figure 5A This is a block diagram of the core particle.

[0023] Figure 5B Another block diagram of the core particle.

[0024] Fig. 6A Another block diagram of the core particle.

[0025] Figure 6B Another block diagram of the core particle.

[0026] Figure 6C Yet another block diagram of a core particle.

[0027] Figure 7 Flowchart of the chiplet interconnection method.

[0028] Fig. 8A Flowchart of a method for distinguishing information types.

[0029] Figure 8B A flow chart of another method for distinguishing information types.

[0030] Fig.9A This is an example diagram for distinguishing information types.

[0031] Fig. 9B Another example diagram for distinguishing information types.

[0032] Fig. 10A This is an example diagram of the core particle clock.

[0033] Fig. 10B Another clock example diagram of the core particle. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] To understand the core particle system, let's take two core particles as an example. Figure 1 The structure of the core particle system is shown as an example. Figure 1 As shown, the core particle may include an interconnection interface 110 and a plurality of functional modules 120. Inside the core particle, the interconnection interface 110 is connected to the plurality of functional modules 120 via a system bus. Between two core particles, the two core particles are interconnected via the interconnection interface.

[0036] It should be noted that the two core particles interconnected through the interconnection interface may be two core particles of any type. For example, two functional core particles may be interconnected through the interconnection interface, a functional core particle and an interface core particle may be interconnected through the interconnection interface, etc.

[0037] Based on the different types of core particles, the form of the functional modules that implement the core particle functions in the core particles may also be different. For example, the functional core particles may include processor core core particles (such as CPU core particles), and the functional modules in the processor core core particles may be modules integrating the processor core and the cache (Cache), as well as other functional modules. For another example, the interface core particle may be a core particle where the interface module for communication modes such as docking network communication, USB (Universal Serial Bus) communication, PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) communication is located.

[0038] The core particles can be interconnected according to the interconnection protocol of the interconnection interface. The interconnection protocol can define a hierarchical mechanism for core particles to transmit information through the interconnection interface. For example, Figure 2 The following is an exemplary diagram showing the layered example of the interconnection protocol: Figure 2 As shown, in the core particle, the layering of the interconnection protocol may include a protocol layer 210 , a link layer 220 , and a physical layer 230 .

[0039] The protocol layer 210 is used to support the service protocols corresponding to the services carried by the core particles, which are related to the types of services carried by the core particles; the service protocols supported by the protocol layer include but are not limited to the AXI (Advanced Extensible Interface) bus protocol, and through extension, it can support bus protocols such as CHI (Coherent Hub Interface), ACE (AXI Coherency Extensions), and HAI (Highbandwidth memory Access Interface) access protocol, etc. Further, the protocol layer can also support user-defined protocols, such as protocols corresponding to user-defined services.

[0040] The protocol layer 210 and the link layer 220 can be connected through a compatible interface. The link layer 220 can provide reliability assurance for communication between core particles, including but not limited to: error correction, verification, retransmission mechanism, etc. The link layer 220 and the physical layer 230 can be connected through a compatible interface. The physical layer 230 can provide a physical path (referred to as a path) for core particles to transmit information.

[0041] One of the purposes of chiplet interconnection is to achieve communication between chiplets, that is, information transmission between chiplets. The information transmitted between chiplets may be data information or control information, so the physical layer path can be divided into a data lane for transmitting data information and a sideband path for transmitting control information. For ease of understanding, Figure 3 An example diagram of the physical layer is shown in FIG. Figure 2 and Figure 3 As shown, the physical layer 230 may include a data path 310 and a sideband path 320. The number of data paths in the physical layer may be multiple.

[0042] The data path 310 , as a basic unit of the physical layer, can be regarded as a collection of multiple IO (input and output) ports, and the multiple IO ports share a data path clock, which can be in the form of a differential clock, for example.

[0043] Based on the fact that the information transmitted by the chip is divided into sending information and receiving information, the information transmission direction of the chip is divided into sending direction and receiving method. The sending direction can be the direction in which the chip sends information to the opposite chip, and the receiving direction can be the direction in which the chip receives information sent by the opposite chip. For any chip, the opposite chip of the chip can be the other chip that communicates with the chip.

[0044] Regarding data information, the core particle transmission data information can be divided into sending data information and receiving data information. Figure 3 As shown, the data lane 310 can be divided into a transmit data lane (Tx Data Lane) 311 and a receive data lane (Rx Data Lane) 312; Tx represents transmit, and Rx represents receive. The number of transmit data lanes in the physical layer can be one or more, and the number of receive data lanes in the physical layer can be one or more.

[0045] The transmit data path 311 is a data path for the physical layer to send data information; the transmit data path 311 may be a collection of multiple IO ports that share a transmit clock in the transmit direction. For example, when the chiplet sends data information, the data information may be sent through multiple IO ports of the transmit data path 311 and accompanied by a transmit clock. The transmit clock may be a data path clock corresponding to the transmit direction.

[0046] The receiving data path 312 is a data path for the physical layer to receive data information; the receiving data path 312 may be a collection of multiple IO ports that share a receiving clock in the receiving direction. For example, when the chip receives data information, the data information may be received through multiple IO ports of the receiving data path 312 and accompanied by a receiving clock. The receiving clock may be a data path clock corresponding to the receiving direction.

[0047] In an example, from the perspective of the protocol layer to the physical layer, in the sending direction of the core particle, the protocol layer can transmit the data information that the core particle needs to send to the link layer through a corresponding interface (the data information to be sent can come from the upper-layer business of the core particle); the link layer divides the data information to be sent into data blocks (Flit), so that the data information is transmitted in data blocks, and the data format of the data block can be defined according to the business protocol supported by the protocol layer; then, the link layer distributes the data block to the physical layer through a corresponding interface, and the physical layer sends the data block to the opposite end core particle through the transmission data path.

[0048] In one example, in the receiving direction, the physical layer receives the data block sent by the opposite end chip through the receiving data path, and transmits it to the link layer through the corresponding interface; the link layer transmits the data block to the protocol layer through the corresponding interface; the protocol layer assembles the data block into data information, and transmits the data information to the upper layer service of the chip.

[0049] The above article introduces the mechanism of core particles transmitting data information through the interconnection interface. In addition to data information, the information transmitted between core particles may also be control information. Control information can be used for purposes such as link control. For example, the transmission of control information between core particles may involve the following scenarios:

[0050] Before a chiplet establishes a link with a peer chiplet (i.e., during the link establishment process), the link configuration needs to be performed through control information to synchronize the link configuration commands between the chiplets;

[0051] After the chiplet establishes a link with the opposite chiplet, it may also be necessary to perform state control through control information. For example, after the link is established, the low power consumption state of the chiplet may be controlled through control information.

[0052] In the core, control information can be transmitted through the sideband path of the physical layer. Figure 3 As shown, the sideband path 320 may be a physical path in the physical layer that cooperates with the data path and is used to transmit control information; the sideband path may be a collection of multiple IO ports that share a sideband path clock.

[0053] The sideband path of the core can also be divided into a sending direction and a receiving direction. The sending direction of the sideband path can be connected using a clock signal and a data signal, and optionally supports a redundant IO port; the data signal connected in the sending direction of the sideband path corresponds to the control information sent by the sideband path to the opposite core. At the same time, the receiving direction of the sideband path can also be connected using a clock signal and a data signal, and optionally supports a redundant IO port; the data signal connected in the receiving direction of the sideband path corresponds to the control information received by the sideband path from the opposite core.

[0054] For example, Figure 4 The following is an example diagram showing the content transmitted between core particles through the sideband path. Figure 4 As shown, the sideband path of the core particle is connected to a clock signal (e.g., a sideband transmitter clock), a data signal (e.g., a sideband transmitter data) in the sending direction, and optionally supports a redundant IO port (e.g., sideband transmitter redundancy); the sideband path of the core particle is connected to a clock signal (e.g., a sideband receiver clock), a data signal (e.g., sideband receiver data) in the receiving direction, and optionally supports a redundant IO port (e.g., sideband receiver redundancy).

[0055] The previous article mentioned concepts such as link and path. What needs to be explained is that in the field of chiplet interconnection, link and path are different concepts. A link is a link unit managed by the link layer, which corresponds to the service bandwidth managed by the link layer. For example, the bandwidth requirement of a link can be determined based on the service bandwidth, and the link layer can bind different numbers of data paths in the physical layer based on the service bandwidth to form links with different bandwidths; then, the data information on the link can be transmitted through the data path of the corresponding bandwidth. Therefore, there is a process of establishing a link between chiplets, such as initialization, training and other link establishment processes, so that data information can be transmitted at high speed between chiplets through the data path corresponding to the link.

[0056] From the above description, it can be seen that the physical layer of the chiplet is provided with a data path and a sideband path, and the data path is used to transmit data information, and the sideband path is used to transmit control information. However, the setting of the sideband path to transmit control information alone may occupy more hardware resources of the chiplet, for example:

[0057] In order to cope with business scenarios with high bandwidth requirements, the chip needs to increase the number of data channels to increase the transmission bandwidth of data information; however, the increase in the number of data channels will increase the number of sideband channels accordingly, which leads to an increase in the hardware resources occupied by the sideband channels; that is, as the number of sideband channels increases, the number of sideband channels also increases accordingly, resulting in more and more hardware resources occupied by the sideband channels, and the sideband channels are only used to transmit control information, not for transmitting business data information;

[0058] In the core, the link layer and the physical layer need to be connected by wiring. The setting of the sideband channel to transmit control information separately and the increase in the number of sideband channels will lead to an increase in the wiring of the core, which will increase the occupation of hardware resources.

[0059] It can be seen that the setting of transmitting control information separately through the sideband path will occupy more hardware resources of the chip, resulting in an increase in the bump of the chip, which affects the bandwidth efficiency of the chip interconnection. Among them, the bump refers to the physical structure used to connect the chip and the interposer or substrate in the package.

[0060] Based on this, the embodiment of the present application provides an improved chip interconnection solution, which transmits control information by multiplexing data paths so that sideband paths can be used as optional configurations in the chip, thereby providing the possibility of reducing the hardware resources occupied by the sideband paths, and further providing the possibility of saving the resources of the chip.

[0061] Based on the above ideas, as an optional implementation, the embodiment of the present application can design a scheme for multiplexing data path transmission control information, so that before the core grain establishes a link with the opposite core grain, the data path is multiplexed to transmit control information, and after the core grain establishes a link with the opposite core grain, while the data path can transmit data information, the data path is multiplexed to transmit control information, so that the sideband path can become an optional configuration in the core grain. The sideband path can become an optional configuration in the core grain, for example, the sideband path can be deleted in the core grain, or the sideband path can be retained in the core grain but disabled.

[0062] To achieve the above purpose, as an optional implementation, the embodiment of the present application can improve the information transmission mode of the data path, so that the data path can transmit control information before establishing a link, and can transmit data information and control information after establishing a link. Figure 5A An optional block diagram of a core particle is shown as an example. Figure 5A As shown, the core may include a link layer 220 and a physical layer 230, wherein the physical layer 230 may include a data path 310. In the embodiment of the present application, the data path has two information transmission modes, and the information transmission modes of the data path include a bypass mode 511 and a normal mode 512. The transmission rate of the bypass mode is lower than the transmission rate of the normal mode.

[0063] In an optional implementation, the normal mode may be the information transmission mode of the data path corresponding to the link after the core particle establishes a link with the opposite core particle. It should be noted that the establishment of the link is through the link establishment process such as initialization and training so that the data path is in the normal mode, and then the core particles can perform high-speed data information transmission in the normal mode through the data path corresponding to the link; that is, through the link establishment process such as initialization and training, the data path can be in the normal mode corresponding to the link, and then the data path can perform high-speed data information transmission in the normal mode in a normal working state.

[0064] In order to multiplex the data path to transmit control information before establishing a link, the embodiment of the present application can add a bypass mode to the data path. As an optional implementation, the bypass mode can be regarded as a low-speed information transmission mode added to the data path before establishing a link.

[0065] In the case where the data path has a bypass mode and a normal mode, combined Figure 5A As shown, the embodiment of the present application can put the data path in bypass mode before establishing a link, and then the core particle can use the bypass mode of the data path to transmit control information to the opposite core particle.

[0066] As an optional implementation, before establishing a link, the core particle may at least generate a bypass control signal, so that the core particle may control the data path of the core particle to be in bypass mode based on the bypass control signal, so that the core particle may transmit control information with the opposite core particle through the bypass mode of the data path.

[0067] In one implementation example, combining Figure 5A As shown, the bypass control signal can be generated by the link layer; before establishing the link, the link layer can generate the bypass control signal and pass the bypass control signal to the data path; thus, before establishing the link, the data path can use the bypass mode to transmit control information with the other end chip based on the bypass control signal.

[0068] After the link is established, the Figure 5A As shown, the normal mode of the data path is in an available state, so that the chiplet can disable the bypass mode of the data path and enable the normal mode of the data path, so that the chiplet can transmit information with the opposite chiplet through the normal mode of the data path.

[0069] As an optional implementation, after the link is established, the information transmitted by the core particle using the normal mode of the data path can be divided into data information and control information. That is, in the case where the sideband path is deleted or disabled in the embodiment of the present application, after the link is established, in addition to transmitting data information using the normal mode of the data path, the core particle also needs to transmit control information using the normal mode.

[0070] The core particle provided by the embodiment of the present application includes a link layer and a physical layer, the physical layer includes a data path, and the information transmission mode of the data path includes a bypass mode and a normal mode, the transmission rate of the bypass mode is lower than the normal mode, and the normal mode is the information transmission mode corresponding to the link between the data path and the core particle at the opposite end after the core particle establishes a link with the core particle at the opposite end; thus, before the link is established, the link layer of the core particle can generate a bypass control signal, and transmit the bypass control signal to the data path, so that the data path can use the bypass mode to transmit control information with the core particle at the opposite end based on the bypass control signal before the link is established. It can be seen that before the link is established, the embodiment of the present application can use the bypass mode of the data path to multiplex the data path to transmit control information, avoid using the sideband path to transmit control information, so that the sideband path can be used as an optional configuration in the core particle, and provide a solution to the problem that the sideband path occupies more hardware resources, thereby providing a possibility for reducing the resources occupied by the core particle interconnection.

[0071] As an optional implementation, the bypass mode and the normal mode of the data path can be implemented by setting two information transmission channels for the IO port of the data path; optionally, Figure 5B Another optional block diagram of the core particle is shown as an example, combined with Figure 5A and Figure 5B As shown, the data path 310 has an IO port 520 (the data path can be regarded as a collection of multiple IO ports), and the IO port 520 has a first information transmission channel 521 and a second information transmission channel 522. Among them, the first information transmission channel of the IO port can match the bypass mode of the data path, and is used to transmit control information before establishing a link. The second information transmission channel of the IO port can match the normal mode of the data path, and is used to transmit information (divided into control information and data information) with the opposite end chip after establishing a link.

[0072] In an optional implementation, the second information transmission channel of the IO port may be a transmission channel corresponding to the IO port and the link after the link is established. That is to say, when the data path transmits data information through the IO port (the data path needs to transmit data information after the link is established), the data path transmits data information through the second information transmission channel of the IO port; thus, for the IO port in the data path, the embodiment of the present application may add a first information transmission channel to the IO port on the basis of the second information transmission channel of the IO port, thereby enabling the IO port to have the ability to transmit control information before the link, so as to realize that the data path has a bypass mode before the link is established in addition to the normal mode after the link is established. Optionally, based on the transmission rate of the bypass mode of the data path being lower than that of the normal mode, the transmission rate of the first information transmission channel of the IO port of the data path may be lower than that of the second information transmission channel.

[0073] It should be noted that setting a first information transmission channel and a second information transmission channel for the IO port of the data path so that the data path has a bypass mode and a normal mode is only an optional implementation method. The embodiment of the present application can also support other methods to enable the data path to have a bypass mode and a normal mode, as long as the data path is guaranteed to be able to transmit control information before establishing a link.

[0074] As an optional implementation, based on the data path being divided into a transmitting data path in the transmitting direction and a receiving data path in the receiving direction, when the data path has a bypass mode and a normal mode, the transmitting data path can have a bypass mode and a normal mode accordingly, and the receiving data path can have a bypass mode and a normal mode accordingly. Fig. 6A Another optional block diagram of the core particle is shown as an example, combined with Figure 5A and Fig. 6A As shown, the data path of the physical layer 230 may include a transmit data path 311 and a receive data path 312. The transmit data path 311 has two information transmission modes, including a bypass mode 511 and a normal mode 512; the information transmission mode of the transmit data path may be an information transmission mode in which the transmit data path sends information. The receive data path 312 has two information transmission modes, including a bypass mode 511 and a normal mode 512; the information transmission mode of the receive data path may be an information transmission mode in which the receive data path receives information.

[0075] The normal mode of the transmission data path can be the information transmission mode corresponding to the transmission data path and the link after the link is established, that is, the information transmission mode corresponding to the transmission data path and the link for sending information; that is, after the link is established, the transmission data path sends the information that the core needs to send to the opposite core in normal mode. The bypass mode of the transmission data path can be a low-speed information transmission mode added to the transmission data path, which is used to send control information to the opposite core before the link is established. Before the link is established, the transmission data path can be in bypass mode based on the bypass control signal transmitted by the link layer.

[0076] The normal mode of the receiving data path may be the information transmission mode corresponding to the link after the link is established, that is, the information transmission mode corresponding to the link for receiving information; that is, after the link is established, the receiving data path receives the information sent by the opposite end chip in the normal mode. The bypass mode of the receiving data path may be a low-speed information transmission mode added to the receiving data path, which is used to receive the control information sent by the opposite end chip before the link is established. Before the link is established, the receiving data path may be in the bypass mode based on the bypass control signal transmitted by the link layer.

[0077] It can be seen that after the link is established, the information transmitted between the coreparticle and the opposite coreparticle includes: information sent by the coreparticle to the opposite coreparticle, and information received by the coreparticle from the opposite coreparticle. For the sake of convenience, the information sent by the coreparticle to the opposite coreparticle after the link is established is referred to as sent information, and the information received by the coreparticle from the opposite coreparticle is referred to as received information. It should be noted that after the link is established, since there is a need to transmit control information and data information between the coreparticles through the data path, the sent information may be data information or control information. Similarly, the received information may be data information or control information.

[0078] As an optional implementation, the embodiment of the present application can set two information transmission channels at the transmission IO port of the transmission data path (the IO port of the transmission data path is called the transmission IO port) so that the transmission data path has a bypass mode and a normal mode. For example, the transmission IO port can have a first information transmission channel matching the bypass mode, which is used to send the control information transmitted by the link layer to the opposite end chip before the link is established; and the transmission IO port can have a second information transmission channel matching the normal mode, which is used to send the transmission information to the opposite end chip after the link is established.

[0079] As an optional implementation, the embodiment of the present application can set two information transmission channels at the receiving IO port of the receiving data path (the IO port of the receiving data path is called the receiving IO port) so that the receiving data path has a bypass mode and a normal mode. For example, the receiving IO port can have a first information transmission channel matching the bypass mode, which is used to pass the control information sent by the other end chip to the link layer before the link is established; and the receiving IO port can have a second information transmission channel matching the normal mode, which is used to pass the received information to the link layer after the link is established.

[0080] In an implementation example, Figure 6B Another optional block diagram of the core particle is shown as an example, combined with Figure 5A , Fig. 6A and Figure 6B As shown, the transmit data path 311 is provided with a transmit IO port 610, and the receive data path 312 is provided with a receive IO port 620. Optionally, the transmit IO port 610 may be in the form of a multiplexer (mux), which may be a combinational logic circuit with multiple inputs and a single output.

[0081] As an optional implementation, to match the bypass mode and normal mode of the transmitting IO port, combine Figure 6B As shown, the transmit IO port 610 may include a first input terminal 611 , a second input terminal 612 , a first control terminal 613 , and an output terminal 614 .

[0082] The first input terminal 611 corresponds to the bypass mode of the transmitting IO port 610; that is, the information transmission channel from the first input terminal 611 to the output terminal 614 is the first information transmission channel that matches the transmitting IO port with the bypass mode. Therefore, before establishing a link, the transmitting IO port can receive the control information transmitted by the link layer through the first input terminal 611, and send it to the opposite end chip through the output terminal 614.

[0083] The second input terminal 612 corresponds to the normal mode of the transmitting IO port 610; that is, the information transmission channel from the second input terminal 612 to the output terminal 614 is the second information transmission channel that matches the normal mode of the transmitting IO port; that is, after the link is established, the information transmission channel from the second input terminal 612 to the output terminal 614 is the information transmission channel that corresponds to the transmitting IO port and the link. Therefore, after the link is established, the transmitting IO port can receive the transmission information transmitted by the link layer through the second input terminal 612, and send it to the opposite end chip through the output terminal 614.

[0084] As an optional implementation, the first control terminal 613 of the transmitting IO port may be used to receive a bypass control signal transmitted by the link layer before establishing a link, so as to put the transmitting IO port in a bypass mode.

[0085] In an implementation example, combining Figure 6B As shown, before establishing a link, the link layer can generate a bypass control signal and transmit it to the first control terminal 613 of the transmitting IO port; the first control terminal 613 receives the bypass control signal transmitted by the link layer to put the transmitting IO port in bypass mode; in bypass mode, the transmitting IO port enables the information transmission channel from the first input terminal 611 to the output terminal 614; thus, the control information transmitted by the link layer is received through the first input terminal 611, and the control information received by the first input terminal 611 is output to the opposite end chip through the output terminal 614;

[0086] After the link is established, the transmitting IO port can be in normal mode. In normal mode, the transmitting IO port disables the first input terminal 611 and enables the information transmission channel from the second input terminal 612 to the output terminal 614; thereby, the transmitting information (which may be data information or control information) transmitted by the link layer is received through the second input terminal 612, and the transmitting information received by the second input terminal 612 is sent to the opposite end chip through the output terminal 614.

[0087] As an optional implementation, to match the bypass mode and normal mode of the receiving IO port, combine Figure 6B As shown, the receiving IO port 620 may include a first receiving end 621 , a second receiving end 622 , and a second control end 623 .

[0088] The first receiving end 621 corresponds to the bypass mode of the receiving IO port; that is, the information transmission channel of the first receiving end 621 is the first information transmission channel that matches the receiving IO port with the bypass mode. Therefore, before establishing a link, the receiving IO port can receive the control information sent by the opposite end chiplet through the first receiving end 621 and pass it to the link layer.

[0089] The second receiving end 622 corresponds to the normal mode of the receiving IO port; that is, the information transmission channel of the second receiving end 622 is the second information transmission channel that matches the normal mode of the receiving IO port; that is, after the link is established, the information transmission channel of the second receiving end 622 is the information transmission channel that corresponds to the receiving IO port and the link. Therefore, after the link is established, the receiving IO port can receive the receiving information sent by the opposite end chiplet through the second receiving end 622 and pass it to the link layer.

[0090] As an optional implementation, the second control terminal 623 of the receiving IO port may be used to receive a bypass control signal transmitted by the link layer before establishing a link, so as to put the receiving IO port in a bypass mode.

[0091] In an implementation example, combining Figure 6BAs shown, before establishing a link, the link layer can generate a bypass control signal and transmit it to the second control terminal 623 of the receiving IO port; the second control terminal 623 receives the bypass control signal transmitted by the link layer to put the receiving IO port in bypass mode; in bypass mode, the receiving IO port enables the information transmission channel of the first receiving terminal 621, receives the control information sent by the opposite end chip through the first receiving terminal 621, and transmits it to the link layer;

[0092] After the link is established, the receiving IO port is in normal mode. In normal mode, the receiving IO port disables the information transmission channel of the first receiving end 621 and enables the information transmission channel of the second receiving end 622; thereby receiving the receiving information (which may be data information or control information) sent by the opposite end chip through the second receiving end 622 and passing it to the link layer.

[0093] As an optional implementation, Figure 6C Another optional block diagram of the core particle is shown as an example, combined with Figure 6B and Figure 6C As shown, the link layer can set a transmit data path (Tx Data Path) 631, a receive data path (Rx Data Path) 632, and a control logic (Control Logic) 633.

[0094] The transmission data path 631 corresponds to the transmission data path 311. The link layer can transmit the information that the core needs to send to the transmission data path through the transmission data path. As an optional implementation, before establishing a link, the control information generated by the link layer can be transmitted from the transmission data path to the transmission data path; for example, in combination with Figure 6C As shown, before establishing the link, the transmit data path may pass the control information to the first input terminal 611 of the transmit IO port 610. As an optional implementation, after establishing the link, the transmit information may be passed by the transmit data path to the transmit data path; for example, in combination with Figure 6C As shown, after the link is established, the transmit data path can pass the transmit information to the second input terminal 612 of the transmit IO port 610.

[0095] The receiving data path 632 corresponds to the receiving data path 312. The link layer can receive information transmitted by the receiving data path through the receiving data path. As an optional implementation, before establishing a link, the control information sent by the peer chiplet can be transmitted by the receiving data path to the receiving data path, so as to realize the transmission of the control information sent by the peer chiplet to the link layer; for example, in combination with Figure 6CAs shown, before establishing a link, the first receiving end 621 of the receiving IO port can pass the control information sent by the other end chip to the receiving data path 632. After establishing the link, the receiving information sent by the other end chip can be passed to the receiving data path by the receiving data path to achieve the transmission of the receiving information to the link layer; for example, in combination with Figure 6C As shown, after the link is established, the second receiving end 622 of the receiving IO port can pass the received information to the receiving data path 632.

[0096] The control logic can be the logic that acts on the link negotiation in the link layer before the link is established; because before the link is established, the embodiment of the present application multiplexes the data path to transmit the control information, so when the core grain sends the control information, the control information is no longer passed to the sideband path through the control logic of the link layer, but is passed by the transmission data path of the link layer to the corresponding transmission data path for transmission. In addition, in the embodiment of the present application, the control logic is adjusted to: before the link is established, a bypass control signal is generated, the bypass control signal is passed to the transmission data path (for example, the first control end of the transmission IO port), and the bypass control signal is passed to the receiving data path (for example, the second control end of the receiving IO port). That is to say, before the link is established, the bypass control signal is passed by the control logic to the transmission data path and the receiving data path.

[0097] As an implementation example, Figure 7 An optional flow chart of the chiplet interconnection method is shown as an example, combined with Figure 6C and Figure 7 As shown, the process may include the following steps.

[0098] In step S710, before establishing a link, the link layer generates a bypass control signal.

[0099] In step S711, the link layer transmits a bypass control signal to the transmit data path and the receive data path of the physical layer.

[0100] Before a core particle establishes a link with a peer core particle, based on the need for the core particle and the peer core particle to perform link negotiation through control information, the link layer can generate a bypass control signal and pass the bypass control signal to the transmit data path and receive data path of the physical layer, so that the transmit data path and the receive data path are in bypass mode.

[0101] Optionally, the control logic of the link layer may transmit the bypass control signal to a first control end of a transmit IO port of a transmit data path and a second control end of a receive IO port of a receive data path.

[0102] In step S712, the link layer passes the control information to the transmit data path.

[0103] In step S713, the transmit data path uses the bypass mode to send control information to the opposite end chiplet.

[0104] When the core needs to send control information to the core at the other end to negotiate the link, the control information generated by the core can be passed by the link layer to the transmission data path (for example, the transmission data path of the link layer can pass the control information to the first input end of the transmission IO port), so that the transmission data path can use the bypass mode to send control information to the core at the other end (for example, the transmission IO port can output the control information received at the first input end through the output end to send the control information to the core at the other end).

[0105] In step S714, the receiving data path uses the bypass mode to pass the control information sent by the opposite end chiplet to the link layer.

[0106] Before establishing a link, the chip needs to receive control information sent by the chip at the opposite end, so the receiving data path can use the bypass mode to receive the control information sent by the chip at the opposite end and pass it to the link layer. For example, the first receiving end of the receiving IO port receives the control information sent by the chip at the opposite end and passes it to the receiving data path of the link layer.

[0107] In step S715, after the link is established, the link layer encodes the transmitted information according to the information type of the transmitted information to obtain the encoding result of the transmitted information.

[0108] In step S716, the link layer passes the transmission information and the encoding result of the transmission information to the transmission data path.

[0109] In step S717, the transmit data path uses the normal mode to send the transmit information and the encoding result of the transmit information to the opposite end chiplet.

[0110] After the link is established, the transmitting data path can send information in normal mode (for example, the transmitting IO port uses the information transmission channel from the second input end to the output end to send information), and the receiving data path can receive information in normal mode (for example, the receiving IO port uses the information transmission channel from the second receiving end to receive information).

[0111] When the chip has the need to send information, the link layer can pass the sending information to the transmission data path (for example, the sending data path of the link layer can pass the sending information to the second input end of the transmitting IO port); thereby, the transmitting data path can use the normal mode to send the sending information to the opposite chip (for example, the transmitting IO port can output the sending information received at the second input end through the output end to send the sending information to the opposite chip).

[0112] Furthermore, since after the link is established, both data information and control information are transmitted through the normal mode of the data path, the transmission information sent by the transmission data path may be data information or control information. Based on this, when the chiplet sends information to the chiplet at the opposite end, the embodiment of the present application provides a method for enabling the chiplet at the opposite end to distinguish whether the transmission information is data information or control information, and when the chiplet receives the reception information sent by the chiplet at the opposite end, it provides a method for distinguishing whether the reception information is data information or control information.

[0113] Combination Figure 7 As shown, when the core needs to send information to the peer core, the link layer can encode the information according to the information type of the information to obtain the encoding result of the information; thus, the link layer can pass the encoding result of the information to the transmission data path along with the information; the transmission data path can use the normal mode to send the information and the encoding result of the information to the peer core. Furthermore, the peer core can re-encode the information when receiving the information sent by the core, and confirm the type of information by comparing the re-encoding result with the received encoding result.

[0114] As an optional implementation, take the example of a core particle sending information to a peer core particle. Fig. 8A The flowchart of the method for distinguishing information types is shown as an example. The method can be executed by the protocol layer of the core particle. Fig. 8A , the process may include:

[0115] In step S810, after the link is established, the information to be sent is encoded according to the information type of the information to be sent using a coding algorithm corresponding to the information type to obtain a coding result of the information to be sent.

[0116] As an optional implementation, the link layer can use different encoding algorithms to encode the transmitted information based on the different information types of the transmitted information, so as to obtain the encoding result of the transmitted information. Taking the information types of the transmitted information as data information and control information as an example, the embodiment of the present application can set a first encoding algorithm corresponding to the data information and a second encoding algorithm corresponding to the control information; thus, if the transmitted information is data information, the link layer can use the first encoding algorithm corresponding to the data information to encode the transmitted information to obtain the encoding result of the transmitted information; if the transmitted information is control information, the link layer can use the second encoding algorithm corresponding to the control information to encode the transmitted information to obtain the encoding result of the transmitted information.

[0117] In step S811, the encoding result of the transmission information is transmitted to the transmission data path along with the transmission information.

[0118] As an optional implementation, after establishing a link, when the link layer passes the transmission information to the transmission data path, it can pass the encoding result of the transmission information along with the transmission information to the transmission data path. For example, the link layer can pass the transmission information and the encoding result of the transmission information to the second input end of the transmission IO port through the transmission data path. Thus, the transmission data path can use the normal mode to send the transmission information and the encoding result of the transmission information to the opposite end chip; for example, the transmission IO port can output the transmission information and the encoding result of the transmission information received at the second input end through the output end to send the transmission information and the encoding result of the transmission information to the opposite end chip.

[0119] It should be noted that any chip can send information according to Fig. 8A The information is encoded in the manner shown, so that the core particle receiving the information can distinguish the type of information through the encoding result.

[0120] Back to Figure 7 As shown, in step S718, the receiving data path uses the normal mode to pass the receiving information sent by the opposite end core particle and the encoding result of the receiving information to the link layer.

[0121] In step S719, the link layer re-encodes the received information to obtain a re-encoding result of the received information, and confirms the information type of the received information based on the re-encoding result and the encoding result of the received information.

[0122] After the link is established, the receiving data path can use the normal mode to receive the receiving information sent by the opposite end chiplet and pass it to the link layer. For example, the second receiving end of the receiving IO port receives the receiving information sent by the opposite end chiplet and passes it to the receiving data path of the link layer.

[0123] Furthermore, the received information received by the receiving data path may be data information or control information. Based on the mechanism for distinguishing information types provided in the embodiment of the present application, when the receiving data path obtains the received information, it can obtain the encoding result of the received information at the same time, and pass the received information and the encoding result of the received information to the link layer; thus, the link layer can confirm the information type of the received information by re-encoding the received information and matching the re-encoding result with the received encoding result.

[0124] As an optional implementation, take the case where a chip receives the receiving information sent by the other chip. Figure 8B Another method flow chart for distinguishing information types is shown as an example. This method flow chart can be executed by the protocol layer of the core particle. Figure 8B , the process may include:

[0125] In step S820, after the link is established, the receiving information transmitted by the receiving data path and the encoding result of the receiving information are obtained.

[0126] Since the core particle of the information sender needs to encode the information, the core particle can obtain the encoding result of the received information when obtaining the received information. Optionally, the receiving data path of the core particle can obtain the received information and the encoding result of the received information after establishing the link, and pass the encoding result of the received information to the link layer together with the received information, so that the link layer obtains the received information and the encoding result of the received information. For example, the second receiving end of the receiving IO port can pass the received information and the encoding result of the received information to the receiving data path of the link layer.

[0127] In step S821, the received information is re-encoded using a coding algorithm corresponding to at least one information type to obtain a re-encoding result of the received information corresponding to at least one information type.

[0128] The link layer can use encoding algorithms corresponding to different information types to re-encode the received information, so as to determine the information type of the received information by comparing the re-encoding results corresponding to the encoding algorithms of different information types with the encoding results of the received information.

[0129] Taking the example that the information type of received information is divided into data information and control information, the embodiment of the present application can set a first encoding algorithm corresponding to the data information and a second encoding algorithm corresponding to the control information; thus, the link layer can use the first encoding algorithm corresponding to the data information to re-encode the received information to obtain the re-encoding result of the first encoding algorithm; and, use the second encoding algorithm corresponding to the control information to re-encode the received information to obtain the re-encoding result of the second encoding algorithm.

[0130] In step S822, the information type of the received information is determined according to the re-encoding result of the received information corresponding to at least one information type and the encoding result of the received information.

[0131] The embodiment of the present application can compare the re-encoding result corresponding to at least one information type of the received information with the encoding result of the received information. If there is a re-encoding result that is consistent with the encoding result of the received information, the information type corresponding to the re-encoding result can be used as the information type of the received information; if there is no re-encoding information that is consistent with the encoding result of the received information, it means that an error occurred in the transmission process of the received information.

[0132] As an optional implementation, after the link layer re-encodes the received information using the first encoding algorithm corresponding to the data information, the re-encoding result of the first encoding algorithm can be compared with the encoding result of the received information. If the re-encoding result of the first encoding algorithm matches (for example, is consistent with) the encoding result of the received information, the received information is confirmed to be data information.

[0133] As an optional implementation, after the link layer re-encodes the received information using a second encoding algorithm corresponding to the control information, the link layer can compare the re-encoding result of the second encoding algorithm with the encoding result of the received information. If the re-encoding result of the second encoding algorithm matches the encoding result of the received information, the received information is confirmed to be control information.

[0134] If both the re-encoding result of the first encoding algorithm and the re-encoding result of the second encoding algorithm do not match the encoding result of the received information, the received information is erroneous during the transmission process.

[0135] As an optional implementation, the encoding algorithm used in the embodiment of the present application may be, for example, a CRC (Cyclic Redundancy Check) algorithm, and different information types may correspond to different CRC algorithms. Optionally, the first encoding algorithm corresponding to the data information may be, for example, a first CRC algorithm, and the first CRC algorithm may be regarded as a CRC algorithm used by the link layer for performing CRC check on the data information, which may be expressed as CRC / D. Optionally, the second encoding algorithm corresponding to the control information may be, for example, a second CRC algorithm, and the second CRC algorithm may be regarded as a CRC algorithm used by the link layer for performing CRC check on the control information, which may be expressed as CRC / C.

[0136] As an implementation example, Fig.9A The following is an exemplary diagram showing the implementation of differentiating information types: Fig.9A As shown, taking the case where the first core sends data information to the second core as an example, the first core can encode the data information using the CRC / D algorithm, so that the data information and the encoding result can be sent to the second core. After the second core receives the information and the encoding result, in order to distinguish whether the information is data information or control information, the received information can be re-encoded using the CRC / D algorithm and the CRC / C algorithm respectively; the second core detects that the re-encoding result of the CRC / D algorithm matches the received encoding result, while the re-encoding result of the CRC / C algorithm does not match the received encoding result, and it can be confirmed that the information received from the first core is data information, not control information. Further, if the second core detects that the re-encoding result of the CRC / D algorithm and the re-encoding result of the CRC / C algorithm do not match the received encoding result, it can be confirmed that the information is wrong during transmission.

[0137] It should be noted that after the link is established, the manner in which the core particle sends and receives data information can refer to the description of the corresponding part above, which will not be repeated here.

[0138] As an implementation example, Fig. 9B Another example diagram of differentiating information types is shown as follows: Fig. 9B As shown, taking the example of the first core sending control information to the second core, the first core can encode the control information using the CRC / C algorithm, so that the control information and the encoding result can be sent to the second core. After the second core receives the information and the encoding result, in order to distinguish whether the information is data information or control information, the received information can be re-encoded using the CRC / D algorithm and the CRC / C algorithm respectively; the second core detects that the re-encoding result of the CRC / C algorithm matches the received encoding result, while the re-encoding result of the CRC / D algorithm does not match the received encoding result, and it can be confirmed that the information received from the first core is control information, not data information. Further, if the second core detects that the re-encoding result of the CRC / C algorithm and the re-encoding result of the CRC / D algorithm do not match the received encoding result, it can be confirmed that the information is wrong during transmission.

[0139] In the case of multiplexing the data path to transmit control information, the embodiment of the present application can control the transmission of control information and data information based on the data path clock corresponding to the data path; that is, the transmission of control information and data information is controlled by the data path clock, for example, the control information and data information are transmitted in time-sharing based on the data path clock. Therefore, the embodiment of the present application can avoid the core grain using the sideband path clock of the sideband path, and reduce the clock network burden of the interconnection interface of the core grain.

[0140] For ease of understanding, let's take the example of a core particle with a data path and a sideband path in its physical layer. Fig. 10A The clock diagram of the core particle is shown as an example. Fig. 10A As shown, in a core having a data path and a sideband path, in the sending direction, the sideband path has an independent always-on sideband path clock, which is passed from the upper layer of the core to the link layer (e.g., the part of the link layer related to sideband control), and even to the physical layer (e.g., the sideband path of the physical layer); at the same time, in the sending direction, the data path (e.g., the transmit data path) has an independent always-on data path clock, which is passed from the upper layer of the core to the link layer (e.g., the transmit data path of the link layer), and even to the physical layer (e.g., the transmit data path of the physical layer). It can be seen that the sideband path requires an independent always-on sideband path clock, which increases the clock network burden of the interconnect interface of the core.

[0141] The embodiment of the present application transmits control information by multiplexing the data path, so that both control information and data information can be transmitted under the action of the data path clock, and avoid using the sideband path clock, thereby reducing the clock network burden of the interconnect interface of the core particle. As an implementation example, Fig. 10B Another clock example diagram of the core particle is shown as an example, combined with Fig. 10A and Fig. 10B As shown, in the embodiment of the present application, the core particle can omit the sideband path clock, and under the action of the data path clock, the transmission of data information and control information is controlled in time-sharing. Fig. 10B In the example, both the link layer and the physical layer work in one clock domain (ie, the data path clock), which enables the interconnection interface of the chip to reduce the burden brought by the sideband path clock.

[0142] In an optional implementation, the link layer may control the transmission of control information and data information in the sending direction based on the data path clock. Optionally, the control information and data information are transmitted in time-sharing based on the data path clock. For example, before establishing a link, in the sending direction, the link layer may control the transmission of control information under the action of the data path clock; after establishing a link, in the sending direction, the link layer may control the transmission of control information based on the control information transmission time of the data path clock, and control the transmission of data information based on the data information transmission time of the data path clock.

[0143] Optionally, the link layer may determine the control information transmission time and data information transmission time of the data path clock according to the operation state of the internal state machine. The internal state machine may correspond to different states at different working stages of the chiplet, including but not limited to chiplet configuration, testing, initialization, training, normal mode, low power mode, bandwidth switching and other states.

[0144] In the embodiment of the present application, the sideband path can be used as an optional configuration, so that when designing the core, the sideband path can be deleted in the core, or the sideband path can be retained. For example, when designing the core, the hardware configuration option of the core is added. If the core design has the requirement of interconnection through the sideband path, the design of the sideband path can be selected in the hardware configuration option of the core, so that the core design with the sideband path is obtained after synthesis; or the design of the sideband path can be not selected in the hardware configuration option of the core, so that the core design without the sideband path is obtained after synthesis.

[0145] If the sideband path is deleted in the core, the solution provided by the embodiment of the present application can be directly used to multiplex the data path to transmit control information before and after the link is established. If the sideband path is retained in the core, the sideband path can be set to a disabled state through software configuration information; thus, when the core responds to the software configuration information and sets the sideband path to be disabled, the core can use the solution provided by the embodiment of the present application to multiplex the data path to transmit control information before and after the link is established.

[0146] When designing a chiplet, whether the chiplet retains the sideband path or deletes the sideband path can be determined according to design requirements, and the present application embodiment does not limit this. The present application embodiment can provide a way to use the chiplet interconnection solution provided by the present application embodiment in both the case where the chiplet deletes the sideband path and retains the sideband path.

[0147] The embodiment of the present application also provides a core particle system, including multiple core particles, and the core particles can be the core particles provided in the embodiment of the present application.

[0148] An embodiment of the present application also provides a computer device, such as a server device or a terminal device, which may include the core particle system provided in an embodiment of the present application.

[0149] The use of a separate sideband path to transmit control information will increase the chiplet resource usage, power consumption, and clock network burden. In the embodiment of the present application, bypass mode and normal mode are set for the data path, so that the chiplet can reuse the data path to transmit control information before and after the link is established; further, the transmission control information and data information can be transmitted in a time-sharing manner. Therefore, in the embodiment of the present application, the sideband path can be used as an optional configuration in the chiplet, which brings at least the following advantages:

[0150] Save the hardware resources of the chip, save the bump of the chip, improve the bandwidth density of the chip, and the unit boundary length of the chip can accommodate more data paths; simplify the internal connection of the chip, save the winding resources within the chip; simplify the clock network of the chip and reduce the burden of the clock network.

[0151] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0152] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A core particle, characterized in that: include: Link layer and physical layer; The physical layer includes a data path, and the information transmission mode of the data path includes a bypass mode and a normal mode, and the transmission rate of the bypass mode is lower than that of the normal mode; wherein the normal mode is an information transmission mode corresponding to the link of the data path after the core particle establishes a link with the opposite core particle; The link layer is used to, before establishing a link, at least generate a bypass control signal and transmit the bypass control signal to the data path; The data path is used to transmit control information to the opposite end chiplet using a bypass mode based on the bypass control signal before establishing a link.

2. The core particle according to claim 1, characterized in that The data path is also used to disable the bypass mode and enable the normal mode after the link is established, and use the normal mode to transmit information with the opposite end chip.

3. The core particle according to claim 2, characterized in that The IO port in the data path has a first information transmission channel and a second information transmission channel; the first information transmission channel matches the bypass mode and is used to transmit control information to the opposite end chip before establishing a link; The second information transmission channel matches the normal mode and is used to transmit information to the opposite end chip after the link is established; the second information transmission channel is the information transmission channel between the IO port and the link after the link is established.

4. The core particle according to claim 3, characterized in that The data path includes a transmit data path; The link layer is also used to transmit control information sent to the peer chiplet to the transmission data path before establishing the link; The transmit data path is used to send control information to the opposite end chiplet using a bypass mode based on the bypass control signal and control information transmitted by the link layer before establishing the link.

5. The core particle according to claim 4, characterized in that After the link is established, the information transmitted between the corelet and the opposite corelet includes: the sending information sent by the corelet to the opposite corelet; The link layer is also used to, after the link is established, pass the transmission information to the transmission data path; The transmit data path is further used to disable the bypass mode and enable the normal mode after the link is established, and use the normal mode to send the transmission information transmitted by the link layer to the opposite end chiplet.

6. The core particle according to claim 5, characterized in that The link layer includes: control logic, and a transmit data path corresponding to the transmit data path; before establishing the link, the bypass control signal is transmitted to the transmit data path by the control logic; before establishing the link, the control information is transmitted to the transmit data path by the transmit data path; after establishing the link, the transmit information is transmitted to the transmit data path by the transmit data path.

7. The core particle according to claim 4 or 5, characterized in that The transmit data path includes a transmit IO port; the transmit IO port includes a first input terminal, a second input terminal, a first control terminal and an output terminal; wherein the information transmission channel from the first input terminal to the output terminal is a first information transmission channel that matches the bypass mode of the transmit IO port; and the information transmission channel from the second input terminal to the output terminal is a second information transmission channel that matches the normal mode of the transmit IO port.

8. The core particle according to claim 7, characterized in that Before establishing the link, the first control end receives a bypass control signal transmitted by the link layer to put the transmitting IO port in bypass mode; In bypass mode, the transmitting IO port enables the information transmission channel from the first input end to the output end; receiving control information transmitted by the link layer through the first input end, and outputting the control information received by the first input end to the opposite end chiplet through the output end; After the link is established, the transmitting IO port is in a normal mode, in which the transmitting IO port disables the first input end and enables an information transmission channel from the second input end to the output end; The sending information transmitted by the link layer is received through the second input end, and the sending information received by the second input end is sent to the opposite end chip through the output end.

9. The core particle according to claim 4 or 5, characterized in that The link layer is further used to, after establishing the link, encode the information to be sent according to the information type of the information to be sent using a coding algorithm corresponding to the information type to obtain a coding result of the information to be sent; and transmit the coding result of the information to a transmission data path; The encoding result of the transmission information is sent to the opposite end chiplet through the transmission data path along with the transmission information.

10. The core particle according to claim 9, characterized in that: The transmission information is divided into data information and control information; if the transmission information is data information, the link layer encodes the transmission information using a first encoding algorithm corresponding to the data information to obtain an encoding result of the transmission information; If the transmission information is control information, the link layer encodes the transmission information using a second encoding algorithm corresponding to the control information to obtain an encoding result of the transmission information.

11. The core particle according to claim 3, characterized in that The data path includes a receiving data path; the receiving data path is used to receive control information sent by the opposite end core particle using a bypass mode based on a bypass control signal transmitted by the link layer before establishing a link, and transmit the control information to the link layer.

12. The core particle according to claim 11, characterized in that After the link is established, the information transmitted between the corelet and the opposite corelet includes: reception information received by the corelet from the opposite corelet; The receiving data path is also used to, after the link is established, disable the bypass mode and enable the normal mode, use the normal mode to receive reception information sent by the opposite end chiplet, and pass the reception information to the link layer.

13. The core particle according to claim 12, characterized in that The link layer includes: control logic, and a receiving data path corresponding to the receiving data path; before establishing the link, the bypass control signal is transmitted to the receiving data path by the control logic; before establishing the link, the control information sent by the opposite end core particle is transmitted to the receiving data path by the receiving data path; after establishing the link, the receiving information is transmitted to the receiving data path by the receiving data path.

14. The core particle according to claim 12 or 13, characterized in that The receiving data path includes a receiving IO port; the receiving IO port includes a first receiving end, a second receiving end and a second control end; wherein the information transmission channel of the first receiving end is a first information transmission channel that matches the bypass mode of the receiving IO port; the information transmission channel of the second receiving end is a second information transmission channel that matches the normal mode of the receiving IO port.

15. The core particle according to claim 14, characterized in that Before establishing the link, the second control end receives a bypass control signal transmitted by the link layer to put the receiving IO port in bypass mode; In bypass mode, the receiving IO port enables the information transmission channel of the first receiving end, receives the control information sent by the opposite end chiplet through the first receiving end, and transmits it to the link layer; After the link is established, the receiving IO port is in a normal mode, in which the receiving IO port disables the information transmission channel of the first receiving end and enables the information transmission channel of the second receiving end; The receiving information sent by the opposite end core particle is received through the second receiving end, and is transmitted to the link layer.

16. The core particle according to claim 12 or 13, characterized in that The receiving data path is also used to receive the encoding result of the receiving information after the link is established, and pass the encoding result of the receiving information to the link layer together with the receiving information; The link layer is further used to re-encode the received information using a coding algorithm corresponding to at least one information type to obtain a re-encoding result of the received information corresponding to at least one information type; The information type of the received information is determined according to a re-encoding result of the received information corresponding to at least one information type and an encoding result of the received information.

17. The core particle according to claim 16, characterized in that The received information is divided into data information and control information; the encoding algorithm corresponding to the at least one information type includes: a first encoding algorithm corresponding to the data information, and a second encoding algorithm corresponding to the control information; After the link layer re-encodes the received information using the first encoding algorithm, if the re-encoding result of the first encoding algorithm matches the encoding result of the received information, then the received information is data information; After the link layer re-encodes the received information using the second encoding algorithm, if the re-encoding result of the second encoding algorithm matches the encoding result of the received information, then the received information is control information.

18. The core particle according to claim 1, characterized in that The link layer is also used to control the transmission of control information and data information based on a data path clock corresponding to the data path; the control information and data information are transmitted in time-sharing based on the data path clock.

19. The core particle according to claim 18, characterized in that Before establishing the link, the link layer controls the transmission of control information under the action of the data path clock; after establishing the link, the link layer controls the transmission of control information based on the control information transmission timing of the data path clock, and controls the transmission of data information based on the data information transmission timing of the data path clock.

20. The core particle according to claim 1, characterized in that The physical layer further includes a sideband path; the sideband path is configured to be disabled based on software configuration information.

21. A chip-particle interconnection method, characterized in that: Applied to the core particle, the method comprises: Before the core particle establishes a link with the opposite end core particle, at least a bypass control signal is generated; Based on the bypass control signal, control the data path of the core particle to be in bypass mode, so that the core particle transmits control information with the opposite end core particle through the bypass mode of the data path; The information transmission mode of the data path includes a bypass mode and a normal mode. The transmission rate of the bypass mode is lower than that of the normal mode. The normal mode is the information transmission mode corresponding to the data path and the link after the link is established.

22. The method according to claim 21, characterized in that Also includes: After the link is established, the bypass mode of the data path is disabled and the normal mode of the data path is enabled, so that the chiplet transmits information with the opposite chiplet through the normal mode of the data path.

23. The method according to claim 22, characterized in that Before establishing a link, the control information transmitted between the coregist and the opposite coregist includes: the control information sent by the coregist to the opposite coregist, and the control information received by the coregist from the opposite coregist; After the link is established, the information transmitted between the corelet and the opposite corelet includes: sending information sent by the corelet to the opposite corelet, and receiving information received by the corelet from the opposite corelet; Wherein, in the sending direction of the core grain sending information, the information is sent through the transmitting data path of the data path; and in the receiving direction of the core grain receiving information, the information is received through the receiving data path of the data path.

24. The method according to claim 23, characterized in that The method further comprises: After the link is established, the information to be sent is encoded according to the information type of the information to be sent using a coding algorithm corresponding to the information type to obtain a coding result of the information to be sent; the coding result of the information to be sent to the opposite end chiplet along with the information to be sent.

25. The method according to claim 24, characterized in that The transmitted information is divided into data information and control information; and according to the information type of the transmitted information, encoding the transmitted information using a coding algorithm corresponding to the information type, to obtain the coding result of the transmitted information includes: If the sent information is data information, encoding the sent information using a first encoding algorithm corresponding to the data information to obtain an encoding result of the sent information; If the transmission information is control information, the transmission information is encoded using a second encoding algorithm corresponding to the control information to obtain an encoding result of the transmission information.

26. The method according to claim 23, characterized in that The method further comprises: After the link is established, receiving the encoding result of the received information, the encoding result of the received information being received together with the received information; Re-encode the received information using a coding algorithm corresponding to at least one information type to obtain a re-encoding result of the received information corresponding to at least one information type; The information type of the received information is determined according to a re-encoding result corresponding to at least one information type of the received information and an encoding result of the received information.

27. The method according to claim 26, characterized in that The received information is divided into data information and control information; the encoding algorithm corresponding to the at least one information type includes: a first encoding algorithm corresponding to the data information, and a second encoding algorithm corresponding to the control information; The re-encoding the received information using a coding algorithm corresponding to at least one information type to obtain a re-encoding result of the received information corresponding to at least one information type includes: Re-encoding the received information using a first encoding algorithm to obtain a re-encoding result of the first encoding algorithm; and re-encoding the received information using a second encoding algorithm to obtain a re-encoding result of the second encoding algorithm; The determining the information type of the received information according to the re-encoding result corresponding to at least one information type of the received information and the encoding result of the received information comprises: If the re-encoding result of the first encoding algorithm matches the encoding result of the received information, determining that the received information is data information; If the re-encoding result of the second encoding algorithm matches the encoding result of the received information, it is determined that the received information is control information.

28. The method according to any one of claims 21 to 27, characterized in that: Also includes: Controlling the transmission of control information and data information based on a data path clock corresponding to the data path; The control information and data information are transmitted in time-sharing manner based on a data path clock.

29. The method according to claim 28, characterized in that The controlling the transmission of control information and data information based on a data path clock corresponding to the data path includes: Before establishing a link, the control information is transmitted under the action of the data path clock; After the link is established, the control information is controlled to be transmitted based on the control information transmission timing of the data path clock, and the data information is controlled to be transmitted based on the data information transmission timing of the data path clock.

30. The method according to claim 21, characterized in that The method further comprises: In response to the software configuration information, the sideband path of the chip is set to be disabled.

31. A core particle system, characterized in that: It comprises a plurality of core particles, wherein the core particles are the core particles as described in any one of claims 1-20.

32. A computer device, characterized in that: Comprising the core particle system as described in claim 31.

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