Overlay target design for improved target placement accuracy

Abstract

A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned by projecting optical radiation onto the semiconductor substrate through at least one mask using a projection system having a predefined resolution limit to produce an overlay target having a specified geometric form. The mask contains: target features having a target feature size no less than the predefined resolution limit in an arrangement corresponding to the specified geometric form of the overlay target; and assist features interleaved with the target features and having at least one assist feature size less than the predefined resolution limit.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 290,651, filed on December 17, 2021, which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to the fabrication of semiconductor devices, and in particular, to methods and target features for semiconductor circuit metrology. Background Art

[0004] Semiconductor circuits are typically manufactured using photolithographic methods. In the photolithographic process, a thin layer of a photosensitive polymer (photoresist) is deposited on a semiconductor substrate. The photoresist is patterned by an exposure system, typically including a scanner or stepper, which typically projects an image of a mask (also called a "photomask" or "reticle") onto the photoresist using ultraviolet (UV) or extreme ultraviolet (EUV) radiation. After patterning, the substrate is modified by methods such as etching and ion bombardment to change the material properties and / or morphology of the substrate, while the portions of the substrate covered by the photoresist are not affected.

[0005] Semiconductor circuit metrology is used to measure the properties of patterned photoresists, such as the topography and position of patterned features. The precise position of patterned features of photoresists relative to previously patterned process layers is critical to achieving high yields in photolithography processes. Any error (drift) in the registration of patterned photoresists relative to underlying process layers is called "overlay error". As an example, in a typical semiconductor circuit with a minimum line width (critical dimension, CD) of 10 to 14 nm (the so-called 10 nm design rule), the maximum permissible overlay error is 2 to 3 nm. In advanced cutting-edge semiconductor circuits, line widths are shrinking to 5 nm, with a concomitant reduction in the maximum permissible overlay error.

[0006] Overlay errors are typically measured using optical overlay metrology equipment (often referred to as optical overlay metrology tools) because optical radiation in visible and infrared wavelengths can penetrate photoresist layers and through dielectric layers beneath the photoresist. In addition, infrared wavelengths can penetrate semiconductor substrates (e.g., silicon), enabling through-substrate metrology. Overlay errors are measured from overlay targets positioned in the scribe lines (lines separating adjacent dies) of the semiconductor substrate and / or within the die.

[0007] Commonly used overlay metrology targets fall into two categories: scatterometry tools and imaging tools. Scatterometry tools such as the ATL100 from KLA Corporation (Milpitas, California, USA)TM A method for measuring an overlay error is provided by capturing a diffraction (scattering) image of a periodic target feature of an overlay target from an exit pupil of an objective of a metrology tool. The scattering image, which indicates the angular distribution of optical radiation scattered from the target feature, is processed to measure an overlay error.

[0008] Imaging tools (such as KLA's Archer TM series tools) for overlay targets (such as KLA's AIM TM The method uses an image analysis algorithm to locate the center of symmetry of the target feature in the process layer and the center of symmetry of the target feature in the photoresist layer. The overlay error is calculated based on the displacement between the centers of symmetry of the target features in the two layers.

[0009] The terms "optical radiation" and "light" as used in this specification and claims generally refer to any and all of visible, infrared, ultraviolet and extreme ultraviolet radiation. Summary of the invention

[0010] Embodiments of the present invention described below provide improved methods and systems for patterning overlay targets.

[0011] Therefore, according to an embodiment of the present invention, a method for semiconductor metrology is provided, comprising depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The method further comprises patterning the first and second film layers to produce an overlay target having a specified geometric form by projecting optical radiation onto the semiconductor substrate through at least one mask using a projection system having a predefined resolution limit. The mask contains: target features having a target feature size not less than the predefined resolution limit in an arrangement corresponding to the specified geometric form of the overlay target; and assist features interleaved with the target features and having at least one assist feature size less than the predefined resolution limit.

[0012] In the disclosed embodiment, the specified geometric form comprises a plurality of parallel equidistant bars. Alternatively, the specified geometric form comprises a box-in-box object.

[0013] In some embodiments, the target feature comprises a plurality of parallel linear segments oriented along a first direction, and the auxiliary target comprises a linear grating oriented along a second direction that is not parallel to the first direction. In the disclosed embodiments, the second direction is perpendicular to the first direction. Additionally or alternatively, the at least one mask further comprises circuit features having a predefined critical dimension, and the linear segments have respective widths equal to the predefined critical dimension. In the disclosed embodiments, the plurality of parallel linear segments are grouped together to define at least one bar, and the auxiliary features are disposed on both sides of the at least one bar. Further additionally or alternatively, the plurality of parallel linear segments are grouped together to define a plurality of parallel bar, and the auxiliary features are disposed between the plurality of parallel bar. In some embodiments, the linear grating of the auxiliary features has a pitch of less than 10 nm.

[0014] According to an embodiment of the present invention, there is also provided a mask for patterning a semiconductor wafer in a lithography projection system having a predefined resolution limit, wherein the mask comprises a transparent substrate and features disposed on the transparent substrate. The features comprise: a target feature having a target feature size not less than the predefined resolution limit in an arrangement corresponding to a specified geometric form of a superimposed target; and an auxiliary feature interleaved with the target feature and having at least one auxiliary feature size less than the predefined resolution limit.

[0015] The present invention will be more fully understood from the following detailed description of embodiments of the invention taken together with the accompanying drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic side view of an exposure system for patterning a photoresist layer on a semiconductor substrate according to an embodiment of the present invention;

[0017] Figure 2 is a schematic side view of an imaging metrology device according to an embodiment of the present invention;

[0018] Figure 3A is a schematic front view of a segmented stacking target according to an embodiment of the present invention;

[0019] Figure 3B is a method for patterning according to an embodiment of the present invention Figure 3A Schematic detailed view of a portion of a mask of a segmented bar in a superimposed target;

[0020] Figure 4A is a schematic front view of a segmented frame-in-frame superimposed target according to another embodiment of the present invention;

[0021] Figure 4Bis a method for patterning according to an embodiment of the present invention Figure 4A a schematic detailed view of a portion of a mask of a segmented bar in a superimposed target; and

[0022] Figure 5A and 5B Simulated graphs of aerial image amplitude without and with printing of a segmented mask of a sub-resolution assist target (SRAF) according to an embodiment of the present invention, respectively. DETAILED DESCRIPTION

[0023] Overview

[0024] The optical properties of overlay metrology tools known in the art place lower limits on the feature size and periodicity of overlay targets. For example, for an optical instrument with a numerical aperture (NA) of 0.9 coll ) and a light collecting optical device having a wavelength λ of 500 nm metr For optical radiation superposition metrology tools, the pitch P of periodic target features should exceed P = λ metr / NA coll ≈550nm. (In this specification, λ metr Used to denote the wavelength of an optical superposition metrology tool, while λ exp ) In order for the overlay target to have significant diffraction efficiency in this overlay metrology tool, the feature size of the target should be at least about 100 nm. Therefore, the pitch and feature size of the overlay target are much larger than the critical dimensions of semiconductor circuits (which are typically about 10 to 14 nm using current technology).

[0025] Because the size of the overlay target is much larger than the size of the circuit features, the target features in the lithography mask are segmented (e.g., divided) into linear segments whose sizes are compatible with the circuit features but cannot be resolved by the optics of the overlay metrology tool. Even so, the optical aberrations of the lithography system can still cause the target features to shift by an amount different from the amount experienced by the circuit features. This shift will cause an error in the measurement between the overlay error measured by the optical metrology system and the actual overlay error of the circuit features, called pattern placement error (PPE). The source of this PPE is the difference between the corresponding line widths of the extreme segments of the segmented target features. Due to residual optical aberrations of the exposure system, this difference can arise due to the differential shift between the so-called aerial image of the segment and the aerial image of the target feature as a whole. A typical value for the line width difference is about 1 nm, resulting in a PPE value of the same order of magnitude.

[0026] Embodiments described herein address this problem by interleaving sub-resolution assist features (SRAFs) with target features in the lithography mask. (In the background of this specification and in the claims, the term "interleaving" means that at least one SRAF is included between two adjacent target features and / or at least one target feature is included between two adjacent SRAFs.) The size of the SRAFs is below the resolution limit of the exposure system, and therefore, the SRAFs are not patterned in the photoresist layer on the wafer. However, interleaving the SRAFs with the target features reduces amplitude variations at the edges of the target features in the aerial image. Reducing these amplitude variations results in a reduction in the size difference between the extreme segments of the target feature and thus mitigates PPE.

[0027] In some embodiments, each SRAF comprises, for example, parallel equidistant lines, wherein the pitch of the lines in the SRAF is below the resolution limit of the exposure system. The lines of the SRAF may be oriented in a direction perpendicular to or otherwise non-parallel to the segments of the segmented target feature so as to avoid modulation and distortion of the aerial image of the segments. The inventors have found that the application of the SRAF to the segmented target feature reduces the typical size difference between the extreme segments from about 1 nm to about 0.1 nm, thus improving the accuracy of the optical overlay error metrology. The resolution limit may be different for each system. For example, for an immersion scanner with an illumination wavelength of 193 nm and a numerical aperture (NA) of about 1.4, pitches less than about 60 to 70 nm cannot be resolved. Mask manufacturing may also affect the minimum pitch size, which may have a limit of about 20 nm. Therefore, the resolution limit may include structures having a pitch greater than about 20 nm and less than about 60 nm, a pitch greater than about 20 nm and less than about 70 nm, or other unresolvable ranges depending on the system.

[0028] Thus, in the disclosed example, a first film layer is deposited on a semiconductor substrate and a second film layer is deposited on the first film layer. The first and second film layers are patterned by projecting optical radiation onto the semiconductor substrate through at least one mask to produce an overlay target having a specified geometric form using a lithographic projection system having a predefined resolution limit. The mask contains target features having a size not less than the predefined resolution limit in an arrangement corresponding to the specified geometric form of the overlay target. The mask further contains assist features, referred to herein as SRAFs, which are interleaved with the target features and have at least one assist feature size less than the predefined resolution limit. These assist features are particularly useful in reducing PPE, as explained above.

[0029] Patterning and metrology systems

[0030] Figure 1is a schematic side view of an exposure system 20 for patterning a photoresist layer 22 on a semiconductor substrate 24 (eg, a silicon wafer) in accordance with an embodiment of the present invention. The exposure system 20 is shown by way of example, and other kinds of exposure systems may alternatively be used.

[0031] Exposure system 20 (representing a scanner or stepper in simplified form) includes exposure light source 26, mask stage 28, projection optics 30, wafer stage 32, and exposure system controller 34. Semiconductor substrate 24 having one or more process layers 38 and photoresist layer 22 deposited over its top surface is positioned on wafer stage 32. The orientation of exposure system 20, as well as the orientation of items in the following figures, is referenced to Cartesian coordinates 40.

[0032] A mask 36 defining a pattern in photoresist layer 22 is positioned in mask stage 28. Mask 36 includes both patterns for forming features of electronic circuits and patterns for forming overlay targets, as will be described in detail below. As previously mentioned, these subsequent patterns include target features having a target feature size no less than a predefined resolution limit of system 20 and assist features having at least one assist feature size less than this resolution limit. Various embodiments of the present invention (e.g., Figure 3A / B and the embodiments shown in 4A / B) use masks with different features.

[0033] Exposure light source 26 emits optical radiation indicated by arrow 42 to illuminate mask 36. The optical radiation typically includes wavelengths in the UV or EUV spectral range. Although the emitted optical radiation in the figures is shown as uniform and collimated radiation, it may alternatively include radiation with different spatial and / or angular distributions.

[0034] Mask stage 28 includes actuators controlled by exposure system controller 34 that can move the stage (and therefore mask 36) linearly in the x, y, and z directions, as well as rotate the stage about the z-axis and tilt it about the x and y axes. Mask 36 typically includes a substrate (e.g., quartz) that is transparent to the optical radiation emitted by exposure light source 26, having a pattern formed on the substrate with a thin film of a suitable material to modulate the amplitude and / or phase of the optical radiation transmitted by the mask.

[0035] For simplicity, projection optics 30 is shown as a single lens, but typically includes multiple lenses and / or mirrors, whose positions and orientations can be controlled by exposure system controller 34 to obtain optimal optical performance. The resolution limit of projection optics 30, and therefore exposure system 20, is determined by the minimum line width (called critical dimension CD) that can be patterned by the exposure system. min ). This minimum line width is approximately min =k1×λ exp / NA proj Given, where k1 (often referred to as k1 factor) is a coefficient of the encapsulation process related factor and typically has a value of about 0.4. exp is the wavelength emitted by the exposure light source 26, and NA proj is the numerical aperture of the projection optics 30 .

[0036] Wafer stage 32 includes actuators controlled by exposure system controller 34 that can move the stage (and thus semiconductor substrate 24) in the x, y, and z directions, as well as rotate the stage about the z-axis.

[0037] An exposure system controller 34 is coupled to light source 26, mask stage 28, projection optics 30, and wafer stage 32. Controller 34 typically includes a programmable processor programmed with software and / or firmware to perform the functions described herein, along with suitable digital and / or analog interfaces for connecting to other elements of exposure system 20. Alternatively or in addition, controller 34 includes hardwired and / or programmable hardware logic circuitry that performs at least some of the functions of the controller. Although in Figure 1 Controller 34 is shown in FIG. 3 , but for simplicity, as a single monolithic functional block, when in reality the controller may include a plurality of interconnected control units having suitable interfaces for receiving and outputting the signals illustrated in the figure and described in the text.

[0038] For the purpose of patterning the photoresist layer 22, the exposure system controller 34 moves the wafer stage 32 under the projection optics 30 so that the photoresist layer 22 on the semiconductor substrate 24 is in a desired position and orientation relative to the optics. The exposure light source 26 emits optical radiation to illuminate the mask 36. The optical radiation impinging on the mask 36 is transmitted and / or diffracted by the mask and projected toward the projection optics 30, which focuses the radiation onto the photoresist layer 22, thereby exposing the photoresist. The spatial distribution of the intensity of the optical radiation illuminating the photoresist 22 is referred to as an "aerial image."

[0039] The exposed photoresist layer 22 is developed to remove the exposed pattern. The displacement between the overlay target features in the photoresist layer 22 and the corresponding target features previously formed in the underlying process layer 38 is measured to evaluate the overlay error between the photoresist layer 22 and the process layer 38 using an optical metrology tool, as will be described in detail below. If the overlay error complies with a predetermined tolerance, the process layer 38 is modified by methods such as etching and ion bombardment to change the material properties and / or morphology of the process layer, while the portion of the process layer covered by the remaining portion of the photoresist layer 22 is not affected.

[0040] Figure 2is a schematic side view of an imaging metrology apparatus 50 according to an embodiment of the present invention. The apparatus 50 is shown by way of example to illustrate a method of performing overlay error metrology using an overlay target patterned according to an embodiment of the present invention. Alternatively, such a target may be used in other kinds of metrology systems.

[0041] Imaging metrology apparatus 50 includes an imaging assembly 52, an illumination assembly 54, a metrology processor 56, and a stage 58 on which a semiconductor substrate (such as substrate 24 exposed by exposure system 20) is mounted. Imaging assembly 52 includes an NA coll , a cube beam splitter 62, and an imaging lens 64. The imaging assembly 52 further includes a two-dimensional sensor array 66, which includes, for example, a complementary metal oxide semiconductor (CMOS) detector having a two-dimensional array of pixels 68. The imaging lens 64 images the top surface of the semiconductor substrate 24 onto the sensor array 66. The illumination assembly 54 includes an emitting λ metr The imaging resolution of the metrology device 50 is limited by the wavelength λ metr and the characteristics of the imaging lens 64 and is typically about at least several hundred nanometers.

[0042] The stage 58 is positioned proximate the objective lens 60 and includes actuators controlled by the metrology processor 56 that can move the stage linearly in the x, y, and z directions, as well as rotate the stage about the z-axis. The semiconductor substrate 24 having the process layer 38 and the photoresist layer 22 deposited over its top surface is positioned on the stage 58. The photoresist layer 22 has been patterned by the exposure system 20, as described above.

[0043] The metrology processor 56 is coupled to the sensor array 66 and to the stage 58. The metrology processor 56 typically includes a programmable processor programmed with software and / or firmware to perform the functions described herein, along with suitable digital and / or analog interfaces for connecting to other elements of the apparatus 50. Alternatively or in addition, the processor 56 includes hardwired and / or programmable hardware logic circuits that perform at least some of the functions of the processor. Although in Figure 2 Processor 56 is shown in FIG. 5 , but for simplicity, as a single monolithic functional block; in reality, the processor may include a plurality of interconnected control units having appropriate interfaces for receiving and outputting the signals illustrated in the figure and described in the text.

[0044] To capture an image of a metrology target in the photoresist layer 22, the semiconductor substrate 24 is positioned on the stage 58 and the stage is moved so that the target is within the field of view (FOV) of the objective lens 60. The light source 70 projects a beam of optical radiation to a lens 72, which further projects the beam to a cube beam splitter 62. The beam splitter 62 reflects the beam into the objective lens 60, which projects the beam onto the semiconductor substrate 24, thereby illuminating the metrology target. The radiation impinging on the semiconductor substrate 24 is reflected back to the objective lens 60 and is further focused by the lens 64 onto the sensor array 66.

[0045] The metrology processor 56 captures and processes the images to measure the overlay error. Specifically, the processor 56 processes the images of the metrology target to find the corresponding centers of symmetry in both the x and y directions of the target features in the process layer and the photoresist layer. The two-dimensional displacement between the centers of symmetry is the overlay error.

[0046] Overlay target pattern and mask

[0047] Reference Figure 3A and 3B , which schematically illustrates details of a segmented overlay target 100 and a mask 200 for patterning the target 100 in a photoresist layer 22 according to an embodiment of the present invention.

[0048] Overlay Target 100 with AIM TM The target form includes a process layer 38 ( Figure 1 ) and four target features 104a, 104b, 104c and 104d formed in photoresist layer 22. Each of target features 104a, 104b, 104c and 104d includes four parallel equidistant segmented bars. The width of the linear segments making up each bar is compatible with the width of the circuit features but cannot be resolved by the overlay metrology tool. The specific features of target 100 are shown by example, and the principles of the present embodiment can be applied to other target geometries alternatively after appropriate modifications.

[0049] For example, target feature 104a includes bars 106a, 106b, 106c, and 106d, each of which is further segmented into seven linear segments 110a, 110b, 110c, 110d, 110e, 110f, and 110g. For clarity, the segmentation is not shown in the general view of target 100, but in inset 108. Thus, the general view of target 100 represents an image of the target that an optical metrology tool would capture. (Alternatively, the target feature may include a smaller or larger number of bars, and the bars may be segmented into a smaller or larger number of segments. AIM TMThe target may alternatively comprise an unsegmented bar.)

[0050] As previously mentioned, the typical width of the four bars in each of target features 102a-102d and 104a-104d is on the order of hundreds of nanometers in order to achieve resolution of an optical image of target 100 captured by an optical overlay metrology tool. An example of segmentation of three of the four bars (bars 106a, 106b, and 106c) of vertical target feature 104a is shown in inset 108. (The terms "vertical" and "horizontal" are used to refer to the y and x axes of Cartesian coordinates 40, respectively.) Bar 106a is segmented into vertical segments 110a, 110b, 110c, 110d, 110e, 110f, and 110g of equal width and spacing. The common width of segments 110a-110g is selected so as to be compatible with circuit features in mask 36 but cannot be obtained by an overlay metrology tool (e.g., Figure 2 The device 50 in FIG. 1 can be used to distinguish the segments, and an image of the collective features of the segments (bars 160a) can be captured by the tool. For example, the width of the segments can be selected to be 10 nm or 20 nm, or any other suitable value compatible with the circuit features, and the collective width of the segments forms an optically distinguishable bar.

[0051] Target features 104a-104d of target 100 are patterned in photoresist layer 22 by exposure system 20 through mask 200. (Target features 102a-102d of target 100 have been patterned in process layer 38 at a previous stage of the photolithography process using a suitable pattern in a different mask.) Mask 200 includes segmented vertical bar bars 202a, 202b, and 202c and is used to pattern segmented vertical bar bars 106a, 106b, and 106c in inset 108. For example, segmented bar bar 202a includes linear segments 204a, 204b, 204c, 204d, 204e, 204f, and 204g that pattern corresponding segments 110a, 110b, 110c, 110d, 110e, 110f, and 110g in segmented bar bar 106a.

[0052] In addition to including vertical segmented bars 202a, 202b, and 202c, mask 200 also includes SRAFs 206 staggered on both sides of the segmented bars. Each SRAF in the drawn example includes a linear grating including nine parallel equidistant bars 208 oriented in the horizontal direction (perpendicular to the vertical segmented bars). The vertical orientation is useful to avoid modulation and distortion of the aerial image of the segment. The width and spacing of the bars 208 of the SRAF 206 are selected so that they are below the resolution limit of the exposure system 20 and therefore, are not patterned in the photoresist layer 22. For example, the pitch of the bars 208 may be less than 10 nm (meaning that the width of the bars is less than 5 nm, which is below the resolution of the exposure system 20). However, as will be further described below, it reduces the amplitude of the aerial image between the segmented features and thus reduces the variation between the widths of the extreme segments 110a and 110g, typically reducing it to within 0.1 nm.

[0053] Reference Figure 4A and 4B , which schematically illustrates details of a segmented overlay target 300 and a mask 400 for patterning the target 300 in a photoresist layer 22 according to another embodiment of the present invention.

[0054] The stacking target 300 is a frame-in-frame target, which includes a Figure 1 ) and four segmented bar bars 304a, 304b, 304c and 304d formed in photoresist layer 22. Each bar in the drawn example is segmented into seven linear segments 308a, 308b, 308c, 308d, 308e, 308f and 308g. (The bars may alternatively be segmented into other numbers of segments. The bars of the box-box objects may alternatively be unsegmented.) The segments of the bars are compatible with circuit features in mask 400 but cannot be detected by an overlay metrology tool (e.g., device 50( Figure 2 ))Distinguish.

[0055] For clarity, the segments of bar 304 are not shown in the general view of target 300, but are in inset 306. Thus, the general view of target 300 is a schematic representation of an image that would be captured by an optical metrology tool, such as apparatus 50. Overlay error between process layer 38 and photoresist layer 22 is measured in apparatus 50 by capturing an image of target 300 and processing the image to find corresponding centers of symmetry in both the x and y directions of target features of the process layer and photoresist layer. The two-dimensional displacement between the centers of symmetry is the overlay error.

[0056] As previously described, the typical width of bars 302a-302d and 304a-304d is on the order of hundreds of nanometers in order to enable apparatus 50 to resolve optical images of target 300. An example of segmentation of bars is shown using the portion of bar 304d shown in inset 306. Bar 304d oriented in the vertical direction is segmented into linear segments 308a, 308b, 308c, 308d, 308e, 308f, 308g of equal width and spacing. The common width of segments 308a-308g is chosen to be compatible with circuit features but cannot be measured by overlay metrology tools such as apparatus 50( Figure 2 )) is distinguished, and an image of the collective features of the fragments (bar 304d) can be captured by the tool. Figure 3A ), the width of the segments can be chosen to be, for example, 10 nm or 20 nm, or any other suitable value that is compatible with the circuit features and forms an optically resolvable bar as a collection of segments.

[0057] Bars 304a-304d of target 300 are patterned in photoresist layer 22 by exposure system 20 through mask 400. (Bars 302a-302d of target 300 have been patterned in process layer 38 at a previous stage of the lithography process using a suitable pattern in a different mask.) Mask 400 includes vertical linear segments 402a, 402b, 402c, 402d, 402e, 402f, and 402g that pattern corresponding segments 308a, 308b, 308c, 308d, 308e, 308f, 308g in inset 306.

[0058] In addition to vertical segments 402a-402g, mask 400 also includes SRAFs 404a and 404g adjacent to respective segments 402a and 402g. Each SRAF includes a linear grating, which in the depicted example includes nine parallel equidistant bars 406 oriented in the horizontal direction (perpendicular to the segmented bars). Similar to SRAF 206 ( Figure 3B ), the width and spacing of bars 406 are selected so that they are below the resolution limit of exposure system 20 and, therefore, are not patterned into photoresist layer 22. However, as will be described in further detail below, they reduce the amplitude of the aerial image adjacent to extreme segments 308a and 308g and, therefore, reduce the variation between the widths of these extreme segments.

[0059] Figure 5A and 5B Simulated graphs 500 and 540 of aerial image amplitude and details of segmentation masks 502 and 542 without and with SRAF for patterning segmented bars, respectively, are shown according to an embodiment of the present invention. TMThe lithography simulation tool performs the simulation. Cartesian coordinates 40 are used as references for masks 502 and 542. Figure 5A , the y-axis ranges from 0.0 to 0.4.

[0060] like Figure 5A 500, mask 502 includes seven vertical bars 504a, 504b, 504c, 504d, 504e, 504f, and 504g with pitch P for patterning seven segments in photoresist layer 22 without SRAF. Graph 500 includes curve 506 showing the amplitude of an aerial image produced by exposure system 20 for exposing photoresist layer 22 using mask 502. Curve 506 is calculated along line 508 across mask 502 when projected onto photoresist layer 22, and contains seven valleys 510a, 510b, 510c, 510d, 510e, 510f, and 510g corresponding to the seven segments 504a, 504b, 504c, 504d, 504e, 504f, and 504g. Horizontal line 512 represents the patterning threshold of the photoresist development process, i.e., the amplitude of the aerial image above which the exposed photoresist becomes soluble. Thus, valleys 510a to 510g will form similar patterns to bars 304d ( Figure 4A ) has seven segments of a segmented bar with width W.

[0061] Since optical aberrations of an optical system (e.g., projection optics 30 in exposure system 20) are typically low at the center of an optical aperture and increase toward its edges, these aberrations tend to shift patterned features transmitted through the edges of the aperture more than patterned features transmitted through near the center. Thus, in this example, troughs 510a-510g are shifted in the x-direction relative to an aerial image of an overall segmented barbar whose width W is dominated by steep slopes 514a and 514b at either side of curve 506. Assuming that optical aberrations shift troughs 510a-510g in the positive x-direction, as shown by arrow 516, trough 510g moves closer to slope 514b, while trough 510a moves away from slope 514a, relative to the aerial image of the barbar. These shifts have the effect of narrowing trough 510g, but widening trough 510a, thus causing the segment patterned by trough 510g to be slightly narrower than the segment patterned by trough 510a. The resulting difference ΔCD between the widths of the extreme segments of the patterned segmented bar will result in an error in the measured overlay error due to the PPE.

[0062] like Figure 5B, mask 542 includes seven vertical bars 544a , 544b , 544c , 544d , 544e , 544f , and 544g having a pitch P for patterning seven segments in photoresist layer 22 . Figure 5B The y-axis in FIG. 5 ranges from 0.0 to 0.5. Unlike mask 502, mask 542 also includes two SRAFs 546, each of which includes nine parallel equidistant lines 548 oriented perpendicular to vertical bars 544a-544g in this example. Similar to mask 400, the width and spacing of lines 548 are selected so that they are below the resolution limit of exposure system 20 and, therefore, are not patterned into photoresist layer 22.

[0063] Similar to Figure 5A , graph 540 includes curve 550 showing the amplitude of an aerial image produced by exposure system 20 for exposing photoresist layer 22 using mask 542. Curve 550 is calculated along line 552 of segment 542 when projected onto photoresist layer 22, and similar to curve 506, it shows seven valleys 554a, 554b, 554c, 554d, 554e, 554f, and 554g corresponding to seven segments 544a, 544b, 544c, 544d, 544e, 544f, and 544g. Horizontal line 556 represents the patterning threshold of the photoresist development process, which is approximately the same value as horizontal line 512. Thus, similar to Figure 5A , valleys 554a to 554g will form seven segments of a segmented bar having a width W similar to bar 304d after photoresist development.

[0064] Similar to troughs 510a-510g, troughs 554a-554g are shifted due to optical aberrations of projection optics 30, as shown by arrow 558. However, SRAF 546 scatters part of the optical radiation exposing photoresist layer 22 away from regions adjacent to the segmented stripes, thereby reducing the amplitude of the aerial image outside troughs 510a-510g and reducing the aerial image amplitude slopes 560a and 560b adjacent to troughs 554a and 554g. (To understand the reduction in slopes 560a and 560b compared to slopes 514a and 514b, note the difference in the image amplitude scale between graphs 500 and 540.) Although the image amplitude is still sufficient to expose the photoresist layer 22 outside the valleys 554a to 554g, the effect of slopes 560a and 560b on the extreme valleys 554a and 554g is reduced, thereby reducing the variation ΔCD in the width between the extreme segments of the patterned bars and thereby reducing PPE.

[0065] It should be understood that the embodiments described above are cited by way of example, and the present invention is not limited to what has been shown and described in detail above. Specifically, the scope of the present invention includes both the combination and sub-combination of the various features described above, as well as changes and modifications thereof that will occur to those skilled in the art after reading the foregoing description and that are not disclosed in the prior art.

Claims

1. A method for semiconductor metrology, comprising: Depositing a first film layer on a semiconductor substrate and depositing a second film layer overlying the first film layer; and The first and second film layers are patterned to produce a superimposed target having a specified geometric form by projecting optical radiation onto the semiconductor substrate using a projection system with a predefined resolution limit through at least one mask, the at least one mask containing: target features having a target feature size no less than the predefined resolution limit in an arrangement corresponding to the specified geometric form of the superimposed target; and Assist features are interleaved with the target features and have at least one assist feature size that is less than the predefined resolution limit.

2. The method of claim 1, wherein the specified geometric form comprises a plurality of parallel equidistant bars. The method of claim 1 , wherein the specified geometric form comprises a box-in-box object.

4. The method of claim 1, wherein the target feature comprises a plurality of parallel linear segments oriented along a first direction, and wherein the assist feature comprises a linear grating oriented along a second direction that is non-parallel to the first direction. The method according to claim 4 , wherein the second direction is perpendicular to the first direction.

6. The method of claim 4, wherein the at least one mask further comprises circuit features having a predefined critical dimension, and wherein the linear segments have respective widths equal to the predefined critical dimension.

7. The method of claim 4, wherein the plurality of parallel linear segments are grouped together to define at least one bar, and wherein the assist features are disposed on both sides of the at least one bar.

8. The method of claim 7, wherein the plurality of parallel linear segments are grouped together to define a plurality of parallel bars, and wherein the assist features are disposed between the plurality of parallel bars.

9. The method of claim 4, wherein the linear grating of the assist features has a pitch less than 10 nm.

10. A mask for patterning a semiconductor wafer in a lithography projection system having a predefined resolution limit, the mask comprising: Transparent substrate; and Features disposed on the transparent substrate, the features comprising: target features having a target feature size no less than the predefined resolution limit in an arrangement corresponding to a specified geometric form of the superimposed target; and Assist features are interleaved with the target features and have at least one assist feature size that is less than the predefined resolution limit.

11. The mask of claim 10, wherein the specified geometric form comprises a plurality of parallel equidistant bars.

12. The mask of claim 10, wherein the specified geometric form comprises a box-in-box object.

13. The mask of claim 10, wherein the target features comprise a plurality of parallel linear segments oriented along a first direction, and wherein the assist features comprise linear gratings oriented along a second direction that is non-parallel to the first direction. The mask of claim 13 , wherein the second direction is perpendicular to the first direction.

15. The mask of claim 13, wherein the features on the transparent substrate further comprise circuit features having a predefined critical dimension, and wherein the linear segments have respective widths equal to the predefined critical dimension.

16. The mask of claim 13, wherein the plurality of parallel linear segments are grouped together to define at least one barbar, and wherein the assist features are disposed on both sides of the at least one barbar.

17. The mask of claim 16, wherein the plurality of parallel linear segments are grouped together to define a plurality of parallel bars, and wherein the assist features are disposed between the plurality of parallel bars.

18. The mask of claim 13, wherein the linear grating of the assist features has a pitch less than 10 nm.

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