latches, flip-flops and chips

Abstract

The application provides a latch, a flip-flop and a chip, relates to the field of digital circuits, and can reduce the number of transistors in the flip-flop. The latch comprises a signal input end, a signal output end, a control signal end, a first voltage end, a second voltage end, a pull-up circuit and a pull-down circuit. Wherein, the transistors in the latch are all N-type field effect transistors. The pull-up circuit is connected with the first voltage end and the signal output end. The pull-up circuit is configured to pull up the voltage of the signal output end according to the voltage of the first voltage end. The pull-down circuit is connected with the signal input end, the control signal end, the signal output end and the second voltage end. The pull-down circuit is configured to pull down the voltage of the signal output end according to the voltage of the second voltage end under the signal control of the control signal end and the signal input end.

Description

Technical Field

[0001] This application relates to the field of digital circuits, and more particularly to a latch, a flip-flop, and a chip. Background Technology

[0002] In digital logic chips, flip-flops (FFs) occupy 50% of the total area of ​​the digital logic circuit. Reducing the area overhead of flip-flops is crucial for the miniaturization and performance improvement of digital logic chips.

[0003] In traditional flip-flops using CMOS (complementary metal oxide semiconductor) technology, the number of transistors is approximately 18. Therefore, if the number of transistors required for CMOS can be reduced, the area required for the flip-flop can be effectively reduced. Summary of the Invention

[0004] This application provides a latch, a flip-flop, and a chip. The flip-flop is formed using an NFET-based latch, which can reduce the number of transistors in the flip-flop.

[0005] This application provides a latch, including a signal input terminal, a signal output terminal, a control signal terminal, a first voltage terminal, a second voltage terminal, a pull-up circuit, and a pull-down circuit. The transistors in the latch are all N-channel field-effect transistors (NFETs). The pull-up circuit is connected to the first voltage terminal and the signal output terminal; the pull-up circuit is configured to pull up the voltage of the signal output terminal based on the voltage of the first voltage terminal. The pull-down circuit is connected to the signal input terminal, the control signal terminal, the signal output terminal, and the second voltage terminal. The pull-down circuit is configured to pull down the voltage of the signal output terminal based on the voltage of the second voltage terminal under the control of the signals from the control signal terminal and the signal input terminal.

[0006] In this case, both the pull-up and pull-down circuits in the latch use NFETs. The pull-up circuit outputs the high-level voltage of the first voltage terminal to the signal output terminal, thus pulling up the voltage of the signal output terminal. The pull-down circuit controls the signal input terminal and outputs the low-level voltage of the second voltage terminal to the signal output terminal, thus pulling down the voltage of the signal output terminal and latching the signal.

[0007] In some possible implementations, the pull-up circuit includes a first resistor. One end of the first resistor is connected to a first voltage terminal, and the other end of the first resistor is connected to a signal output terminal.

[0008] In some possible implementations, the pull-up circuit includes a first NFET; the first NFET is a depletion-mode NFET; the first terminal of the first NFET is connected to a first voltage terminal, and the gate and second terminal of the first NFET are both connected to the signal output terminal. When the first NFET is a depletion-mode NFET, the threshold voltage (V) of the first NFET... th The value is less than zero, thus ensuring that the first NFET remains on.

[0009] In some possible implementations, the pull-up circuit includes a first NFET; the first NFET is an enhancement-mode NFET; the first terminal and gate of the first NFET are both connected to a first voltage terminal, and the second terminal of the first NFET is connected to a signal output terminal. When the first NFET is an enhancement-mode NFET, the threshold voltage (V) of the first NFET... th The value is greater than zero, thus ensuring that the first NFET remains on.

[0010] In some possible implementations, the pull-up circuit includes a first NFET; the first NFET includes a first gate and a second gate; the first gate and the first terminal of the first NFET are both connected to a first voltage terminal, and the second gate and the second terminal of the first NFET are both connected to a signal output terminal. In this case, the first NFET is turned on under the control of a high-level voltage at the first voltage terminal, and outputs the high-level voltage at the first voltage terminal to the signal output terminal; the high-level voltage at the signal output terminal forms positive feedback to the second gate of the first NFET, further turning on the first NFET, thereby rapidly increasing the potential at the signal output terminal.

[0011] In some possible implementations, the pull-down circuit includes a second NFET, a third NFET, and a first capacitor. The first gate of the second NFET is connected to the control signal terminal, the first terminal of the second NFET is connected to the signal input terminal, and the second terminal of the second NFET is connected to the first node. The first gate of the third NFET is connected to the first node, the first terminal of the third NFET is connected to the signal output terminal, and the second terminal of the third NFET is connected to the second voltage terminal. The first terminal of the first capacitor is connected to the first node, and the second terminal of the first capacitor is connected to the second voltage terminal. In this case, the second NFET can be turned on and off by controlling the signal at the control signal terminal, and the signal at the signal input terminal can be transmitted to the gate of the third NFET; and the first capacitor connected to the gate of the third NFET can store the signal at the signal input terminal. When the voltage input at the signal input terminal is a high level voltage (i.e., logic "1"), the third NFET turns on and outputs a low level voltage from the second voltage terminal (such as ground) to the signal output terminal; at the same time, due to the presence of the first capacitor, even when the second NFET is off, the high level potential stored in the first capacitor can still maintain the third NFET on, that is, signal latching is achieved.

[0012] In some possible implementations, the second NFET also includes a second gate; the second gate of the second NFET is connected to a control signal terminal.

[0013] In some possible implementations, the third NFET also includes a second gate; the second gate of the third NFET is connected to the first node.

[0014] This application provides a latch, including a signal input terminal, a signal output terminal, a control signal terminal, a first voltage terminal, a second voltage terminal, a pull-up circuit, and a pull-down circuit. All transistors in the latch are NFETs. The pull-up circuit is connected to the signal input terminal, the signal control terminal, the first voltage terminal, and the signal output terminal. The pull-up circuit is configured to pull up the voltage of the signal output terminal based on the voltage of the first voltage terminal, under the signal control of the control signal terminal and the signal input terminal. The pull-down circuit is connected to the signal output terminal and the second voltage terminal. The pull-down circuit is configured to pull down the voltage of the signal output terminal based on the voltage of the second voltage terminal.

[0015] In this case, both the pull-up and pull-down circuits in the latch use NFETs. The pull-down circuit outputs the low-level voltage of the second voltage terminal to the signal output terminal to pull down the voltage of the signal output terminal. The pull-up circuit is controlled by the control signal terminal and the signal input terminal to output the high-level voltage of the first voltage terminal to the signal output terminal to pull up the voltage of the signal output terminal and realize signal latching.

[0016] In some possible implementations, the pull-down circuit includes a first resistor; one end of the first resistor is connected to a second voltage terminal, and the other end of the first resistor is connected to a signal output terminal.

[0017] In some possible implementations, the pull-down circuit includes a first NFET; the first NFET is a depletion-mode NFET; the gate and first terminal of the first NFET are both connected to a second voltage terminal, and the second terminal of the first NFET is connected to a signal output terminal. When the first NFET is a depletion-mode NFET, the threshold voltage (V) of the first NFET a1 is... th The value is less than zero, thus ensuring that the first NFET remains on.

[0018] In some possible implementations, the pull-down circuit includes a first NFET; the first NFET is a depletion-type NFET; the first NFET includes a first gate and a second gate; the first gate, the second gate, and the first terminal of the first NFET are all connected to a second voltage terminal, and the second terminal of the first NFET is connected to a signal output terminal. When the first NFET is a depletion-type NFET, the threshold voltage (V) of the first NFET... th If the value is less than zero, it ensures that the first NFET is always in the ON state.

[0019] In some possible implementations, the pull-up circuit includes a second NFET, a third NFET, and a first capacitor. The first gate of the second NFET is connected to the control signal terminal, the first terminal of the second NFET is connected to the signal input terminal, and the second terminal of the second NFET is connected to the first node. The first gate of the third NFET is connected to the first node, the first terminal of the third NFET is connected to the first voltage terminal, and the second terminal of the third NFET is connected to the signal output terminal. The first terminal of the first capacitor is connected to the first node, and the second terminal of the first capacitor is connected to the second voltage terminal. In this case, by controlling the second NFET to turn it on and off through the signal at the control signal terminal, the signal at the signal input terminal can be transmitted to the gate of the third NFET; and the first capacitor connected to the gate of the third NFET can store the signal at the signal input terminal. When the voltage input to the signal input terminal is a high-level voltage (i.e., logic "1"), the third NFET turns on, outputting the high-level voltage at the first voltage terminal to the signal output terminal; due to the presence of the first capacitor, even when the second NFET is off, the high-level potential stored in the first capacitor can still maintain the third NFET on, that is, signal latching is achieved.

[0020] In some possible implementations, the second NFET also includes a second gate; the second gate of the second NFET is connected to a control signal terminal.

[0021] In some possible implementations, the third NFET also includes a second gate; the second gate of the third NFET is connected to the first node.

[0022] This application embodiment also provides a trigger, including a first latch and a second latch; both the first latch and the second latch are latches provided in any of the aforementioned possible implementations; the signal output terminal of the first latch is connected to the signal input terminal of the second latch.

[0023] Compared to the approximately 18 transistors in a traditional flip-flop using CMOS technology, the number of NFETs in the flip-flop provided in some embodiments of this application is only 6 (i.e., 6T structure); even when the flip-flop uses an inverter with 2 transistors (FETs), the number of transistors in the flip-flop is only 8 (i.e., 8T structure), which means that the flip-flop provided in the embodiments of this application can significantly reduce the number of transistors.

[0024] This application also provides a chip including a digital logic circuit; the digital logic circuit includes a latch as provided in any of the aforementioned possible implementations.

[0025] In some possible implementations, latches can be integrated into the chip in subsequent processes to meet the chip's requirements for three-dimensional monolithic stacking technology, thereby reducing chip area, lowering chip power consumption, and improving chip performance.

[0026] In some possible implementations, the chip further includes a substrate and a first device layer and a second device layer disposed on the substrate. The second device layer is located on the side of the first device layer facing away from the substrate, and the first and second device layers are electrically connected. A CMOS transistor is disposed in the first device layer. The NFETs in the latch are oxide semiconductor field-effect transistors, and the NFETs in the latch are distributed in the second device layer.

[0027] By configuring the digital logic circuit of the chip, using the flip-flops and / or latches provided in the embodiments of this application, and configuring the NFETs in the flip-flops and / or latches to be N-type oxide semiconductor field-effect transistors, the temperature conditions for chip fabrication in the back-end process can be met. In this way, the first device layer can be fabricated using CMOS technology in the front-end process (FEOL), and the second device layer can be fabricated in the back-end process (BEOL). That is, the digital logic circuit is integrated with the back-end process of the chip, which meets the requirements of the chip for three-dimensional single-unit stacking technology, reduces the chip area, reduces the chip power consumption, and improves the chip performance.

[0028] This application also provides an electronic device, which includes a printed circuit board and a chip as provided in any of the aforementioned possible implementations; the chip is electrically connected to the printed circuit board. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of a latch provided in an embodiment of this application;

[0030] Figure 2 Schematic diagrams of four different pull-up circuits provided in the embodiments of this application;

[0031] Figure 3 This is a schematic diagram of a pull-down circuit provided in an embodiment of this application;

[0032] Figure 4 This is a schematic diagram of a pull-down circuit provided in an embodiment of this application;

[0033] Figure 5 This is a schematic diagram of the structure of a latch provided in an embodiment of this application;

[0034] Figure 6 for Figure 5 Simulation results of the latch;

[0035] Figure 7 This is a schematic diagram of the structure of a latch provided in an embodiment of this application;

[0036] Figure 8 Schematic diagrams of three different pull-down circuits provided in the embodiments of this application;

[0037] Figure 9 This is a schematic diagram of a pull-up circuit provided in an embodiment of this application;

[0038] Figure 10 This is a schematic diagram of a pull-up circuit provided in an embodiment of this application;

[0039] Figure 11 This is a schematic diagram of the structure of a latch provided in an embodiment of this application;

[0040] Figure 12 A schematic diagram of a trigger structure provided in an embodiment of this application;

[0041] Figure 13 for Figure 12 Simulation results of the trigger;

[0042] Figure 14 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Words such as "connected," "linked," etc., are used to express communication or interaction between different components and may include direct connection or indirect connection through other components. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as "upper," "lower," "left," and "right," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0045] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0046] This application provides a flip-flop (FF) that can be formed by connecting a set of latches (i.e., two latches) in series, and the transistors in the latches are all NFETs (n-channel field effect transistors). Compared to the approximately 18 transistors required in a CMOS flip-flop, the flip-flop provided in this application significantly reduces the number of transistors.

[0047] It should be noted that, for the NFETs used in the embodiments of this application, some NFETs can be single-gate structures (i.e., having one gate), and some NFETs can be dual-gate structures (i.e., having two gates, a first gate and a second gate), as detailed in the relevant description below. Of course, it is understood that, in addition to the gate, an NFET also includes a first terminal and a second terminal, one of which is the source and the other is the drain; the first and second terminals can be interchanged. The following embodiments of this application use the first terminal as the source and the second terminal as the drain for illustrative purposes.

[0048] The following provides two different types of latches (latch one and latch two), and uses latch one and latch two to illustrate the setting of the trigger provided in the embodiments of this application.

[0049] Latch 1

[0050] like Figure 1 As shown, latch 10 includes: a pull-up network (PUN), a pull-down network (PDN), an input terminal (Input), an output terminal (Output), a control signal terminal (CLK), a first voltage terminal, and a second voltage terminal. The first voltage terminal can be a high-level voltage terminal, such as a power supply terminal V. DD The second voltage terminal can be a low-level voltage terminal, such as the ground terminal GND, but is not limited to this. The following embodiments all use the first voltage terminal as the high-level voltage terminal and the power supply terminal V. DD The explanation will be based on the example where the second voltage terminal is the ground terminal GND.

[0051] refer to Figure 1 As shown, in this latch 10, the pull-up circuit PUN is connected to the first voltage terminal (V). DD The signal output terminal (Output) is connected. The pull-up circuit (PUN) is configured to operate according to the first voltage terminal (V). DD The voltage at the Output terminal of the voltage pull-up signal.

[0052] For illustrative purposes only, please refer to the following: Figure 1 and Figure 2 As shown in (a), in some possible implementations, the pull-up circuit PUN may include a first resistor R1. One end of the first resistor R1 is connected to a first voltage terminal (V). DD The first resistor R1 is connected to the signal output terminal Output.

[0053] For illustrative purposes only, please refer to the following: Figure 1 and Figure 2 As shown in (b), in some possible implementations, the pull-up circuit PUN may include a first NFET a1. This first NFET a1 is a depletion-type NFET. The source of the first NFET a1 is connected to a first voltage terminal (V... DD The first NFET a1 is connected to the signal output terminal Output, with both its gate and drain connected.

[0054] It can be understood here that, in the case where the first NFET a1 is a depletion-mode NFET, the threshold voltage (V) of the first NFET a1 is... th ) is less than zero, thus in the adoption Figure 2 In the circuit connection method of (b), it can be ensured that the first NFET a1 remains in the on state.

[0055] For illustrative purposes only, please refer to the following: Figure 1 and Figure 2 As shown in (c), in some possible implementations, the pull-up circuit PUN may include a first NFET. This first NFET is an enhancement-mode NFET; wherein both the source and gate of the first NFET are connected to a first voltage terminal (V). DD The drain of the first NFET is connected to the signal output terminal Output. Figure 2 (Not shown in the image) Connection.

[0056] It can be understood here that, when the first NFET a1 is an enhancement-mode NFET, the threshold voltage (V) of the first NFET a1 is... th ) is greater than zero, thus in the adoption Figure 2 In the circuit connection method of (c), it can be ensured that the first NFET a1 remains in the on state, so as to keep the first voltage terminal (V) DD The voltage output signal output terminal Output is pulled up.

[0057] For illustrative purposes only, please refer to the following: Figure 1 and Figure 2As shown in (d), in some possible implementations, the pull-up circuit PUN may include a first NFET a1. This first NFET a1 includes a first gate g1 and a second gate g2, meaning the first NFET is a dual-gate structure. The first gate g1 and source of the first NFET a1 are both connected to a first voltage terminal (V). DD The second gate g2 and drain of the first NFET a1 are both connected to the signal output terminal Output. Figure 2 (Not shown in the image). Among them, Figure 2 In diagram (d), the example is only illustrated with the first gate g1 as the top gate and the second gate g2 as the back gate. In other possible implementations, the first gate g1 can be the back gate and the second gate g2 can be the top gate. The following embodiments are all illustrated with the first gate g1 as the top gate and the second gate g2 as the back gate.

[0058] refer to Figure 2 As shown in (d), when the first NFET a1 adopts a dual-gate structure, the first NFET a1 at the first voltage terminal (V DD Under the control of a high-level voltage, the first NFET a1 is turned on, and the first voltage terminal (V) is opened. DD The high-level voltage of the signal output terminal is output to the signal output terminal Output, which pulls up the voltage of the signal output terminal Output; at the same time, the high-level voltage of the signal output terminal Output will form positive feedback to the second gate g2 of the first NFET a1, further turning on the first NFET a1, thereby rapidly increasing the potential of the signal output terminal Output.

[0059] Additionally, refer to Figure 1 As shown, in this latch 10, the pull-down circuit PDN is connected to the signal input terminal Input, the control signal terminal CLK, the signal output terminal Output, and the second voltage terminal (GND). The pull-down circuit PDN is configured to pull down the voltage of the signal output terminal Output according to the voltage of the second voltage terminal (GND) under the signal control of the control signal terminal CLK and the signal input terminal Input.

[0060] As shown in the illustration, among some possible implementation methods, see reference. Figure 1 and Figure 3As shown, the pull-down circuit PDN may include a second NFET a2, a third NFET a3, and a first capacitor C1. The gate of the second NFET a2 is connected to the control signal terminal CLK, the source of the second NFET a2 is connected to the signal input terminal Input, and the drain of the second NFET a2 is connected to the first node N1. The gate of the third NFET a3 is connected to the first node N1, the source of the third NFET a3 is connected to the signal output terminal Output, and the drain of the third NFET a3 is connected to the second voltage terminal (GND). The first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second voltage terminal (GND). It should be noted that the first capacitor C1 can be composed of the gate capacitor of the third NFET a3, a separately designed load capacitor, or a combination thereof.

[0061] In this scenario, by controlling the turn-on and turn-off of the second NFET a2 via the signal at the control signal terminal CLK, the signal at the signal input terminal Input can be transmitted to the gate of the third NFET a3. Furthermore, the first capacitor C1, connected to the gate of the third NFET a3, can store the signal at the signal input terminal Input. When the voltage input at the signal input terminal Input is a high level (i.e., logic "1"), the third NFET a3 turns on and outputs a low level voltage from the second voltage terminal (GND) to the signal output terminal Output, thus pulling down the voltage at Output. Simultaneously, due to the presence of the first capacitor C1, even when the second NFET a2 is off, the high-level potential stored in the first capacitor C1 can still maintain the third NFET a3 on, thus achieving signal latching.

[0062] Of course, as an alternative implementation method, such as Figure 4 As shown, the second NFET a2 can be a dual-gate structure, that is, the second NFET a2 includes two gates (a first gate and a second gate), and both gates of the second NFET a2 are connected to the control signal terminal CLK.

[0063] Similarly, in some possible implementations, the third NFET a3 can also be a dual-gate structure, that is, the third NFET a3 includes two gates (a first gate and a second gate), and both gates of the third NFET a3 are connected to the first node N1.

[0064] Figure 4This illustration only uses the example of both the second NFET a2 and the third NFET a3 being dual-gate structures. In other possible implementations, one of the second NFET a2 and the third NFET a3 can be a dual-gate structure, while the other can be a single-gate structure. For example, the second NFET a2 is a dual-gate structure (see reference). Figure 4 The third NFET a3 is a single-gate structure (see reference). Figure 3 For example, the second NFET a2 is a single-gate structure (see reference). Figure 3 The third NFET a3 has a dual-gate structure (see reference). Figure 4 ).

[0065] Figure 5 The image shows a latch-10 with a 3T (i.e., 3 NFETs) structure; in this latch-10, the pull-up circuit PUN adopts... Figure 2 In the circuit structure of (d), the pull-down circuit PDN adopts... Figure 3 The circuit structure in it. Figure 6 yes Figure 5 The simulation results of latch-10 are as follows. The following is combined with... Figure 5 and Figure 6 The working principle of the latch-10 provided in this application is briefly illustrated.

[0066] refer to Figure 5 and Figure 6 When the clock signal input to the control signal terminal CLK is a high-level voltage, the second NFET a2 turns on, and the high-level voltage (i.e., logic "1") input to the signal input terminal Input is transmitted to the gate of the third NFET a3, charging the first capacitor C1. The third NFET a3 then turns on, outputting the low-level voltage of the second voltage terminal (GND) to the signal output terminal Output, thus pulling down the voltage at the signal output terminal Output. At this time, the resistance of the pull-down circuit PDN is much smaller than the resistance of the pull-up circuit PUN. When the clock signal input to the control signal terminal CLK turns low, the second NFET a2 turns off, and the high-level voltage previously stored in the first capacitor C1 keeps the third NFET a3 on, continuously outputting the low-level voltage of the second voltage terminal (GND) to the signal output terminal Output, thus achieving signal latching. When the clock signal input to the control signal terminal CLK is a high-level voltage and the signal input terminal Input is a low-level voltage (i.e., logic "0"), the second NFET a2 is turned on and the third NFET a3 is turned off. At this time, the resistance of the pull-down circuit PDN is much greater than the resistance of the pull-up circuit PUN, and the first voltage terminal (V DD The high-level voltage of the signal output terminal Output is output through the first NFET a1 to pull up the voltage of the signal output terminal Output.

[0067] Latch 2

[0068] like Figure 7 As shown, the latch 20 includes: a pull-up circuit PUN, a pull-down circuit PDN, a signal input terminal Input, a signal output terminal Output, a control signal terminal CLK, and a first voltage terminal (V). DD ), second voltage terminal (GND).

[0069] refer to Figure 7 As shown, in this latch 20, the pull-down circuit PDN is connected to the signal output terminal Output and the second voltage terminal (GND). The pull-down circuit PDN is configured to pull down the voltage of the signal output terminal Output based on the voltage of the second voltage terminal (GND).

[0070] As shown in the illustration, among some possible implementation methods, see reference. Figure 7 and Figure 8 As shown in (a), the pull-down circuit PDN described above may include a first resistor R1. One end of the first resistor R1 is connected to the second voltage terminal (GND), and the other end of the first resistor R1 is connected to the signal output terminal Output.

[0071] As shown in the illustration, among some possible implementation methods, see reference. Figure 7 and Figure 8 As shown in (b), the pull-down circuit PDN described above may include a first NFET a1. The first NFET a1 is a depletion-type NFET. The gate and source of the first NFET a1 are both connected to the second voltage terminal (GND), and the drain of the first NFET a1 is connected to the signal output terminal Output.

[0072] It can be understood here that, in the case where the first NFET a1 is a depletion-mode NFET, the threshold voltage (V) of the first NFET a1 is... th ) is less than zero, thus in the adoption Figure 8 In the circuit connection method of (b), it can be ensured that the first NFET a1 remains in the on state so as to pull down the voltage output signal output terminal Output of the second voltage terminal (GND).

[0073] As shown in the illustration, among some possible implementation methods, see reference. Figure 7 and Figure 8As shown in (c), the aforementioned pull-down circuit PDN may include a first NFET a1. This first NFET a1 is a depletion-type NFET, and it includes a first gate g1 and a second gate g2, i.e., it is a dual-gate structure. The first gate g1, the second gate g2, and the source of the first NFET a1 are all connected to the second voltage terminal (GND), and the drain of the first NFET a1 is connected to the signal output terminal Output. When the first NFET a1 is a depletion-type NFET, the threshold voltage (V) of the first NFET a1 is... th If the value is less than zero, it ensures that the first NFET a1 remains on, thereby pulling down the voltage output of the second voltage terminal (GND) at the Output terminal. Figure 8 (c) is only an illustration of the example where the first gate g1 is the top gate and the second gate g2 is the back gate. In other possible implementations, the first gate g1 can be the back gate and the second gate g2 can be the top gate.

[0074] Additionally, refer to Figure 7 As shown, in this latch 20, the pull-up circuit PUN is connected to the signal input terminal Input, the control signal terminal CLK, and the first voltage terminal (V). DD The signal output terminal (Output) is connected. This pull-up circuit (PUN) is configured to, under the control of the control signal terminal (CLK) and the signal input terminal (Input), adjust according to the first voltage terminal (V). DD The voltage at the Output terminal of the voltage pull-up signal.

[0075] As shown in the illustration, among some possible implementation methods, see reference. Figure 7 and Figure 9 As shown, the pull-up circuit PUN may include a second NFET a2, a third NFET a3, and a first capacitor C1. The gate of the second NFET a2 is connected to the control signal terminal CLK, the source of the second NFET a2 is connected to the signal input terminal Input, and the drain of the second NFET a2 is connected to the first node N1. The gate of the third NFET a3 is connected to the first node N1, and the source of the third NFET a3 is connected to the first voltage terminal (V). DD The drain of the third NFET a3 is connected to the signal output terminal (Output). The first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second voltage terminal (GND). It should be noted that the first capacitor C1 can be composed of the gate capacitor of the third NFET a3, a separately designed load capacitor, or a combination thereof.

[0076] In this case, by controlling the turn-on and turn-off of the second NFET a2 through the signal at the control signal terminal CLK, the signal at the signal input terminal Input can be transmitted to the gate of the third NFET a3; and the first capacitor C1 connected to the gate of the third NFET a3 can store the signal at the signal input terminal Input. When the voltage input at the signal input terminal Input is a high level voltage (i.e., logic "1"), the third NFET a3 turns on, transmitting the signal at the first voltage terminal (V... DD The high-level voltage of the first capacitor C1 is output to the signal output terminal Output to pull up the voltage of the signal output terminal Output. Due to the presence of the first capacitor C1, even when the second NFET a2 is turned off, the high-level potential stored in the first capacitor C1 can still maintain the third NFET a3 on, that is, the signal is latched.

[0077] Of course, as an alternative implementation method, such as Figure 10 As shown, the second NFET a2 can be a dual-gate structure, that is, the second NFET a2 includes two gates (a first gate and a second gate), and both gates of the second NFET a2 are connected to the control signal terminal CLK.

[0078] Similarly, in some possible implementation methods, such as Figure 10 As shown, the third NFET a3 can also be a dual-gate structure, that is, the third NFET a3 includes two gates (a first gate and a second gate), and both gates of the third NFET a3 are connected to the first node N1.

[0079] Figure 10 This illustration only uses the example of both the second NFET a2 and the third NFET a3 being dual-gate structures. In other possible implementations, one of the second NFET a2 and the third NFET a3 can be a dual-gate structure, while the other can be a single-gate structure. For example, the second NFET a2 is a dual-gate structure (see reference). Figure 10 The third NFET a3 is a single-gate structure (see reference). Figure 9 For example, the second NFET a2 is a single-gate structure (see reference). Figure 9 The third NFET a3 has a dual-gate structure (see reference). Figure 10 ).

[0080] Figure 11 The image shows a latch 20 with a 3T (i.e., 3 NFETs) structure; in this latch 20, the pull-up circuit PUN adopts... Figure 9 The circuit structure, the pull-down circuit PDN adopts Figure 8 The circuit structure in (b) is shown below. Figure 11The working principle of latch 20 provided in this application will be briefly explained.

[0081] refer to Figure 11 As shown, when the clock signal input to the control signal terminal CLK is a high-level voltage (i.e., logic "1"), the second NFET a2 is turned on. The high-level voltage input to the signal input terminal Input is transmitted to the gate of the third NFET a3 and charges the first capacitor C1. The third NFET a3 is then turned on, and the first voltage terminal (V... DD The high-level voltage of the first NFET (a2) is output to the signal output terminal (Output) to pull up the voltage at the Output terminal. At this time, the resistance of the pull-up circuit (PUN) is much smaller than the resistance of the pull-down circuit (PDN). When the clock signal input at the control signal terminal (CLK) turns low, the second NFET (a2) turns off, and the high-level voltage previously stored in the first capacitor (C1) keeps the third NFET (a3) ​​on, thus turning on the first voltage terminal (V... DD The high-level voltage of the control signal terminal CLK is continuously output to the signal output terminal Output. When the clock signal input at the control signal terminal CLK is a high-level voltage and the signal input terminal Input is a low-level voltage (i.e., logic "0"), the second NFET a2 is turned on and the third NFET a3 is turned off. At this time, the resistance of the pull-down circuit PDN is much smaller than the resistance of the pull-up circuit PUN. The low-level voltage of the second voltage terminal (GND) is output to the signal output terminal Output through the first NFET a1 to pull down the voltage of the signal output terminal Output.

[0082] The trigger proposed in the embodiments of this application will be described below in conjunction with the aforementioned latches (such as 10 and 20).

[0083] like Figure 12 As shown, the trigger F provided in this embodiment may include two latches (a first latch A1 and a second latch A2). The first latch A1 may also be called the master latch, and the second latch A2 may also be called the slave latch. The two latches (A1 and A2) can each employ any of the aforementioned latch types (such as 10 and 20). The signal output terminal Output of the first latch A1 is connected to the signal input terminal Input of the second latch A2 (corresponding to...). Figure 12 The input terminal of the first latch A1 (Input) serves as the input terminal D of the flip-flop F, and the output terminal of the second latch A2 (Output) serves as the output terminal Q of the flip-flop F.

[0084] It should be noted that, Figure 12This illustration is merely illustrative, using the example of both the first latch A1 and the second latch A2 employing the aforementioned latch 10, but this application is not limited to this. For example, in some possible implementations, both the first latch A1 and the second latch A2 may employ the aforementioned latch 20. Furthermore, in some possible implementations, one of the first latch A1 and the second latch A2 may employ the aforementioned latch 10, and the other may employ the aforementioned latch 20.

[0085] Furthermore, it should be noted that the circuit structures of the first latch A1 and the second latch A2 can be exactly the same or different; this application does not impose any restrictions on this. For example, as Figure 12 As shown, in some possible implementations, the two latches 10 used by the flip-flop F can have the same circuit structure; for example, in other possible implementations, the two latches 10 used by the flip-flop F can have different circuit structures.

[0086] Figure 13 yes Figure 12 The simulation results of the trigger F in the model; where, Figure 12 The signal input to the control signal terminal CLK1 of the first latch A1 is: Figure 13 The CLK signal in the second latch A2, the control signal input to CLK2 is... Signal; CLK signal and The signal is a set of inverted clock signals.

[0087] Combination Figure 12 and Figure 13 As shown, when the signal input to the control signal terminal CLK1 of the first latch A1 is a high-level voltage, the control signal input to the control signal terminal CLK2 of the second latch A2 is a low-level voltage (i.e., CLK = 1). The input signal at input terminal D of flip-flop F is transmitted to terminal S through the first latch A1. However, due to... At this time, the output state of the second latch A2 is independent of the output at the S terminal. When the signal input to the control signal terminal CLK1 of the first latch A1 becomes a low-level voltage (i.e., CLK = 0), When the CLK signal transitions from a high level to a low level (i.e., the negative CLK edge, or the falling edge of the clock signal), the signal at the input D of the flip-flop F can be output to the output Q. This means the flip-flop achieves falling-edge triggering (i.e., negative-edge-triggered FF).

[0088] Of course, in some other possible implementations, the input signals of the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2 can be interchanged, that is, the input of the control signal terminal CLK2 of the second latch A2 can be changed. Figure 13 The CLK signal in the first latch A1 is the control signal input CLK1. Signal. In this case, the flip-flop can achieve rising edge triggering (i.e., positive-edge-triggered FF), that is, the input signal at the input terminal D of the flip-flop F can only be output to the output terminal Q when the clock signal changes from a low level to a high level.

[0089] For a set of inverted clock signals input to the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2, in some possible implementations, an inverter can be used to invert the CLK signals to obtain... The signals are used to satisfy the signal requirements of the control signal terminal CLK1 of the first latch A1 and the control signal terminal CLK2 of the second latch A2 in the above-mentioned trigger.

[0090] This application does not limit the specific configuration of the inverter described above. For example, in some possible implementations, an inverter formed by an NFET can be used, allowing the inverter to be fabricated using the same process as a flip-flop. As another example, in some possible implementations, a CMOS inverter can be used; in practice, the configuration can be selected as needed.

[0091] It is understood that, compared to the approximately 18 transistors in a traditional flip-flop using CMOS technology, the flip-flop provided in this application embodiment has only 6 NFETs (i.e., a 6T structure); in some embodiments where the flip-flop uses an inverter with 2 transistors (FETs), the number of transistors is only 8 (i.e., an 8T structure), which means that the flip-flop provided in this application embodiment can significantly reduce the number of transistors.

[0092] It should be noted that the latch provided in this application embodiment is not limited to the application in the above-mentioned trigger. Depending on actual needs, the latch provided in this application embodiment can also be applied in other logic function devices.

[0093] This application also provides a chip in which the logic function devices in the digital logic circuit can be the aforementioned flip-flops and / or latches.

[0094] In some chips, flip-flops occupy 50% of the area of ​​the entire digital logic circuit. In this case, when using the flip-flops provided in the embodiments of this application, the chip area overhead can be significantly reduced, which is more conducive to chip miniaturization and performance improvement.

[0095] Furthermore, regarding the fabrication of the flip-flops and / or latches provided in the embodiments of this application, in some possible implementations, the NFET in the flip-flops and / or latches provided in the embodiments of this application can be an N-type oxide semiconductor (OS) field-effect transistor, that is, the channel layer of the NFET is made of oxide semiconductor material. In other possible implementations, the NFET in the flip-flops and / or latches provided in the embodiments of this application can be fabricated using low-temperature polycrystalline silicon (LTPS) technology, that is, the channel layer of the NFET is made of polycrystalline silicon material.

[0096] Taking chip fabrication as an example, the back-end of line (BEOL) processes of chips cannot meet the high-temperature fabrication requirements of CMOS technology, resulting in incompatibility between digital logic circuits and BEOL processes. This limits the chip's need for three-dimensional single-unit stacking technology. Furthermore, LTPS technology suffers from complex processes, high costs, significant fluctuations in device electrical characteristics, and poor uniformity, making it difficult to meet the requirements of circuit design and large-scale integration. In contrast, the NFETs in the flip-flops and / or latches provided in this application can be N-type oxide semiconductor field-effect transistors, thereby meeting the temperature requirements for chip fabrication in the back-end of line processes. Based on this, in some possible implementations, the logic functional devices such as the aforementioned flip-flops and / or latches can be integrated into the back-end of the chip, thereby meeting the chip's requirements for three-dimensional single-unit stacking technology, reducing chip area, lowering chip power consumption, and improving chip performance.

[0097] Indicative, such as Figure 14 As shown, this application embodiment provides a chip, which includes a substrate 100 and a first device layer 101 and a second device layer 102 disposed on the substrate 100. The second device layer 102 is located on the side of the first device layer 101 away from the substrate 100, and the first device layer 101 and the second device layer 102 are electrically connected. Hintly, the first device layer 101 and the second device layer 102 can be electrically connected through metal microvias.

[0098] The first device layer 101 contains CMOS transistors (complementary metal-oxide-semiconductor field-effect transistors). The digital logic circuits in this chip include flip-flops and / or latches provided in the aforementioned embodiments. The NFETs in the flip-flops and / or latches are all N-type oxide semiconductor field-effect transistors and are distributed in the second device layer 202.

[0099] In this case, the first device layer 101 can be fabricated using CMOS technology in the front end of line (FEOL) process, and then the second device layer 102 can be fabricated in the back end of line (BEOL) process; this achieves compatibility between digital logic circuits and the back end of line process, thereby meeting the chip's requirements for three-dimensional single-unit stacking technology.

[0100] In addition, this application embodiment also provides an electronic device, which includes a printed circuit board (PCB) and a chip as described above; the chip is electrically connected to the PCB.

[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A latch, characterized in that, It includes signal input terminal, signal output terminal, control signal terminal, first voltage terminal, second voltage terminal, pull-up circuit, and pull-down circuit; The transistors in the latch are all N-type field-effect transistors (NFETs). The pull-up circuit is connected to the first voltage terminal and the signal output terminal; the pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal; The pull-down circuit is connected to the signal input terminal, the control signal terminal, the signal output terminal, and the second voltage terminal. The pull-down circuit is configured to pull down the voltage of the signal output terminal according to the voltage of the second voltage terminal under the signal control of the control signal terminal and the signal input terminal.

2. The latch according to claim 1, characterized in that, The pull-up circuit includes a first resistor; one end of the first resistor is connected to the first voltage terminal, and the other end of the first resistor is connected to the signal output terminal. Alternatively, the pull-up circuit includes a first NFET; the first NFET is a depletion-type NFET; the first terminal of the first NFET is connected to the first voltage terminal, and the gate and the second terminal of the first NFET are both connected to the signal output terminal; Alternatively, the pull-up circuit includes a first NFET; the first NFET is an enhancement-mode NFET; The first terminal and gate of the first NFET are both connected to the first voltage terminal, and the second terminal of the first NFET is connected to the signal output terminal. Alternatively, the pull-up circuit includes a first NFET; the first NFET includes a first gate and a second gate; the first gate and the first electrode of the first NFET are both connected to the first voltage terminal, and the second gate and the second electrode of the first NFET are both connected to the signal output terminal.

3. The latch according to claim 1 or 2, characterized in that, The pull-down circuit includes a second NFET, a third NFET, and a first capacitor; The first gate of the second NFET is connected to the control signal terminal, the first electrode of the second NFET is connected to the signal input terminal, and the second electrode of the second NFET is connected to the first node; The first gate of the third NFET is connected to the first node, the first electrode of the third NFET is connected to the signal output terminal, and the second electrode of the third NFET is connected to the second voltage terminal; The first terminal of the first capacitor is connected to the first node, and the second terminal of the first capacitor is connected to the second voltage terminal.

4. The latch according to claim 3, characterized in that, The second NFET also includes a second gate; the second gate of the second NFET is connected to the control signal terminal.

5. The latch according to claim 3 or 4, characterized in that, The third NFET also includes a second gate; the second gate of the third NFET is connected to the first node.

6. A latch, characterized in that, It includes signal input terminal, signal output terminal, control signal terminal, first voltage terminal, second voltage terminal, pull-up circuit, and pull-down circuit; The transistors in the latch are all NFETs; The pull-up circuit is connected to the signal input terminal, the control signal terminal, the first voltage terminal, and the signal output terminal; the pull-up circuit is configured to pull up the voltage of the signal output terminal according to the voltage of the first voltage terminal under the signal control of the control signal terminal and the signal input terminal. The pull-down circuit is connected to the signal output terminal and the second voltage terminal; the pull-down circuit is configured to pull down the voltage of the signal output terminal according to the voltage of the second voltage terminal.

7. The latch according to claim 6, characterized in that, The pull-down circuit includes a first resistor; one end of the first resistor is connected to the second voltage terminal, and the other end of the first resistor is connected to the signal output terminal. Alternatively, the pull-down circuit includes a first NFET; the first NFET is a depletion-type NFET; the gate and first terminal of the first NFET are both connected to the second voltage terminal, and the second terminal of the first NFET is connected to the signal output terminal; Alternatively, the pull-down circuit includes a first NFET; the first NFET is a depletion-type NFET; the first NFET includes a first gate and a second gate; the first gate, the second gate, and the first terminal of the first NFET are all connected to the second voltage terminal, and the second terminal of the first NFET is connected to the signal output terminal.

8. The latch according to claim 6 or 7, characterized in that, The pull-up circuit includes a second NFET, a third NFET, and a first capacitor; The first gate of the second NFET is connected to the control signal terminal, the first electrode of the second NFET is connected to the signal input terminal, and the second electrode of the second NFET is connected to the first node; The first gate of the third NFET is connected to the first node, the first terminal of the third NFET is connected to the first voltage terminal, and the second terminal of the third NFET is connected to the signal output terminal. The first terminal of the first capacitor is connected to the first node, and the second terminal of the first capacitor is connected to the second voltage terminal.

9. The latch according to claim 8, characterized in that, The second NFET also includes a second gate; the second gate of the second NFET is connected to the control signal terminal.

10. The latch according to claim 8 or 9, characterized in that, The third NFET also includes a second gate; the second gate of the third NFET is connected to the first node.

11. A trigger, characterized in that, It includes a first latch and a second latch; both the first latch and the second latch are latches as described in any one of claims 1-10; The signal output terminal of the first latch is connected to the signal input terminal of the second latch.

12. A chip, characterized in that, Including digital logic circuits; The digital logic circuit includes a latch as described in any one of claims 1-10.

13. The chip according to claim 12, characterized in that, The latch is integrated into the subsequent process.

14. An electronic device, characterized in that, It includes a printed circuit board and a chip as described in claim 12 or 13; the chip is electrically connected to the printed circuit board.

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