Testing methods, apparatus, systems, equipment, and media for computing fast link devices

Abstract

This application discloses a testing method, apparatus, system, device, and medium for computing fast link devices, relating to the field of computer technology. The performance testing system for computing fast link devices includes a host, a computing fast link device connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host. The method includes: obtaining performance indicators corresponding to basic test items based on data transmission between different components; wherein the components include a host, a computing fast link device, and a high-speed peripheral device interconnect bus standard device; comparing the performance indicators corresponding to different basic test items to generate performance test results for the computing fast link device. This application achieves comprehensive performance testing of computing fast link devices in various scenarios.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a testing method, apparatus, system, device, and medium for a computing fast link device. Background Technology

[0002] CXL (Compute Express Link) is a high-performance, low-latency interconnect technology used to connect processors, accelerators, and memory devices. CXL Type 3 devices are a group of memory modules that provide persistent, volatile, or combined memory.

[0003] Due to the lack of real physical devices, current methods for obtaining the performance characteristics of CXL devices include simulating and physically implementing CXL type3 devices. Using the access performance of remote numa nodes to approximate the performance may not accurately represent the performance of CXL devices. In addition, the physical device implementation of CXL is limited to type3, which cannot systematically reflect the performance of CXL devices in various scenarios.

[0004] Therefore, how to perform performance testing on computing fast link devices in various scenarios is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a performance testing method, apparatus, device, and medium for computing fast link devices, enabling comprehensive performance testing of computing fast link devices in various scenarios.

[0006] To achieve the above objectives, this application provides a performance testing method for a computing fast link device, applied to a performance testing system for computing fast link devices. The performance testing system includes a host, computing fast link devices connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host. The method includes:

[0007] The performance indicators corresponding to the basic test items are obtained based on the data transmission between different components. The components include the host, the fast computing link device, and the high-speed peripheral interconnect bus standard device. The basic test items include any one or a combination of any of the following: the fast computing link device accessing its own memory; the high-speed peripheral interconnect bus standard device accessing its own memory; the first fast computing link device accessing the memory of the second fast computing link device; the fast computing link device accessing the memory of the high-speed peripheral interconnect bus standard device; the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device; the host accessing the memory of the fast computing link device; the host accessing the memory of the high-speed peripheral interconnect bus standard device; the fast computing link device accessing the memory of the host; the high-speed peripheral interconnect bus standard device accessing the memory of the host; and the first host accessing the memory of the second host.

[0008] The performance metrics corresponding to the different basic test items are compared to generate the performance test results of the computing fast link device.

[0009] Wherein, the fast computing link device accessing its own memory includes: when the fast computing link device is connected to the host through different fast computing links and the fast computing link device has different control modes and different bias modes, the computing unit in the fast computing link device accesses memory of different memory types in the fast computing link device;

[0010] The high-speed peripheral device interconnect bus standard device accessing its own memory includes: the computing unit in the high-speed peripheral device interconnect bus standard device accessing its own memory.

[0011] Wherein, the first computing fast link device accessing the memory of the second computing fast link device includes: when the first computing fast link device is connected to the host through different computing fast links and the second computing fast link device has different control modes and different bias modes, the first computing fast link device accesses the memory of the second computing fast link device.

[0012] The access to the memory of the high-speed peripheral interconnect bus standard device by the computing fast link device includes: when the computing fast link device and the host are connected via different computing fast links and the computing fast link device is in a different control mode, the computing fast link device accesses the high-speed peripheral interconnect bus standard device.

[0013] The host accessing the memory of the computing fast link device includes: the host accessing the memory of the computing fast link device when the computing fast link device is in different control modes.

[0014] Wherein, the fast computing link device accessing the host's memory includes: the fast computing link device accessing the host's memory through a fast computing link;

[0015] The high-speed peripheral device interconnect bus standard device accessing the host's memory includes: the high-speed peripheral device interconnect bus standard device accessing the host's memory through the high-speed peripheral device interconnect bus standard.

[0016] The performance metrics include latency and / or bandwidth.

[0017] The comparison of performance metrics corresponding to different basic test items includes:

[0018] The performance metrics of the computing units in the computing fast link device accessing the device memory managed by the host in the computing fast link device are compared in host-biased mode and device-biased mode.

[0019] The comparison of performance metrics corresponding to different basic test items includes:

[0020] The performance metrics of the computing units in the computing fast link device accessing the device memory managed by the host in the computing fast link device are compared under different control modes.

[0021] The comparison of performance metrics corresponding to different basic test items includes:

[0022] Compare the performance metrics of the computing units in the computing fast link device accessing the device memory managed by the host in the computing fast link device and the device private memory.

[0023] The comparison of performance metrics corresponding to different basic test items includes:

[0024] The performance metrics of the first computing fast link device accessing the memory of the second computing fast link device are compared when the second computing fast link device is in a different control mode.

[0025] The comparison of performance metrics corresponding to different basic test items includes:

[0026] Compare the performance metrics of the first high-speed computing link device accessing the host-managed device memory in the second high-speed computing link device with the performance metrics of the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device.

[0027] The comparison of performance metrics corresponding to different basic test items includes:

[0028] The performance metrics of the first high-speed computing link device accessing the memory of the second high-speed computing link device via memory copying are compared with the performance metrics of the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device.

[0029] The comparison of performance metrics corresponding to different basic test items includes:

[0030] The performance metrics of the first fast computing link device accessing the memory of the second fast computing link device under different control modes are compared.

[0031] The comparison of performance metrics corresponding to different basic test items includes:

[0032] Comparing the performance metrics of the host accessing the host-managed device memory in the computing fast link device under different control modes.

[0033] The comparison of performance metrics corresponding to different basic test items includes:

[0034] Compare the performance metrics of the host accessing the host-managed device memory in the computing fast link device with the performance metrics of the host accessing the memory of the high-speed peripheral interconnect bus standard device.

[0035] The comparison of performance metrics corresponding to different basic test items includes:

[0036] Compare the performance metrics of the host accessing the device memory managed by the host in the computing fast link device with the performance metrics of the first host accessing the memory of the second host.

[0037] Specifically, the host accesses the memory of the computing fast link device by using memory access instructions without temporary storage and / or storing and writing back memory access instructions;

[0038] The host accesses the memory of the high-speed peripheral interconnect bus standard device via load / store memory access instructions in the form of memory-mapped ports.

[0039] The step of comparing the performance metrics corresponding to different basic test items to generate the performance test results of the computing fast link device includes:

[0040] The performance indicators corresponding to different basic test items under different influencing factors are compared to generate the performance test results of the computing fast link device; wherein, the influencing factors include any one or a combination of any of the following: number of memory access threads, access method, whether they belong to the same non-consistent memory access node, and data volume; the access method includes sequential access and random access.

[0041] To achieve the above objectives, this application provides a performance testing apparatus for a computing fast link device, applied to a performance testing system for computing fast link devices. The performance testing system for computing fast link devices includes a host, computing fast link devices connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host. The apparatus includes:

[0042] The acquisition module is used to acquire performance indicators corresponding to basic test items based on data transmission between different components; wherein, the components include the host, the fast computing link device, and the high-speed peripheral device interconnect bus standard device, and the basic test items include any one or any combination of any of the following: the fast computing link device accessing its own memory, the high-speed peripheral device interconnect bus standard device accessing its own memory, the first fast computing link device accessing the memory of the second fast computing link device, the fast computing link device accessing the memory of the high-speed peripheral device interconnect bus standard device, the first high-speed peripheral device interconnect bus standard device accessing the memory of the second high-speed peripheral device interconnect bus standard device, the host accessing the memory of the fast computing link device, the host accessing the memory of the high-speed peripheral device interconnect bus standard device, the fast computing link device accessing the memory of the host, the high-speed peripheral device interconnect bus standard device accessing the memory of the host, and the first host accessing the memory of the second host;

[0043] The comparison module is used to compare the performance indicators corresponding to different basic test items in order to generate the performance test results of the computing fast link device.

[0044] To achieve the above objectives, this application provides a performance testing system for computing fast link devices, used to perform the performance testing method for computing fast link devices as described above;

[0045] The performance testing system for the computing fast link device includes a host, a computing fast link device connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host.

[0046] To achieve the above objectives, this application provides an electronic device, comprising:

[0047] Memory, used to store computer programs;

[0048] A processor, used to execute the computer program to implement the steps of the performance testing method for a fast computing link device as described above.

[0049] To achieve the above objectives, this application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the performance testing method for the computing fast link device described above.

[0050] As can be seen from the above scheme, the performance testing method for a computing fast link device provided in this application is applied to a performance testing system for computing fast link devices. The performance testing system for computing fast link devices includes a host, a computing fast link device connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host. The method includes: obtaining performance indicators corresponding to basic test items based on data transmission between different components; wherein, the components include the host, the computing fast link device, and the high-speed peripheral device interconnect bus standard device; the basic test items include the computing fast link device accessing its own memory, the high-speed peripheral device interconnect bus standard device accessing its own memory, and a first computing fast link device... The performance test results of the computing fast link device are generated by comparing the performance indicators corresponding to different basic test items. This includes: the link device accessing the memory of the second computing fast link device; the computing fast link device accessing the memory of the high-speed peripheral device interconnect bus standard device; the first high-speed peripheral device interconnect bus standard device accessing the memory of the second high-speed peripheral device interconnect bus standard device; the host accessing the memory of the computing fast link device; the host accessing the memory of the high-speed peripheral device interconnect bus standard device; the computing fast link device accessing the memory of the host; the high-speed peripheral device interconnect bus standard device accessing the memory of the host; and the first host accessing the memory of the second host.

[0051] The performance testing method for fast computing link devices provided in this application designs basic test items based on data transmission scenarios between different components, and achieves more comprehensive performance testing by comparing the performance indicators corresponding to different basic test items. This application also discloses a performance testing apparatus, system, electronic device, and computer-readable storage medium for fast computing link devices, which can achieve the same technical effects.

[0052] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings are used to provide a further understanding of this disclosure and constitute a part of the specification. They are used together with the following detailed description to explain this disclosure, but do not constitute a limitation of this disclosure. In the drawings:

[0054] Figure 1 This is a structural diagram illustrating a performance testing system for a computing fast link device according to an exemplary embodiment;

[0055] Figure 2 This is a flowchart illustrating a method for testing the performance of a fast link device according to an exemplary embodiment;

[0056] Figure 3 This is a memory path diagram illustrating a fast-link computing device accessing itself according to an exemplary embodiment;

[0057] Figure 4 This is a diagram illustrating a transmission path for memory data between computing fast link devices, according to an exemplary embodiment.

[0058] Figure 5 This is a transmission path diagram illustrating a host accessing memory data of a computing fast link device according to an exemplary embodiment;

[0059] Figure 6 This is a diagram illustrating a transmission path for a computing fast link device to access host memory data, according to an exemplary embodiment.

[0060] Figure 7 This is a structural diagram illustrating a performance testing apparatus for a computing fast link device according to an exemplary embodiment;

[0061] Figure 8 This is a structural diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0062] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, in the embodiments of this application, "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0063] This application provides a performance testing system for computing fast link devices, such as... Figure 1 As shown, it includes a host, a computing fast link device connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host.

[0064] Endpoint devices (EPs) can be either Compute Fast Link (CXL) devices or Peripheral Component Interconnect Express (PCIe) devices. Multiple endpoint devices are connected via a root complex. In either CXL or PCIe devices, the compute unit is optional. For CXL devices, the extended memory can be either Host-managed Device Memory (HDM) or Private Device Memory (PDM). Considering the basic performance characteristics of feasible data access or transmission between any two of these three environments in both CXL and PCIe environments, these operations are fundamental to upper-layer applications and help to better leverage the advantages of CXL.

[0065] The consistent access characteristic brought by the CXL protocol can be tested using specific tools. Because the cache hit rate when CXL device memory data is loaded into the CPU cache varies depending on the application, the test plan only considers the overhead caused by different data access paths due to protocol differences. Furthermore, the latency and bandwidth differences caused by different storage media are not considered in this plan; the same storage media must be used during testing.

[0066] This application discloses a performance testing method for computing fast link devices, which enables comprehensive performance testing of computing fast link devices in various scenarios.

[0067] See Figure 1 A flowchart illustrating a performance testing method for a fast link device according to an exemplary embodiment is shown below. Figure 1 As shown, it includes:

[0068] S101: Obtain performance indicators corresponding to basic test items based on data transmission between different components; wherein, the components include the host, the fast computing link device, and the high-speed peripheral interconnect bus standard device, and the basic test items include any one or a combination of any of the following: the fast computing link device accessing its own memory, the high-speed peripheral interconnect bus standard device accessing its own memory, the first fast computing link device accessing the memory of the second fast computing link device, the fast computing link device accessing the memory of the high-speed peripheral interconnect bus standard device, the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device, the host accessing the memory of the fast computing link device, the host accessing the memory of the high-speed peripheral interconnect bus standard device, the fast computing link device accessing the memory of the host, the high-speed peripheral interconnect bus standard device accessing the memory of the host, and the first host accessing the memory of the second host;

[0069] In practical implementation, performance indicators corresponding to basic test items are obtained based on data transmission between different components. Basic test items include: the memory access of a fast computing link device to itself, the memory access of a high-speed peripheral interconnect bus standard device to itself, the memory access of a first fast computing link device to a second fast computing link device, the memory access of a fast computing link device to a high-speed peripheral interconnect bus standard device, the memory access of a first high-speed peripheral interconnect bus standard device to a second high-speed peripheral interconnect bus standard device, the memory access of a host to a fast computing link device, the memory access of a host to a high-speed peripheral interconnect bus standard device, the memory access of a fast computing link device to a host, the memory access of a high-speed peripheral interconnect bus standard device to a host, and the memory access of a first host to a second host. Performance indicators may include latency and bandwidth.

[0070] As a feasible implementation, the fast computing link device accessing its own memory includes: when the fast computing link device and the host are connected via different fast computing links and the fast computing link devices have different control modes and different bias modes, the computing units in the fast computing link device access memory of different memory types in the fast computing link device; the high-speed peripheral interconnect bus standard device accessing its own memory includes: the computing units in the high-speed peripheral interconnect bus standard device accessing their own memory.

[0071] In practical implementation, the endpoint device accesses its own memory path as follows: Figure 3As indicated by the dashed arrows, the first scenario involves a CXL device as the endpoint, connected to the host via the CXL.cache+CXL.mem protocol channel. The device's memory is in HDM-D mode. Basic test items include the performance of the CXL device's compute unit accessing HDM data under host bias and the performance of the CXL device's compute unit accessing HDM data under device bias. The second scenario involves a CXL device as the endpoint, connected to the host via the CXL.cache+CXL.mem protocol channel. The device's memory is partly in HDM-DB mode and partly in PDM mode. Basic test items include the performance of the CXL device's compute unit accessing HDM data and the performance of the CXL device's compute unit accessing PDM data. The third scenario involves a PCIe device as the endpoint, with basic test items including the performance of the PCIe device's compute unit accessing data from its own memory.

[0072] As one possible implementation, the first fast computing link device accessing the memory of the second fast computing link device includes: when the first fast computing link device and the host are connected via different fast computing links and the second fast computing link device has different control modes and different bias modes, the first fast computing link device accesses the memory of the second fast computing link device; the fast computing link device accessing the memory of the high-speed peripheral interconnect bus standard device includes: when the fast computing link device and the host are connected via different fast computing links and the fast computing link device has different control modes, the fast computing link device accesses the high-speed peripheral interconnect bus standard device.

[0073] In practical implementation, the data transfer path between endpoint devices is as follows: Figure 4As shown by the dashed arrow, the first scenario involves a CXL device accessing the memory of another CXL device. The device contains HDM and potential computing units. If the first fast computing link device directly accesses the HDM data of the second fast computing link device via the CXL.cache protocol channel, the basic test items include performance under different bias modes when the HDM data of the second fast computing link device is in HDM-D mode, performance in HDM-DB mode, and performance in HDM-H mode. If both the first and second fast computing link devices are connected to the host via the CXL.mem protocol channel, the basic test items include the performance of data transfer between the first and second fast computing link devices via memcpy (memory copy function). The second scenario involves a CXL device accessing a PCIe device. If the compute fast link device connects to the host via the CXL.cache protocol channel, the basic test items include the performance of the compute fast link device directly accessing the memory data of a high-speed peripheral interconnect bus standard device via the CXL.cache protocol channel; the data transfer performance between the memory data of the high-speed peripheral interconnect bus standard device and the compute fast link device in HDM-D mode; and the data transfer performance between the memory data of the high-speed peripheral interconnect bus standard device and the compute fast link device in HDM-DB mode. If the compute fast link device connects to the host via the CXL.mem protocol channel, the basic test items include the data transfer performance between the memory data of the high-speed peripheral interconnect bus standard device and the compute fast link device in HDM-H mode. The third scenario involves a PCIe device accessing the memory of a PCIe device. The basic test items include the memory data transfer performance of the first PCIe device and the second PCIe device.

[0074] As one possible implementation, the host accessing the memory of the computing fast link device includes: the host accessing the memory of the computing fast link device when the computing fast link device is in different control modes.

[0075] In practical implementation, the transmission path for the host to access the endpoint device's memory data is as follows: Figure 5 As indicated by the dashed arrows, the first scenario involves an endpoint device that is a CXL device. Basic test items include the performance of the host accessing HDM data in HDM-H mode, the performance of the host accessing HDM data in HDM-D mode, and the performance of the host accessing HDM data in HDM-DB mode. The second scenario involves an endpoint device that is a PCIe device. Basic test items include the performance of the host accessing PCIe device memory.

[0076] As one possible implementation, the fast computing link device accessing the host's memory includes: the fast computing link device accessing the host's memory via a fast computing link; the high-speed peripheral device interconnect bus standard device accessing the host's memory includes: the high-speed peripheral device interconnect bus standard device accessing the host's memory via a high-speed peripheral device interconnect bus standard.

[0077] In practical implementation, the transmission path for endpoint devices to access host memory data is as follows: Figure 6 As shown by the dashed arrow, the basic test items include the performance of CXL devices accessing host memory data via the CXL.cache protocol and the performance of PCIe devices accessing host memory data via the PCIe protocol.

[0078] The first host accesses the memory of the second host, which is the data transfer between different numa nodes between hosts.

[0079] S102: Compare the performance metrics corresponding to the different basic test items to generate the performance test results of the computing fast link device.

[0080] In this step, a more comprehensive performance test is achieved by comparing the performance metrics corresponding to different basic test items.

[0081] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators of the computing unit in the computing fast link device accessing the device memory managed by the host in the computing fast link device under host bias mode and device bias mode.

[0082] In practical implementation, since the data access in the two bias modes has different paths, the performance of the device computing unit accessing HDM data is compared under host bias and device bias.

[0083] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators corresponding to the access of the computing unit in the computing fast link device to the device memory managed by the host in the computing fast link device under different control modes.

[0084] In practical implementation, since the consistency between the HDM-DB mode and HDM-D mode of the CXL device memory is maintained by CXL.cache and CXL.mem respectively, and the maintenance overhead of different protocols is different, the performance of the device computing unit accessing HDM data in HDM-DB mode and HDM-D mode can be compared.

[0085] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators corresponding to the access of computing units in the computing fast link device to the device memory managed by the host and the device private memory in the computing fast link device.

[0086] In practical implementation, since the memory of the CXL device can be partially used as HDM and the remaining part of the memory is device-private, i.e. PDM, the performance of the device's computing unit accessing HDM and PDM respectively can be compared.

[0087] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators of the first computing fast link device accessing the memory of the second computing fast link device when the second computing fast link device is in different control modes.

[0088] In practical implementation, since CXL devices can access host memory space using the CXL.cache protocol channel, and the memory on CXL devices is uniformly addressed with the host memory, the HDM data of another CXL device can be accessed using the CXL.cache protocol. Therefore, the performance of EP1 accessing HDM data in different modes in EP2 using CXL.cache can be compared.

[0089] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators corresponding to the access of the first computing fast link device to the host-managed device memory in the second computing fast link device and the performance indicators corresponding to the access of the first high-speed peripheral device interconnect bus standard device to the memory of the second high-speed peripheral device interconnect bus standard device.

[0090] In practice, since the CXL.cache protocol can be used to access the HDM data of another CXL device, which is different from the existing P2P data transmission method between devices, the two can be compared in terms of performance.

[0091] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators corresponding to the first fast computing link device accessing the memory of the second fast computing link device through memory copying and the performance indicators corresponding to the first high-speed peripheral device interconnect bus standard device accessing the memory of the second high-speed peripheral device interconnect bus standard device.

[0092] In practical implementation, since the CXL.mem protocol channel can unify the addressing of CXL device memory and host memory, data transmission between two CXL devices can be achieved through memcpy operation, which is different from the existing P2P data transmission method between devices. Therefore, the performance of the two can be compared.

[0093] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators of the first computing fast link device accessing the memory of the second computing fast link device when the first computing fast link device is in different control modes.

[0094] In practical implementation, since the CXL.mem protocol channel can unify the addressing of CXL device memory and host memory, its data transmission method with PCIe devices is different from the existing P2P data transmission method between devices. However, the HDM in CXL devices has different modes: HDM-H, HDM-DB, and HDM-D. Therefore, the performance of data transmission between devices with different host management device memory data modes can be compared.

[0095] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators corresponding to the host accessing the host-managed device memory in the computing fast link device under different control modes.

[0096] In practice, different consistency maintenance protocols result in different protocol overheads, which leads to differences in the performance of hosts accessing HDM data under different modes.

[0097] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators corresponding to the host accessing the host-managed device memory in the computing fast link device and the performance indicators corresponding to the host accessing the memory of the high-speed peripheral interconnect bus standard device.

[0098] In practice, the performance of host accessing HDM data and PCIe device memory is compared.

[0099] As a feasible implementation method, the comparison of performance indicators corresponding to different basic test items includes: comparing the performance indicators corresponding to the host accessing the device memory managed by the host in the computing fast link device and the performance indicators corresponding to the first host accessing the memory of the second host.

[0100] In practice, the performance of host accessing device HDM data and remote numa nodes is compared.

[0101] To illustrate the use of the above test items or comparative experiments, an application of a CXL type3 device can be used as an example. The performance of host accessing data in the type3 device's memory can be obtained through basic test items regarding the performance of host accessing HDM data in HDM-H mode. However, the performance is lower than that of data transfer between different NUMA nodes on different hosts. Therefore, when considering applications, applications with high cache hit rates can be prioritized, with a hit rate high enough to compensate for the performance disadvantage of host accessing HDM data in HDM-H mode. Furthermore, since the performance difference between host accessing HDM data in HDM-H mode and data transfer between different NUMA nodes on different hosts is not orders of magnitude, the CXL type3 device can be used as a swapping area for host memory. A novel page swapping mechanism can be designed between host memory and CXL memory to improve the utilization of host memory, thereby improving application performance.

[0102] The performance testing method for computing fast link devices provided in this application designs basic test items based on data transmission scenarios between different components, including computing fast link devices accessing their own memory, first computing fast link devices accessing the memory of second computing fast link devices, hosts accessing the memory of computing fast link devices, computing fast link devices accessing the memory of hosts, and first hosts accessing the memory of second hosts. At the same time, a more comprehensive performance test is achieved by comparing the performance indicators corresponding to different basic test items.

[0103] Based on the above embodiments, as a feasible implementation method, the host accesses the memory of the computing fast link device by means of memory access instructions without temporary storage and / or memory access instructions that are stored and written back; the host accesses the memory of the high-speed peripheral interconnect bus standard device by means of memory-mapped port load / store memory access instructions.

[0104] In practical implementation, since CXL devices differ from PCIe devices in that CXL device memory can be cached by the host cache, different instruction types need to be considered to control whether access goes through the cache. Load / Store memory access instructions transfer data between ARM registers and memory. No-temperal Store instructions indicate that the host writes data directly to memory without going through the cache, while Store and Write back instructions indicate that the host writes data to memory through the cache. PCIe device memory access is handled by Load / Store instructions in the form of MMIO (Memory-Mapped I / O).

[0105] Based on the above embodiments, as a feasible implementation method, the step of comparing the performance indicators corresponding to different basic test items to generate the performance test results of the computing fast link device includes: comparing the performance indicators corresponding to different basic test items under different influencing factors to generate the performance test results of the computing fast link device; wherein, the influencing factors include any one or a combination of any of the following: number of memory access threads, access method, whether they belong to the same non-consistent memory access node, and data volume, and the access method includes sequential access and random access.

[0106] In practical implementation, when testing the host's access to the memory performance of a fast-link computing device, the following influencing factors need to be considered:

[0107] 1. The number of threads accessing CXL memory.

[0108] 2. The bandwidth difference between sequential and random access to CXL memory.

[0109] 3. CXL memory access within the same NUMA node and CXL memory access across NUMA nodes.

[0110] 4. For CXL memory transfer between the host and NUMA nodes, and for CXL memory transfer between the host and NUMA nodes, the impact of the amount of data transferred on performance needs to be further considered.

[0111] For performance testing between extended memory devices, DMA and memcpy can be used for data transfer. The difference between DMA and memcpy is that memcpy requires CPU intervention, while DMA does not. Since CXL device memory is considered system memory, both DMA and memcpy can be used for data transfer. In this case, the bandwidth performance metric must consider the amount of data transferred. DMA can be used for data transfer between PCIe devices.

[0112] When conducting comparative tests, the performance indicators corresponding to different basic test items under different influencing factors can be compared to generate performance test results.

[0113] The following describes a performance testing apparatus for a computing fast link device provided in an embodiment of this application. The performance testing apparatus for a computing fast link device described below and the performance testing method for a computing fast link device described above can be referred to each other.

[0114] See Figure 7A structural diagram of a performance testing apparatus for a computing fast link device is shown according to an exemplary embodiment, as follows: Figure 7 As shown, it includes:

[0115] The acquisition module 701 is used to acquire performance indicators corresponding to basic test items based on data transmission between different components; wherein, the components include the host, the fast computing link device, and the high-speed peripheral device interconnect bus standard device, and the basic test items include any one or any combination of any of the following: the fast computing link device accessing its own memory, the high-speed peripheral device interconnect bus standard device accessing its own memory, the first fast computing link device accessing the memory of the second fast computing link device, the fast computing link device accessing the memory of the high-speed peripheral device interconnect bus standard device, the first high-speed peripheral device interconnect bus standard device accessing the memory of the second high-speed peripheral device interconnect bus standard device, the host accessing the memory of the fast computing link device, the host accessing the memory of the high-speed peripheral device interconnect bus standard device, the fast computing link device accessing the memory of the host, the high-speed peripheral device interconnect bus standard device accessing the memory of the host, and the first host accessing the memory of the second host;

[0116] The comparison module 702 is used to compare the performance indicators corresponding to different basic test items in order to generate the performance test results of the computing fast link device.

[0117] The performance testing device for computing fast link devices provided in this application designs basic test items according to data transmission scenarios between different components, and achieves more comprehensive performance testing by comparing the performance indicators corresponding to different basic test items.

[0118] Based on the above embodiments, as a preferred embodiment, the fast computing link device accessing its own memory includes: when the fast computing link device is connected to the host through different fast computing links and the fast computing link device has different control modes and different bias modes, the computing unit in the fast computing link device accesses memory of different memory types in the fast computing link device;

[0119] The high-speed peripheral device interconnect bus standard device accessing its own memory includes: the computing unit in the high-speed peripheral device interconnect bus standard device accessing its own memory.

[0120] Based on the above embodiments, as a preferred embodiment, the first computing fast link device accessing the memory of the second computing fast link device includes: when the first computing fast link device and the host are connected through different computing fast links and the second computing fast link device has different control modes and different bias modes, the first computing fast link device accesses the memory of the second computing fast link device.

[0121] The access to the memory of the high-speed peripheral interconnect bus standard device by the computing fast link device includes: when the computing fast link device and the host are connected via different computing fast links and the computing fast link device is in a different control mode, the computing fast link device accesses the high-speed peripheral interconnect bus standard device.

[0122] Based on the above embodiments, as a preferred embodiment, the host accessing the memory of the computing fast link device includes: when the computing fast link device is in different control modes, the host accessing the memory of the computing fast link device.

[0123] Based on the above embodiments, as a preferred embodiment, the fast computing link device accessing the host's memory includes: the fast computing link device accessing the host's memory through a fast computing link;

[0124] The high-speed peripheral device interconnect bus standard device accessing the host's memory includes: the high-speed peripheral device interconnect bus standard device accessing the host's memory through the high-speed peripheral device interconnect bus standard.

[0125] Based on the above embodiments, as a preferred implementation, the performance indicators include latency and / or bandwidth.

[0126] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators of the computing unit in the computing fast link device accessing the device memory managed by the host in the computing fast link device under host bias mode and device bias mode.

[0127] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators corresponding to the access of the computing unit in the computing fast link device to the device memory managed by the host in the computing fast link device under different control modes.

[0128] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators corresponding to the computing unit in the computing fast link device accessing the device memory managed by the host in the computing fast link device and the device private memory.

[0129] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators corresponding to the first computing fast link device accessing the memory of the second computing fast link device when the second computing fast link device is in different control modes.

[0130] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators of the first computing fast link device accessing the device memory managed by the host in the second computing fast link device with the performance indicators of the first high-speed peripheral device interconnect bus standard device accessing the memory of the second high-speed peripheral device interconnect bus standard device.

[0131] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators of the first computing fast link device accessing the memory of the second computing fast link device through memory copying with the performance indicators of the first high-speed peripheral device interconnect bus standard device accessing the memory of the second high-speed peripheral device interconnect bus standard device.

[0132] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators corresponding to the first computing fast link device accessing the memory of the second computing fast link device when the first computing fast link device is in different control modes.

[0133] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators corresponding to the host-managed device memory in the computing fast link device when the computing fast link device is in different control modes.

[0134] Based on the above embodiments, as a preferred embodiment, the comparison module 702 is specifically used to: compare the performance indicators corresponding to the host accessing the host-managed device memory in the computing fast link device with the performance indicators corresponding to the host accessing the memory of the high-speed peripheral device interconnect bus standard device.

[0135] Based on the above embodiments, as a preferred implementation, the comparison module 702 is specifically used to: compare the performance indicators corresponding to the host accessing the device memory managed by the host in the computing fast link device with the performance indicators corresponding to the first host accessing the memory of the second host.

[0136] Based on the above embodiments, as a preferred implementation, the host accesses the memory of the computing fast link device by means of memory access instructions without temporary storage and / or memory access instructions that are stored and written back; the host accesses the memory of the high-speed peripheral interconnect bus standard device by means of memory-mapped port load / store memory access instructions.

[0137] Based on the above embodiments, as a preferred implementation, the comparison module 702 is specifically used to: compare the performance indicators corresponding to different basic test items under different influencing factors, so as to generate the performance test results of the computing fast link device; wherein, the influencing factors include any one or a combination of any of the following: number of memory access threads, access method, whether they belong to the same non-consistent memory access node, and data volume, and the access method includes sequential access and random access.

[0138] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0139] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiments of this application, the embodiments of this application also provide an electronic device. Figure 8 This is a structural diagram of an electronic device according to an exemplary embodiment, such as... Figure 8 As shown, the electronic device includes:

[0140] Communication interface 1 enables information exchange with other devices, such as network devices;

[0141] Processor 2 is connected to communication interface 1 to enable information interaction with other devices. When running a computer program, it executes the performance testing method for the high-speed computing link device provided by one or more of the above-mentioned technical solutions. The computer program is stored in memory 3.

[0142] Of course, in practical applications, the various components in an electronic device are coupled together through bus system 4. It can be understood that bus system 4 is used to achieve communication and connection between these components. In addition to the data bus, bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 8 The general will label all buses as Bus System 4.

[0143] The memory 3 in this embodiment is used to store various types of data to support the operation of the electronic device. Examples of such data include any computer program used to operate on the electronic device.

[0144] It is understood that memory 3 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 3 described in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0145] The methods disclosed in the embodiments of this application can be applied to processor 2, or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 2 or by instructions in the form of software. The processor 2 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the aforementioned method in combination with its hardware.

[0146] When processor 2 executes the program, it implements the corresponding processes in the various methods of the embodiments of this application. For the sake of brevity, these will not be described in detail here.

[0147] In an exemplary embodiment, this application also provides a storage medium, namely a computer storage medium, specifically a computer-readable storage medium, such as a memory 3 that stores a computer program, which can be executed by a processor 2 to complete the steps described in the aforementioned method. The computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disc, or CD-ROM.

[0148] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0149] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A performance testing method for computing fast link devices, characterized in that, A performance testing system for computing fast link devices, the system comprising a host, computing fast link devices connected to the host, and high-speed peripheral device interconnect bus standard devices connected to the host, the method comprising: Performance metrics corresponding to basic test items are obtained based on data transmission between different components. The components include the host, the fast computing link device, and the high-speed peripheral interconnect bus standard device. The basic test items include at least one or a combination of any of the following: the fast computing link device accessing its own memory; the first fast computing link device accessing the memory of the second fast computing link device; the fast computing link device accessing the memory of the high-speed peripheral interconnect bus standard device; the host accessing the memory of the fast computing link device; and the fast computing link device accessing the memory of the host. The basic test items also include any one or a combination of any of the following: the high-speed peripheral interconnect bus standard device accessing its own memory; the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device; the host accessing the memory of the high-speed peripheral interconnect bus standard device; the high-speed peripheral interconnect bus standard device accessing the memory of the host; and the first host accessing the memory of the second host. The performance metrics corresponding to the different basic test items are compared to generate the performance test results of the computing fast link device.

2. The performance testing method according to claim 1, characterized in that, The fast computing link device accessing its own memory includes: when the fast computing link device is connected to the host through different fast computing links and the fast computing link device has different control modes and different bias modes, the computing unit in the fast computing link device accesses memory of different memory types in the fast computing link device. The high-speed peripheral device interconnect bus standard device accessing its own memory includes: the computing unit in the high-speed peripheral device interconnect bus standard device accessing its own memory.

3. The performance testing method according to claim 1, characterized in that, Access to the memory of the second computing fast link device by the first computing fast link device includes: when the first computing fast link device is connected to the host through different computing fast links and the second computing fast link device has different control modes and different bias modes, the first computing fast link device accesses the memory of the second computing fast link device. The access to the memory of the high-speed peripheral interconnect bus standard device by the computing fast link device includes: when the computing fast link device and the host are connected via different computing fast links and the computing fast link device is in a different control mode, the computing fast link device accesses the high-speed peripheral interconnect bus standard device.

4. The performance testing method according to claim 1, characterized in that, The host accessing the memory of the computing fast link device includes: the host accessing the memory of the computing fast link device when the computing fast link device is in different control modes.

5. The performance testing method according to claim 1, characterized in that, The fast computing link device accessing the host's memory includes: the fast computing link device accessing the host's memory via a fast computing link; The high-speed peripheral device interconnect bus standard device accessing the host's memory includes: the high-speed peripheral device interconnect bus standard device accessing the host's memory through the high-speed peripheral device interconnect bus standard.

6. The performance testing method according to claim 1, characterized in that, The performance metrics include latency and / or bandwidth.

7. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: The performance metrics of the computing units in the computing fast link device accessing the device memory managed by the host in the computing fast link device are compared in host-biased mode and device-biased mode.

8. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: The performance metrics of the computing units in the computing fast link device accessing the device memory managed by the host in the computing fast link device are compared under different control modes.

9. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: Compare the performance metrics of the computing units in the computing fast link device accessing the device memory managed by the host in the computing fast link device and the device private memory.

10. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: The performance metrics of the first computing fast link device accessing the memory of the second computing fast link device are compared when the second computing fast link device is in a different control mode.

11. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: Compare the performance metrics of the first high-speed computing link device accessing the host-managed device memory in the second high-speed computing link device with the performance metrics of the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device.

12. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: The performance metrics of the first high-speed computing link device accessing the memory of the second high-speed computing link device via memory copying are compared with the performance metrics of the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device.

13. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: The performance metrics of the first fast computing link device accessing the memory of the second fast computing link device under different control modes are compared.

14. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: Comparing the performance metrics of the host accessing the host-managed device memory in the computing fast link device under different control modes.

15. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: Compare the performance metrics of the host accessing the host-managed device memory in the computing fast link device with the performance metrics of the host accessing the memory of the high-speed peripheral interconnect bus standard device.

16. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items includes: Compare the performance metrics of the host accessing the device memory managed by the host in the computing fast link device with the performance metrics of the first host accessing the memory of the second host.

17. The performance testing method according to claim 1, characterized in that, The host accesses the memory of the computing fast link device by using memory access instructions without temporary storage and / or storing and writing back memory access instructions; The host accesses the memory of the high-speed peripheral interconnect bus standard device via load / store memory access instructions in the form of memory-mapped ports.

18. The performance testing method according to claim 1, characterized in that, The comparison of performance metrics corresponding to different basic test items to generate performance test results for the computing fast link device includes: The performance indicators corresponding to different basic test items under different influencing factors are compared to generate the performance test results of the computing fast link device; wherein, the influencing factors include any one or a combination of any of the following: number of memory access threads, access method, whether they belong to the same non-consistent memory access node, and data volume; the access method includes sequential access and random access.

19. A performance testing apparatus for computing fast link devices, characterized in that, A performance testing system for computing fast link devices, comprising a host, computing fast link devices connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host, the device comprising: An acquisition module is used to acquire performance indicators corresponding to basic test items based on data transmission between different components. The components include the host, the fast computing link device, and the high-speed peripheral interconnect bus standard device. The basic test items include at least one or a combination of any of the following: the fast computing link device accessing its own memory; the first fast computing link device accessing the memory of the second fast computing link device; the fast computing link device accessing the memory of the high-speed peripheral interconnect bus standard device; the host accessing the memory of the fast computing link device; and the fast computing link device accessing the memory of the host. The basic test items also include any one or a combination of any of the following: the high-speed peripheral interconnect bus standard device accessing its own memory; the first high-speed peripheral interconnect bus standard device accessing the memory of the second high-speed peripheral interconnect bus standard device; the host accessing the memory of the high-speed peripheral interconnect bus standard device; the high-speed peripheral interconnect bus standard device accessing the memory of the host; and the first host accessing the memory of the second host. The comparison module is used to compare the performance indicators corresponding to different basic test items in order to generate the performance test results of the computing fast link device.

20. A performance testing system for computing fast link devices, characterized in that, A method for performing performance testing of a computing fast link device as described in any one of claims 1 to 18; The performance testing system for the computing fast link device includes a host, a computing fast link device connected to the host, and a high-speed peripheral device interconnect bus standard device connected to the host.

21. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the performance testing method for a computing fast link device as described in any one of claims 1 to 18 when executing the computer program.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the performance testing method for a computing fast link device as described in any one of claims 1 to 18.

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