Power saving mode control circuit and control method

Abstract

The present application relates to a power saving mode control circuit and control method, which belongs to the field of chip energy saving technology. The control circuit includes a power supply management unit, a processing unit, a primary power saving circuit and a secondary power saving circuit; the primary power saving circuit generates a state detection signal SW in response to a first trigger signal, and receives a response signal EN1 returned by the processing unit to output a state switching signal LOAD; the secondary power saving circuit generates a power supply signal in response to a second trigger signal P and receives a maintenance signal EN2 returned by the power supply management unit to control the state switching of the power supply management unit; the power supply management unit responds to the power supply signal to provide a working voltage to the processing unit; and receives a state switching signal LOAD to control the working state of the processing unit; the processing unit responds to the state detection signal SW to output a response signal EN1, and responds to the working voltage to output a maintenance signal EN2. The present application has the effect of facilitating the realization of the dormancy and activation of the energy storage system.

Description

Technical Field

[0001] The present invention relates to the technical field of chip energy saving, and in particular to a power saving mode control circuit and a control method. Background Art

[0002] Energy storage systems such as battery packs usually require a BMS (Battery Management System) to control charging and discharging. However, the internal standby power consumption of the battery management system is large, which is not conducive to the long-term storage of battery pack power.

[0003] At present, in order to extend the storage time of the battery pack, a power saving mode is usually designed so that the system can enter a low-energy state when not in use. Since the battery management system itself is powered by the battery pack, when the battery pack is seriously low on power, it can no longer supply power to the battery management system. At this time, the battery management system cannot work and cannot control the charging of the battery pack, making the energy storage system unable to activate. Therefore, how to control the dormancy and activation of the system is an urgent problem to be solved. Summary of the invention

[0004] In order to facilitate the dormancy and activation of an energy storage system, the present application provides a power saving mode control circuit and a control method.

[0005] In a first aspect, the present application provides a power saving mode control circuit, which adopts the following technical solution:

[0006] A power saving mode control circuit comprises a power supply management unit, a processing unit, a primary power saving circuit and a secondary power saving circuit;

[0007] The first-level power saving circuit is connected to the power management unit, the processing unit and the power supply B+, generates a state detection signal SW in response to the first trigger signal, receives a response signal EN1 returned by the processing unit, and outputs a state switching signal LOAD;

[0008] A secondary power saving circuit is connected to the power management unit and the processing unit, generates a power supply signal in response to the second trigger signal P-, and receives a maintenance signal EN2 returned by the power management unit to control the state switching of the power management unit;

[0009] The power supply management unit is connected to the processing unit, responds to the power supply signal to provide the processing unit with an operating voltage; and receives a state switching signal LOAD to control the working state of the processing unit;

[0010] The processing unit outputs a response signal EN1 in response to the state detection signal SW and outputs a maintenance signal EN2 in response to the working voltage.

[0011] By adopting the above technical solution, when the power supply management unit is working normally, the first-level power saving circuit is used to switch the processing unit to the power saving state or switch from the power saving state to the normal working state based on the first trigger signal. When the power supply management unit stops working due to power shortage, the second-level power saving circuit is used to first activate the power supply management unit based on the second trigger signal P-, so that the power supply management unit provides the working voltage to the processing unit, thereby activating the processing unit, that is, the first-level power saving circuit and the second-level power saving circuit are used to facilitate the system to enter the power saving state and activate from the power saving state.

[0012] Optionally, the first-level power saving circuit includes a state detection subcircuit, a response subcircuit and a first control subcircuit;

[0013] The state detection subcircuit is connected to the processing unit, the response subcircuit and the first control subcircuit; the response subcircuit is connected to the first control subcircuit and the processing unit; the first control subcircuit is connected to the power supply management unit and the power supply B+.

[0014] By adopting the above technical solution, the state detection subcircuit is used to receive the first trigger signal to generate the state detection signal SW and output it to the processing unit, so that the processing unit outputs the response signal EN1 to the response subcircuit, so that the response subcircuit controls the first control subcircuit to output the state switching signal LOAD based on the response signal EN1, and outputs the state switching signal LOAD to the processing unit, thereby achieving the effect of switching the state of the processing unit.

[0015] Optionally, the first control subcircuit includes a PMOS tube Q1, a first resistor R1, a first capacitor C1 and a second capacitor C2;

[0016] The source of the PMOS tube Q1 is connected to the power supply B+, one end of the first resistor R1 and one end of the first capacitor C1 to output the state switching signal LOAD, the drain is connected to the power supply management unit and one end of the second capacitor C2, and the gate is connected to the other end of the first resistor R1, the other end of the first capacitor C1, the other end of the second capacitor C2, the state detection subcircuit and the response subcircuit.

[0017] By adopting the above technical solution, when the gate of the PMOS tube Q1 is at a low level, the PMOS is turned on, and the high-level state switching signal LOAD is transmitted to the processing unit to enable the processing unit to work normally. When the gate of the PMOS tube Q1 is at a high level, the PMOS is turned off, and at this time, the PMOS tube Q1 outputs a low-level state switching signal LOAD to the processing unit to control the processing unit to enter a power saving mode. The first resistor R1, the first capacitor C1, and the second capacitor C2 facilitate providing a bias voltage to the PMOS tube Q1, so that the gate of the PMOS tube Q1 can accurately receive a level signal.

[0018] Optionally, the response subcircuit includes an NMOS transistor Q2; the gate of the NMOS transistor Q2 is connected to the processing unit to receive the response signal EN1, the drain is connected to the first control subcircuit, and the source is grounded.

[0019] By adopting the above technical solution, when the response signal EN1 received by the NMOS tube Q2 is at a high level, the NMOS tube Q2 is turned on, and the control sub-circuit is grounded at this time, that is, a low-level signal is output to the control sub-circuit; when the response signal EN1 received by the NMOS tube Q2 is at a low level, the NMOS tube Q2 is turned off, and a high-level signal is output to the control sub-circuit, thereby making it easier for the control sub-circuit to output a state switching signal LOAD of different states.

[0020] Optionally, the state detection subcircuit includes a trigger switch K1, a first NPN transistor Q3, a second resistor R2 and a third resistor R3;

[0021] One end of the trigger switch K1 is connected to the first control subcircuit, and the other end is connected to the base of the first NPN transistor Q3 and one end of the third resistor R3; the other end of the third resistor R3 is grounded;

[0022] The collector of the first NPN transistor Q3 is connected to one end of the second resistor R2 and the processing unit, and the emitter is grounded; the other end of the second resistor R2 is connected to the power supply VCC.

[0023] By adopting the above technical solution, if the processing unit is in the power saving state, the trigger switch K1 is closed at the moment of closing, and the control sub-circuit is grounded through the trigger switch K1 and the third resistor R3, so that the control sub-circuit receives a low-level signal to output a high-level state switching signal LOAD to control the processing unit to start working; then the trigger switch K1 is disconnected, so that the NPN transistor is disconnected, and the power supply VCC is output through the second resistor R2 to generate a high-level switching detection signal. After receiving the high-level switching detection signal, the processing unit continues to output a high-level response signal EN1, so that the processing unit continues to be in a normal working state.

[0024] Optionally, the secondary power saving circuit includes a second control subcircuit, a trigger subcircuit and a maintenance subcircuit;

[0025] The second control subcircuit is connected to the power supply management unit, the trigger subcircuit and the maintenance subcircuit; the maintenance subcircuit is connected to the trigger subcircuit and the processing unit.

[0026] By adopting the above technical solution, the trigger sub-circuit is used to receive the second trigger signal P-, and the second control sub-circuit is turned on to supply power to the power supply management unit. The power supply management unit then activates the processing unit to output the maintenance signal EN2. After the maintenance sub-circuit receives the maintenance signal EN2, the second control sub-circuit is continuously turned on, thereby realizing the control of the working state of the power supply management unit.

[0027] Optionally, the second control subcircuit includes a PNP transistor Q5 and a fourth resistor R4; the base of the PNP transistor Q5 is connected to one end of the fourth resistor R4, the trigger subcircuit and the maintaining subcircuit, and the emitter is connected to the power supply B+ and the other end of the fourth resistor R4; the collector is connected to the power supply management unit.

[0028] By adopting the above technical solution, the base of the PNP transistor Q5 is connected to the power supply B+ through the fourth resistor R4, so as to provide a bias voltage to the base of the PNP transistor Q5. When the base of the PNP transistor Q5 is at a low level, the PNP transistor Q5 is cut off, and the power supply management system stops working; when the base of the PNP transistor Q5 is at a high level, the PNP transistor is turned on, so that the power supply management system starts working, thereby facilitating the switching of the working state of the power supply management system.

[0029] Optionally, the trigger subcircuit includes a first diode D1, a second diode D2 and a second NPN transistor Q4;

[0030] The base of the second NPN transistor Q4 is grounded, the collector is connected to the cathode of the second diode D2, and the emitter is connected to the anode of the first diode D1;

[0031] The anode of the first diode D1 is connected to an external circuit to receive a second trigger signal P-; the anode of the second diode D2 is connected to a maintaining subcircuit and a second control subcircuit;

[0032] Wherein, the second trigger signal P- is a negative potential signal.

[0033] By adopting the above technical solution, when the second trigger signal P- is received, the emitter of the second NPN transistor Q4 is at a negative potential and the base is at a zero potential, the second NPN transistor Q4 is turned on, and a low-level signal is output to the second control subcircuit to control the second control subcircuit to be turned on.

[0034] Optionally, the maintaining sub-circuit includes a third NPN transistor Q6 and a third diode D3;

[0035] The base of the third NPN transistor Q6 is connected to the cathode of the third diode D3, the collector is connected to the trigger subcircuit and the second control subcircuit, and the emitter is grounded;

[0036] An anode of the third diode D3 is connected to the processing unit to receive the sustain signal EN2 .

[0037] By adopting the above technical solution, when the maintenance signal EN2 is at a high level, the maintenance signal EN2 passes through the third diode D3 to make the base of the third NPN transistor Q6 at a high level, and the third NPN transistor Q6 is turned on, thereby pulling the control subcircuit down to a low level.

[0038] In a second aspect, the present application provides a power saving mode control method, which adopts the following technical solution:

[0039] A power saving mode control method, based on the above circuit, comprises:

[0040] In response to the first trigger signal, a state detection signal SW is generated, and a response signal EN1 returned by the processing unit is received, and a state switching signal LOAD is output;

[0041] In response to the second trigger signal P-, a power supply signal is generated, and a maintenance signal EN2 returned by the processing unit is received to control the state switching of the power supply management unit;

[0042] Responding to the power supply signal to provide the operating voltage to the processing unit; and receiving the state switching signal LOAD to control the working state of the processing unit;

[0043] In response to the state detection signal SW, a response signal EN1 is output; in response to the operating voltage, a maintenance signal EN2 is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a block diagram of a power saving mode control circuit according to one embodiment of the present application.

[0045] Figure 2 It is a connection structure diagram of a power saving mode control circuit according to one embodiment of the present application.

[0046] Explanation of the accompanying drawings: 1. Power supply management unit; 2. Processing unit; 3. Level 1 power saving circuit; 31. Status detection sub-circuit; 32. Response sub-circuit; 33. First control sub-circuit; 4. Level 2 power saving circuit; 41. Second control sub-circuit; 42. Trigger sub-circuit; 43. Maintain sub-circuit. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] The present application embodiment discloses a power saving mode control circuit. Figure 1 A power saving mode control circuit includes a power saving mode control circuit, including a power supply management unit 1, a processing unit 2, a first-level power saving circuit 3 and a second-level power saving circuit 4; wherein the state of the power supply management unit 1 includes a normal working state and a power-off state, and the working state of the processing unit 2 includes a normal working state and a power saving state.

[0049] The first-level power saving circuit 3 is connected to the power management unit 1, the processing unit 2 and the power supply B+, generates a state detection signal SW in response to the first trigger signal, receives a response signal EN1 returned by the processing unit 2, and outputs a state switching signal LOAD.

[0050] Among them, there are two sources of the response signal EN1. One is that the first trigger signal is received to generate the state detection signal SW. When the processing unit 2 receives the state detection signal SW, the processing unit 2 returns the response signal EN1. The other is that the power supply management unit 1 autonomously sends instructions to the processing unit 2, so that the processing unit 2 returns the response signal EN1. As an example, when the power supply management unit 1 detects that the output voltage of the power supply B+ is less than the first preset value, the power supply management unit 1 sends instructions to the processing unit 2, so that the working state of the processing unit 2 can be switched in time when undervoltage occurs.

[0051] It should also be noted that the first trigger signal is an external artificial trigger signal.

[0052] The secondary power saving circuit 4 is connected to the power management unit 1 and the processing unit 2, generates a power signal in response to the second trigger signal P-, and receives a maintenance signal EN2 returned by the power management unit 1 to control the state switching of the power management unit 1.

[0053] The second trigger signal P- is a negative voltage when connected to the external power source B+, which indicates that the external charging condition is met.

[0054] It should be noted that when the first-level power saving circuit 3 receives the first trigger signal or the first-level power saving circuit 3 can only control the working state of the processing unit 2, the power supply management unit 1 is still in a normal working state; when the output voltage of the power supply B+ is less than the second preset value, the second preset value is less than the first preset value, and the power supply management unit 1 is in a power-off state. At this time, the second trigger signal P- is required to activate the power supply management unit 1.

[0055] The power management unit 1 is connected to the processing unit 2, responds to the power supply signal to provide the operating voltage to the processing unit 2; and receives the state switching signal LOAD to control the working state of the processing unit 2;

[0056] The processing unit 2 responds to the state detection signal SW to output a response signal EN1 ; and responds to the working voltage to output a maintenance signal EN2 .

[0057] It should be understood that the present embodiment adopts a two-stage power-off activation mode. When the power is low, the processing unit 2 is first turned off automatically through the first-stage power-saving circuit 3. At this time, the processing unit 2 can be activated through the first-stage power-saving circuit 3. When the power continues to decrease until it cannot support the operation of the power supply management unit 1, that is, the power supply management unit 1 is powered off and turned off, when activating, the power supply management unit 1 needs to be activated first by the second-stage power-saving circuit 4 to make it work normally, and then the processing unit 2 is manually activated by the power supply management unit 1 or through the power-saving circuit. The specific method can be selected according to the actual situation.

[0058] In the above implementation, when the power supply management unit 1 is working normally, the first-level power saving circuit 3 is used to switch the processing unit 2 to the power saving state or from the power saving state to the normal working state based on the first trigger signal. When the power supply management unit 1 stops working due to power shortage, the second-level power saving circuit 4 is used to first activate the power supply management unit 1 based on the second trigger signal P-, so that the power supply management unit 1 provides the working voltage to the processing unit 2, thereby activating the processing unit 2, that is, the first-level power saving circuit 3 and the second-level power saving circuit 4 are used to facilitate the system to enter the power saving state and activate from the power saving state.

[0059] As an application scenario of the present application, a power saving mode control circuit is applied to an energy storage system. At this time, the power supply management unit is the BMS (battery management system) in the energy storage system, and the processing unit 2 is a single-chip microcontroller (Microcontroller) in the energy storage system. Specifically, in the energy storage system, the BMS is responsible for monitoring the voltage, current, temperature and other parameters of the battery pack, and is also responsible for preventing the battery from overcharging, over-discharging and overheating. For a battery pack composed of multiple battery cells, the BMS can perform battery balancing operations; to ensure that the battery pack operates within a safe operating range and improve the performance and life of the battery pack. The single-chip microcomputer is used to control various parts of the energy storage system, such as inverters, chargers, dischargers, etc., to perform tasks such as battery charging, discharging, energy management and system operation. The single-chip microcomputer can also provide a user interface, such as an LCD screen or buttons, so that the user can interact with the energy storage system and can communicate with external systems for data exchange.

[0060] Specifically, when the first-level power saving circuit 3 receives the first trigger signal or the undervoltage trigger, the power saving circuit first shuts down the processing unit 2 to enter the power saving mode. If the undervoltage continues, the BMS will also enter the power-off state. If the BMS needs to be activated, the external power supply B+, that is, the second trigger signal P-, is required to activate the BMS.

[0061] It should be noted that, taking the use scenario of the energy storage system as an example, since the BMS plays a more critical role in the management and protection of the battery pack, in the event of a power shortage, the microcontroller is first turned off to put the system into a low-power state, reducing control and operation, but the BMS is still active at this time to monitor and protect the battery, which helps to extend the battery life.

[0062] Reference Figure 2 , as an implementation of the primary power saving circuit 3, the primary power saving circuit 3 includes a state detection subcircuit 31, a response subcircuit 32 and a first control subcircuit 33;

[0063] The state detection subcircuit 31 is connected to the processing unit 2, the response subcircuit 32 and the first control subcircuit 33; the response subcircuit 32 is connected to the first control subcircuit 33 and the processing unit 2; the first control subcircuit 33 is connected to the power management unit 1 and the power supply B+.

[0064] In the above embodiment, the state detection subcircuit 31 receives the first trigger signal to generate the state detection signal SW and output it to the processing unit 2, so that the processing unit 2 outputs the response signal EN1 to the response subcircuit 32, so that the response subcircuit 32 controls the first

[0065] The control subcircuit outputs the state switching signal LOAD, and outputs the state switching signal LOAD to the processing unit 2 , thereby achieving the effect of switching the state of the processing unit 2 .

[0066] As an implementation of the first control subcircuit 33, the first control subcircuit 33 includes a PMOS transistor Q1, a first resistor R1, a first capacitor C1 and a second capacitor C2;

[0067] The source of the PMOS tube Q1 is connected to the power supply B+, one end of the first resistor R1 and one end of the first capacitor C1 to output the state switching signal LOAD, the drain is connected to the power supply management unit 1 and one end of the second capacitor C2, and the gate is connected to the other end of the first resistor R1, the other end of the first capacitor C1, the other end of the second capacitor C2, the state detection sub-circuit 31 and the response sub-circuit 32.

[0068] In the above embodiment, when the gate of the PMOS tube Q1 is at a low level, the PMOS is turned on, and the high-level state switching signal LOAD is transmitted to the processing unit 2, so that the processing unit 2 works normally. When the gate of the PMOS tube Q1 is at a high level, the PMOS is turned off, and at this time, the PMOS tube Q1 outputs a low-level state switching signal LOAD to the processing unit 2 to control the processing unit 2 to enter the power saving mode. The first resistor R1, the first capacitor C1, and the second capacitor C2 facilitate providing a bias voltage to the PMOS tube Q1, so that the gate of the PMOS tube Q1 can accurately receive the level signal.

[0069] As an implementation of the response subcircuit 32 , the response subcircuit 32 includes an NMOS transistor Q2 ; the gate of the NMOS transistor Q2 is connected to the processing unit 2 to receive the response signal EN1 , the drain is connected to the first control subcircuit 33 , and the source is grounded.

[0070] Specifically, the drain of the NMOS transistor Q2 is connected to the gate of the PMOS transistor Q1 , one end of the first resistor R1 , and one end of the first capacitor C1 .

[0071] In the above embodiment, when the response signal EN1 received by the NMOS tube Q2 is at a high level, the NMOS tube Q2 is turned on, and the control sub-circuit is grounded, that is, a low-level signal is output to the control sub-circuit; when the response signal EN1 received by the NMOS tube Q2 is at a low level, the NMOS tube Q2 is turned off, and a high-level signal is output to the control sub-circuit, so that the control sub-circuit can output a state switching signal LOAD of different states.

[0072] As an implementation of the state detection subcircuit 31, the state detection subcircuit 31 includes a trigger switch K1, a first NPN transistor Q3, a second resistor R2 and a third resistor R3;

[0073] One end of the trigger switch K1 is connected to the first control subcircuit 33, and the other end is connected to the base of the first NPN transistor Q3 and one end of the third resistor R3; the other end of the third resistor R3 is grounded;

[0074] Specifically, one end of the trigger switch K1 is connected to the gate of the PMOS transistor Q1 , one end of the first resistor R1 , and one end of the first capacitor C1 .

[0075] The collector of the first NPN transistor Q3 is connected to one end of the second resistor R2 and the processing unit 2, and the emitter is grounded; the other end of the second resistor R2 is connected to the power supply VCC.

[0076] The trigger switch K1 may be a normally open tact switch, which can complete the switch operation by applying a slight pressure when pressing the button, and can bounce back quickly, that is, once the button is released, the tact switch will immediately return to the unpressed state.

[0077] In the above embodiment, if the processing unit 2 is in the power saving state, the trigger switch K1 is closed at the moment of closing, and the control sub-circuit is grounded through the trigger switch K1 and the third resistor R3, so that the control sub-circuit receives a low-level signal to output a high-level state switching signal LOAD to control the processing unit 2 to start working; then the trigger switch K1 is disconnected, so that the NPN transistor is disconnected, and the power supply VCC is output through the second resistor R2 to generate a high-level switching detection signal. After receiving the high-level switching detection signal, the processing unit 2 continues to output a high-level response signal EN1, so that the processing unit 2 continues to be in a normal working state.

[0078] Reference Figure 2 , as an implementation of the secondary power saving circuit 4, the secondary power saving circuit 4 includes a second control subcircuit 41, a trigger subcircuit 42 and a maintenance subcircuit 43;

[0079] The second control sub-circuit 41 is connected to the power supply management unit 1 , the trigger sub-circuit 42 and the maintenance sub-circuit 43 ; the maintenance sub-circuit 43 is connected to the trigger sub-circuit 42 and the processing unit 2 .

[0080] Specifically, the trigger sub-circuit 42 and the sustain sub-circuit 43 are connected in parallel.

[0081] In the above embodiment, the trigger sub-circuit 42 is used to receive the second trigger signal P-, and the second control sub-circuit 41 is turned on to supply power to the power supply management unit 1. The power supply management unit 1 then activates the processing unit 2 to output the maintenance signal EN2. After receiving the maintenance signal EN2, the maintenance sub-circuit 43 keeps the second control sub-circuit 41 turned on, thereby realizing the control of the working state of the power supply management unit 1.

[0082] As an implementation mode of the second control subcircuit 41, the second control subcircuit 41 includes a PNP transistor Q5 and a fourth resistor R4; the base of the PNP transistor Q5 is connected to one end of the fourth resistor R4, the trigger subcircuit 42 and the maintaining subcircuit 43, the emitter is connected to the power supply B+ and the other end of the fourth resistor R4; the collector is connected to the power supply management unit 1.

[0083] In the above embodiment, the base of the PNP transistor Q5 is connected to the power supply B+ through the fourth resistor R4, so as to provide a bias voltage to the base of the PNP transistor Q5. When the base of the PNP transistor Q5 is at a low level, the PNP transistor Q5 is cut off, and the power supply management system stops working; when the base of the PNP transistor Q5 is at a high level, the PNP transistor is turned on, so that the power supply management system starts working, thereby facilitating the switching of the working state of the power supply management system.

[0084] As an implementation of the trigger sub-circuit 42, the trigger sub-circuit 42 includes a first diode D1, a second diode D2, and a second NPN transistor Q4;

[0085] The base of the second NPN transistor Q4 is grounded, the collector is connected to the cathode of the second diode D2, and the emitter is connected to the anode of the first diode D1;

[0086] The anode of the first diode D1 is connected to the external circuit to receive the second trigger signal P-; the anode of the second diode D2 is connected to the maintaining sub-circuit 43 and the second control sub-circuit 41;

[0087] The second trigger signal P- is a negative potential signal.

[0088] The external circuit may be a charging circuit, so that the negative voltage generated by charging is used as the second trigger signal P-.

[0089] In the above embodiment, when the second trigger signal P- is received, the emitter of the second NPN transistor Q4 is at a negative potential and the base is at a zero potential, the second NPN transistor Q4 is turned on, and a low level signal is output to the second control subcircuit 41 to control the second control subcircuit 41 to be turned on.

[0090] As an implementation of the maintaining sub-circuit 43, the maintaining sub-circuit 43 includes a third NPN transistor Q6 and a third diode D3;

[0091] The base of the third NPN transistor Q6 is connected to the cathode of the third diode D3, the collector is connected to the trigger sub-circuit 42 and the second control sub-circuit 41, and the emitter is grounded;

[0092] An anode of the third diode D3 is connected to the processing unit 2 to receive the sustain signal EN2 .

[0093] Specifically, the collector of the third NPN transistor Q6 is connected to the anode of the second diode D2 and the base of the PNP transistor Q5 .

[0094] In the above embodiment, when the sustain signal EN2 is at a high level, the sustain signal EN2 passes through the third diode D3 to make the base of the third NPN transistor Q6 at a high level, and the third NPN transistor Q6 is turned on, thereby pulling the control subcircuit down to a low level.

[0095] The embodiment of the present application discloses a power saving mode control method. A power saving mode control method, based on the above circuit, includes:

[0096] In response to the first trigger signal, a state detection signal SW is generated, and a response signal EN1 returned by the processing unit 2 is received, and a state switching signal LOAD is output;

[0097] In response to the second trigger signal P-, a power supply signal is generated, and a maintenance signal EN2 returned by the processing unit 2 is received to control the state switching of the power supply management unit 1;

[0098] In response to the power supply signal, the processing unit 2 is provided with an operating voltage; and a state switching signal LOAD is received to control the working state of the processing unit 2;

[0099] In response to the state detection signal SW, a response signal EN1 is output; in response to the operating voltage, a maintenance signal EN2 is output.

[0100] A power saving mode control method provided in the present application can realize the above-mentioned power saving mode control circuit, and the specific working process of a power saving mode control method can refer to the corresponding process in the above-mentioned method embodiment.

[0101] It should be noted that in the above embodiments, the description of each embodiment has different emphases, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0102] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A power saving mode control circuit, characterized in that: It comprises a power supply management unit (1), a processing unit (2), a primary power saving circuit (3) and a secondary power saving circuit (4); The first-level power saving circuit (3) is connected to the power management unit (1), the processing unit (2) and the power supply B+, generates a state detection signal SW in response to a first trigger signal, receives a response signal EN1 returned by the processing unit (2), and outputs a state switching signal LOAD; The secondary power saving circuit (4) is connected to the power management unit (1) and the processing unit (2), generates a power supply signal in response to a second trigger signal P-, and receives a maintenance signal EN2 returned by the power management unit (1) to control the state switching of the power management unit (1); The power supply management unit (1) is connected to the processing unit (2), responds to the power supply signal to provide an operating voltage to the processing unit (2), and receives the state switching signal LOAD to control the working state of the processing unit (2); The processing unit (2) outputs the response signal EN1 in response to the state detection signal SW; In response to the working voltage, outputting the sustain signal EN2; The first-level power saving circuit (3) comprises a state detection subcircuit (31), a response subcircuit (32) and a first control subcircuit (33); the state detection subcircuit (31) is connected to the processing unit (2), the response subcircuit (32) and the first control subcircuit (33); the response subcircuit (32) is connected to the first control subcircuit (33) and the processing unit (2); the first control subcircuit (33) is connected to the power management unit (1) and the power supply B+; The secondary power saving circuit (4) comprises a second control subcircuit (41), a trigger subcircuit (42) and a maintaining subcircuit (43); the second control subcircuit (41) is connected to the power supply management unit (1), the trigger subcircuit (42) and the maintaining subcircuit (43); the maintaining subcircuit (43) is connected to the trigger subcircuit (42) and the processing unit (2).

2. The circuit according to claim 1, characterized in that: The first control subcircuit (33) comprises a PMOS tube Q1, a first resistor R1, a first capacitor C1 and a second capacitor C2; the source of the PMOS tube Q1 is connected to a power supply B+, one end of the first resistor R1 and one end of the first capacitor C1 to output the state switching signal LOAD, the drain is connected to the power supply management unit (1) and one end of the second capacitor C2, and the gate is connected to the other end of the first resistor R1, the other end of the first capacitor C1, the other end of the second capacitor C2, the state detection subcircuit (31) and the response subcircuit (32).

3. The circuit according to claim 1, characterized in that: The response subcircuit (32) comprises an NMOS transistor Q2; the gate of the NMOS transistor Q2 is connected to the processing unit (2) to receive the response signal EN1, the drain is connected to the first control subcircuit (33), and the source is grounded.

4. The circuit according to claim 1, characterized in that: The state detection subcircuit (31) comprises a trigger switch K1, a first NPN transistor Q3, a second resistor R2 and a third resistor R3; One end of the trigger switch K1 is connected to the first control subcircuit (33), and the other end is connected to the base of the first NPN transistor Q3 and one end of the third resistor R3; the other end of the third resistor R3 is grounded; The collector of the first NPN transistor Q3 is connected to one end of the second resistor R2 and the processing unit (2), and the emitter is grounded; the other end of the second resistor R2 is connected to the power supply VCC.

5. The circuit according to claim 1, characterized in that: The second control subcircuit (41) comprises a PNP transistor Q5 and a fourth resistor R4; the base of the PNP transistor Q5 is connected to one end of the fourth resistor R4, the trigger subcircuit (42) and the maintaining subcircuit (43), the emitter is connected to a power supply B+ and the other end of the fourth resistor R4, and the collector is connected to the power supply management unit (1).

6. The circuit according to claim 1, characterized in that: The trigger subcircuit (42) comprises a first diode D1, a second diode D2 and a second NPN transistor Q4; The base of the second NPN transistor Q4 is grounded, the collector is connected to the cathode of the second diode D2, and the emitter is connected to the anode of the first diode D1; The anode of the first diode D1 is connected to an external circuit to receive the second trigger signal P-; the anode of the second diode D2 is connected to the maintaining subcircuit (43) and the second control subcircuit (41); Wherein, the second trigger signal P- is a negative potential signal.

7. The circuit according to claim 1, characterized in that: The maintaining subcircuit (43) comprises a third NPN transistor Q6 and a third diode D3; The base of the third NPN transistor Q6 is connected to the cathode of the third diode D3, the collector is connected to the trigger subcircuit (42) and the second control subcircuit (41), and the emitter is grounded; An anode of the third diode D3 is connected to the processing unit (2) to receive the sustain signal EN2.

8. A power saving mode control method, based on the circuit according to any one of claims 1 to 7, characterized in that: include: In response to the first trigger signal, a state detection signal SW is generated, and a response signal EN1 returned by the processing unit (2) is received, and a state switching signal LOAD is output; In response to the second trigger signal P-, a power supply signal is generated, and a maintenance signal EN2 returned by the processing unit (2) is received to control the state switching of the power supply management unit (1); Responding to the power supply signal to provide an operating voltage to the processing unit (2); and receiving a state switching signal LOAD to control the working state of the processing unit (2); In response to the state detection signal SW, to output a response signal EN1; In response to the operating voltage, a sustain signal EN2 is output.

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