Data processing method and device, electronic device and storage medium

Abstract

Embodiments of the present disclosure provide a data processing method and apparatus, an electronic device, and a storage medium. The data processing method includes: in response to receiving a write request from a first cache to write first data back to a memory, a cache consistency node writes the first data to the memory or discards the first data, wherein the write request carries the first data, and the cache consistency node is configured to maintain the consistency of data stored in multiple caches, the multiple caches including the first cache; and after the cache consistency node writes the first data to the memory or discards the first data, the cache consistency node returns a write response signal to the first cache to directly end the processing operation of the write request. This method can reduce the number of ACK messages, reduce the protocol's demand for ACK messages, reduce the power consumption and delay generated by the transmission of ACK messages, and reduce bandwidth occupancy, and optimize the turnover rate of the buffer on the master device side. Under the same performance, the master device side requires fewer buffers, saving area and power consumption.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing method, a data processing device, an electronic device, and a storage medium. Background Art

[0002] A network-on-a-chip (NOC) system is an essential bus system for enabling communication between components in large-scale integrated circuits. A system-on-chip (SOC) contains multiple subsystems, such as the CPU, GPU, memory, and I / O devices. Each subsystem may have multiple entities that need to communicate with each other (data and control signals) to work together.

[0003] In a SoC, multiple subsystems frequently interact with each other through read and write operations. To ensure high-performance data exchange between subsystems, the NOC system provides a high-bandwidth transaction exchange network to connect the various on-chip components. This network enables efficient data transmission between subsystems. However, when caches corresponding to different subsystems operate on data at the same address, consistency issues arise. To address this issue, various technologies have emerged to maintain data consistency. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a data processing method, which includes: in response to receiving a write request from a first cache to write first data back to a memory, a cache consistency node writes the first data to the memory or discards the first data, wherein the write request carries the first data, the cache consistency node is configured to maintain the consistency of data stored in multiple caches, the multiple caches include the first cache, and after the cache consistency node writes the first data to the memory or discards the first data, the cache consistency node returns a write response signal to the first cache to directly end the processing operation of the write request.

[0005] For example, in the data processing method provided by at least one embodiment of the present disclosure, in response to receiving a write request from the first cache to write the first data back to the memory, the cache consistency node writes the first data to the memory or discards the first data, including: in response to receiving the write request from the first cache to write the first data back to the memory, the cache consistency node determines whether the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side; and in response to determining that the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side, the cache consistency node writes the first data to the memory.

[0006] For example, in the data processing method provided by at least one embodiment of the present disclosure, after the cache coherence node writes the first data to the memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly end the processing operation of the write request, including: after the cache coherence node writes the first data to the memory, the memory returns a write response to the cache coherence node indicating that the first data has been written to the memory; and in response to receiving the write response from the memory indicating that the first data has been written to the memory, the cache coherence node returns the write response signal to the first cache indicating that the first data has been written back to the memory to directly end the processing operation of the write request.

[0007] For example, in the data processing method provided by at least one embodiment of the present disclosure, the data processing method also includes: after the cache consistency node writes the first data to the memory, the cache consistency node sets the data state of the first cache to an invalid state, a shared state or an exclusive state, wherein the invalid state indicates that the first cache does not cache the first data, the shared state indicates that the first cache and other caches both cache the first data, and the exclusive state indicates that the first data is cached only in the first cache.

[0008] For example, in the data processing method provided by at least one embodiment of the present disclosure, the data processing method further includes: in response to receiving a read request for the first data from the second cache and the cache consistency node side recording that the first data is in an exclusive state or a shared state in the first cache, the cache consistency node initiates a monitoring signal to the first cache; in response to the first cache receiving the monitoring signal after issuing the write request, the first cache returns a monitoring response carrying the first data to the cache consistency node in response to the monitoring signal.

[0009] For example, in the data processing method provided by at least one embodiment of the present disclosure, the data processing method also includes: in response to receiving the monitoring response, the cache consistency node returns the first data to the second cache; and after receiving the first data, the second cache returns a message to the cache consistency node indicating that the first data has been received to end the read request.

[0010] For example, in the data processing method provided by at least one embodiment of the present disclosure, in response to receiving the monitoring response, the cache consistency node returns the first data to the second cache, including: in response to receiving the monitoring response, the cache consistency node returns the first data to the second cache, and sets the data state of the second cache to an exclusive state, and the exclusive state indicates that the first data is only cached in the second cache.

[0011] For example, in the data processing method provided by at least one embodiment of the present disclosure, after the cache consistency node writes the first data to the memory or discards the first data, the cache consistency node returns a write response signal to the first cache to directly end the processing operation of the write request, including: after receiving the message, the cache consistency node discards the first data written by the write request on the cache consistency node side, and returns the write response signal to the first cache to directly end the processing operation of the write request.

[0012] For example, in the data processing method provided by at least one embodiment of the present disclosure, after receiving the message, the cache consistency node discards the first data written by the write request to the cache consistency node side, including: in response to determining that the first data written by the write request to the cache consistency node side is invalid data after receiving the message, the cache consistency node discards the first data written by the write request to the cache consistency node side.

[0013] At least one embodiment of the present disclosure also provides an electronic device, comprising multiple caches and cache consistency nodes, the multiple caches including a first cache, and the cache consistency node being configured to, in response to receiving a write request from the first cache to write the first data back to the memory, write the first data to the memory or discard the first data, and after the cache consistency node writes the first data to the memory or discards the first data, return a write response signal to the first cache to directly end the processing operation of the write request, wherein the write request carries the first data, and the cache consistency node is configured to maintain the consistency of the data stored in the multiple caches.

[0014] For example, in the electronic device provided by at least one embodiment of the present disclosure, the cache consistency node is further configured to: in response to receiving the write request from the first cache to write the first data back to the memory, determine whether the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side, and in response to determining that the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node side, write the first data to the memory.

[0015] For example, in the electronic device provided by at least one embodiment of the present disclosure, the memory is configured to: after the cache consistency node writes the first data to the memory, return a write response to the cache consistency node indicating that the first data has been written to the memory, and the cache consistency node is further configured to: in response to receiving the write response from the memory indicating that the first data has been written to the memory, return the write response signal to the first cache indicating that the first data has been written back to the memory to directly end the processing operation of the write request.

[0016] For example, in the electronic device provided by at least one embodiment of the present disclosure, the cache consistency node is further configured to: in response to receiving a read request for the first data from the second cache and the cache consistency node side recording that the first data is in an exclusive state or a shared state in the first cache, initiate a monitoring signal to the first cache, and the first cache is configured to: in response to the first cache receiving the monitoring signal after issuing the write request, return a monitoring response carrying the first data to the cache consistency node.

[0017] At least one embodiment of the present disclosure further provides a data processing device, comprising a memory and a processor, wherein the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the method described in any of the above embodiments.

[0018] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the method described in any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0020] Figure 1 A schematic diagram of an electronic device is shown.

[0021] Figure 2A A schematic diagram of an electronic device reading data is shown.

[0022] Figure 2B A schematic diagram of data write-back in an electronic device is shown.

[0023] Figure 3AA flow chart of a data processing method provided by at least one embodiment of the present disclosure is shown.

[0024] Figure 3B A schematic diagram of data write-back of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0025] Figure 4 A schematic diagram of read and write operations of an electronic device provided by at least one embodiment of the present disclosure when a read and write conflict occurs is shown.

[0026] Figure 5 A schematic diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0027] Figure 6 A schematic diagram of a data processing device provided by at least one embodiment of the present disclosure is shown.

[0028] Figure 7 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0031] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components.

[0032] During the operation of a computer system consisting of multiple processors (or processor cores) and multiple caches, data at the same address may be stored simultaneously in different caches. To ensure that data at the same address remains consistent across caches, a directory-based consistency protocol has been developed. This protocol tracks the state of data in the caches. For example, the directory storage structure can be implemented using static random access memory (SRAM), similar to the caches. For example, the directory storage structure can also be implemented using other forms of memory, as long as directory storage is feasible.

[0033] Figure 1 1 shows a schematic diagram of an electronic device (or electronic system) 100. Figure 1 As shown, the electronic device 100 may include multiple caches (hereinafter also referred to as "caches") 1~n, processors (or processor cores) 1~n, an interconnection network, cache consistency nodes 1~n, memories 1~n and directories 1~n, etc.

[0034] For example, each of caches 1-n is configured to store data storage information corresponding to at least one piece of data information. For example, caches 1-n may each include one or more sub-caches.

[0035] For example, cache coherence nodes 1-n can help track the status of cache data in caches 1-n respectively, including whether cache 1-n has only a single copy of the cache data, multiple copies of the cache data, or the data is only stored in main memory. Cache coherence nodes 1-n will track processors 1-n (for example, Figure 1 Each processor in the cache (including one or more sub-processors) tracks the status of caches 1-n and stores the tracked status information (or directory information) in directories 1-n. When a cache coherence node detects a coherence transaction while listening to the bus, it queries the tracked status information in directories 1-n and issues the corresponding probe to complete coherence maintenance.

[0036] For example, directories 1-n are configured to store directory information corresponding to data information stored in caches 1-n to maintain cache coherence. For example, the directory includes multiple storage groups, each of which can store multiple entries of directory information. For example, when directory information needs to be stored in the directory, the directory places the directory information into the corresponding storage group based on the mapping relationship.

[0037] For example, Figure 1 As shown, an interconnection network (e.g., a network on chip (NOC)) in the system is directly coupled to caches 1-n and also directly coupled to cache coherence nodes 1-n. The interconnection network is a public communication trunk for information transmission. For example, the interconnection network can be a transmission line bundle composed of electronic components such as wires.

[0038] For example, Figure 1 As shown, cache consistency nodes 1~n are configured to connect directories 1~n to the Internet respectively, and cache consistency nodes 1~n are configured to connect memories 1~n to the Internet respectively, so as to maintain the consistency of all data stored in caches 1~n.

[0039] For example, in a non-uniform memory access (NUMA) architecture, different processor (or processor core) and memory device combinations belong to different nodes. Therefore, a directory consistency-based design places a static random access memory (SRAM) directory structure near each memory controller. In a NUMA architecture, each node has its own local memory.

[0040] Figure 2A A schematic diagram of an electronic device reading data is shown. Figure 2B A schematic diagram of data write-back in an electronic device is shown.

[0041] For example, in Figure 2A In the example, master 0 can correspond to Figure 1 Any one of the caches 1 to n in the slave device can correspond to Figure 1 Any of the cache coherence nodes 1 to n in the MEM can correspond to Figure 1 Any one of the memories 1 to n in . For example, Figure 2A As shown, when master device 0 initiates an exclusive request RdE (see Table 2 below) to a slave device to obtain exclusive data, since a system (e.g., an electronic system) may have multiple master devices, the slave device needs to manage data consistency across the multiple master devices. For example, the slave device in the system can adopt a directory-based cache consistency protocol, which records which master device caches the data and the current status of the data in the corresponding master device.

[0042] For example, Figure 2A As shown, when the slave device receives an exclusive request RdE, and the directory corresponding to the current slave device side is, for example Figure 2A When the invalid state I represented by Dir@I in the table (see Table 1 below, for example, the invalid state I indicates that no master device currently caches this data (for example, the data corresponding to the address accessed by the request)), the slave device directly reads the main memory (for example, the memory) data by sending a read request Rdmem to the memory and receiving a data response rddat returned by the memory to the slave device, and returns an exclusive data response DatRspE (see Table 5 below) to the master device 0 as the requester, and sets the corresponding directory on the slave device side to E:Master0 (for example Figure 2AIn the example, Dir@E:Master0 is used to indicate this), thereby recording that the master device 0 caches this data and is in an exclusive state (E: Exclusive). After receiving the exclusive data response DatRspE, the master device 0 sends a message ACK to the slave device to end the read request.

[0043] The master device generally caches a lot of data, and in the event of overflow on the master device, the overflowed data needs to be written back to the slave device from the master device. Figure 2B As shown, when the cache data of master device 0 overflows, master device 0 initiates a write-back request to the slave device ( Figure 2B In the description, only WBI is used as an example, but it is not limited to this write-back request), and the data to be written back to the memory is sent to the slave device through the signal WrDat. After the slave device confirms that it has received the write-back data, it returns a write response WrRap to the master device 0. After receiving the write response WrRap, the master device 0 sends a message (or write response) ACK to the slave device. For example, Figure 2B As shown, after the slave receives the message ACK sent by master device 0, the corresponding directory status on the slave side is set from Dir@E:Master0 to Dir@1. For example, after receiving the message ACK, the slave side sends a write request Rdmem to the memory to write the data to be written back to the memory, and receives the data write response WrRap returned by the memory to the slave device, ending the write request.

[0044] In existing cache consistency protocols, both read and write transactions need to carry ACK messages. ACK messages extend the life cycle of transactions in the slave device, that is, the time the slave device buffer (for example, a cache or other storage area that can be used to implement a directory) is occupied becomes longer, which reduces the turnover rate of the slave device buffer and wastes resources. In addition, the transmission of ACK messages requires a certain amount of power consumption.

[0045] At least one embodiment of the present disclosure provides a data processing method. For example, the present disclosure provides a data processing method including: in response to receiving a write request from a first cache to write first data back to a memory, a cache coherence node writes the first data to the memory or discards the first data, wherein the write request carries the first data, and the cache coherence node is configured to maintain the consistency of data stored in multiple caches, the multiple caches including the first cache; and after the cache coherence node writes the first data to the memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly end the processing operation of the write request.

[0046] In the data processing method of the above-mentioned embodiment of the present disclosure, scenario identification is performed by comparing the write-back transaction and the directory. After the master device receives the write response, it directly ends the write transaction processing and no longer needs to send an ACK message to the slave device, thereby reducing the number of ACK messages, reducing the protocol's demand for ACK messages, reducing the power consumption and delay as well as bandwidth occupancy generated by the ACK message transmission, and optimizing the turnover rate of the buffer on the master device side. Under the same performance, the number of buffers required on the master device side is smaller, saving area and power consumption.

[0047] At least some embodiments of the present disclosure further provide an electronic device comprising multiple caches and a cache coherence node. The multiple caches include a first cache, the cache coherence node being configured to, in response to receiving a write request from the first cache to write the first data back to the memory, write the first data to the memory or discard the first data, and after the cache coherence node writes the first data to the memory or discards the first data, return a write response signal to the first cache to directly terminate the processing operation of the write request, wherein the write request carries the first data, and the cache coherence node is configured to maintain the consistency of the data stored in the multiple caches.

[0048] The technical effects of the electronic device of the above embodiment of the present disclosure are the same as the technical effects of the above data processing method, and therefore are not described in detail.

[0049] In the above embodiment, the first cache can be any cache among multiple caches, and the first data can be, for example, data corresponding to any accessed address, that is, the "first" (and "second", etc.) here is only used to identify the cache or data as the description object, rather than specifically referring to a specific cache or data.

[0050] The various embodiments of the present disclosure will be described below with reference to specific examples.

[0051] Figure 3A FIG. 1 is a flow chart showing a data processing method provided by at least one embodiment of the present disclosure. Figure 3A As shown, in some embodiments of the present disclosure, the data processing method includes the following steps S101-S102.

[0052] Step S101, in response to receiving a write request from a first cache to write first data back to a memory, the cache consistency node writes the first data to the memory or discards the first data, wherein the write request carries the first data, and the cache consistency node is configured to maintain consistency of data stored in multiple caches, and the multiple caches include the first cache.

[0053] Step S102: After the cache coherence node writes the first data into the memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly end the processing operation of the write request.

[0054] Figure 3B A schematic diagram of data write-back of an electronic device provided by at least one embodiment of the present disclosure is shown. Figure 3B As shown, in response to receiving a write request from a first cache (or "master device 0") to write first data back to the memory, the cache coherence node (or "slave device") writes the first data to the memory MEM. For example, the write request carries the first data, and the cache coherence node is configured to maintain the consistency of data stored in multiple caches, including the first cache. For example, after the cache coherence node writes the first data to the memory MEM, the cache coherence node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.

[0055] Figure 4 FIG. 1 shows a schematic diagram of a read / write operation of an electronic device provided by at least one embodiment of the present disclosure when a read / write conflict occurs. Figure 4 As shown, in response to receiving a write request from a first cache (or "master device 0") to write first data back to the memory, the cache coherence node (or "slave device") discards the first data. For example, the write request carries the first data, and the cache coherence node is configured to maintain the consistency of data stored in multiple caches, including the first cache. For example, after the cache coherence node discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.

[0056] It should be noted that although the present disclosure Figure 3B and Figure 4 The specific first cache (e.g., master device 0), the second cache (e.g., master device 1), the cache consistency node (e.g., slave device) and the memory (e.g., MEM) and their related specific operations are shown in the figure, but the contents shown in the figure are only exemplary to facilitate the description of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited to this, and any other operations that can be thought of based on the specific examples of the present disclosure are included in the scope of the present disclosure.

[0057] The following is an exemplary description of some provisions of the cache coherence protocol of the embodiment of the present disclosure in conjunction with Tables 1-9.

[0058] For example, the master device (or cache) specified in the protocol of the embodiment of the present disclosure has multiple states, as shown in Table 1:

[0059] Table 1

[0060]

[0061]

[0062] For example, in Table 1, the cache state may be the state of the first cache, and the main memory may be the memory MEM. For example, the first cache may include the M state, the E state, the S state, and the I state. The M state indicates that the first cache exclusively owns the corresponding data and the data has been modified; the E state indicates that the first cache exclusively owns the corresponding data and the data has not been modified; the S state indicates that the first cache shares the corresponding data with other master devices; and the I state indicates that the first cache does not cache the corresponding data. For example, when the first cache is in the M state, since the first cache has modified the corresponding data, the corresponding data in the memory MEM is invalid. At this time, the other caches are all in the I state where the modified data is not cached; when the first cache is in the E state, the other caches are all in the I state where the data is not cached; when the first cache is in the S state, there are other caches in the S state where the data is shared; when the first cache is in the I state, the other caches can be in any of the M state, the E state, the S state, and the I state.

[0063] It should be noted that, in the embodiment of the present disclosure, the state of the master device (eg, the first cache) is not limited to the four states listed above, and the master device may have other different states according to different needs.

[0064] For example, Table 2 shows the request types that can be issued by the master device as specified in the protocol of the present disclosure, as well as the corresponding cache state transitions and slave device response messages.

[0065] Table 2

[0066]

[0067]

[0068] The following description is made by taking the case where the master device is the first cache as an example.

[0069] For example, in Table 2, the request type may be a request type initiated by the first cache to the slave device. For example, the read request types that the first cache may initiate may include RdE (obtaining an exclusive data copy), RdD (obtaining a data copy in a non-I state, i.e., caching this data copy), RdS (obtaining a shared data copy), RdI (obtaining a data snapshot, not caching this data copy), and RdEE (obtaining exclusive data permission, not acquiring data). The embodiments of the present disclosure are not limited thereto, and the first cache may also initiate other different read request types as needed.

[0070] For example, when the read request type initiated by the first cache to the slave device is RdE, the cache state (or cache data state) when the first cache initiates the request can be I state, S state or E state; when the RdE request ends, the cache state of the first cache can be E state (in this case, the slave device returns a response DatRspE (see Table 6 below) to the first cache, so that the slave device obtains a response of an exclusive data copy) or M state (in this case, the slave device returns a response DatRspM (see Table 6 below), so that the slave device obtains a response of a modified data copy). For example, when the read request type initiated by the first cache to the slave device is RdD, the cache state of the first cache when initiating the request may be I state; when the RdD request ends, the cache state of the first cache may be S state (in this case, the slave device returns a response DatRspS to the first cache (see Table 6 below), so that the slave device obtains a response of a copy of the shared data), E state (in this case, the slave device returns a response DatRspE to the first cache), or M state (in this case, the slave device returns a response DatRspM to the first cache). For example, when the read request type initiated by the first cache to the slave device is RdS, the cache state of the first cache when initiating the request may be I state; when the RdS request ends, the cache state of the first cache may be S state (in this case, the slave device returns a response DatRspS to the first cache). For example, when the read request type initiated by the first cache to the slave device is RdI, the cache state of the first cache when initiating the request may be I state; when the RdI request ends, the cache state of the first cache may be I state (in this case, the slave device returns a response DatRspI (see Table 6 below) to the first cache, so that the slave device obtains a response of a data copy). For example, when the read request type initiated by the first cache to the slave device is RdEE, the cache state of the first cache when initiating the request may be I state or S state; when the RdEE request ends, the cache state of the first cache may be E state (in this case, the slave device returns a response RspE (see Table 6 below), so that the slave device obtains a response of exclusive permission).

[0071] For example, in Table 2, the write request types that can be initiated by the first cache may include WBI (writing a cached copy of data back to the main memory, setting the cache to the invalid I state), WBS (writing a cached copy of data back to the main memory, setting the cache to the shared S state), and WBE (writing a cached copy of data back to the main memory, setting the cache to the exclusive E state). The embodiments of the present disclosure are not limited to this, and the first cache may also initiate other different write request types as needed.

[0072] For example, when the write request type initiated by the first cache to the slave device is WBI, the cache state of the first cache when initiating the request may be M; when the write request WBI ends, the cache state of the first cache may be I (in this case, the slave device returns a response WrRsp to the first cache). For example, when the write request type initiated by the first cache to the slave device is WBS, the cache state of the first cache when initiating the request may be M; when the write request WBS ends, the cache state of the first cache may be I (in this case, the slave device returns a response WrRsp to the first cache) or S (in this case, the slave device returns a response WrRsp to the first cache). For example, when the write request type initiated by the first cache to the slave device is WBE, the cache state of the first cache when initiating the request may be M; when the write request WBE ends, the cache state of the first cache may be I (in this case, the slave device returns a response WrRsp to the first cache), S (in this case, the slave device returns a response WrRsp to the first cache), or E (in this case, the slave device returns a response WrRsp to the first cache).

[0073] For example, in Figure 3B and Figure 4 In the embodiment, the first cache write request is not limited to WBI, and the write request may also be WBS or WBE as shown in Table 2. For example, when the cache data of the first cache overflows, the first cache may initiate a write request WBI to the slave device. In response to receiving the write request WBI from the first cache to write the first data back to the memory MEM, the cache coherence node writes the first data into the memory MEM (e.g., Figure 3B As shown) or discard the first data (as shown Figure 4 As shown). For example, after the cache coherence node writes the first data into the memory MEM or discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request. For example, when the cache data of the first cache overflows, the first cache can initiate a write request WBS to the slave device. In response to receiving the write request WBS from the first cache to write the first data back to the memory MEM, the cache coherence node writes the first data into the memory MEM (as shown). Figure 3B As shown) or discard the first data (as shown Figure 4 As shown). For example, after the cache coherence node writes the first data into the memory MEM or discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request. For example, when the cache data of the first cache overflows, the first cache can initiate a write request WBE to the slave device. In response to receiving the write request WBE from the first cache to write the first data back to the memory MEM, the cache coherence node writes the first data into the memory MEM (as shown). Figure 3B As shown) or discard the first data (as shown Figure 4 For example, after the cache coherence node writes the first data into the memory MEM or discards the first data, the cache coherence node returns a write response signal WrRsp to the first cache to directly end the processing operation of the write request.

[0074] For example, in response to receiving a write request from the first cache to write the first data back to the memory MEM, the cache coherence node determines whether the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache coherence node side, and in response to determining that the first cache is the same as the cache that currently exclusively owns the first data recorded on the cache coherence node side, the cache coherence node writes the first data to the memory MEM.

[0075] For example, Figure 3B As shown, in response to receiving a write request from the master device 0 to write the first data back to the memory MEM, the slave device determines whether the master device 0 is the same as the cache currently exclusively occupying the first data recorded on the slave device side. Figure 3B As shown in , in response to determining that the cache of the current exclusive first data recorded by the master device 0 is the same as that recorded by the slave device side (for example, the slave device side records Src:Master0==Dir@E:Master0), the slave device writes the first data back to the memory MEM through a write memory operation Wrmem. After receiving the write memory operation Wrmem, the memory MEM returns a write response WrRsp to the cache consistency node to indicate to the slave device that the memory MEM has successfully received the first data. For example, in response to determining that the cache of the current exclusive first data recorded by the master device 0 is not the same as that recorded by the slave device side (for example, the slave device side records Src:Master0!=Dir@E:Master0), it is determined that the slave device does not have permission to write the first data to the memory MEM, and the slave device does not perform the operation of writing the first data to the memory MEM.

[0076] For example, after the cache coherence node writes the first data to the memory, the memory returns a write response to the cache coherence node indicating that the first data has been written to the memory, and in response to receiving a write response from the memory indicating that the first data has been written to the memory, the cache coherence node returns a write response signal to the first cache indicating that the first data has been written back to the memory to directly end the processing operation of the write request.

[0077] For example, Figure 3BAs shown, after the slave device writes the first data to the memory MEM, the memory MEM returns a write response WrRsp to the slave device indicating that the first data has been written to the memory MEM. In response to receiving the write response WrRsp from the memory MEM indicating that the first data has been written to the memory MEM, the slave device returns a write response signal WrRsp to the master device 0 indicating that the first data has been written back to the memory MEM, thereby directly terminating the processing operation of the write request. For example, at this time, the master device 0 directly terminates the processing operation of the write request without sending a message to the slave device.

[0078] For example, after the cache coherence node writes the first data into the memory, the cache coherence node sets the data state of the first cache to an invalid state, a shared state, or an exclusive state. For example, the invalid state indicates that the first cache does not cache the first data, the shared state indicates that the first cache and other caches cache the first data, and the exclusive state indicates that only the first cache caches the first data.

[0079] For example, after the slave device writes the first data back to the memory MEM, the slave device changes the data state of the first cache (e.g., master device 0) among the multiple caches to an invalid state (I state), a shared state (S state), or an exclusive state (e.g., E state). For example, the invalid state indicates that the first cache does not cache the first data, the shared state indicates that the first cache and other caches cache the first data, and the exclusive state indicates that only the first cache caches the first data.

[0080] For example, as shown in Table 2 above, if the first cache initiates a write request WBI to the slave device, then when the write request WBI ends, the cache state of the first cache may be I state. For example, if the first cache initiates a write request WBS to the slave device, then when the write request WBS ends, the cache state of the first cache may be I state (e.g., after the first cache writes the data back to the memory MEM, the data cached in the first cache is replaced by other data) or S state (e.g., after the first cache writes the data back to the memory MEM, the data cached in the first cache is not replaced by other data). For example, if the first cache initiates a write request WBE to the slave device, then when the write request WBE ends, the cache state of the first cache may be I state (e.g., after the first cache writes the data back to the memory MEM, the data cached in the first cache is replaced by other data), S state (e.g., the data written back to the memory MEM by the first cache is shared by other caches), or E state (e.g., the data written back to the memory MEM by the first cache is not shared by other caches, and after the first cache writes the data back to the memory MEM, the data cached in the first cache is not replaced by other data).

[0081] For example, Figure 4As shown, in response to receiving a read request for the first data from the second cache (or "master device 1") and the cache consistency node side (for example, from the directory corresponding to the device) recording that the first data is in an exclusive state or a shared state in the first cache (or "master device 0"), the cache consistency node initiates a monitoring signal (for example, ExpI) to the first cache; in response to the first cache receiving the monitoring signal after issuing a write request, the first cache returns a monitoring response (for example, ExpRspIDat) carrying the first data to the cache consistency node in response to the monitoring signal.

[0082] For example, Table 3 shows the monitoring signal types and their descriptions specified in the protocol of the present disclosure. The detection signal Exp* is used to monitor the cache status and data at the master device and set the monitored master device to a corresponding state.

[0083] Table 3

[0084]

[0085] Table 4 shows the monitoring response types specified in the protocol of the present disclosure, that is, the monitoring responses that the master device may return to the slave device when being monitored by the detection signal Exp*.

[0086] Table 4

[0087] Monitoring response type illustrate ExpRspI There is no data monitoring response, and the monitored cache is set to I state. ExpRspS If there is no data monitoring response, the monitored cache is set to S state. ExpRspE There is no data monitoring response, and the monitored cache is set to E / M state. ExpRspIDat There is a data monitoring response, and the monitored cache is set to I state. ExpRspSDat There is a data monitoring response, and the monitored cache is set to S state. ExpRspEDat There is a data monitoring response, and the monitored cache is set to E / M state.

[0088] Table 5 shows the non-monitoring response transaction types and their descriptions specified in the protocol of this disclosure.

[0089] Table 5

[0090]

[0091]

[0092] Table 6 is a state transition table of monitoring transactions on the master device side and monitoring response actions specified in the protocol of the present disclosure, which defines the target states that the master device side cache may transition to after being monitored, and sends corresponding monitoring response messages.

[0093] Table 6

[0094]

[0095] For example, as shown in Table 6, when the first cache receives the detection signal ExpI, if the current cache state of the first cache is I, S, E, or M, the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI (for example, when the current state of the first cache is I) or ExpRspIDat (for example, when the current state of the first cache is S, E, or M) to the cache coherence node.

[0096] For example, when the first cache receives the detection signal ExpS, if the current cache state of the first cache is I, the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI to the cache consistency node; when the first cache receives the detection signal ExpS, if the current cache state of the first cache is S, the state of the first cache after processing the monitoring signal is S, and the first cache returns a detection response ExpRspS to the cache consistency node; when the first cache receives the detection signal ExpS, if the current cache state of the first cache is E or M, the state of the first cache after processing the monitoring signal is S, and the first cache returns a detection response ExpRspS to the cache consistency node (for example, when the first cache executes a write request WBS or WBE) or ExpRspSDat (for example, when the first cache executes a write request WBI).

[0097] For example, when the first cache receives the detection signal ExpE, if the current cache state of the first cache is I, the state of the first cache after processing the monitoring signal is I, and the first cache returns a detection response ExpRspI to the cache consistency node; when the first cache receives the detection signal ExpE, if the current cache state of the first cache is S, the state of the first cache after processing the monitoring signal is S, and the first cache returns a detection response ExpRspS to the cache consistency node; when the first cache receives the detection signal ExpE, if the current cache state of the first cache is E or M, the state of the first cache after processing the monitoring signal is E or M, and the first cache returns a detection response ExpRspE (for example, when the first cache executes a write request WBS or WBE) or ExpRspEDat (for example, when the first cache executes a write request WBI) to the cache consistency node.

[0098] Table 7 shows the situation where the monitoring transaction specified in the protocol of the present disclosure is processed on the master device side and there is a conflict, that is, when the monitoring transaction reaches the master device, the master device has currently initiated a read transaction (or read request) Rd* or a write transaction (or write request) WB* for the cache line of the same address.

[0099] Table 7

[0100]

[0101] For example, as shown in Table 7, when the detection signal sent by the cache coherence node to the first cache is ExpI, and when the monitoring transaction arrives at the first cache, the first cache has already initiated a read transaction Rd* for the cache line of the same address, if the current state of the first cache is I, S or E, then after processing the monitoring signal, the state of the first cache is I, and the first cache returns a detection response ExpRspI (for example, when the state of the master device is I) or ExpRspIDat (for example, when the state of the first cache is S or E) to the cache coherence node; when the detection signal sent by the cache coherence node to the first cache is ExpI, and when the monitoring transaction arrives at the first cache, the first cache has already initiated a write transaction WB* for the cache line of the same address, if the current state of the first cache is M, then the first cache returns a detection response ExpRsplDat to the cache coherence node, and the state of the first cache after processing the monitoring signal is I.

[0102] For example, as shown in Table 7, when the detection signal sent by the cache coherence node to the first cache is ExpS, and when the monitoring transaction arrives at the first cache, the first cache has already initiated a read transaction Rd* for the cache line of the same address, if the current state of the first cache is I, S or E, then after processing the monitoring signal, the state of the first cache is I, and the first cache returns a detection response ExpRspI (for example, when the state of the first cache is I) or ExpRspIDat (for example, when the state of the first cache is S or E) to the cache coherence node; when the detection signal sent by the cache coherence node to the first cache is ExpS, and when the monitoring transaction arrives at the first cache, the first cache has already initiated a read transaction WB* for the cache line of the same address, if the current state of the first cache is M, the first cache returns a detection response ExpRsplDat to the cache coherence node, and the state of the first cache after processing the monitoring signal ExpS is I.

[0103] For example, as shown in Table 7, when the detection signal sent by the cache coherence node to the first cache is ExpE, and when the monitoring transaction arrives at the first cache, the first cache has already initiated a read transaction Rd* for the cache line of the same address, if the current state of the first cache is I, S or E, then after processing the monitoring signal, the state of the first cache is I, and the first cache returns a detection response ExpRspI (for example, when the state of the first cache is I) or ExpRspIDat (for example, when the state of the first cache is S or E) to the cache coherence node; when the detection signal sent by the cache coherence node to the first cache is ExpE, and when the monitoring transaction arrives at the first cache, the first cache has already initiated a read transaction WB* for the cache line of the same address, if the current state of the first cache is M, the first cache returns a detection response ExpRsplDat to the cache coherence node, and the state of the first cache after processing the monitoring signal ExpE is I.

[0104] Table 8 defines the state transition that may need to be performed based on the directory status after the slave device receives a read or write request from the master device according to the protocol of the present disclosure (including triggering a monitoring command, returning a response command to the master device, or reading and writing memory data).

[0105] Table 8

[0106]

[0107]

[0108] For example, as shown in Table 8, in response to receiving a read request RdE for the first data from the second cache and the first data being in the I state in the directory corresponding to the cache coherence node, the cache coherence node directly reads the first data from the memory and returns the first data to the second cache. For example, in response to receiving a read request RdE for the first data from the second cache and the cache coherence node side (for example, from the directory corresponding to the device) records that the first data is in the S state or the exclusive state E in the directory corresponding to the cache coherence node, the cache coherence node initiates a monitoring signal ExpI to the first cache (monitoring the target cache, obtaining the latest data copy, and setting its cached data to an invalid state).

[0109] For example, in response to receiving the monitoring response, the cache coherence node returns the first data to the second cache, and after receiving the first data, the second cache returns a message to the cache coherence node indicating that the first data has been received to end the read request. Figure 4 As shown, in response to receiving the monitoring response ExpRspIDat, the slave device returns the first data to the master device 1 (for example, through the response signal DatRspM) in response to the monitoring response ExpRspIDat, and sets the data state of the master device 1 on the slave device side to an exclusive state (for example, the slave device side records Dir@E:Master1). The exclusive state (or Dir@E:Master1) indicates that the first data is cached only in the master device 1. For example, after receiving the first data, the master device 1 returns a message ACK to the slave device indicating that the first data has been received, thereby ending the read request RdE.

[0110] For example, after receiving the message, the cache coherence node discards the first data written by the write request to the cache coherence node side, and returns a write response signal to the first cache to directly end the processing operation of the write request. Figure 4As shown, after the slave device receives the message ACK from the master device 1, the read request RdE previously issued by the master device is processed and completed, and the slave device side is in a blocked state (after the slave device processes the read request initiated by the master device 1, it is in a blocked state (that is, since the slave device can only process one transaction with the same address at the same time, the write request WB* initiated by the master device 0 is always in a blocked state before the RdE processing of the master device 1 is completed)). The write request WB* previously issued by the master device 0 is awakened and continued to be processed. At this time, since the slave device side records that the master device 1 has obtained the exclusive state of the first data, and the write request is initiated by the master device 0, the data in the write transaction of the master device 0 is already expired and invalid data, so the slave device determines that this write transaction or write operation should be invalid data due to the conflict (such as Figure 4 As shown in , Src:Master0!=Dir@E:Master1, that is, the master device 0 requesting the write back is not the master device 1 that the slave device exclusively uses for the first data. Therefore, the data already written by master device 0 to the slave device is directly discarded. For example, if the slave device determines that the first data written to the slave device by the write request is invalid, the slave device discards the first data written to the slave device by the write request and returns a write response signal WrRsp to master device 0 to directly terminate the processing of the write request. For example, after receiving the write response signal WrRsp, the slave device directly terminates the corresponding write transaction processing without sending an ACK message to the slave device.

[0111] For example, in response to receiving a read request RdD, RdS, or RdI for the first data from the second cache and the first data is in the I state or the S state in the directory corresponding to the cache consistency node, the cache consistency node can directly read the first data from the memory and return the first data to the second cache. For example, in response to receiving a read request RdD, RdS, or RdI for the first data from the second cache and the cache consistency node side (for example, from the directory corresponding to the device) records that the first data is in the exclusive state E in the directory corresponding to the cache consistency node, the cache consistency node initiates a monitoring signal ExpS to the first cache (monitoring the target cache, obtaining the latest data copy, and setting its cached data to an invalid or shared state).

[0112] For example, in response to receiving the monitoring response, the cache coherence node returns the first data to the second cache, and after receiving the first data, the second cache returns a message to the cache coherence node indicating that the first data has been received to end the read request. Figure 4As shown, in response to receiving the monitoring response ExpRspIDat, the slave device returns the first data to the master device 1 in response to the monitoring response ExpRspIDat (for example, through the response signal DatRspM), and sets the data state of the master device 1 on the slave device side to an exclusive state (for example, the slave device side records Dir@E:Master1). The exclusive state (or Dir@E:Master1) indicates that the first data is cached only in the master device 1. For example, after receiving the first data, the master device 1 returns a message ACK to the slave device indicating that the first data has been received, thereby ending the read request (for example, RdD or RdS).

[0113] For example, after receiving the message, the cache coherence node discards the first data written by the write request to the cache coherence node side, and returns a write response signal to the first cache to directly end the processing operation of the write request. Figure 4 As shown, after the slave device receives the message ACK from the master device 1, the read request RdD, RdS or RdI previously issued by the master device is processed, and the write request WB* previously issued by the master device 0 in the blocked state on the slave device side is awakened to continue processing. At this time, since the slave device side records that the master device 1 has obtained the exclusive state or shared state of the first data, and the write request is initiated by the master device 0, the data in the write transaction of the master device 0 is already expired and invalid data, so the slave device determines that this write transaction or write operation should be invalid data due to the conflict, and directly discards the data that has been written to the slave device by the master device 0. For example, the slave device determines that the first data written by the write request to the slave device side is invalid data, the slave device discards the first data written by the write request to the slave device side, and returns a write response signal WrRsp to the master device 0 to directly end the processing operation of the write request. For example, after the slave device receives the write response signal WrRsp, it directly ends the corresponding write transaction processing without sending the message ACK again.

[0114] For example, in response to receiving a read request RdEE for the first data from the second cache and the first data is in the I state in the directory corresponding to the cache consistency node, the cache consistency node returns a response RspE (no data monitoring response, the monitored cache is set to the E state or the M state) to the second cache to end the read request RdEE. For example, in response to receiving a read request RdEE for the first data from the second cache and the cache consistency node side (for example, from the directory corresponding to the device) records that the first data is in the S state or the exclusive state E in the directory corresponding to the cache consistency node, the cache consistency node initiates a monitoring signal ExpE to the first cache (monitoring the target cache, obtaining the latest data copy, and not changing its cache data state).

[0115] For example, in response to receiving the monitoring response, the cache coherence node returns the first data to the second cache, and after receiving the first data, the second cache returns a message to the cache coherence node indicating that the first data has been received to end the read request. Figure 4 As shown, in response to receiving the monitoring response ExpRspIDat, the slave device returns the first data to the master device 1 (for example, through the response signal DatRspM) in response to the monitoring response ExpRspIDat. For example, after receiving the first data, the master device 1 returns a message ACK to the slave device indicating that the first data has been received to end the read request RdEE.

[0116] For example, after receiving the message, the cache coherence node discards the first data written by the write request to the cache coherence node side, and returns a write response signal to the first cache to directly end the processing operation of the write request. Figure 4 As shown, after the slave device receives the message ACK from the master device 1, the read request RdEE previously issued by the master device is processed, and the write request WB* previously issued by the master device 0 in the blocked state on the slave device side is awakened to continue processing. At this time, since the slave device side records that the master device 0 is no longer in the state of exclusive possession of the first data, and the write request is initiated by the master device 0, the data in the write transaction of the master device 0 is already expired and invalid data, so the slave device determines that this write transaction or write operation should be invalid data due to the conflict, and directly discards the data that has been written to the slave device by the master device 0. For example, the slave device determines that the first data written by the write request to the slave device side is invalid data, the slave device discards the first data written by the write request to the slave device side, and returns a write response signal WrRsp to the master device 0 to directly end the processing operation of the write request. For example, after the slave device receives the write response signal WrRsp, it directly ends the corresponding write transaction processing without sending the message ACK again.

[0117] For example, in response to receiving a write request (e.g., WBI, WBS, or WBE) for data sent by the second cache to the cache coherence node, no matter what state the directory is in at this time (e.g., I, S, or E), the detection signal will not be triggered, and the cache coherence node will return a response WrRsp to the second cache. For example, if the data that the second cache needs to write is recorded in an exclusive state by the cache coherence node and points to the second cache that initiated the write request WBI, the data is written to the memory; otherwise, the data is discarded.

[0118] Table 9 is a state transition table after the slave device receives a response from the master device as specified in the protocol of the present disclosure.

[0119] Table 9

[0120]

[0121] For example, as shown in Table 9, if the first cache sends a response signal ExpRspI, ExpRspS, or ExpRspE to the cache coherence node, and the cache coherence node receives any type of read request from the second cache (for example, the cache coherence node creates a read request transaction table entry in response to receiving the read request from the second cache, and records the status related to the current read request transaction), then after receiving the response signal ExpRspI, ExpRspS, or ExpRspE sent by the first cache to the cache coherence node, the cache coherence node needs to read the memory data. For example, after the cache coherence node reads the memory data, it sends the data to the second cache and sets the status of the read request transaction table entry corresponding to the read request from the second cache to a waiting for confirmation state (for example, WaitACK), waiting for the second cache to send an acknowledgment signal (ACK) confirming that the data has been successfully received.

[0122] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdI (for example, the cache coherence node creates a read request transaction processing table entry in response to receiving the read request RdI from the second cache, and records the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspI carrying data to the second cache, and sets the status of the read request transaction processing table entry corresponding to the read request RdI of the second cache to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.

[0123] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdS (for example, after the cache coherence node responds to receiving the read request RdS from the second cache, it creates a read request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspS carrying data to the second cache, and sets the status of the read request transaction processing table entry corresponding to the read request RdS of the second cache to a waiting for confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.

[0124] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdD (for example, after the cache coherence node responds to receiving the read request RdD from the second cache, it creates a read request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspE (recording that the second cache exclusively owns this data) or DatRspM (recording that the second cache exclusively owns this modified data) carrying data to the second cache, and sets the status of the read request transaction processing table entry corresponding to the read request RdD of the second cache to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.

[0125] For example, as shown in Table 9, if the first cache sends a response signal ExpRspIDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdE (for example, after the cache coherence node responds to receiving the read request RdE from the second cache, it creates a read request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ExpRspIDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspE (recording that the second cache exclusively owns this data) or DatRspM (recording that the second cache exclusively owns this modified data) carrying data to the second cache, and sets the status of the read request transaction processing table entry corresponding to the read request RdE of the second cache to a waiting confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.

[0126] For example, as shown in Table 9, if the first cache sends a response signal ExpRspSDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdS or RdD (for example, after the cache coherence node responds to receiving the read request RdS or RdD from the second cache, it creates a read request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ExpRspSDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspS carrying data to the second cache (recording that the second cache shares this data), and sets the status of the read request transaction processing table entry corresponding to the read request RdS or RdD of the second cache to a waiting for confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.

[0127] For example, as shown in Table 9, if the first cache sends a response signal ExpRspEDat to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request RdI (for example, after the cache coherence node responds to receiving the read request RdI from the second cache, it creates a read request transaction processing table entry and records the status related to the current read request transaction), then after receiving the response signal ExpRspEDat sent by the first cache to the cache coherence node, the cache coherence node sends a response signal DatRspI carrying data to the second cache (recording that the second cache obtains a copy of this data), and sets the status of the read request transaction processing table entry corresponding to the read request RdI of the second cache to a waiting for confirmation state (for example, WaitACK), waiting for the second cache to send a confirmation signal (ACK) confirming that the data has been successfully received.

[0128] For example, as shown in Table 9, if the first cache sends a response signal ACK to the cache coherence node, and the request type received by the cache coherence node from the second cache is a read request Rd* (for example, after the cache coherence node responds to receiving the read request Rd* from the second cache, it creates a read request transaction processing table entry or a write request transaction processing table entry to record the status related to the current read request transaction), then after receiving the response signal ACK sent by the first cache to the cache coherence node, the cache coherence node sets the status of the read request transaction processing table entry to the end state to confirm that the data reading has been successfully completed.

[0129] In the data processing method of the embodiment of the present invention, scenario identification is performed by comparing the write-back transaction and the directory. After the master device receives the write response, it directly ends the write transaction processing and does not need to send an ACK message to the slave device, thereby reducing the number of ACK messages, reducing the protocol's demand for ACK messages, reducing the power consumption and delay generated by the ACK message transmission, and reducing the bandwidth occupancy. It also optimizes the turnover rate of the buffer on the master device side. Under the same performance, the master device side requires fewer buffers, saving area and power consumption.

[0130] Figure 5 A schematic diagram of an electronic device 60 provided by at least one embodiment of the present disclosure is shown. For example, the electronic device 60 includes a cache consistency node 605, a first cache 606, and a second cache 607. For example, the cache consistency node 605 is configured to write the first data to the memory or discard the first data in response to receiving a write request from the first cache 606 to write the first data back to the memory, and after the cache consistency node 605 writes the first data to the memory or discards the first data, return a write response signal to the first cache 606 to directly end the processing operation of the write request. For example, the write request carries the first data, and the cache consistency node 605 is configured to maintain the consistency of the data stored in multiple caches. The cache included in the electronic device 60 of the present disclosure is not limited to Figure 5 The two caches (a first cache 606 and a second cache 607) are shown in FIG. , and the number of electronic devices 60 can be set to any number as needed.

[0131] For example, the cache consistency node 605 is further configured to: in response to receiving a write request from the first cache 606 to write the first data back to the memory, determine whether the first cache 606 is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node 605 side, and in response to determining that the first cache 606 is the same as the cache that currently exclusively owns the first data recorded on the cache consistency node 605 side, write the first data to the memory.

[0132] For example, the memory is configured to: after the cache coherence node 605 writes the first data into the memory, return a write response indicating that the first data has been written into the memory to the cache coherence node 605. For example, the cache coherence node 605 is further configured to: in response to receiving the write response indicating that the first data has been written into the memory from the memory, return a write response signal indicating that the first data has been written back into the memory to the first cache 606, thereby directly ending the processing operation of the write request.

[0133] For example, the cache coherence node 605 is further configured to: after the cache coherence node 605 writes the first data into the memory, set the data state of the first cache 606 to an invalid state, a shared state, or an exclusive state. For example, the invalid state indicates that the first cache 606 does not cache the first data, the shared state indicates that the first cache 606 and other caches cache the first data, and the exclusive state indicates that only the first cache 606 caches the first data.

[0134] For example, cache coherence node 605 is further configured to: in response to receiving a read request for the first data from second cache 607 and cache coherence node 605 recording that the first data is in an exclusive state or a shared state in first cache 606, initiate a monitoring signal to first cache 606. For example, first cache 606 is configured to: in response to receiving the monitoring signal after first cache 606 issues a write request, return a monitoring response carrying the first data to cache coherence node 605.

[0135] For example, cache coherence node 605 is further configured to, in response to receiving the monitoring response, return the first data to second cache 607. For example, after receiving the first data, second cache 607 is further configured to return a message to cache coherence node 605 indicating that the first data has been received to end the read request.

[0136] For example, the cache coherence node 605 is further configured to: in response to receiving the monitoring response, return the first data to the second cache 607 and set the data state of the second cache 607 to exclusive. For example, the exclusive state indicates that only the second cache 607 caches the first data.

[0137] For example, the cache coherence node 605 is further configured to: after receiving the message, discard the first data written by the write request to the cache coherence node 605 side, and return a write response signal to the first cache 606 to directly end the processing operation of the write request.

[0138] For example, the cache coherence node 605 is further configured to: in response to determining that the first data written by the write request to the cache coherence node 605 side is invalid data after receiving the message, discard the first data written by the write request to the cache coherence node 605 side.

[0139] In the electronic device 60 of the embodiment of the present disclosure, scenario identification is performed by comparing the write-back transaction and the directory. After receiving the write response, the master device directly ends the write transaction processing and does not need to send an ACK message to the slave device, thereby reducing the number of ACK messages, reducing the protocol's demand for ACK messages, reducing the power consumption and delay generated by the ACK message transmission, and reducing the bandwidth occupancy. It also optimizes the turnover rate of the buffer on the master device side. Under the same performance, the master device side requires fewer buffers, saving area and power consumption.

[0140] At least some embodiments of the present disclosure further provide a data processing device comprising a memory and a processor. For example, the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions. For example, when the computer-executable instructions are executed by the processor, the data processing method provided in at least one embodiment of the present disclosure is implemented.

[0141] Figure 6 A schematic diagram of a data processing device 500 provided by at least one embodiment of the present disclosure is shown.

[0142] like Figure 6 As shown, the electronic device 500 according to an embodiment of the present disclosure includes a processor 501 and a memory 502 , and the processor 501 and the memory 502 may be interconnected via a bus 503 .

[0143] The processor 501 can perform various actions and processes according to the program or code stored in the memory 502. Specifically, the processor 501 can be an integrated circuit chip with signal processing capabilities. For example, the above-mentioned processor 501 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the various methods and steps disclosed in the embodiments of the present disclosure. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can be an X86 architecture or an ARM architecture, etc.

[0144] The memory 502 is used to non-temporarily store computer-executable instructions, and the processor 501 is used to run the computer-executable instructions. When the computer-executable instructions are executed by the processor 501, the data processing method provided by at least one embodiment of the present disclosure is implemented.

[0145] For example, memory 502 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memory. Non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. Volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0146] In the data processing device 500 of the embodiment of the present disclosure, scenario identification is performed by comparing the write-back transaction and the directory. After the master device receives the write response, it directly ends the write transaction processing and does not need to send an ACK message to the slave device, thereby reducing the number of ACK messages, reducing the protocol's demand for ACK messages, reducing the power consumption and delay as well as bandwidth occupancy generated by the ACK message transmission, and optimizing the turnover rate of the master device side buffer. Under the same performance, the master device side requires fewer buffers, saving area and power consumption.

[0147] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, the data processing method provided by at least one embodiment of the present disclosure is implemented.

[0148] Figure 7 Schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Figure 7 As shown, the non-transitory storage medium 600 can non-transitory store computer-executable instructions 610 , which implement the data processing method provided by any embodiment of the present disclosure when executed by a computer.

[0149] Similarly, the non-transitory storage medium in the embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0150] The technical effects of the above-mentioned non-transitory storage medium are the same as the technical effects of the above-mentioned data processing method, and will not be repeated here.

[0151] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to the various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, and the module, program segment, or part of the code contains at least one executable instruction for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions.

[0152] In general, various example embodiments of the present disclosure may be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device. When various aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other graphical representation, it will be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented, as non-limiting examples, in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or a controller or other computing device, or some combination thereof.

[0153] Regarding this disclosure, the following points need to be explained:

[0154] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0155] (2) For the sake of clarity, the thickness and size of layers or structures in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0156] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0157] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A data processing method, comprising: In response to receiving a write request from a first cache to write first data back to a memory, the cache coherence node writes the first data to the memory or discards the first data, wherein the write request carries the first data, and the cache coherence node is configured to maintain consistency of data stored in a plurality of caches, the plurality of caches including the first cache, and After the cache coherence node writes the first data into the memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly end the processing operation of the write request; The step of, in response to receiving a write request from the first cache to write the first data back to the memory, the cache coherence node writing the first data to the memory or discarding the first data, comprising: In response to receiving the write request from the first cache to write the first data back to the memory, the cache coherence node determines whether the first cache is the same as the cache currently exclusively occupying the first data recorded on the cache coherence node side, and In response to determining that the first cache is the same as the cache currently exclusively occupying the first data recorded on the cache coherence node side, the cache coherence node writes the first data into the memory; The method further comprises: In response to receiving a read request for the first data from the second cache and the cache coherence node recording that the first data is in an exclusive state or a shared state in the first cache, the cache coherence node initiates a monitoring signal to the first cache; In response to the first cache receiving the monitoring signal after issuing the write request, the first cache returns a monitoring response carrying the first data to the cache coherence node in response to the monitoring signal.

2. The data processing method according to claim 1, wherein after the cache coherence node writes the first data to a memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly end the processing operation of the write request, comprising: After the cache coherence node writes the first data into the memory, the memory returns a write response to the cache coherence node indicating that the first data has been written into the memory, and In response to receiving the write response from the memory indicating that the first data has been written to the memory, the cache coherence node returns the write response signal to the first cache indicating that the first data has been written back to the memory to directly end the processing operation of the write request.

3. The data processing method according to claim 1, further comprising: After the cache coherence node writes the first data into the memory, the cache coherence node sets the data state of the first cache to an invalid state, a shared state, or an exclusive state. The invalid state indicates that the first cache does not cache the first data, the shared state indicates that the first cache and other caches cache the first data, and the exclusive state indicates that only the first cache caches the first data.

4. The data processing method according to claim 1, further comprising: In response to receiving the monitoring response, the cache coherence node returns the first data to the second cache, and After receiving the first data, the second cache returns a message to the cache coherence node indicating that the first data has been received to end the read request.

5. The data processing method according to claim 4, wherein in response to receiving the monitoring response, the cache coherence node returns the first data to the second cache, comprising: In response to receiving the monitoring response, the cache coherence node returns the first data to the second cache and sets the data state of the second cache to an exclusive state, where the exclusive state indicates that the first data is cached only in the second cache.

6. The data processing method according to claim 4, wherein after the cache coherence node writes the first data to a memory or discards the first data, the cache coherence node returns a write response signal to the first cache to directly end the processing operation of the write request, comprising: After receiving the message indicating that the first data has been received, the cache coherence node discards the first data written by the write request on the cache coherence node side, and returns the write response signal to the first cache to directly end the processing operation of the write request.

7. The data processing method according to claim 6, wherein after receiving the message, the cache coherence node discards the first data written by the write request to the cache coherence node side, comprising: In response to determining that the first data written by the write request to the cache consistency node side is invalid data after receiving the message indicating that the first data has been received, the cache consistency node discards the first data written by the write request to the cache consistency node side.

8. An electronic device comprising: a plurality of caches, including a first cache; as well as a cache coherence node configured to, in response to receiving a write request from the first cache to write first data back to the memory, write the first data to the memory or discard the first data, and after the cache coherence node writes the first data to the memory or discards the first data, return a write response signal to the first cache to directly end the processing operation of the write request, wherein the write request carries the first data, and the cache coherence node is configured to maintain the consistency of the data stored in the multiple caches; Wherein, the cache consistency node is further configured as: In response to receiving the write request from the first cache to write the first data back to the memory, determining whether the first cache is the same as the cache currently exclusively occupying the first data recorded on the cache coherence node side, and In response to determining that the first cache is the same as the cache currently exclusively occupying the first data recorded on the cache coherence node side, writing the first data into the memory; The cache coherence node is further configured to: in response to receiving a read request for the first data from the second cache and the cache coherence node recording that the first data is in an exclusive state or a shared state in the first cache, initiate a monitoring signal to the first cache, and The first cache is configured to: in response to the first cache receiving the monitoring signal after issuing the write request, return a monitoring response carrying the first data to the cache coherence node.

9. The electronic device according to claim 8, wherein: The memory is configured to: after the cache coherence node writes the first data into the memory, return a write response to the cache coherence node indicating that the first data has been written into the memory, and The cache consistency node is also configured to: in response to receiving the write response from the memory indicating that the first data has been written to the memory, return the write response signal to the first cache indicating that the first data has been written back to the memory to directly end the processing operation of the write request.

10. A data processing device comprising: a memory configured to store computer-executable instructions; as well as a processor configured to execute the computer-executable instructions, When the computer executable instructions are executed by the processor, the method according to any one of claims 1 to 7 is implemented.

11. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein: When the computer-executable instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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