SIMT-based register allocation method, device, equipment and storage medium

Abstract

The present disclosure relates to a register allocation method, apparatus, device and storage medium based on SIMT. The method comprises: determining a first number of registers required for input variables of a target program executed by a target thread group and a total number of registers required by the target program; in response to the target thread group satisfying a preset execution start condition, allocating a first register group corresponding to the first number to the target thread group; initializing the first register group; in response to the completion of initialization of the first register group, allocating register groups corresponding to intermediate variables and output variables of the target program to the target thread group based on the total number.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a register allocation method, device, electronic device and storage medium based on SIMT. Background Art

[0002] For GPU (Graphics Processing Unit), tasks are usually executed in SIMT (Same Instruction Multi Threads) mode. In SIMT mode, the GPU will split the task into hundreds or thousands of threads, each thread executes the same instructions and processes different data. Generally speaking, in order to reduce the overhead of task scheduling, the GPU core will group multiple (for example, 32, 64 or 128) threads into a thread group for execution, where different threads in a thread group share instructions but have independent register resources. The more thread groups that can be scheduled simultaneously, the higher the GPU throughput and the better the performance.

[0003] All threads in a task execute the same program. Since the register resources inside the GPU are limited, the more register resources the program requires, the fewer thread groups that can be executed in parallel. Assuming that in a program, each thread requires 512B of register resources, and a thread group containing 32 threads requires 512×32B=16KB of register resources, then a GPU core with 128KB of register resources can run up to 8 thread groups simultaneously. Summary of the invention

[0004] The present disclosure provides a register allocation technology solution based on single instruction multiple thread (SIMT).

[0005] According to one aspect of the present disclosure, a register allocation method based on single instruction multiple thread (SIMT) is provided, comprising:

[0006] Determining a first number of registers required for input variables of a target program executed by a target thread group and a total number of registers required by the target program;

[0007] In response to the target thread group satisfying a preset execution start condition, allocating a first register group corresponding to the first number to the target thread group;

[0008] Initializing the first register group;

[0009] In response to completion of initialization of the first register group, register groups corresponding to intermediate variables and output variables of the target program are allocated to the target thread group based on the total number.

[0010] In a possible implementation, the method further includes:

[0011] In response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, the first register group and / or the second register group are released, wherein the early release condition at least includes that data is completely used.

[0012] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes:

[0013] In response to the data in the first register group and the second register group being completely used, the first register group and the second register group are released.

[0014] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes:

[0015] For any register in the first register group and the second register group, in response to data in the register being completely used, the register is released.

[0016] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes:

[0017] In response to the number of registers in the first register group and the second register group whose data have been used up reaching a preset number, the registers in which data have been used up are released, wherein the preset number is greater than 1.

[0018] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes:

[0019] In response to the data in the first register group being used up, releasing the first register group;

[0020] In response to the data in the second register group being completely used up, the second register group is released.

[0021] In a possible implementation, the method further includes:

[0022] In response to the target thread group being executed completely, releasing the third register group corresponding to the output variable.

[0023] In a possible implementation, the preset execution start condition at least includes:

[0024] The target thread group has released its dependency on other thread groups, or the target thread group does not depend on other thread groups.

[0025] According to one aspect of the present disclosure, a register allocation device based on single instruction multiple thread (SIMT) is provided, comprising:

[0026] A first determination module, configured to determine a first number of registers required for input variables of a target program executed by a target thread group, and a total number of registers required for the target program;

[0027] A first allocation module, configured to allocate the first register group corresponding to the first quantity to the target thread group in response to the target thread group satisfying a preset execution start condition;

[0028] An initialization module, used for initializing the first register group;

[0029] The second allocation module is configured to allocate register groups corresponding to the intermediate variables and output variables of the target program to the target thread group based on the total number in response to completion of initialization of the first register group.

[0030] In a possible implementation manner, the device further includes:

[0031] An early release module is used to release the first register group and / or the second register group corresponding to the first register group and / or the intermediate variable in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, wherein the early release condition at least includes that the data is used up.

[0032] In a possible implementation, the early release module is used to:

[0033] In response to the data in the first register group and the second register group being completely used, the first register group and the second register group are released.

[0034] In a possible implementation, the early release module is used to:

[0035] For any register in the first register group and the second register group, in response to data in the register being completely used, the register is released.

[0036] In a possible implementation, the early release module is used to:

[0037] In response to the number of registers in the first register group and the second register group whose data have been used up reaching a preset number, the registers in which data have been used up are released, wherein the preset number is greater than 1.

[0038] In a possible implementation, the early release module is used to:

[0039] In response to the data in the first register group being used up, releasing the first register group;

[0040] In response to the data in the second register group being completely used up, the second register group is released.

[0041] In a possible implementation manner, the device further includes:

[0042] The release module is used to release the third register group corresponding to the output variable in response to the target thread group completing execution.

[0043] In a possible implementation, the preset execution start condition at least includes:

[0044] The target thread group has released its dependency on other thread groups, or the target thread group does not depend on other thread groups.

[0045] According to one aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0046] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0047] According to one aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0048] In an embodiment of the present disclosure, by determining a first number of registers required for input variables of a target program executed by a target thread group and a total number of registers required for the target program, in response to the target thread group satisfying a preset execution start condition, a first register group corresponding to the first number is allocated to the target thread group, the first register group is initialized, and in response to completion of initialization of the first register group, based on the total number, a register group corresponding to intermediate variables and output variables of the target program is allocated to the target thread group. Thus, when allocating registers to the target thread group, the allocation of registers required for intermediate variables of the target program executed by the target thread group and registers required for output variables of the target program is delayed, thereby reducing the time that the thread group occupies registers and improving register utilization, which in turn helps to improve the parallelism of thread group execution in the GPU, that is, to increase the number of thread groups executed in parallel in the GPU, improve the throughput of the GPU, and improve the performance of the GPU.

[0049] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0050] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0052] Figure 1 A flowchart of a SIMT-based register allocation method provided by an embodiment of the present disclosure is shown.

[0053] Figure 2 A block diagram of a register allocation device based on single instruction multiple threads (SIMT) provided by an embodiment of the present disclosure is shown.

[0054] Figure 3 A block diagram of an electronic device 1900 provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0055] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0056] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0057] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0058] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0059] In the related art, the register resources required by the program are mainly reduced through compiler optimization. For example, by reducing the register resources required by each thread from 512B to 256B, the number of thread groups running simultaneously can be doubled.

[0060] However, for some complex programs, the compiler has limited room for optimization and there are obvious marginal effects. For example, if the register resources required by each thread are optimized to 496B, the maximum number of thread groups that can be executed simultaneously is still 8. Only by optimizing to less than 456B can the number be increased to 9, which is very difficult for the compiler.

[0061] In order to solve technical problems similar to those described above, an embodiment of the present disclosure provides a register allocation method based on SIMT, which determines a first number of registers required for input variables of a target program executed by a target thread group and a total number of registers required for the target program, allocates a first register group corresponding to the first number to the target thread group in response to the target thread group satisfying a preset execution start condition, initializes the first register group, and allocates register groups corresponding to intermediate variables and output variables of the target program to the target thread group based on the total number in response to completion of initialization of the first register group, thereby delaying the allocation of registers required for intermediate variables of the target program executed by the target thread group and registers required for output variables of the target program when allocating registers to the target thread group, thereby reducing the time that the thread group occupies registers and improving the utilization rate of registers, thereby helping to improve the parallelism of thread group execution in the GPU, that is, increasing the number of thread groups executed in parallel in the GPU, improving the throughput of the GPU, and improving the performance of the GPU.

[0062] The SIMT-based register allocation method provided by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings.

[0063] Figure 1 A flow chart of a SIMT-based register allocation method provided in an embodiment of the present disclosure is shown. In one possible implementation, the execution subject of the SIMT-based register allocation method may be a SIMT-based register allocation device. For example, the SIMT-based register allocation method may be executed by a terminal device or a server or other electronic device. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device. In some possible implementations, the SIMT-based register allocation method may be implemented by a processor calling computer-readable instructions stored in a memory. For example, Figure 1 As shown, the SIMT-based register allocation method includes steps S11 to S14.

[0064] In step S11 , a first number of registers required for input variables of a target program executed by a target thread group and a total number of registers required for the target program are determined.

[0065] In step S12, in response to the target thread group satisfying a preset execution start condition, a first register group corresponding to the first number is allocated to the target thread group.

[0066] In step S13, the first register group is initialized.

[0067] In step S14 , in response to completion of initialization of the first register group, register groups corresponding to intermediate variables and output variables of the target program are allocated to the target thread group based on the total number.

[0068] The SIMT-based register allocation method provided in the embodiments of the present disclosure may be applied to a GPU (Graphics Processing Unit) or a CPU (Central Processing Unit), etc., without limitation herein.

[0069] In the embodiments of the present disclosure, the target thread group may represent any thread group to be executed. The target program may represent a program executed by the target thread group. The target program may be any type of program. For example, the target program may be a shader program, etc., which is not limited here.

[0070] Typically, a program includes input variables (input), intermediate variables (internal), and output variables (output). In the case where the target program includes input variables, intermediate variables, and output variables, the registers required for the input variables of the target program, the registers required for the intermediate variables of the target program, and the registers required for the output variables of the target program can be allocated to the target thread group. In some application scenarios, the program may only include input variables and output variables, but not intermediate variables. In this case, only the registers required for the input variables of the target program and the registers required for the output variables of the target program can be allocated to the target thread group, and the registers required for the intermediate variables of the target program do not need to be allocated to the target thread group. In other words, the number of registers required for the intermediate variables of the target program is 0.

[0071] In an embodiment of the present disclosure, before allocating registers to a target thread group, a first number of registers required for input variables of a target program executed by the target thread group and a total number of registers required for the target program may be counted. The first number may represent the number of registers required for input variables of the target program executed by the target thread group, and the total number may represent the total number of registers required for input variables, intermediate variables, and output variables of the target program executed by the target thread group.

[0072] In a possible implementation, before allocating registers to the target thread group, a first number of registers required for input variables of a target program executed by the target thread group, a second number of registers required for intermediate variables of the target program, and a third number of registers required for output variables of the target program may be counted. The first number may represent the number of registers required for input variables of the target program executed by the target thread group, the second number may represent the number of registers required for intermediate variables of the target program, and the third number may represent the number of registers required for output variables of the target program.

[0073] In a possible implementation, after assembling the target program, the compiler may count the first number of registers required for the input variables of the target program executed by the target thread group, the second number of registers required for the intermediate variables of the target program, and the third number of registers required for the output variables of the target program. After counting the first number, the second number, and the third number, the compiler may send the first number, the second number, and the third number to the driver to notify the driver. When creating a GPU task, the driver may send the first number, the second number, and the third number to the GPU core processor. When executing a task, the GPU core processor may first allocate a first register group corresponding to the first data and initialize the first register group.

[0074] In one example, the input variables of the target program executed by the target thread group are 7 texture coordinates (texcoord0 to texcoord6), each texture coordinate occupies 4 registers, then the first number of registers required for the input variables of the target program is 7×4=28. For example, the input variables of the target program are:

[0075] struct PS_INPUT

[0076] {

[0077] linear float4 texcoord0:texcoord0;

[0078] linear float4 texcoord1:texcoord1;

[0079] linear float4 texcoord2:texcoord2;

[0080] linear float4 texcoord3:texcoord3;

[0081] linear float4 texcoord4:texcoord4;

[0082] linear float4 texcoord5:texcoord5;

[0083] linear float4 texcoord6:texcoord6;

[0084] };

[0085] The target program can sample the texture from the input texture coordinates and perform a series of calculations to obtain the output variable.

[0086] For example, the calculation process of the target program is as follows:

[0087] float4 main(PS_INPUT input):SV_Target{

[0088] float4 x=tex2D(s1,input.texcoord0.xy+input.texcoord0.zw);

[0089] float4 y=tex2D(s1,input.texcoord1.xy+input.texcoord1.zw);

[0090] float4 z=tex2D(s1,input.texcoord2.xy+input.texcoord2.zw);

[0091] float4 a=tex2D(s1,input.texcoord3.xy+input.texcoord3.zw);

[0092] float4 b=tex2D(s1,input.texcoord4.xy+input.texcoord4.zw);

[0093] float4 c=tex2D(s1,input.texcoord5.xy+input.texcoord5.zw);

[0094] float4 d=tex2D(s1,input.texcoord6.xy+input.texcoord6.zw);

[0095] float4 e=x+y+z+a+b+c+d+e;

[0096] e = e + input.texcoord0.xyzw;

[0097] e=e / 7.0;

[0098] e=e*(e+1.0);

[0099] e=1.0 / e;

[0100] return e+1.0;

[0101] }

[0102] Among them, x, y, z, a, b, c, d are intermediate variables of the target program, each of which occupies 4 registers, so the second number of registers required by the intermediate variables of the target program is 7×4=28. e is the output variable of the target program, which occupies 4 registers, that is, the third number of registers required by the output variable of the target program is 4.

[0103] In an embodiment of the present disclosure, after determining a first number of registers required for input variables of a target program executed by a target thread group, a first register group corresponding to the first number may be allocated to the target thread group in response to the target thread group satisfying a preset execution start condition. The first register group may represent a register group allocated to the input variables of the target program. The number of registers in the first register group is the first number.

[0104] In a possible implementation, the preset execution start condition at least includes: the target thread group has released its dependence on other thread groups, or the target thread group is not dependent on other thread groups.

[0105] As an example of this implementation, the preset execution start condition may further include: the number of unallocated registers is greater than or equal to the first number. In this example, in response to the target thread group having released its dependence on other thread groups or the target thread group not being dependent on other thread groups, and the number of unallocated registers is greater than or equal to the first number, a first register group corresponding to the first number may be allocated to the target thread group.

[0106] As another example of this implementation, the preset execution start condition may only include: the target thread group has released its dependence on other thread groups, or the target thread group is not dependent on other thread groups. In this example, in response to the target thread group having released its dependence on other thread groups or the target thread group being not dependent on other thread groups, the first register group corresponding to the first number may be allocated to the target thread group. Wherein, the allocation of the first register group corresponding to the first number to the target thread group may include: determining whether the number of unallocated registers is greater than or equal to the first number, if so, allocating the first register group corresponding to the first number to the target thread group, otherwise, waiting until the number of unallocated registers is greater than or equal to the first number, and then allocating the first register group corresponding to the first number to the target thread group.

[0107] In this implementation, in response to the target thread group satisfying a preset execution start condition, the first register group corresponding to the first quantity is allocated to the target thread group, wherein the preset execution start condition at least includes that the target thread group has released its dependence on other thread groups or that the target thread group is not dependent on other thread groups. Thus, the first register group is allocated to the target thread group only when the target thread group is capable of execution, so that the registers allocated to the target thread group can be used immediately, thereby further improving the utilization rate of the registers.

[0108] In the embodiment of the present disclosure, after allocating the first number of first register groups corresponding to the target thread group, the first register group may be initialized, wherein initializing the first register group may mean writing input variables into the first register group.

[0109] In an embodiment of the present disclosure, in response to completion of initialization of the first register group, the register group corresponding to the intermediate variables and output variables of the target program may be allocated to the target thread group according to the difference between the total number and the first number. In a possible implementation, in response to completion of initialization of the first register group, a second register group corresponding to the second number and a third register group corresponding to the third number may be allocated to the target thread group. Wherein, in response to completion of initialization of the first register group, it may be checked whether the number of unallocated registers is greater than or equal to the sum of the second number and the third number. If so, the second register group corresponding to the second number and the third register group corresponding to the third number may be allocated to the target thread group. Otherwise, the second register group corresponding to the second number and the third register group corresponding to the third number may be allocated to the target thread group after waiting for the number of registers to be greater than or equal to the sum of the second number and the third number.

[0110] The second register group may represent a register group allocated to the intermediate variables of the target program. The number of registers in the second register group is a second number. The third register group may represent a register group allocated to the output variables of the target program. The number of registers in the third register group is a third number.

[0111] In the disclosed embodiment, by delaying the application of registers required for the intermediate variables of the target program and the registers required for the output variables of the target program, the register resource requirements of the intermediate variables and output variables of the target program can be ignored during the allocation phase of the first register group and the initialization phase of the first register group.

[0112] In a possible implementation, an input register size field may be added to the interface and the steps of task execution may be fine-tuned to implement the register delay application function.

[0113] In a possible implementation, the method further includes: in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group, wherein the early release condition at least includes that the data has been used up.

[0114] In this implementation, during the execution of the target program, registers in the first register group and / or the second register group can be released in advance. That is, registers in the first register group and / or the second register group can be released before the execution of the target program ends. That is, registers in the first register group and / or the second register group can be released earlier than registers in the third register group.

[0115] As an example of this implementation, by adding a release instruction, the register can be released in advance with a low hardware cost.

[0116] As an example of this implementation, a compiler may identify when data in a register has been completely used.

[0117] In this implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, the first register group and / or the second register group are released, wherein the early release condition at least includes that the data has been used up, thereby releasing in advance the registers required for the input variables of the target program executed by the target thread group and / or the registers required for the intermediate variables of the target program, thereby further reducing the time that the thread group occupies the registers and improving the utilization rate of the registers, thereby helping to further increase the number of thread groups executed in parallel in the GPU, so that more thread groups have the opportunity to apply for sufficient registers and participate in parallel computing.

[0118] As an example of this implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: in response to the data in the first register group and the second register group being used up, releasing the first register group and the second register group.

[0119] In this example, in response to the data in the first register group and the second register group being used up, each register in the first register group and the second register group may be released. In this example, each register in the first register group and the second register group may be released at the same time.

[0120] In one example, a special instruction gpr_release can be used to release registers in advance. The syntax can be: gpr_release idx. The release instruction can indicate that all registers with numbers greater than or equal to idx are released. For example, the compiler can assign registers r0 to r3 to the variable e. After the calculation of e=x+y+z+a+b+c+d is completed, a gpr_release 4 instruction can be added, so that the GPU core will release registers r4 to r59 in the first register group and the second register group.

[0121] In this example, in response to the data in the first register group and the second register group being used up, the first register group and the second register group are released, thereby not only reducing the time that the target thread group occupies the registers in the first register group and the second register group, but also improving the efficiency of releasing the registers in the first register group and the second register group.

[0122] As another example of this implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: for any register in the first register group and the second register group, in response to the data in the register being used up, releasing the register.

[0123] In this example, for any register in the first register group and the second register group, the register can be released immediately in response to the data in the register being used up. In this example, the registers in the first register group and the second register group can be released one by one.

[0124] In this example, by releasing any register in the first register group and the second register group in response to the data in the register being used up, the utilization rate of the registers in the first register group and the second register group can be maximized, so that the registers in the first register group and the second register group can be used by other thread groups as soon as possible.

[0125] As another example of this implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: in response to the number of registers whose data has been used up in the first register group and the second register group reaching a preset number, releasing the registers whose data has been used up, wherein the preset number is greater than 1.

[0126] The preset number may be 5, 4, 6, etc., and is not limited here.

[0127] In this example, the number of registers in the first register group and the second register group whose data have been used up can be accumulated by a counter, and each register whose data have been used up can be released in response to the count value of the counter reaching a preset number. In this example, registers in the first register group and the second register group whose data have been used up at a similar time can be released at the same time.

[0128] In this example, in response to the number of registers whose data has been used up in the first register group and the second register group reaching a preset number, the registers whose data has been used up are released, wherein the preset number is greater than 1, thereby being able to better balance the utilization of registers and the efficiency of releasing registers.

[0129] As another example of this implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: in response to the data in the first register group being used up, releasing the first register group; in response to the data in the second register group being used up, releasing the second register group.

[0130] In this example, each register in the first register group may be released in response to the data in the first register group being used up; each register in the second register group may be released in response to the data in the second register group being used up. In this example, each register in the first register group may be released at the same time, and each register in the second register group may be released at the same time. The registers in the first register group may be released at different times than the registers in the second register group.

[0131] In this example, in response to the data in the first register group being used up, the first register group is released, and in response to the data in the second register group being used up, the second register group is released, thereby achieving a better balance between register utilization and register release efficiency.

[0132] In a possible implementation, the method further includes: in response to the target thread group completing execution, releasing the third register group corresponding to the output variable. In this implementation, by releasing the third register group in response to the target thread group completing execution, registers in the third register group can be allocated to other thread groups for use.

[0133] The SIMT-based register allocation method provided by the embodiments of the present disclosure may also be combined with a traditional compiler optimization scheme for register resources, thereby being more conducive to breaking through the limitation of register resources.

[0134] The SIMT-based register allocation method provided by the embodiments of the present disclosure can be applied to technical fields such as GPU, task scheduling, and register allocation, which are not limited here.

[0135] The SIMT-based register allocation method provided by the embodiments of the present disclosure can be applied to programs containing input variables, intermediate variables and output variables, and can also be applied to programs containing only input variables and output variables. Therefore, the SIMT-based register allocation optimization solution provided by the embodiments of the present disclosure has a wide range of applications.

[0136] The following is a specific application scenario to illustrate the SIMT-based register allocation method provided by the embodiment of the present disclosure. In this application scenario, the processor is a GPU and the target program is a shader program.

[0137] In this application scenario, after assembling the shader program, the compiler can count the first number of registers required for the input variables of the shader program, the second number of registers required for the intermediate variables of the shader program, and the third number of registers required for the output variables of the shader program. For example, the input variables of the shader program include texcoord0 to texcoord6, and the 7 input variables occupy 4 registers respectively. Therefore, the first number of registers required for the input variables of the shader program is 28; the intermediate variables of the shader program include x, y, z, a, b, c, and d, and the 7 intermediate variables occupy 4 registers respectively. Therefore, the second number of registers required for the intermediate variables of the shader program is 28; the output variables of the shader program include e, which occupies 4 and memory, so the third number of registers required for the output variables of the shader program is 4.

[0138] After calculating the first number, the second number, and the third number, the compiler may send the first number, the second number, and the third number to the driver to notify the driver.

[0139] When creating a GPU task, the driver may send the first quantity, the second quantity, and the third quantity to the GPU core processor. When executing a task, the GPU core processor may first allocate a first register group corresponding to the first quantity and initialize the first register group. In response to the completion of the initialization of the first register group, the GPU core processor may allocate a second register group corresponding to the second quantity and a third register group corresponding to the third quantity. In this way, delayed application of registers may be achieved. The number of registers whose data has been used up in the first register group and the second register group may be accumulated by a counter, and each register whose data has been used up may be released in response to the count value of the counter reaching a preset number. In this way, early release of registers may be achieved. The third register group may be released in response to the completion of the execution of the shader program.

[0140] In this application scenario, the combination of delayed application and early release of registers can significantly reduce the demand for register resources, allowing more thread groups to have the opportunity to apply for enough registers and participate in parallel computing.

[0141] Taking the example that the first number of registers required for the input variables of the target program executed by the target thread group is 28, the second number of registers required for the intermediate variables of the target program is 28, and the third number of registers required for the output variables of the target program is 4, the related technology and the embodiment of the present disclosure are compared in terms of the number of registers required for each step when the target thread group executes the target program.

[0142] In the related art, when the target thread group executes the target program, the number of registers required for each step is as follows:

[0143] step Number of registers Register Allocation First quantity + second quantity + third quantity = 60 Initialize the first register group First quantity + second quantity + third quantity = 60 Target program execution First quantity + second quantity + third quantity = 60 Execution ends, registers are released 0

[0144] In one implementation of the embodiment of the present disclosure, when the target thread group executes the target program, the number of registers required for each step is as follows:

[0145]

[0146]

[0147] Compared with the related art, this implementation method of the embodiment of the present disclosure delays the application of registers required for the intermediate variables of the target program and the registers required for the output variables of the target program, and releases the registers corresponding to the input variables of the target program in advance, thereby reducing the time of occupying registers.

[0148] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0149] The disclosed embodiment also provides a SIMT-based register allocation method, comprising: determining the total number of registers required for a target program executed by a target thread group; allocating register groups to the target thread group based on the total number; in response to a first register group of input variables of the target program and / or a second register group corresponding to an intermediate variable of the target program satisfying a preset early release condition, releasing the first register group and / or the second register group, wherein the early release condition at least includes that data has been used up.

[0150] In a possible implementation, determining the total number of registers required for a target program executed by a target thread group includes: determining a first number of registers required for input variables of a target program executed by the target thread group, a second number of registers required for intermediate variables of the target program, and a third number of registers required for output variables of the target program; and allocating register groups to the target thread group based on the total number includes: allocating a first register group corresponding to the first number, a second register group corresponding to the second number, and a third register group corresponding to the third number to the target thread group.

[0151] In a possible implementation, allocating the first register group corresponding to the first quantity to the target thread group, allocating the second register group corresponding to the second quantity and the third register group corresponding to the third quantity to the target thread group includes: in response to the target thread group satisfying a preset execution start condition, allocating the first register group corresponding to the first quantity to the target thread group; initializing the first register group; in response to completion of initialization of the first register group, allocating the second register group corresponding to the second quantity and the third register group corresponding to the third quantity to the target thread group.

[0152] In a possible implementation, the preset execution start condition at least includes: the target thread group has released its dependence on other thread groups, or the target thread group is not dependent on other thread groups.

[0153] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: in response to the data in the first register group and the second register group being used up, releasing the first register group and the second register group.

[0154] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: for any register in the first register group and the second register group, in response to the data in the register being used up, releasing the register.

[0155] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: in response to the number of registers whose data has been used up in the first register group and the second register group reaching a preset number, releasing the registers whose data has been used up, wherein the preset number is greater than 1.

[0156] In a possible implementation, in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: in response to the data in the first register group being used up, releasing the first register group; in response to the data in the second register group being used up, releasing the second register group.

[0157] In a possible implementation, the method further includes: in response to completion of execution of the target thread group, releasing a third register group corresponding to an output variable of the target program.

[0158] In addition, the present disclosure also provides a register allocation device, an electronic device, a computer-readable storage medium, and a computer program product based on single instruction multi-thread SIMT, all of which can be used to implement any register allocation method based on single instruction multi-thread SIMT provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method part and will not be repeated here.

[0159] Figure 2 FIG. 1 is a block diagram of a register allocation device based on single instruction multiple threads (SIMT) according to an embodiment of the present disclosure. Figure 2 As shown, the register allocation device based on single instruction multiple thread (SIMT) comprises:

[0160] A first determination module 21, configured to determine a first number of registers required for input variables of a target program executed by a target thread group, and a total number of registers required for the target program;

[0161] A first allocation module 22, configured to allocate the first number of first register groups corresponding to the target thread group in response to the target thread group satisfying a preset execution start condition;

[0162] An initialization module 23, used for initializing the first register group;

[0163] The second allocation module 24 is configured to allocate register groups corresponding to the intermediate variables and output variables of the target program to the target thread group based on the total number in response to completion of initialization of the first register group.

[0164] In a possible implementation manner, the device further includes:

[0165] An early release module is used to release the first register group and / or the second register group corresponding to the first register group and / or the intermediate variable in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, wherein the early release condition at least includes that the data is used up.

[0166] In a possible implementation, the early release module is used to:

[0167] In response to the data in the first register group and the second register group being completely used, the first register group and the second register group are released.

[0168] In a possible implementation, the early release module is used to:

[0169] For any register in the first register group and the second register group, in response to data in the register being completely used, the register is released.

[0170] In a possible implementation, the early release module is used to:

[0171] In response to the number of registers in the first register group and the second register group whose data have been used up reaching a preset number, the registers in which data have been used up are released, wherein the preset number is greater than 1.

[0172] In a possible implementation, the early release module is used to:

[0173] In response to the data in the first register group being used up, releasing the first register group;

[0174] In response to the data in the second register group being completely used up, the second register group is released.

[0175] In a possible implementation manner, the device further includes:

[0176] The release module is used to release the third register group corresponding to the output variable in response to the target thread group completing execution.

[0177] In a possible implementation, the preset execution start condition at least includes:

[0178] The target thread group has released its dependency on other thread groups, or the target thread group does not depend on other thread groups.

[0179] The embodiment of the present disclosure also provides a register allocation device based on single instruction multiple threads (SIMT), including:

[0180] A second determination module is used to determine the total number of registers required for the target program executed by the target thread group;

[0181] an allocating module, configured to allocate register groups to the target thread group based on the total number;

[0182] An early release module is used to release the first register group and / or the second register group corresponding to the input variables of the target program and / or the intermediate variables of the target program in response to the first register group and / or the second register group corresponding to the intermediate variables of the target program meeting a preset early release condition, wherein the early release condition at least includes that the data has been used up.

[0183] In a possible implementation, the second determination module is used to: determine a first number of registers required for input variables of a target program executed by a target thread group, a second number of registers required for intermediate variables of the target program, and a third number of registers required for output variables of the target program; and allocating register groups to the target thread group based on the total number includes: allocating a first register group corresponding to the first number, a second register group corresponding to the second number, and a third register group corresponding to the third number to the target thread group.

[0184] In a possible implementation, the allocation module is used to: in response to the target thread group satisfying a preset execution start condition, allocate a first register group corresponding to the first quantity to the target thread group; initialize the first register group; in response to completion of initialization of the first register group, allocate a second register group corresponding to the second quantity and a third register group corresponding to the third quantity to the target thread group.

[0185] In a possible implementation, the preset execution start condition at least includes: the target thread group has released its dependence on other thread groups, or the target thread group is not dependent on other thread groups.

[0186] In a possible implementation, the early release module is used to release the first register group and the second register group in response to data in the first register group and the second register group being completely used.

[0187] In a possible implementation, the early release module is used to: for any register in the first register group and the second register group, in response to data in the register being completely used, release the register.

[0188] In a possible implementation, the early release module is used to release the registers whose data have been used up in response to the number of registers whose data have been used up in the first register group and the second register group reaching a preset number, wherein the preset number is greater than 1.

[0189] In a possible implementation, the early release module is used to: release the first register group in response to the data in the first register group being completely used; and release the second register group in response to the data in the second register group being completely used.

[0190] In a possible implementation, the device further includes: a releasing module, configured to release a third register group corresponding to the output variable of the target program in response to completion of execution of the target thread group.

[0191] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0192] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium may be a non-volatile computer-readable storage medium, or may be a volatile computer-readable storage medium.

[0193] The embodiment of the present disclosure further provides a computer program, including a computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the above method.

[0194] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0195] An embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; and a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0196] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0197] Figure 3 1 is a block diagram of an electronic device 1900 provided in an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal. Figure 3 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0198] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (MacOS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0199] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0200] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0201] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0202] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0203] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0204] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0205] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0206] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0207] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0208] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0209] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0210] If the technical solution of the embodiments of the present disclosure involves personal information, the product using the technical solution of the embodiments of the present disclosure has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of the embodiments of the present disclosure involves sensitive personal information, the product using the technical solution of the embodiments of the present disclosure has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the requirement of "explicit consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to collect his or her personal information; or on the device for processing personal information, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0211] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A register allocation method based on single instruction multiple thread (SIMT), characterized in that: include: Determine a first number of registers required for input variables of a target program executed by a target thread group, and a total number of registers required for the target program, wherein the total number is the sum of the first number, the number of registers required for intermediate variables of the target program, and the number of registers required for output variables of the target program; In response to the target thread group satisfying a preset execution start condition, allocating a first register group corresponding to the first number to the target thread group; Initializing the first register group; In response to completion of initialization of the first register group, based on a difference between the total number and the first number, allocating register groups corresponding to intermediate variables and output variables of the target program to the target thread group; In response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, the first register group and / or the second register group are released, wherein the early release condition at least includes that data is completely used.

2. The method according to claim 1, characterized in that In response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: In response to the data in the first register group and the second register group being completely used, the first register group and the second register group are released.

3. The method according to claim 1, characterized in that: In response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: For any register in the first register group and the second register group, in response to data in the register being completely used, the register is released.

4. The method according to claim 1, characterized in that In response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: In response to the number of registers in the first register group and the second register group whose data have been used up reaching a preset number, the registers in which data have been used up are released, wherein the preset number is greater than 1.

5. The method according to claim 1, characterized in that In response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, releasing the first register group and / or the second register group includes: In response to the data in the first register group being used up, releasing the first register group; In response to the data in the second register group being completely used up, the second register group is released.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: In response to the target thread group being executed completely, releasing the third register group corresponding to the output variable.

7. The method according to any one of claims 1 to 5, characterized in that The preset execution start condition at least includes: The target thread group has released its dependency on other thread groups, or the target thread group does not depend on other thread groups.

8. A register allocation device based on single instruction multiple thread (SIMT), characterized in that: include: a first determining module, configured to determine a first number of registers required for input variables of a target program executed by a target thread group, and a total number of registers required for the target program, wherein the total number is the sum of the first number, the number of registers required for intermediate variables of the target program, and the number of registers required for output variables of the target program; A first allocation module, configured to allocate the first register group corresponding to the first quantity to the target thread group in response to the target thread group satisfying a preset execution start condition; An initialization module, used for initializing the first register group; a second allocation module, configured to allocate register groups corresponding to intermediate variables and output variables of the target program to the target thread group in response to completion of initialization of the first register group and based on a difference between the total number and the first number; An early release module is used to release the first register group and / or the second register group corresponding to the first register group and / or the intermediate variable in response to the first register group and / or the second register group corresponding to the intermediate variable satisfying a preset early release condition, wherein the early release condition at least includes that the data is used up.

9. An electronic device, characterized in that: include: one or more processors; a memory for storing executable instructions; The one or more processors are configured to call the executable instructions stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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