A circuit for reducing static power consumption in a low-dropout state

Abstract

The application provides a circuit for reducing static power consumption in a pressure drop state, which is applied to a low-dropout linear voltage regulator and comprises a power tube, which is used for regulating and stabilizing an input signal under the action of a gate control signal to generate an output signal; the circuit comprises: an adjusting unit, which is used for processing a second voltage division signal of the input signal under the action of the output signal to generate a first signal lower than the output signal when a first voltage division signal of the input signal is higher than a reference signal; a first comparison unit connected with the adjusting unit, which is used for comparing the first signal with the output signal to generate a first comparison signal; and a control unit connected with the first comparison unit, which is used for generating a control signal under the action of the first comparison signal to pull up the voltage of the gate control signal according to the control signal. The application has the beneficial effects of reducing the power consumption of the LDO in the pressure drop area, prolonging the battery use time, and having the characteristics of simple structure and low cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a circuit for reducing static power consumption in a voltage drop state. BACKGROUND

[0002] A low-dropout linear regulator (LDO) is a common voltage regulator device used to convert an input voltage to a lower output voltage. Compared with traditional linear regulators, LDO has a lower drop out, that is, it can still work normally when the input voltage is close to the output voltage.

[0003] The LDO drop-out region refers to the difference between the input voltage and the output voltage, that is, the voltage that the LDO needs to consume when working. Generally, the drop-out region of the LDO is small, usually between a few hundred millivolts and a few volts. This means that the LDO can still work normally when the input voltage is close to the output voltage, thereby providing a more stable output voltage.

[0004] With the popularity of portable electronic devices, the demand for power management chips is becoming more and more urgent. People's requirements for power consumption are also getting higher and higher, especially for the static power consumption of portable products and long standby products. When designing ultra-low power circuits, the static power consumption problem of the LDO drop-out state becomes more prominent, which has an unavoidable impact on the circuit. SUMMARY

[0005] To solve the above technical problems, the present application provides a circuit for reducing static power consumption in a voltage drop state.

[0006] The technical problem solved by the present application can be realized by the following technical solutions:

[0007] A circuit for reducing static power consumption in a voltage drop state is applied to a low-dropout linear regulator, which includes a power tube, the power tube is used to adjust and stabilize the input signal under the action of a gate control signal to generate an output signal;

[0008] The circuit includes:

[0009] An adjustment unit is used to process a second divided signal of the input signal under the action of the output signal to generate a first signal lower than the output signal when a first divided signal of the input signal is lower than a reference signal;

[0010] A first comparison unit is connected to the adjustment unit and is used to compare the first signal and the output signal to generate a first comparison signal;

[0011] a control unit connected to the first comparison unit, for generating a control signal under the action of the first comparison signal, so as to pull up the voltage of the gate control signal according to the control signal.

[0012] Preferably, further comprising:

[0013] a resistance voltage dividing unit, the resistance voltage dividing circuit comprising a predetermined number of voltage dividing resistors connected in series between the input signal and a ground terminal, the connection point between the voltage dividing resistors forming a voltage dividing node, and a first voltage dividing signal of the input signal being led out from the voltage dividing node.

[0014] Preferably, further comprising:

[0015] a first NMOS transistor, the gate of the first NMOS transistor being connected to a first bias voltage, the drain of the first NMOS transistor being connected to the input signal, and the source of the first NMOS transistor being connected to the resistance voltage dividing unit.

[0016] Preferably, further comprising:

[0017] a second comparison unit connected to the adjustment unit, for comparing the first voltage dividing signal of the input signal with the reference signal to generate a second comparison signal;

[0018] a first sampling unit connected to the second comparison unit, for sampling the tail current of the second comparison unit under the action of the gate control signal to obtain a first sampling signal;

[0019] a second sampling unit connected to the second comparison unit, for sampling the output current of the second comparison unit under the action of the gate control signal to obtain a second sampling signal.

[0020] Preferably, the second comparison unit comprises:

[0021] a second NMOS transistor, the gate and the drain of the second NMOS transistor being connected to a power supply voltage;

[0022] a third NMOS transistor, the gate of the third NMOS transistor being connected to the gate of the second NMOS transistor, and the drain of the third NMOS transistor being connected to the adjustment unit;

[0023] a fourth NMOS transistor, the gate of the fourth NMOS transistor being connected to the first voltage dividing signal of the input signal, the drain of the fourth NMOS transistor being connected to the source of the second NMOS transistor, and the source of the fourth NMOS transistor being connected to the first sampling unit.

[0024] a fifth NMOS transistor, a gate of the fifth NMOS transistor being connected to the reference signal, a drain of the fifth NMOS transistor being connected to a source of the third NMOS transistor, the source of the third NMOS transistor being connected to a source of the fourth NMOS transistor.

[0025] Preferably, the first sampling unit comprises:

[0026] a sixth NMOS transistor, a gate of the sixth NMOS transistor being connected to the gate control signal, a drain of the sixth NMOS transistor being connected to the source of the fourth NMOS transistor, a source of the sixth NMOS transistor being connected to a ground terminal;

[0027] the second sampling unit comprises:

[0028] a seventh NMOS transistor, a gate of the seventh NMOS transistor being connected to the gate control signal, a drain of the seventh NMOS transistor being connected to the source of the fifth NMOS transistor, a source of the seventh NMOS transistor being connected to the ground terminal.

[0029] Preferably, the adjusting unit comprises:

[0030] a first resistor connected between the input signal and a first adjusting node, the first adjusting node being connected to the second comparing unit;

[0031] a first transistor, a gate of the first transistor being connected to the output signal, a drain of the first transistor being connected to the first resistor, a source of the first transistor being connected to a second adjusting node, the first signal being output from the second adjusting node.

[0032] Preferably, the first comparing unit comprises:

[0033] a first PMOS transistor, a source of the first PMOS transistor being connected to the first signal;

[0034] a second PMOS transistor, a gate of the second PMOS transistor being connected to a gate and a drain of the first PMOS transistor, a source of the second PMOS transistor being connected to the output signal;

[0035] a third PMOS transistor, a source of the third PMOS transistor being connected to a drain of the first PMOS transistor;

[0036] a fourth PMOS transistor, a gate of the fourth PMOS transistor being connected to a gate and a drain of the third PMOS transistor, a source of the fourth PMOS transistor being connected to a drain of the second PMOS transistor, the first comparing signal being output from the drain of the fourth PMOS transistor;

[0037] An eighth NMOS transistor, a gate of the eighth NMOS transistor is connected with a second bias voltage, a drain of the eighth NMOS transistor is connected with a drain of the third PMOS transistor, and a source of the eighth NMOS transistor is connected with a ground terminal through a second resistance;

[0038] A ninth NMOS transistor, a gate of the ninth NMOS transistor is connected with the second bias voltage, a drain of the ninth NMOS transistor is connected with a drain of the fourth PMOS transistor, and a source of the ninth NMOS transistor is connected with the ground terminal through a third resistance.

[0039] Preferably, the control unit comprises:

[0040] A fifth PMOS transistor, a gate of the fifth PMOS transistor is connected with the first comparison signal, and a drain of the fifth PMOS transistor is connected with the ground terminal.

[0041] A tenth NMOS transistor, a gate of the tenth NMOS transistor is connected with a source of the fifth PMOS transistor, a drain of the tenth NMOS transistor is connected with the input signal through a bias tube, and a source of the tenth NMOS transistor outputs the control signal.

[0042] Preferably, the circuit further comprises:

[0043] A first operational amplifier, which is connected between the input signal and the ground terminal and is used for operational amplifying a voltage feedback signal of the reference signal and the output signal to obtain a first operational amplification signal.

[0044] A second operational amplifier, which is connected with the output terminal of the first operational amplifier and the control signal respectively and is used for operational amplifying the second operational amplification signal to obtain a second operational amplification signal, and is used for pulling up the voltage of the first operational amplification signal under the action of the control signal.

[0045] A third operational amplifier, an input terminal of the third operational amplifier is connected with an output terminal of the second operational amplifier, and an output terminal of the third operational amplifier is connected with the gate of the power transistor, and the third operational amplifier is used for operational amplifying the second operational amplification signal to obtain the gate control signal.

[0046] The technical scheme of the present application has the following advantages or beneficial effects:

[0047] The circuit of the present application can effectively reduce the power consumption of the LDO in the voltage drop region, prolong the battery use time, and has the characteristics of simple structure and low cost. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 The circuit schematic diagram of the power consumption reduction module in the preferred embodiment of the present application is shown in the figure.

[0049] Figure 2This is a schematic diagram of the structure of an LDO in a preferred embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the internal module architecture of the LDO in a preferred embodiment of the present invention. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0053] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0054] See Figure 1 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a circuit for reducing static power consumption in the voltage drop state is provided, applied to a low dropout linear regulator (LDO). The low dropout linear regulator includes a power transistor M. P power transistor M P Used to control a gate signal V PG Under the action of the input signal V IN Adjust and regulate the voltage to generate the output signal V. OUT ;

[0055] The circuit includes:

[0056] The adjustment unit is used when the first voltage divider signal (voltage at point A) of the input signal is lower than a reference signal V. REF At that time, in the output signal V OUT The second voltage divider signal (voltage at point C) of the input signal is processed under the action of the voltage divider to generate a voltage lower than that of the output signal V. OUT The first signal (voltage at point E);

[0057] The first comparison unit, connected to the adjustment unit, is used to compare the first signal (voltage at point E) and the output signal V. OUT A comparison is made, generating a first comparison signal;

[0058] The control unit, connected to the first comparison unit, is used to generate a control signal under the action of the first comparison signal, so as to pull up the gate control signal V according to the control signal. PG The voltage.

[0059] Specifically, in order to solve the problem of high power consumption when the existing LDO is in the voltage drop area, in the embodiment of the present application, the first voltage division signal (A point voltage) of the input signal of the LDO is compared with the reference signal V REF When the first voltage division signal (A point voltage) of the input signal is lower than the reference signal V REF , it indicates that the input signal V IN is low at this time; then, the input signal V OUT is processed under the action of the output signal V IN , to obtain the first signal (E point voltage) lower than the output signal V OUT , and the obtained first signal (E point voltage) is compared with the output signal V OUT of the LDO; then, the control signal is generated according to the first comparison signal, so as to pull up the voltage of the gate control signal V PG , thereby reducing the power consumption.

[0060] Further, when the first voltage division signal (A point voltage) of the input signal is higher than the reference signal V REF , the circuit for reducing the static power consumption in the LDO does not work at this time.

[0061] As a preferred embodiment, it further comprises:

[0062] A resistance voltage division unit, the resistance voltage division unit comprises a predetermined number of voltage division resistors connected in series between the input signal V IN and the ground terminal, and the connection point between the voltage division resistors forms a voltage division node, and the first voltage division signal (A point voltage) of the input signal is led out from the voltage division node.

[0063] Specifically, in the embodiment, the voltage division resistors can be set according to actual needs. In the embodiment of the present application, two voltage division resistors are set as an example, the resistance voltage division unit comprises a first voltage division resistor R1 and a second voltage division resistor R3, and the connection point between the first voltage division resistor R1 and the second voltage division resistor R3 is the voltage division node, and the first voltage division signal (A point voltage) of the input signal is led out from the voltage division node.

[0064] As a preferred embodiment, it further comprises:

[0065] A first NMOS tube NM1, the gate of the first NMOS tube NM1 is connected to a first bias voltage, the drain of the first NMOS tube NM1 is connected to the input signal V IN , and the drain of the first NMOS tube NM1 is connected to the resistance voltage division unit.

[0066] Specifically, in the embodiment, the first NMOS tube NM1 provides a bias current for the resistance voltage division unit.

[0067] As a preferred embodiment, wherein, further comprising:

[0068] a second comparison unit connected to the adjusting unit, for comparing the first divided voltage signal (the voltage at point A) of the input signal and the reference signal V REF to generate a second comparison signal.

[0069] Specifically, in this embodiment, the second comparison unit compares the first divided voltage signal (the voltage at point A) of the input signal of the LDO and the reference signal V REF to generate a second comparison signal.

[0070] When the input signal V IN is high, the first divided voltage signal (the voltage at point A) of the input signal is higher than the voltage of the reference signal V REF , the second comparison unit COM1 outputs low level, and COM1 does not flip;

[0071] When the input signal V IN is continuously reduced, the first divided voltage signal (the voltage at point A) of the input signal is lower than the voltage of the reference signal V REF , the second comparison unit COM1 outputs high level, and COM1 flips.

[0072] Further, the embodiment of the present application further comprises a filter circuit, which comprises a filter resistor R2 and a filter capacitor C1, for filtering the first divided voltage signal (the voltage at point A) of the input signal, and then inputting the filtered first divided voltage signal (the voltage at point A) of the input signal to the second comparison unit COM1, so as to compare the filtered first divided voltage signal (the voltage at point A) of the input signal with the voltage of the reference signal V REF .

[0073] As a preferred embodiment, wherein, the second comparison unit comprises:

[0074] a second NMOS tube NM2, the gate and the drain of the second NMOS tube NM2 are connected to a power voltage;

[0075] a third NMOS tube NM3, the gate of the third NMOS tube NM3 is connected to the gate of the second NMOS tube NM2, and the drain of the third NMOS tube NM3 is connected to the adjusting unit;

[0076] a fourth NMOS tube NM4, the gate of the fourth NMOS tube NM4 is connected to the first divided voltage signal (the voltage at point A) of the input signal, the drain of the fourth NMOS tube NM4 is connected to the source of the second NMOS tube, and the source of the fourth NMOS tube NM4 is connected to the first sampling unit;

[0077] a fifth NMOS tube NM5, the gate of the fifth NMOS tube NM5 is connected to the reference signal V REFThe drain of the fifth NMOS transistor NM5 is connected to the source of the third NMOS transistor NM3, and the source of the fifth NMOS transistor NM5 is connected to the source of the fourth NMOS transistor.

[0078] In particular, in the embodiment, the second comparison unit COM1 is implemented by four NMOS transistors, i.e., the second to fifth NMOS transistors.

[0079] As a preferred implementation, the application further comprises:

[0080] The first sampling unit is connected to the second comparison unit and is configured to sample the tail current of the second comparison unit under the action of the gate control signal V PG to obtain a first sampling signal I1.

[0081] As a preferred implementation, the first sampling unit comprises:

[0082] The sixth NMOS transistor has its gate connected to the gate and drain of the eleventh NMOS transistor NM11, its drain connected to the source of the fourth NMOS transistor, and its source connected to a ground terminal.

[0083] As a preferred implementation, the application further comprises:

[0084] The second sampling unit is connected to the second comparison unit and is configured to sample the output current of the second comparison unit under the action of the gate control signal V PG to obtain a second sampling signal I2.

[0085] As a preferred implementation, the second sampling unit comprises:

[0086] The seventh NMOS transistor has its gate connected to the gate and drain of the eleventh NMOS transistor NM11, its drain connected to the source of the fifth NMOS transistor, and its source connected to a ground terminal.

[0087] As a preferred implementation, the adjustment unit comprises:

[0088] The first resistor R4 is connected between the input signal V IN and a first adjustment node C, and the first adjustment node C is connected to the second comparison unit.

[0089] The first transistor NJFET1 has its gate connected to the output signal V OUT , its drain connected to the first resistor R4, and its source connected to a second adjustment node E, from which a first signal (voltage at point E) is derived.

[0090] Specifically, in the embodiment, when the input signal V IN is high, the first voltage-divided signal (the voltage at point A) of the input signal is higher than the voltage of the reference signal V REF , the second comparison unit COM1 does not flip, the first sampling signal I1 and the second sampling signal I2 all flow through the fourth NMOS tube NM4, at this time, the current I3 flowing through the first resistor R4 is small, the voltage at point C is VIN-I3*R4, the voltage at point C is high, and the voltage of the first signal (the voltage at point E) after passing through the first transistor NJFET1 is higher than the output signal V OUT of the LDO.

[0091] When the input signal V IN continuously decreases, the first voltage-divided signal (the voltage at point A) of the input signal is lower than the voltage of the reference signal V REF , the second comparison unit COM1 flips, the first sampling signal I1 and the second sampling signal I2 all flow through the first resistor R4, at this time, the current I3 flowing through the first resistor R4 is large, the voltage at point C is VIN-I3*R4, the voltage at point C is low, and the voltage of the first signal (the voltage at point E) after passing through the first transistor NJFET1 is lower than the output signal V OUT of the LDO.

[0092] As a preferred embodiment, wherein the first comparison unit COM2 comprises:

[0093] a first PMOS tube PM1, the source of the first PMOS tube PM1 being connected to the first signal (the voltage at point E);

[0094] a second PMOS tube PM2, the gate of the second PMOS tube PM2 being connected to the gate and the drain of the first PMOS tube PM1, the source of the second PMOS tube PM2 being connected to the output signal V OUT .

[0095] a third PMOS tube PM3, the source of the third PMOS tube PM3 being connected to the drain of the first PMOS tube PM1;

[0096] a fourth PMOS tube PM4, the gate of the fourth PMOS tube PM4 being connected to the gate and the drain of the third PMOS tube PM3, the source of the fourth PMOS tube PM4 being connected to the drain of the second PMOS tube PM2, and the first comparison signal being output from the drain of the fourth PMOS tube PM4.

[0097] Specifically, in the embodiment, the comparison between the first signal (the voltage at point E) and the output signal V OUT of the LDO is realized by four PMOS tubes, i.e., the first to fourth PMOS tubes.

[0098] Further, when the input signal V INWhen the input signal V OUT is higher, the second comparison unit COM1 does not flip, the voltage of the first signal (the voltage at point E) after the first transistor NJFET1 is higher than the output signal V IN of the LDO, the first comparison unit COM2 outputs low level, and COM2 does not flip.

[0099] When the input signal V IN continuously decreases, the second comparison unit COM1 flips, the voltage of the first signal (the voltage at point E) after the first transistor NJFET1 is lower than the output signal V OUT of the LDO, the first comparison unit COM2 outputs high level, and COM2 flips.

[0100] As a preferred embodiment, the first comparison unit COM2 further comprises:

[0101] an eighth NMOS tube NM8, a gate of the eighth NMOS tube NM8 is connected to a second bias voltage, a drain of the eighth NMOS tube NM8 is connected to a drain of a third PMOS tube PM3, and a source of the eighth NMOS tube is connected to a ground terminal through a second resistor R5;

[0102] a ninth NMOS tube NM9, a gate of the ninth NMOS tube NM9 is connected to the second bias voltage, a drain of the ninth NMOS tube NM9 is connected to a drain of a fourth PMOS tube PM4, and a source of the ninth NMOS tube NM9 is connected to the ground terminal through a third resistor R6.

[0103] Specifically, in the embodiment, the eighth NMOS tube and the ninth NMOS tube are arranged to provide a bias current for the first comparison unit COM2 under the action of the bias voltage.

[0104] As a preferred embodiment, the control unit comprises:

[0105] a fifth PMOS tube PM5, a gate of the fifth PMOS tube PM5 is connected to the first comparison signal, and a drain of the fifth PMOS tube PM5 is connected to the ground terminal;

[0106] a tenth NMOS tube NM10, a gate of the tenth NMOS tube NM10 is connected to a source of the fifth PMOS tube PM5, a drain of the tenth NMOS tube NM10 is connected to the input signal V IN through a bias tube PM6, and a source of the tenth NMOS tube NM10 outputs a control signal.

[0107] Specifically, in the embodiment, when the first comparison unit COM2 outputs low level, the fifth PMOS tube PM5 is cut off, the tenth NMOS tube NM10 is cut off, and the circuit for reducing static power consumption in a low voltage drop state shown in the embodiment does not work.

[0108] When the first comparator COM2 outputs a high level, the fifth PMOS transistor PM5 and the tenth NMOS transistor NM10 are turned on, thereby pulling up the gate voltage of the power transistor and reducing power consumption. The circuit for reducing static power consumption in the voltage drop state shown in this embodiment of the invention has the characteristics of simple circuit structure, small chip area and low cost.

[0109] Furthermore, it also includes: a bias current source, which is also connected to the input signal V. IN Between the gate of the tenth NMOS transistor NM10 and the gate of the LDO, the internal bias current IBIAS1 is generated.

[0110] In a preferred embodiment, the main operational amplifier 7 of the LDO further includes;

[0111] The first operational amplifier A1 is connected to the input signal V. IN The connection between the ground terminal and the reference signal V is used for... REF and the voltage feedback signal V of the output signal B The signal is processed by an operational amplifier to obtain the first operational amplifier signal;

[0112] The second operational amplifier A2 is connected to the output terminal of the first operational amplifier A1 and the control signal, respectively. It is used to process the second operational amplifier signal to obtain the second operational amplifier signal; and to pull up the voltage of the first operational amplifier signal under the action of the control signal.

[0113] The third operational amplifier A3 has its input connected to the output of the second operational amplifier A2, and its output connected to the power transistor M. P The gate is used to process the second operational amplifier signal to obtain the gate control signal V. PG .

[0114] Specifically, in this embodiment, when the first comparator COM2 outputs a high level, the fifth PMOS transistor PM5 is turned on and the tenth NMOS transistor NM10 is turned on, thereby pulling up the input voltage of the second operational amplifier A2 and the gate voltage of the power transistor in the second stage of the main operational amplifier, thereby reducing power consumption. The circuit for reducing static power consumption in the voltage drop state shown in this embodiment of the invention has the characteristics of simple circuit structure, small chip area and low cost.

[0115] Furthermore, LDO also includes: sampling tube M SAM Sampling tube M SAM The gate of the sampling transistor M is connected to the output of the third operational amplifier A3. SAM The source is connected to the input signal V. IN Sampling tube M SAM The drain is connected to the ground terminal, used for the gate control signal V. PG Under the action of power transistor M PThe current of the sampling transistor is sampled, and the sampling current of the output power transistor is output.

[0116] Further, the LDO further comprises an eleventh NMOS transistor NM11, a gate and a drain of the eleventh NMOS transistor NM11 are connected to the sampling transistor M SAM , and a source of the eleventh NMOS transistor NM11 is connected to a ground terminal, for providing a mirror current for the sampling transistor M SAM .

[0117] In the preferred embodiment, as shown in Figure 2 , a structure diagram of the LDO is shown, IN, OUT, EN and GND are four PINs of the LDO, the IN pin is used for receiving an input signal V IN , the OUT pin is used for outputting an output signal V OUT , and the LDO further comprises an input filter capacitor C IN , which is used for filtering the input signal V IN , and an output filter capacitor C OUT , which is used for filtering the output signal V OUT .

[0118] As shown in Figure 3 , a structure diagram of internal modules of the LDO is shown, comprising a reference (VREF) module 1, an enable (EN) module 2, a bias (VBIAS) module 3, an under-voltage lockout (UVLO) module 4, an over-temperature protection (OTP) module 5, an over-current protection (OCP) module 6, a main operational amplifier 7, a discharge (Discharge) module 8, an input terminal of the reference module 1 is connected to an input signal V IN , an output terminal of the reference module 1 is connected to a first input terminal of the main operational amplifier 7, for generating a reference signal V REF , a second input terminal of the main operational amplifier 7 is connected to a voltage feedback signal V B sampled from the output signal, and the loop is stabilized through negative feedback to obtain a stable output power supply; the bias module 3 provides bias current and bias voltage for each module; the enable module 2, the over-temperature protection module 5, the over-current protection module 6 and the under-voltage lockout module 4 are used for controlling the opening or closing of the LDO circuit and protecting the LDO circuit.

[0119] Further, an output terminal of the circuit for reducing static power consumption in a voltage drop state is connected to an input terminal of a second operational amplifier A2 of a second stage of the main operational amplifier, and finally controls a gate of a power transistor and forms a negative feedback to realize the ability of reducing power consumption.

[0120] When the input signal V IN is high or with light load, the circuit for reducing static power consumption in a voltage drop state does not work.

[0121] When the input signal VIN When the lower and LDO is working under heavy load, the first voltage of the input signal (the voltage of point A) is lower than the voltage of the reference signal V REF , the second comparison unit COM1 flips, the first sampling signal I1 and the second sampling signal I2 all flow through the first resistor R4, at this time, the current I3 flowing through the first resistor R4 is larger, the voltage of point C is VIN-I3*R4, the voltage of point C is lower, the voltage of the first signal (the voltage of point E) after the first transistor NJFET1 is lower than the output signal V OUT of the LDO, the first comparison unit COM2 outputs a high level, the fifth PMOS tube PM5 is turned on, the tenth NMOS tube NM10 is turned on, thereby pulling up the voltage of the input end of the second operational amplifier A2 and the gate voltage of the power tube, thereby reducing the power consumption.

[0122] The advantage or beneficial effect of the above technical solution is that the circuit can effectively reduce the power consumption of the LDO in the voltage drop region, prolong the battery use time, has the characteristics of simple structure and low cost.

[0123] The above is only the preferred embodiment of the present application, and does not limit the implementation and protection scope of the present application. Those skilled in the art should realize that any equivalent replacement and obvious change made by using the content of the present application should be included in the protection scope of the present application.

Claims

1. A circuit for reducing static power consumption in a voltage drop state, characterized in that, This is applied to a low-dropout linear regulator, which includes a power transistor used to regulate and stabilize the input signal under the action of a gate control signal to generate an output signal. The circuit includes: An adjustment unit is used to process the second voltage divider signal of the input signal under the action of the output signal when the first voltage divider signal of the input signal is lower than a reference signal, so as to generate a first signal that is lower than the output signal. A first comparison unit, connected to the adjustment unit, is used to compare the first signal and the output signal to generate a first comparison signal; The control unit, connected to the first comparison unit, is used to generate a control signal under the action of the first comparison signal, so as to pull up the voltage of the gate control signal according to the control signal.

2. The circuit for reducing static power consumption in a voltage drop state according to claim 1, characterized in that, Also includes: A voltage divider unit includes a predetermined number of voltage divider resistors connected in series between the input signal and the ground terminal. The points where the voltage divider resistors are connected form voltage divider nodes, and a first voltage divider signal of the input signal is led out from the voltage divider nodes.

3. The circuit for reducing static power consumption in a voltage drop state according to claim 2, characterized in that, Also includes: A first NMOS transistor, the gate of the first NMOS transistor is connected to a first bias voltage, the drain of the first NMOS transistor is connected to the input signal, and the source of the first NMOS transistor is connected to the resistor divider unit.

4. The circuit for reducing static power consumption in a voltage drop state according to claim 1, characterized in that, Also includes: The second comparison unit, connected to the adjustment unit, is used to compare the first voltage divider signal of the input signal and the reference signal to generate a second comparison signal; The first sampling unit is connected to the second comparison unit and is used to sample the tail current of the second comparison unit under the action of the power transistor sampling current signal to obtain the first sampling signal; The second sampling unit, connected to the second comparison unit, is used to sample the output current of the second comparison unit under the action of the sampling current signal of the power transistor to obtain the second sampling signal.

5. The circuit for reducing static power consumption in a voltage drop state according to claim 4, characterized in that, The second comparison unit includes: The second NMOS transistor has its gate and drain connected to a power supply voltage. The third NMOS transistor has its gate connected to the gate of the second NMOS transistor, and its drain connected to the adjustment unit. The fourth NMOS transistor has its gate connected to the first voltage divider signal of the input signal, its drain connected to the source of the second NMOS transistor, and its source connected to the first sampling unit. The fifth NMOS transistor has its gate connected to the reference signal, its drain connected to the source of the third NMOS transistor, and its source connected to the source of the fourth NMOS transistor.

6. The circuit for reducing static power consumption in a voltage drop state according to claim 5, characterized in that, The first sampling unit includes: The sixth NMOS transistor has its gate connected to the power transistor sampling current signal, its drain connected to the source of the fourth NMOS transistor, and its source connected to the ground terminal. The second sampling unit includes: The seventh NMOS transistor has its gate connected to the power transistor for sampling current signals, its drain connected to the drain of the fifth NMOS transistor, and its source connected to the ground terminal.

7. The circuit for reducing static power consumption in a voltage drop state according to claim 4, characterized in that, The adjustment unit includes: A first resistor is connected between the input signal and a first adjustment node, the first adjustment node being connected to the second comparison unit; A first transistor, the gate of which is connected to the output signal, the drain of which is connected to the first resistor, and the source of which is connected to a second adjustment node, from which the first signal is led out.

8. The circuit for reducing static power consumption in a voltage drop state according to claim 1, characterized in that, The first comparison unit includes: The first PMOS transistor, the source of which is connected to the first signal; The second PMOS transistor has its gate connected to the gate and drain of the first PMOS transistor, and its source connected to the output signal. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor. The fourth PMOS transistor has its gate connected to the gate and drain of the third PMOS transistor, and its source connected to the drain of the second PMOS transistor. The first comparison signal is output from the drain of the fourth PMOS transistor. The eighth NMOS transistor has its gate connected to a second bias voltage, its drain connected to the drain of the third PMOS transistor, and its source connected to ground through a second resistor. The ninth NMOS transistor has its gate connected to the second bias voltage, its drain connected to the drain of the fourth PMOS transistor, and its source connected to the ground terminal through a third resistor.

9. The circuit for reducing static power consumption in a voltage drop state according to claim 1, characterized in that, The control unit includes: The fifth PMOS transistor has its gate connected to the first comparison signal and its drain connected to ground. The tenth NMOS transistor has its gate connected to the source of the fifth PMOS transistor, and its drain connected to the input signal via a bias transistor. The control signal is output from the source of the tenth NMOS transistor.

10. The circuit for reducing static power consumption in a voltage drop state according to claim 1, characterized in that, Also includes; The first operational amplifier is connected between the input signal and the ground terminal to perform operational amplifier processing on the voltage feedback signal between the reference signal and the output signal to obtain the first operational amplifier signal; The second operational amplifier is connected to the output terminal of the first operational amplifier and the control signal, respectively, and is used to perform operational amplifier processing on the second operational amplifier signal to obtain the second operational amplifier signal. And, under the action of the control signal, the voltage of the first operational amplifier signal is increased; A third operational amplifier, the input of which is connected to the output of the second operational amplifier, and the output of which is connected to the gate of the power transistor, is used to process the second operational amplifier signal to obtain the gate control signal.

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