A circuit for reducing clock signal jitter
By connecting the relevant output ends of the phase-locking loop chip at the board level, the non-correlation noise of the same frequency and in-phase clock signals is reduced, and the problem of increasing clock signal jitter in high-speed communication systems is solved, and higher clock signal stability is achieved.
Patent Information
- Application Number
- CN202311709206.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-12
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2043-12-12
AI Technical Summary
In high-speed communication systems, there is a large non-correlation noise in the clock signal at the same frequency and phase, resulting in an increase in clock signal jitter. The prior art optimizes the internal circuit of the clock chip but realizes complexity and cannot meet the needs of application circuits.
A circuit structure including a phase-locking loop chip and a plurality of application circuits is designed, and the uncorrelated noise received by the application circuit is reduced by connecting the relevant output ends of the phase-locking loop chip output as a clock signal of the same frequency and phase at the board level, thereby reducing the clock signal jitter.
With this circuit structure, clock signal jitter can be reduced simply and effectively, and the application circuit needs for clock signal stability.
Smart Images
Figure CN117595865B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and in particular to a circuit for reducing clock signal jitter. Background Art
[0002] In a communication system, the clock signal is responsible for synchronizing the communication between various components, ensuring that the various components work in coordination according to a unified time standard, thereby ensuring the accuracy and stability of the system. Currently used high-speed communication systems have increasingly higher requirements for clock signal jitter. Communication systems may require multiple clock signals with the same frequency and phase (referred to as same frequency and same phase) as the reference clock of the communication system. However, clock signals with the same frequency and phase have large uncorrelated noise, which is one of the factors causing clock signal jitter, resulting in increased clock signal jitter.
[0003] Currently, the accuracy and stability of clock signals are improved and the jitter of clock signals is reduced mainly by optimizing the circuit inside the clock chip. However, the implementation circuit of the current method is relatively complex, and the jitter of clock signals with the same frequency and phase still cannot meet the requirements of the application circuit. Summary of the invention
[0004] In view of this, the present application provides a circuit for reducing clock signal jitter. The circuit has a simple circuit structure and can reduce the uncorrelated noise of the same-frequency and same-phase clock signals received by the application circuit, thereby reducing the clock signal jitter.
[0005] To solve the above problems, the technical solutions provided by this application are as follows:
[0006] A circuit for reducing clock signal jitter, the circuit for reducing clock signal jitter comprising: a phase-locked loop chip and a plurality of application circuits, wherein:
[0007] The phase-locked loop chip includes a plurality of output terminals, the plurality of output terminals are respectively connected to the plurality of application circuits, the plurality of output terminals are used to respectively provide clock signals to the plurality of application circuits, and the plurality of application circuits are circuits designed according to application requirements;
[0008] The related output ends among the plurality of output ends have related output ends whose output clock signals have the same frequency and phase, and are connected to the related output ends.
[0009] Optionally, when the clock signal is a differential signal, the multiple output terminals have related output terminals that have the same frequency and phase of the output clock signal, and connecting the related output terminals comprises:
[0010] Connecting the positive electrodes of the differential signals of the relevant output terminals;
[0011] The negative electrodes of the differential signals of the relevant output terminals are connected.
[0012] Optionally, when the clock signal is a differential signal, the circuit for reducing the jitter of the clock signal further includes a plurality of buffers, wherein the plurality of output ends have relevant output ends whose output clock signals have the same frequency and phase, and the relevant output ends are connected, including:
[0013] The first input terminals of the plurality of buffers are respectively connected to the positive electrodes of the differential signals of the relevant output terminals;
[0014] The second input terminals of the plurality of buffers are respectively connected to the negative electrodes of the differential signals of the relevant output terminals;
[0015] The output ends of the plurality of buffers are respectively connected to the plurality of application circuits.
[0016] Optionally, when the clock signal is a single-ended signal, the circuit for reducing the jitter of the clock signal further includes an impedance matching circuit, wherein the relevant output terminals among the plurality of output terminals have the same frequency and phase of the output clock signal, and the relevant output terminals are connected, including:
[0017] connecting the single-ended signals of the relevant output terminals;
[0018] The impedance matching circuit is respectively added to the plurality of application circuits connected to the relevant output terminals.
[0019] Optionally, connecting the relevant output terminal includes:
[0020] The related output terminals are connected according to a preset connection principle, wherein the preset connection principle is that the length of the connection line of the related output terminal is within a first threshold interval, and the distance between the connection line and the phase-locked loop chip is within a second threshold interval.
[0021] Optionally, if there are non-correlated output terminals among the plurality of output terminals that have different frequencies and / or phases of the output clock signals, the related output terminals and the non-correlated output terminals are not connected.
[0022] Optionally, when the clock signal is a differential signal, the relevant output terminal and the non-relevant output terminal are not connected, including:
[0023] The positive electrode of the differential signal of the relevant output terminal and the positive electrode of the differential signal of the non-relevant output terminal are not connected;
[0024] The negative electrode of the differential signal at the relevant output terminal and the negative electrode of the differential signal at the non-relevant output terminal are not connected.
[0025] Optionally, when the clock signal is a single-ended signal, the relevant output terminal and the non-relevant output terminal are not connected, including:
[0026] There is no connection between the single-ended signal of the relevant output terminal and the single-ended signal of the non-relevant output terminal.
[0027] It can be seen that this application has the following beneficial effects:
[0028] The present application provides a circuit for reducing clock signal jitter, and the circuit for reducing clock signal jitter includes: a phase-locked loop chip and multiple application circuits. The phase-locked loop chip includes multiple output terminals, and the multiple output terminals are respectively connected to the multiple application circuits. The multiple output terminals are used to provide clock signals to the multiple application circuits respectively, and the multiple application circuits are circuits designed according to application requirements; the multiple output terminals have related output terminals with the same frequency and phase of the output clock signal, and the related output terminals are connected. In this way, by connecting the related output terminals of the phase-locked loop chip that outputs the clock signal of the same frequency and phase at the board level, the non-correlated noise of the clock signal of the same frequency and phase received by the application circuit can be reduced, thereby reducing the clock signal jitter. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A schematic diagram of the structure of a circuit for reducing clock signal jitter provided in an embodiment of the present application;
[0030] Figure 2 A schematic diagram of the structure of another circuit for reducing clock signal jitter provided in an embodiment of the present application;
[0031] Figure 3 A schematic diagram of the structure of another circuit for reducing clock signal jitter provided in an embodiment of the present application;
[0032] Figure 4 A schematic diagram of the structure of another circuit for reducing clock signal jitter provided in an embodiment of the present application. DETAILED DESCRIPTION
[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0034] In this application, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.
[0035] The clock signal with the same frequency and phase is the reference clock of the communication system, but the clock signal with the same frequency and phase has a large amount of uncorrelated noise. Uncorrelated noise is one of the factors that cause the jitter of the clock signal, resulting in increased jitter of the clock signal. At present, the accuracy and stability of the clock signal are mainly improved by optimizing the circuit inside the clock chip to reduce the jitter of the clock signal. However, the implementation circuit of the current method is relatively complex, and the clock signal with the same frequency and phase still has jitter, which cannot meet the current needs in the application circuit.
[0036] Based on this, an embodiment of the present application provides a circuit for reducing clock signal jitter, and the circuit for reducing clock signal jitter includes: a phase-locked loop chip and multiple application circuits. The phase-locked loop chip includes multiple output terminals, and the multiple output terminals are respectively connected to the multiple application circuits. The multiple output terminals are used to provide clock signals to the multiple application circuits respectively, and the multiple application circuits are circuits designed according to application requirements; the multiple output terminals have related output terminals with the same frequency and phase of the output clock signal, and the related output terminals are connected. In this way, by connecting the related output terminals of the phase-locked loop chip that outputs the same frequency and phase clock signals at the board level, the non-correlated noise of the same frequency and phase clock signals received by the application circuit can be reduced, thereby reducing the clock signal jitter.
[0037] To facilitate understanding of the technical solution provided by the embodiment of the present application, a circuit for reducing clock signal jitter provided by the embodiment of the present application is described below in conjunction with the accompanying drawings.
[0038] The circuit for reducing the jitter of the clock signal includes a phase-locked loop chip and multiple application circuits, wherein: the phase-locked loop chip includes multiple output terminals, the multiple output terminals are respectively connected to the multiple application circuits, the multiple output terminals are used to provide clock signals for the multiple application circuits respectively, and the multiple application circuits are circuits designed according to application requirements; the multiple output terminals have related output terminals with the same frequency and phase of the output clock signal, and the related output terminals are connected. In the embodiment of the present application, the principle of the embodiment of the present application is explained by taking the example that the phase-locked loop chip has three output terminals and the clock signal output by the phase-locked loop chip is a differential signal.
[0039] See also Figure 1 , Figure 1 A schematic diagram of a circuit for reducing clock signal jitter provided in an embodiment of the present application. The circuit for reducing clock signal jitter includes: a phase-locked loop chip 11, a first application circuit 12, a second application circuit 13 and a third application circuit 14.
[0040] The three output terminals of the phase-locked loop chip 11 are used to output the first clock signal Clk1, the second clock signal Clk2 and the third clock signal Clk3, respectively providing clocks for the first application circuit 12, the second application circuit 13 and the third application circuit 14. Among them, the first clock signal Clk1 is a differential signal, including: a positive electrode Clk1+ and a negative electrode Clk1-; the second clock signal Clk2 is a differential signal, including: a positive electrode Clk2+ and a negative electrode Clk2-; the third clock signal Clk3 is a differential signal, including: a positive electrode Clk3+ and a negative electrode Clk3-.
[0041] The first application circuit 12 , the second application circuit 13 and the third application circuit 14 are circuits designed according to application requirements and are connected to the first output terminal, the second output terminal and the third output terminal of the phase-locked loop chip 11 , respectively.
[0042] When the three output ends of the phase-locked loop chip 11 have related output ends whose output clock signals have the same frequency and phase, taking the first clock signal Clk1 output from the first output end and the second clock signal Clk2 output from the second output end of the phase-locked loop chip 11 as an example, the related output ends are the first output end and the second output end. The related output ends having the same frequency and phase of the output clock signals among the multiple output ends are connected, including:
[0043] Connecting a positive electrode Clk1+ of a first clock signal Clk1 outputted from a first output terminal of the phase-locked loop chip 11 to a positive electrode Clk2+ of a second clock signal Clk2 outputted from a second output terminal of the phase-locked loop chip 11;
[0044] A negative electrode Clk1 − of a first clock signal Clk1 outputted from a first output terminal of the phase-locked loop chip 11 is connected to a negative electrode Clk2 − of a second clock signal Clk2 outputted from a second output terminal of the phase-locked loop chip 11 .
[0045] Further, the relevant output terminals are connected according to a preset connection principle, and the preset connection principle is that the length of the connection line of the relevant output terminal is in a first threshold interval, and the distance between the connection line and the phase-locked loop chip is in a second threshold interval. The preset connection principle is that the length of the line connecting the first output terminal and the second output terminal of the phase-locked loop chip 11 is in the first threshold interval, and the distance between the connection line and the phase-locked loop chip 11 is in the second threshold interval. The first threshold interval and the second threshold interval can be set according to actual conditions to meet the requirements that the length of the connection line of the relevant output terminal is short and the distance between the connection line and the phase-locked loop chip 11 is close. The length of the connection line and the distance between the connection line and the phase-locked loop chip 11 are dynamically optimal, which can reduce the jitter of the clock signal.
[0046] Optionally, the multiple output terminals of the phase-locked loop chip 11 also have non-correlated output terminals with different frequencies and / or phases of the output clock signal, and the related output terminals and the non-correlated output terminals are not connected. The third output terminal is described as a non-correlated output terminal.
[0047] The frequency of the third clock signal Clk3 outputted from the third output terminal of the phase-locked loop chip 11 is different from the frequency of the first clock signal Clk1 outputted from the first output terminal of the phase-locked loop chip 11, and / or the phase of the third clock signal Clk3 outputted from the third output terminal of the phase-locked loop chip 11 is different from the phase of the first clock signal Clk1 outputted from the first output terminal of the phase-locked loop chip 11, then the third output terminal of the phase-locked loop chip 11 is not connected to the first output terminal. The third output terminal of the phase-locked loop chip 11 is directly connected to the third application circuit 14.
[0048] Specifically, the positive electrode Clk3+ of the third output end of the phase-locked loop chip 11 is not connected to the positive electrode Clk1+ of the first output end of the phase-locked loop chip 11; the negative electrode Clk3- of the third output end of the phase-locked loop chip 11 is not connected to the negative electrode Clk1- of the first output end of the phase-locked loop chip 11.
[0049] Similarly, the positive electrode Clk3+ of the third output end of the phase-locked loop chip 11 is not connected to the positive electrode Clk2+ of the second output end of the phase-locked loop chip 11; the negative electrode Clk3- of the third output end of the phase-locked loop chip 11 is not connected to the negative electrode Clk2- of the second output end of the phase-locked loop chip 11.
[0050] Another embodiment of the present application provides a schematic diagram of the structure of another circuit for reducing clock signal jitter, and its specific structure is as follows: Figure 2 As shown, it is Figure 1The difference between the illustrated embodiments is that the circuit for reducing the jitter of the clock signal further includes a plurality of buffers, which are described by taking the first buffer 31 and the second buffer 32 as an example. The buffers are used to improve the transmission capability and stability of the clock signal.
[0051] The clock signal is a differential signal, and the multiple output ends have related output ends with the same frequency and phase of the output clock signal, and the related output ends are connected, including: the first input ends of the multiple buffers are respectively connected to the positive poles of the differential signals of the related output ends; the second input ends of the multiple buffers are respectively connected to the negative poles of the differential signals of the related output ends; the output ends of the multiple buffers are respectively connected to the multiple application circuits.
[0052] Specifically, the first clock signal Clk1 outputted from the first output terminal of the phase-locked loop chip 11 has the same frequency and phase as the second clock signal Clk2 outputted from the second output terminal of the phase-locked loop chip 11, and the first output terminal and the second output terminal of the phase-locked loop chip 11 are connected, including:
[0053] The first input end of the first buffer 31 is connected to the positive electrode Clk1+ of the first output end of the phase-locked loop chip 11; the second input end of the first buffer 31 is connected to the negative electrode Clk2- of the second output end of the phase-locked loop chip 11; the output end of the first buffer 31 is connected to the first application circuit 12.
[0054] The first input end of the second buffer 32 is connected to the positive electrode Clk2+ of the second output end of the phase-locked loop chip 11; the second input end of the second buffer 32 is connected to the negative electrode Clk1- of the first output end of the phase-locked loop chip 11; the output end of the second buffer 32 is connected to the second application circuit 13.
[0055] Further, the related output terminals are connected according to a preset connection principle. The preset connection principle is that the length of the line connecting the first buffer 31 and the second buffer 32 to the first output terminal and the second output terminal of the phase-locked loop chip 11 is respectively in the third threshold interval, and the distance between the first buffer 31, the second buffer 32 and the phase-locked loop chip 11 is in the fourth threshold interval. The third threshold interval and the fourth threshold interval can be set according to actual conditions to meet the dynamic optimal situation that the length of the connection line is short and the distance between the buffer and the phase-locked loop chip 11 is close, which can reduce the jitter of the clock signal.
[0056] Optionally, the multiple output terminals of the phase-locked loop chip 11 also have non-correlated output terminals with different frequencies and / or phases of the output clock signal, and the related output terminals and the non-correlated output terminals are not connected. The third output terminal is described as a non-correlated output terminal.
[0057] The frequency of the third clock signal Clk3 outputted from the third output terminal of the phase-locked loop chip 11 is different from the frequency of the first clock signal Clk1 outputted from the first output terminal of the phase-locked loop chip 11, and / or the phase of the third clock signal Clk3 outputted from the third output terminal of the phase-locked loop chip 11 is different from the phase of the first clock signal Clk1 outputted from the first output terminal of the phase-locked loop chip 11, then the third output terminal of the phase-locked loop chip 11 is directly connected to the third application circuit 14.
[0058] The relevant output terminal and the irrelevant output terminal are not connected, specifically: the third output terminal of the phase-locked loop chip 11 is not connected to the first buffer 31. Similarly, the third output terminal of the phase-locked loop chip 11 is not connected to the second buffer 32.
[0059] Another embodiment of the present application provides a schematic diagram of a circuit structure for reducing clock signal jitter, and its specific structure is as follows: Figure 3 As shown, it is Figure 1 The difference of the embodiment shown is that it further includes: the phase-locked loop chip 11 has a fourth output terminal, a fourth application circuit 15, a third buffer 33, a fourth buffer 34 and a fifth buffer 35. The first output terminal, the second output terminal and the third output terminal are related output terminals, and the fourth output terminal is a non-related output terminal.
[0060] In this embodiment, when the frequencies and phases of the first clock signal Clk1 outputted from the first output terminal of the phase-locked loop chip 11, the second clock signal Clk2 outputted from the second output terminal of the phase-locked loop chip 11, and the third clock signal Clk3 outputted from the third output terminal of the phase-locked loop chip 11 are the same, the first output terminal, the second output terminal, and the third output terminal of the phase-locked loop chip 11 are connected, specifically including:
[0061] The first input terminal of the third buffer 33 is connected to the positive electrode Clk1+ of the first output terminal of the phase-locked loop chip 11; the second input terminal of the third buffer 33 is connected to the negative electrode Clk2- of the second output terminal of the phase-locked loop chip 11; the output terminal of the third buffer 33 is connected to the first application circuit 12.
[0062] The first input terminal of the fourth buffer 34 is connected to the positive electrode Clk2+ of the second output terminal of the phase-locked loop chip 11; the second input terminal of the fourth buffer 34 is connected to the negative electrode Clk3- of the third output terminal of the phase-locked loop chip 11; the output terminal of the fourth buffer 34 is connected to the second application circuit 13.
[0063] The first input terminal of the fifth buffer 35 is connected to the positive electrode Clk3+ of the third output terminal of the phase-locked loop chip 11; the second input terminal of the fifth buffer 35 is connected to the negative electrode Clk1- of the first output terminal of the phase-locked loop chip 11; the output terminal of the fifth buffer 35 is connected to the third application circuit 14.
[0064] Further, the related output terminals are connected according to the preset connection principle, specifically, the length of the line connecting the third buffer 33, the fourth buffer 34 and the fifth buffer 35 to the first output terminal, the second output terminal and the third output terminal of the phase-locked loop chip 11 is respectively within the fifth threshold interval, and the distance between the third buffer 33, the fourth buffer 34 and the fifth buffer 35 and the phase-locked loop chip 11 is within the sixth threshold interval. The fifth threshold interval and the sixth threshold interval can be set according to actual conditions to meet the dynamic optimal situation that the length of the connection line is short and the distance between the buffer and the phase-locked loop chip 11 is close, which can reduce the jitter of the clock signal.
[0065] and Figure 2 The embodiment shown is the same, the non-related output terminal is not connected to the buffer, and the non-related output terminal is directly connected to the application circuit. Specifically, the fourth clock signal Clk4 outputted by the fourth output terminal of the phase-locked loop chip 11 is different in frequency or phase from the first clock signal Clk1 outputted by the first output terminal of the phase-locked loop chip 11, and the fourth output terminal of the phase-locked loop chip 11 is directly connected to the fourth application circuit 15.
[0066] Another embodiment of the present application provides a schematic diagram of a circuit structure for reducing clock signal jitter. The specific structure is as follows: Figure 4 As shown, it is Figure 1 The difference between the illustrated embodiments is that the clock signals outputted from the multiple output terminals of the phase-locked loop chip 11 are single-ended signals, that is, the first clock signal Clk21 outputted from the first output terminal, the second clock signal Clk22 outputted from the second output terminal, and the third clock signal Clk23 outputted from the third output terminal are single-ended signals.
[0067] The first output terminal and the second output terminal are related output terminals, and the third output terminal is a non-related output terminal. In this embodiment, the circuit for reducing clock signal jitter also includes an impedance matching circuit, which is a component structure of an application circuit connected to the related output terminal and is not in Figure 4 Shown in.
[0068] The first clock signal Clk21 outputted from the first output terminal of the phase-locked loop chip 11 has the same frequency and phase as the second clock signal Clk22 outputted from the second output terminal of the phase-locked loop chip 11. The first output terminal of the phase-locked loop chip 11 is connected to the second output terminal, specifically, the single-ended signal of the first output terminal is connected to the single-ended signal of the second output terminal. Impedance matching circuits are added to the first application circuit 12 and the second application circuit 13, respectively.
[0069] Further, the relevant output terminals are connected according to a preset connection principle. The preset connection principle is that the length of the line connecting the first output terminal and the second output terminal of the phase-locked loop chip 11 is in the seventh threshold interval, and the distance between the connecting line and the phase-locked loop chip 11 is in the eighth threshold interval. The seventh threshold interval and the eighth threshold interval can be set according to actual conditions to meet the requirements that the length of the connecting line of the relevant output terminal is short and the distance between the connecting line and the phase-locked loop chip 11 is close. The length of the connecting line and the distance between the connecting line and the phase-locked loop chip 11 are dynamically optimal, which can reduce the jitter of the clock signal.
[0070] Optionally, the multiple output ends of the phase-locked loop chip 11 also have non-correlated output ends with different frequencies and / or phases of the output clock signal, and the relevant output ends and the non-correlated output ends are not connected.
[0071] The frequency of the single-ended signal output from the third output terminal of the phase-locked loop chip 11 is different from the frequency of the single-ended signal output from the first output terminal of the phase-locked loop chip 11, and / or the phase of the single-ended signal output from the third output terminal of the phase-locked loop chip 11 is different from the phase of the single-ended signal output from the first output terminal of the phase-locked loop chip 11, then the single-ended signal of the relevant output terminal and the single-ended signal of the non-relevant output terminal are not connected, including: the third output terminal of the phase-locked loop chip 11 is not connected to the first output terminal.
[0072] Specifically, the single-ended signal at the third output terminal of the PLL chip 11 is not connected to the single-ended signal at the first output terminal of the PLL chip 11. Similarly, the single-ended signal at the third output terminal of the PLL chip 11 is not connected to the single-ended signal at the second output terminal of the PLL chip 11.
[0073] The circuit for reducing clock signal jitter in the embodiment of the present application can be applied to the clock circuit in radio or telecommunication network equipment, and can also be applied to the clock circuit in computer equipment. The above is only an example and does not limit the application scenarios of the embodiment of the present application.
[0074] Based on the above, the present application provides a circuit for reducing clock signal jitter, and the circuit for reducing clock signal jitter includes: a phase-locked loop chip and multiple application circuits. The phase-locked loop chip includes multiple output terminals, and the multiple output terminals are respectively connected to the multiple application circuits. The multiple output terminals are used to provide clock signals to the multiple application circuits respectively, and the multiple application circuits are circuits designed according to application requirements; the multiple output terminals have related output terminals with the same frequency and phase of the output clock signal, and the related output terminals are connected. In this way, the related output terminals of the phase-locked loop chip outputting the same frequency and phase clock signals are connected at the board level to reduce the non-correlated noise of the same frequency and phase clock signals received by the application circuit, thereby reducing the clock signal jitter.
[0075] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. Some or all of the circuit modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.
[0076] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A circuit for reducing clock signal jitter, characterized in that: The circuit for reducing clock signal jitter includes: a phase-locked loop chip and multiple application circuits, wherein: The phase-locked loop chip includes a plurality of output terminals, the plurality of output terminals are respectively connected to the plurality of application circuits, the plurality of output terminals are used to respectively provide clock signals to the plurality of application circuits, and the plurality of application circuits are circuits designed according to application requirements; A related output terminal having the same frequency and phase of the output clock signal among the plurality of output terminals is connected to the related output terminal, and the related output terminal includes a first output terminal and a second output terminal; When the clock signal is a differential signal, the circuit for reducing the jitter of the clock signal further includes a first buffer and a second buffer, and the plurality of output ends have related output ends whose output clock signals have the same frequency and phase, and the related output ends are connected, including: The first input terminal of the first buffer is connected to the positive electrode of the differential signal of the first output terminal; the second input terminal of the first buffer is connected to the negative electrode of the differential signal of the second output terminal; The first input terminal of the second buffer is connected to the positive electrode of the differential signal of the second output terminal; the second input terminal of the second buffer is connected to the negative electrode of the differential signal of the first output terminal; The output end of the first buffer and the output end of the second buffer are respectively connected to any one of the plurality of application circuits.
2. The circuit for reducing clock signal jitter according to claim 1, characterized in that: When the clock signal is a single-ended signal, the circuit for reducing the jitter of the clock signal further includes an impedance matching circuit, wherein the plurality of output ends have related output ends whose output clock signals have the same frequency and phase, and the related output ends are connected, including: connecting the single-ended signals of the relevant output terminals; The impedance matching circuit is respectively added to the plurality of application circuits connected to the relevant output terminals.
3. The circuit for reducing clock signal jitter according to claim 1, characterized in that: The connecting the relevant output terminal comprises: The related output terminals are connected according to a preset connection principle, wherein the preset connection principle is that the length of the connection line of the related output terminal is within a first threshold interval, and the distance between the connection line and the phase-locked loop chip is within a second threshold interval.
4. The circuit for reducing clock signal jitter according to claim 1, characterized in that: If there is an irrelevant output terminal among the plurality of output terminals whose output clock signals have different frequencies and / or phases, the relevant output terminal and the irrelevant output terminal are not connected.
5. The circuit for reducing clock signal jitter according to claim 4, characterized in that: When the clock signal is a differential signal, the relevant output terminal and the non-relevant output terminal are not connected, including: The positive electrode of the differential signal of the relevant output terminal and the positive electrode of the differential signal of the non-relevant output terminal are not connected; The negative electrode of the differential signal at the relevant output terminal and the negative electrode of the differential signal at the non-relevant output terminal are not connected.
Citation Information
Patent Citations
Clock jitter elimination circuit based on reconfigurable multi-phase-locked loop
CN111585570A