Reference voltage source circuit, voltage trimming calibration method and stability compensation method

Abstract

The present invention relates to a reference voltage source circuit, a voltage trimming calibration method and a stability compensation method. The circuit comprises: a current source is connected to the emitter of a triode to obtain a node V1, V1 is connected to the inverting input terminal of an operational amplifier, the base and collector of the triode are connected and then grounded; the positive input terminal of the operational amplifier is connected to the gate of a transistor M5 to obtain a node V2, V2 is connected to the drain of M5 and then connected to the gate of a transistor M6 and a first MOS module respectively; the output terminal of the operational amplifier is sequentially connected to transistors M3 and M4, the drain of M3 is connected to the source of M5, the drain of M4 is connected to the source of M6; the drain of M6 is connected to a second MOS module. The present invention constructs a reference voltage source circuit, and performs voltage trimming calibration and stability compensation on it.

Description

Technical Field

[0001] The present invention relates to the technical field of reference voltage source circuits, and in particular to a reference voltage source circuit, a voltage trimming and calibration method, and a stability compensation method. Background Art

[0002] With the popularization of smart IoT nodes and smart microsensor devices and the growth of green energy demand, the demand for integrated circuit systems suitable for such applications has also shown exponential growth. Since IoT nodes and green energy application scenarios have the characteristics of wide distribution, large environmental changes, and high module usage, the corresponding integrated circuits need to have extremely low power consumption / extremely low cost characteristics, and have ultra-long standby capabilities under the conditions of battery power or environmental energy harvesting. In such integrated circuit systems, the voltage reference source circuit needs to provide a high-precision reference voltage over a wide temperature range, and have extremely low power consumption (less than 1 microwatt) and a small area (low cost).

[0003] Although the traditional bandgap reference source circuit can provide a reference voltage with a small temperature coefficient in a wide temperature range, and its reference voltage is mainly determined by the semiconductor band gap and is basically not affected by process changes, the dual triode and resistor network structure it adopts has high matching requirements for semiconductor devices and is sensitive to stress, and the resistor network structure either consumes a large area or causes high power consumption, and it is impossible to achieve the best of both worlds in terms of area and power consumption.

[0004] Although the CMOS resistorless reference voltage source circuit structure based on the threshold voltage of MOS devices can achieve the characteristics of low power consumption and small area at the same time, the reference voltage generated by it is greatly affected by process variations.

[0005] Therefore, people need to develop a new type of reference voltage source circuit that combines the advantages of both bandgap reference source circuit and MOS threshold voltage reference source circuit, that is, a resistance-free and extremely low-power bandgap voltage reference source circuit structure that only uses a single transistor.

[0006] The single transistor reference source circuit proposed in the early research and development work divides the output of the transistor without resistance, but its circuit structure is relatively complex, and due to the limitation of the circuit structure, its temperature coefficient is relatively high. Subsequent work has made improvements on the basis of, but the relevant design temperature range is narrow, and the required power supply voltage is relatively high. Another type of single transistor resistance-free bandgap reference source is based on the switched capacitor circuit. Its disadvantage is that it requires an additional clock circuit, and the leakage current of the switch limits the temperature range. In addition, clock feedthrough and charge leakage will also affect the performance of the reference voltage. In recent years, some new single transistor bandgap voltage reference source circuits with low temperature coefficient and wide temperature range have emerged. The overall development trend of this type of circuit is to pursue low power consumption, small area, low temperature coefficient and adjustable characteristics while simplifying the structure and improving robustness. However, most designs cannot meet all the above requirements at the same time. Summary of the invention

[0007] To this end, the technical problem to be solved by the present invention is to overcome the shortcomings of the single transistor bandgap voltage reference source circuit in the prior art that it cannot simultaneously pursue low power consumption, small area, low temperature coefficient and adjustable characteristics while simplifying the structure and improving the robustness.

[0008] In order to solve the above technical problems, the present invention provides a reference voltage source circuit, including a current source I B1 , transistor Q1 and operational amplifier OP1, the current source I B1 It is used to provide current bias for transistor Q1 and operational amplifier OP1. B1 The emitter of the transistor Q1 is connected to obtain a node V1, the node V1 is connected to the inverting input terminal of the operational amplifier OP1, and the base and collector of the transistor Q1 are connected and then grounded;

[0009] The non-inverting input terminal of the operational amplifier OP1 is connected to the gate of the transistor M5 to obtain a node V2, and the node V2 is connected to the drain of the transistor M5 and then connected to the gate of the transistor M6 and the first MOS module respectively;

[0010] The output end of the operational amplifier OP1 is connected to a transistor M3 and a transistor M4 in sequence, the drain of the transistor M3 is connected to the source of the transistor M5, the source of the transistor M3 is connected to a power supply, the drain of the transistor M4 is connected to the source of the transistor M6, the source of the transistor M4 is connected to a power supply;

[0011] The drain of the transistor M6 is connected to the second MOS module.

[0012] In one embodiment of the present invention, the voltage V between the base and the emitter of the transistor Q1 is BE The expression of temperature change is:

[0013]

[0014] Among them, V BE (T) indicates V BE As a function of temperature, V bgr Indicates V BE Extrapolated to the value at absolute zero; Indicates V BE At the reference temperature T r The first derivative of the temperature T is negative; f r (T) indicates V BE At the reference temperature T r The second and higher derivative components of the temperature T.

[0015] In one embodiment of the present invention, the first MOS module includes N identical transistors M1 connected in series, and the gate and drain of the transistor M1 are connected, the gate and drain of the last transistor M1 in the first MOS module are connected and grounded, and the drain of the transistor M5 is connected to the source of the first transistor M1 in the first MOS module; the second MOS module includes M identical transistors M2 connected in series, the gate and drain of the transistor M2 are connected, the gate and drain of the last transistor M2 in the second MOS module are connected and grounded, and the drain of the transistor M6 is connected to the source of the first transistor M2 in the second MOS module.

[0016] In one embodiment of the present invention, due to the clamping effect of the operational amplifier OP1, the voltage formula across the gate and source of a single transistor M1 is:

[0017] V GS1 =V BE / N (3)

[0018] Among them, V GS1 is the voltage across the gate and source of M1, V BE is the voltage difference between the base and emitter of transistor Q1;

[0019] The transistor M1 operates in the subthreshold current-voltage exponential relationship region, and the expression of the drain current of the transistor M1 is:

[0020]

[0021] in, T is the absolute temperature, k is the Boltzmann constant, q is the electron charge, μ p is the carrier mobility, C ox is the capacitance per unit area of ​​the gate oxide layer, n is the subthreshold gradient factor, V TH1 is the threshold voltage of transistor M1, is the width-to-length ratio of transistor M1;

[0022] The transistor M2 operates in the subthreshold current-voltage exponential relationship region, and the expression of the drain current of the transistor M2 is:

[0023]

[0024] Among them, V GS2 is the voltage across the gate and source of transistor M2, V TH2 is the threshold voltage of transistor M2, is the width-to-length ratio of transistor M2.

[0025] In one embodiment of the present invention, the transistor M3 and the transistor M4 form a current mirror circuit, and the ratio thereof is J1:J2, so the drain current I1 of the transistor M1 and the drain current I2 of the transistor M2 satisfy:

[0026]

[0027] Substituting formula (3), (4), (5) into formula (6), and matching transistor M1 and transistor M2 to have equal threshold voltages, we obtain:

[0028]

[0029] Where, S1=W1 / L1, S1=W2 / L2; Substitute formula (2) into (7) and ignore the third term f on the right side of formula (2) r (T), we get:

[0030]

[0031] According to formula (2), the second term on the right side of formula (8) and V BE It also has a negative temperature coefficient, and its temperature coefficient is V BE One Nth of the Nth, the third term on the right side of formula (8) With a positive temperature coefficient, by adjusting the third term on the right side of formula (8) The temperature coefficient of The temperatures are equal in magnitude and opposite in sign and cancel each other out, giving:

[0032] V GS2 =V bgr / N (9)

[0033] Among them, V bgr Indicates V BE Extrapolated to the value at absolute zero, V GS2 It is a low temperature coefficient reference voltage determined by the bandgap voltage;

[0034] The total output reference voltage expression of the reference voltage source circuit is:

[0035]

[0036] In one embodiment of the present invention, the operational amplifier OP1 functions as a voltage clamp so that the node voltage satisfies:

[0037] V2=V1=V BE (1)

[0038] Among them, V BE is the current source I B1 The voltage difference generated between the base and emitter of transistor Q1 under the current bias.

[0039] In one embodiment of the present invention, the number N of the transistors M1 is greater than or equal to 2, and the number M of the transistors M2 is greater than or equal to 1.

[0040] In order to solve the above technical problems, the present invention provides a voltage trimming and calibration method, which trims and calibrates the output voltage of the above reference voltage source circuit, comprising:

[0041] The calibration is adjusted by adjusting the ratio of the current mirror circuits M3 and M4, where:

[0042] The transistor M3 includes J1 parallel-connected unit transistors and is designed as follows:

[0043] J1=J0+K1 (11)

[0044] The transistor M4 includes J2 parallel-connected unit transistors and is designed as follows:

[0045] J2=J0+2K1 (12)

[0046] Among them, the transistor M4 includes J2 parallel unit transistors, including the transistor M formed by J0 parallel unit transistors. 4a , and a transistor M consisting of 2K1 parallel unit transistors 4b ; Transistor M 4b The 2K1 parallel unit transistors are all controlled on and off by complementary switches SW1 and SW2; when transistor M 4b If the switch SW1 of a unit transistor is turned on, the unit transistor and the transistor M 4a In parallel, when the switch SW2 of the unit transistor is turned on, the unit transistor is turned off;

[0047] According to the formulas (8), (10), (11), and (12), the positive temperature coefficient determined by the current mirror ratio is obtained, and the expression is:

[0048]

[0049] Among them, 0≤x≤2K1; then the range of temperature coefficient K is:

[0050]

[0051] When J1 is relatively large relative to K1, formula (14) is approximately:

[0052]

[0053] According to formula (15), the temperature coefficient of the output voltage of the reference voltage source circuit is trimmed and calibrated.

[0054] In one embodiment of the present invention, the transistor M 4a The gate of the first unit transistor in the transistor M is connected to the gate of the last unit transistor in the transistor M3. 4a The gate of the last unit transistor in the circuit is connected to transistor M through a set of complementary switches SW1 and SW2. 4b The gate of each unit transistor is connected to the transistor M 4b The drain of each unit transistor and the transistor M 4a The drain of the last unit transistor in is connected to the source of transistor M5.

[0055] In order to solve the above technical problems, the present invention provides a stability compensation method, which performs stability compensation on the above reference voltage source circuit: by compensating the capacitor C c It is connected across the node V1 and the output end of the operational amplifier OP1 to implement stability compensation of the reference voltage source circuit.

[0056] The above technical solution of the present invention has the following advantages compared with the prior art:

[0057] The reference voltage source circuit proposed by the present invention combines the voltage of a single crystal triode with a MOS transistor in a subthreshold region, and obtains a reference voltage with a low temperature coefficient in a wide temperature range by adjusting the ratio of the transistors with the assistance of a current mirror. The value of the reference voltage is proportional to the semiconductor bandgap voltage, and the proportional relationship can be adjusted.

[0058] The present invention also proposes a frequency compensation and voltage adjustment scheme suitable for the reference voltage source circuit, which greatly improves the robustness of the circuit. The present invention realizes an adjustable low temperature coefficient bandgap reference voltage output within a wide temperature range under the premise of using relatively few transistors, and only uses one triode device, without resistors and clocks, and has the characteristics of simple structure, low power consumption, small area, strong robustness, wide temperature range, low temperature coefficient, etc.; the reference voltage has two adjustment degrees of freedom, high flexibility, and can generate a reference voltage value proportional to the semiconductor bandgap voltage, which is particularly suitable for providing a rich reference voltage option for the integrated circuit system; it can be widely used in integrated circuit systems related to the Internet of Things, green energy, and intelligent sensing, improves the low power consumption and low cost characteristics of the system, and has strong robustness;

[0059] The present invention uses only a single transistor, relatively few MOS transistors (core MOS transistors are less than 20, for example, M1, M2, M3, and M4 can be used as a transistor as a whole), and no resistors. It realizes an adjustable low temperature coefficient (temperature coefficient is less than 5ppm) bandgap reference voltage output within a wide temperature range (-40°C to 125°C) without the need for a clock, and has the characteristics of simple structure, low power consumption, small area, strong robustness, wide temperature range, low temperature coefficient, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0061] Figure 1 is a schematic diagram of the reference voltage source circuit structure in an embodiment of the present invention;

[0062] Figure 2 It is a schematic diagram of a stability compensation and adjustment structure for a reference voltage source circuit structure in an embodiment of the present invention;

[0063] Figure 3 It is a schematic diagram of the structure of the first reference voltage source circuit in actual use in an embodiment of the present invention;

[0064] Figure 4 is the circuit output reference voltage V in the embodiment of the present invention ref Graph of temperature variation;

[0065] Figure 5 It is a schematic diagram of the structure of a second reference voltage source circuit in actual use in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0067] Embodiment 1

[0068] Reference Figure 1 As shown, the present invention relates to a reference voltage source circuit, comprising a current source I B1 , transistor Q1 and operational amplifier OP1, the current source I B1 It is used to provide current bias for transistor Q1 and operational amplifier OP1. B1 The emitter of the transistor Q1 is connected to obtain a node V1, and the node V1 is connected to the inverting input terminal of the operational amplifier OP1. The base and collector of the transistor Q1 are connected and then grounded; the non-inverting input terminal of the operational amplifier OP1 is connected to the gate of the transistor M5 to obtain a node V2, and the node V2 is connected to the drain of the transistor M5 and then connected to the gate of the transistor M6 and the first MOS module respectively; the output terminal of the operational amplifier OP1 is sequentially connected to the transistor M3 and the transistor M4, the drain of the transistor M3 is connected to the source of the transistor M5, and the source of the transistor M3 is connected to the power supply, the drain of the transistor M4 is connected to the source of the transistor M6, and the source of the transistor M4 is connected to the power supply; the drain of the transistor M6 is connected to the second MOS module.

[0069] The first MOS module includes N identical transistors M1 connected in series, and the gate and drain of the transistor M1 are connected, the gate and drain of the last transistor M1 in the first MOS module are connected and grounded, and the drain of the transistor M5 is connected to the source of the first transistor M1 in the first MOS module; the second MOS module includes M identical transistors M2 connected in series, the gate and drain of the transistor M2 are connected, the gate and drain of the last transistor M2 in the second MOS module are connected and grounded, and the drain of the transistor M6 is connected to the source of the first transistor M2 in the second MOS module.

[0070] The following is a detailed introduction to this embodiment:

[0071] The components of the unique circuit structure proposed by the present invention, the connection relationship between the components and the working principle are referred to Figure 1 The description is as follows. Current source I B1 To provide bias for transistor Q1 and operational amplifier OP1, the current source I B1 Can use publicly available and very low power consumption uT 2 A current source can be used, or a self-biasing method can be used. The present invention will provide implementation schemes of the above two methods in the embodiments. Q1 is a transistor.B1 Under the current bias, a voltage V is generated between the base and emitter of the transistor. BE The function of operational amplifier OP1 is voltage clamping, so that the node voltage satisfies the following relationship:

[0072] V2=V1=V BE (1)

[0073] As mentioned above, V in formula (1) BE is the voltage difference between the base and emitter of the transistor Q1, and its expression of temperature variation is:

[0074]

[0075] Among them, V BE (T) indicates V BE As a function of temperature, V bgr Indicates V BE The value extrapolated to absolute zero is mainly determined by the band gap potential difference between the semiconductor conduction band and valence band, and is minimally affected by the process. Indicates V BE At the reference temperature T r The first derivative of temperature is negative, that is, V BE It has a negative temperature coefficient, that is, the slope changes with temperature T. r (T) indicates V BE At the reference temperature T r The second-order and higher derivative components of the temperature can be ignored in the first-order approximation. Reference temperature T r Usually room temperature is taken, which is 300 Kelvin.

[0076] The diode-connected transistor M1 is composed of N unit transistors of the same size stacked (connected in series), N is greater than or equal to 2, and the size of each unit transistor is is the width-to-length ratio of transistor M1. M1 usually uses PMOS, whose substrate is connected to the source, to avoid the change of transistor threshold voltage caused by body effect. If the process used has a P well, NMOS in the P well can also be used as the device of M1. Due to the clamping effect of operational amplifier OP1, the voltage across the gate and source of a single transistor M1 is:

[0077] V GS1 =V BE / N (3)

[0078] Where V GS1 is the voltage across the gate and source of M1, V BE is the voltage difference between the base and emitter of transistor Q1, and N is the number of M1 transistors stacked in series. BEThe value of is usually less than 700mV and N is greater than or equal to 2. The transistor M1 usually operates in the subthreshold exponential current-voltage relationship region. The expression of the drain current of M1 is:

[0079]

[0080] In formula (4) T is the absolute temperature, k is the Boltzmann constant, q is the electron charge, μ p is the carrier mobility, C ox is the capacitance per unit area of ​​the gate oxide layer, n is the subthreshold gradient factor, V GS1 The voltage across the gate and source of M1 is determined by expression (3), V TH1 is the threshold voltage of transistor M1, is the width-to-length ratio of transistor M1. Transistors M3 and M4 form a current mirror circuit, and the ratio is J1 to J2. M3 and M4 are usually composed of different numbers of parallel transistors, and the ratio is J1 to J2. The role of transistors M5 and M6 is to greatly reduce the influence of channel length modulation effect on the current mirror.

[0081] The diode-connected transistor M2 is composed of M unit transistors of the same size stacked (connected in series), M is greater than or equal to 1, and the size of each unit transistor is The design requires that transistor M2 operates in the subthreshold current-voltage exponential relationship region, and the expression of its drain current is:

[0082]

[0083] In formula (5) T is the absolute temperature, k is the Boltzmann constant, q is the electron charge, μ p is the carrier mobility, C ox is the capacitance per unit area of ​​the gate oxide layer, n is the subthreshold gradient factor, V GS2 is the voltage across the gate and source of M2, V TH2 is the threshold voltage of transistor M2, is the width-to-length ratio of the M2 transistor.

[0084] Due to the action of current mirrors M3 and M4, the relationship between I1 and I2 is as follows:

[0085]

[0086] Substituting formula (3), (4), (5) into formula (6), and assuming that transistors M1 and M2 can be matched to have equal threshold voltages, we can obtain:

[0087]

[0088] Where S1 = W1 / L1, s1 = W2 / L2. Substitute formula (2) into (7), ignoring the higher-order term of temperature, i.e., the third term on the right side of formula (2) f r (T), we can get:

[0089]

[0090] According to the discussion of formula (2), the second term on the right side of formula (8) is and V BE It also has a negative temperature coefficient, and its temperature coefficient is V BE One Nth of the Nth, the third term on the right side of formula (8) With a positive temperature coefficient, by adjusting the third term on the right side of formula (8) The temperature coefficient of can be expressed as the second term on the right side of formula (8) The temperatures are equal in magnitude and opposite in sign, so they cancel each other out. We can get:

[0091] V GS2 =V bgr / N (9)

[0092] N is an integer greater than or equal to 2, V bgr Indicates V BE The value extrapolated to absolute zero is mainly determined by the band gap potential difference between the semiconductor conduction band and the valence band, and is minimally affected by the process. Therefore, V GS2 It is a low temperature coefficient reference voltage mainly determined by the bandgap voltage. Figure 1 In the circuit, M transistors M2 are stacked in series, where M is an integer greater than or equal to 1. The total output reference voltage expression of the circuit is:

[0093]

[0094] The reference voltage has two adjustment degrees of freedom and is highly flexible. It can generate a reference voltage value proportional to the semiconductor bandgap voltage and is particularly suitable for providing a wealth of reference voltage options for integrated circuit systems.

[0095] Embodiment 2

[0096] Since the integrated circuit has process and size deviations during processing, the output voltage needs to be adjusted and calibrated, and the op amp clamping in the present invention forms a negative feedback loop, which needs to be compensated for stability. Voltage reference source circuits with different structures need voltage adjustment and stability compensation circuits suitable for their characteristics. Figure 2 The voltage trimming and stability compensation circuit of the present invention is proposed. The trimming principle is described as follows. The trimming is achieved by adjusting the ratio of the current mirrors M3 and M4. Wherein M3 is composed of J1 parallel unit transistors and is designed as follows:

[0097] J1=J0+K1 (11)

[0098] M4 is composed of J2 parallel unit transistors and is designed as follows:

[0099] J2=J0+2K1 (12)

[0100] like Figure 2 As shown, among the J2 parallel unit transistors of the M4 transistor, J0 is like the transistor M 4a 2K1 units such as transistor M 4b The connection method of transistor M 4b The 2K1 parallel units are controlled on and off by a set of complementary switches SW1 and SW2 (in the 2K1 parallel units, each unit is controlled on and off by complementary switches SW1 and SW2), and the complementary switches are controlled by a set of control words. When SW1 of a unit transistor is turned on, the unit and M 4a In parallel, when SW2 is turned on, the unit is disconnected.

[0101] Specifically, transistor M 4a The gate of the first unit transistor in the transistor M is connected to the gate of the last unit transistor in the transistor M3. 4a The gate of the last unit transistor in the circuit is connected to transistor M through a set of complementary switches SW1 and SW2. 4b The gate of each unit transistor is connected to the transistor M 4b The drain of each unit transistor and the transistor M 4a The drain of the last unit transistor in is connected to the source of transistor M5.

[0102] According to the adjustment principle described above, combined with formulas (8)(10)(11)(12), the expression of the positive temperature coefficient determined by the current mirror ratio can be obtained as follows:

[0103]

[0104] Among them, 0≤x≤2K1. Then the range of temperature coefficient K is:

[0105]

[0106] When J1 is larger than K1, formula (14) can be approximated as:

[0107]

[0108] According to formula (15), using Figure 2 With the trimming circuit structure shown, the present invention can perform linear trimming on the temperature coefficient of the output reference voltage.

[0109] Embodiment 3

[0110] The frequency stability compensation scheme of the present invention is based on Figure 2 The description is as follows. Compensation capacitor C c Connected across nodes V1 and V3, where V3 is the output node of the operational amplifier. c Connected to nodes V2 and V3. Since V2 is a node with relatively low impedance in the present invention, the compensation effect of connecting the compensation capacitor across V2 and V3 is poor. c The additional negative feedback loop formed across nodes V1 and V3 at high frequencies can greatly improve the phase margin of the overall loop.

[0111] The following are two Figure 1 and Figure 2 Specific embodiments of the invention. Figure 3 The first embodiment provided by the present invention is shown. Figure 3 The circuit shown is a bandgap voltage reference source circuit realized by a low temperature coefficient, nanowatt power consumption, resistance-free single triode bandgap reference source circuit structure proposed by the present invention. Figure 3 The dotted line box on the right is the core circuit of the bandgap voltage reference source circuit proposed by the present invention, which is composed of only 14 transistors ( Figure 3 Transistor M7-M 11 The operational amplifier OP1) consists of only one transistor and no resistor. The trimming function can be Figure 2 The solution shown is implemented in Figure 3 No specific display. Figure 3 The dotted box on the left is the uT suitable for providing bias for the core circuit 2 The current generating circuit and the bias circuit have a degeneracy point, and a startup circuit needs to be added to ensure the normal operation of the circuit. Since the startup circuit is not within the scope of the present invention, it is not shown in detail. Figure 3 In the lower right corner, a single transistor M2 is used to generate a reference voltage with a low temperature coefficient. The theoretical value of this voltage is 1 / 3 of the bandgap voltage of silicon semiconductor. The circuit is implemented using a typical 180nm CMOS process. The transistor parameters are set to the values ​​given in Table 1. The curve of the reference voltage changing with temperature is simulated as shown below: Figure 4 As shown, the reference voltage is 411mV, the voltage temperature coefficient between -40 degrees Celsius and 125 degrees Celsius is 5ppm, the total current is 260nA, of which the core circuit current is 160nA. The circuit has the advantages of simple structure, strong robustness, easy adjustment, small area, low power consumption, and low output voltage temperature coefficient.

[0112] Table 1 Figure 3 Transistor parameter table in the embodiment

[0113] Transistor number Width to length ratio [W(um) / L(um)] Transistor number Width to length ratio [W(um) / L(um)] Q1 5ux5u M12 0.25x2 / 15 M1 1x50 / 0.2 M13 0.25x2 / 15 M2 1x1 / 0.2 M14 0.25x2 / 15 M3 1x64 / 2 M15 0.25x2 / 15 M4 1x64 / 2 M16 0.25x2 / 15 M5 1x16 / 0.2 M17 0.25x2 / 15 M6 1x16 / 0.2 M18 0.5x3 / 0.4 M7 1x64 / 2 M19 0.5x2 / 0.4 M8 1x64 / 2 M20 0.25x10 / 15 M9 4x1 / 0.2 M21 0.25x10 / 15 M10 4x1 / 0.2 M22 0.25x2 / 18 M11 0.5 / 5u M23 0.25x2 / 18 Core circuit current 160nA Total current 260nA

[0114] Figure 5 The second embodiment provided by the present invention is shown Figure 3 Transistor M7-M 11 The core circuit of this circuit is Figure 3 The difference is that it adopts a self-biased structure, without Figure 3 The current bias circuit in the dashed box on the left side of the figure further reduces the number of transistors and the overall power consumption. Figure 3 With similar transistor parameters in the , similar output bandgap reference voltage characteristics can be obtained.

[0115] The key points of the present invention are as follows:

[0116] (1) Figure 2 As shown, transistor Q1, bias current I B , operational amplifier OP1, compensation capacitor C c The combination relationship of MOS transistors M1, M2, M3, M4, M5, and M6 constitutes the core of the present invention.

[0117] (2) The diode-connected MOS transistor M1 is N unit transistors of the same size stacked in series, where N is greater than or equal to 2. The diode-connected MOS transistor M2 is M unit transistors of the same size stacked in series, where M is greater than or equal to 1. The unit transistor sizes of M1 and M2 are proportional, and the proportionality coefficient is S1 / S2, which is much greater than 1. Both M1 and M2 operate in the subthreshold current-voltage exponential relationship region.

[0118] (3) M3 and M4 are in a current mirror relationship. M3 is J1=J0+K1 unit transistors connected in parallel, and M4 is J2=J0+2K1 unit transistors connected in parallel. The ratio of J1 to K1 is preferably greater than 4. The unit transistors of M3 and M4 are of equal size. Among them, J1 parallel transistors of M3 are always in the on state, and J0 transistors of J2 parallel transistors of M4 are always in the on state. The 2K1 parallel transistors are turned on and off by switches and external control words to complete the adjustment function.

[0119] (4) Bias current I of transistor Q1 B Can be flexibly configured for additional current bias, such as Figure 3 As shown, or self-biased, such as Figure 5 As shown in Figure 2, the V generated by Q1 under the bias current BEThrough the op amp OP1 clamp, a subthreshold exponential current i1 is generated on transistor M1. i1 generates a current I2 on transistor M2 through the mirror of MOS transistors M3 and M4, and then generates a voltage V GS2 By adjusting the parameters N, J1, J2, S1, S2, V GS2 It has a very low temperature coefficient, the typical value is equal to the semiconductor bandgap voltage V bgr By adjusting the parameter M, the final circuit outputs a reference voltage value V ref Equal to the semiconductor bandgap voltage V bgr M / N.

[0120] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0121] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A reference voltage source circuit, characterized in that: Including current source I B1 , transistor Q1 and operational amplifier OP1, the current source I B1 It is used to provide current bias for transistor Q1 and operational amplifier OP1. B1 The emitter of the transistor Q1 is connected to obtain a node V1, the node V1 is connected to the inverting input terminal of the operational amplifier OP1, and the base and collector of the transistor Q1 are connected and then grounded; The non-inverting input terminal of the operational amplifier OP1 is connected to the gate of the transistor M5 to obtain a node V2, and the node V2 is connected to the drain of the transistor M5 and then connected to the gate of the transistor M6 and the first MOS module respectively; The output end of the operational amplifier OP1 is connected to a transistor M3 and a transistor M4 in sequence, the drain of the transistor M3 is connected to the source of the transistor M5, the source of the transistor M3 is connected to a power supply, the drain of the transistor M4 is connected to the source of the transistor M6, the source of the transistor M4 is connected to a power supply; The drain of the transistor M6 is connected to the second MOS module; The base and emitter voltages of transistor Q1 are V BE The expression of temperature change is: Among them, V BE (T) indicates V BE As a function of temperature, V bgr Indicates V BE Extrapolated to the value at absolute zero; Indicates V BE At the reference temperature T r The first derivative of the temperature T is negative; f r (T) indicates V BE At the reference temperature T r The second and higher derivative components of the temperature T; The first MOS module includes N identical transistors M1 connected in series, and the gate and drain of the transistor M1 are connected, the gate and drain of the last transistor M1 in the first MOS module are connected and grounded, and the drain of the transistor M5 is connected to the source of the first transistor M1 in the first MOS module; the second MOS module includes M identical transistors M2 connected in series, the gate and drain of the transistor M2 are connected, the gate and drain of the last transistor M2 in the second MOS module are connected and grounded, and the drain of the transistor M6 is connected to the source of the first transistor M2 in the second MOS module; Due to the clamping effect of the operational amplifier OP1, the voltage formula across the gate and source of a single transistor M1 is: V GS1 =V BE / N (3) Among them, V GS1 is the voltage across the gate and source of M1, V BE is the voltage difference between the base and emitter of transistor Q1; The transistor M1 operates in the subthreshold current-voltage exponential relationship region, and the expression of the drain current of the transistor M1 is: in, T is the absolute temperature, k is the Boltzmann constant, q is the electron charge, μ p is the carrier mobility, C ox is the capacitance per unit area of ​​the gate oxide layer, n is the subthreshold gradient factor, V TH1 is the threshold voltage of transistor M1, is the width-to-length ratio of transistor M1; The transistor M2 operates in the subthreshold current-voltage exponential relationship region, and the expression of the drain current of the transistor M2 is: Among them, V GS2 is the voltage across the gate and source of transistor M2, V TH2 is the threshold voltage of transistor M2, is the width-to-length ratio of transistor M2; The transistor M3 and the transistor M4 form a current mirror circuit, and the ratio thereof is J1:J2. Therefore, the drain current I1 of the transistor M1 and the drain current I2 of the transistor M2 satisfy: Substituting formula (3), (4), (5) into formula (6), and matching transistor M1 and transistor M2 to have equal threshold voltages, we obtain: Where, S1=W1 / L1, S1=W2 / L2; Substitute formula (2) into (7) and ignore the third term f on the right side of formula (2) r (T), we get: According to formula (2), the second term on the right side of formula (8) and V BE It also has a negative temperature coefficient, and its temperature coefficient is V BE One Nth of the third term on the right side of formula (8) With a positive temperature coefficient, by adjusting the third term on the right side of formula (8) The temperature coefficient of The temperatures are equal in magnitude and opposite in sign and cancel each other out, giving: V GS2 =V bgr / N (9) Among them, V bgr Indicates V BE Extrapolated to the value at absolute zero, V GS2 It is a low temperature coefficient reference voltage determined by the bandgap voltage; The total output reference voltage expression of the reference voltage source circuit is: The number N of the transistors M1 is greater than or equal to 2, and the number M of the transistors M2 is greater than or equal to 1.

2. The reference voltage source circuit according to claim 1, characterized in that: The operational amplifier OP1 functions to clamp the voltage so that the node voltage satisfies: V2=V1=V BE (1) Among them, V BE is the current source I B1 The voltage difference generated between the base and emitter of transistor Q1 under the current bias.

3. A voltage trimming and calibration method, for trimming and calibrating the output voltage of the reference voltage source circuit as claimed in any one of claims 1 to 2, characterized in that: include: The calibration is adjusted by adjusting the ratio of the current mirror circuits M3 and M4, where: The transistor M3 includes J1 parallel-connected unit transistors and is designed as follows: J1=J0+K1(11) The transistor M4 includes J2 parallel-connected unit transistors and is designed as follows: J2=J0+2K1(12) Among them, the transistor M4 includes J2 parallel unit transistors, including the transistor M formed by J0 parallel unit transistors. 4a , and a transistor M consisting of 2K1 parallel unit transistors 4b ; Transistor M 4b The 2K1 parallel unit transistors are all controlled on and off by complementary switches SW1 and SW2; when transistor M 4b If the switch SW1 of a unit transistor is turned on, the unit transistor and the transistor M 4a In parallel, when the switch SW2 of the unit transistor is turned on, the unit transistor is turned off; According to the formulas (8), (10), (11), and (12), the positive temperature coefficient determined by the current mirror ratio is obtained, and the expression is: Among them, 0≤x≤2K1; then the range of temperature coefficient K is: When J1 is relatively large relative to K1, formula (14) is approximately: According to formula (15), the temperature coefficient of the output voltage of the reference voltage source circuit is trimmed and calibrated.

4. The voltage trimming and calibration method according to claim 3, characterized in that: The transistor M 4a The gate of the first unit transistor in the transistor M is connected to the gate of the last unit transistor in the transistor M3. 4a The gate of the last unit transistor in the circuit is connected to transistor M through a set of complementary switches SW1 and SW2. 4b The gate of each unit transistor is connected to the transistor M 4b The drain of each unit transistor and the transistor M 4a The drain of the last unit transistor in is connected to the source of transistor M5.

5. A stability compensation method for performing stability compensation on the reference voltage source circuit as claimed in any one of claims 1 to 2, characterized in that: Through the compensation capacitor C c It is connected across the node V1 and the output end of the operational amplifier OP1 to implement stability compensation of the reference voltage source circuit.

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