Watchdog based field programmable gate array loading universal dual boot switching circuit
By using a watchdog chip and memory chip switching circuit to guide the switching mechanism, the abnormal problem caused by FPGA image loading failure was solved, realizing universality and stable loading for different series of FPGAs and improving the applicability of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING UCAS TECH CO LTD
- Filing Date
- 2023-10-24
- Publication Date
- 2026-06-26
AI Technical Summary
In the existing technology, FPGA image loading failure causes product malfunctions, and the built-in functions of Xilinx 7 series FPGAs are not universal for FPGAs of other series and manufacturers.
A boot switching mechanism based on a watchdog chip and a memory chip switching circuit is adopted. When the first memory chip fails to load, the watchdog chip triggers the memory chip switching circuit to reload from the second memory chip, thereby realizing universal dual boot switching for different series of FPGAs.
It improves the applicability and versatility of field-programmable gate arrays, avoids hardware downtime, and ensures normal circuit loading.
Smart Images
Figure CN117609121B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of embedded systems technology, and in particular to a watchdog-based field-programmable gate array loading universal dual-boot switching circuit. Background Technology
[0002] In the field of embedded system technology, in order to achieve high product reliability, during the design process of Field Programmable Gate Array (FPGA), in order to avoid FPGA image loading failure leading to product malfunction, the image switching method is usually used to achieve normal loading. This method is based on the multi-boot function provided by Xilinx, that is, two or more BOOT.bin image files are stored in the flash memory chip, including a golden image and one or more multi-boot image files. During image upgrade, only the multi-boot image file is updated, while the golden image file is not updated as a backup.
[0003] Specifically, when an error is detected during MultiBoot configuration, the FPGA can trigger a rollback function, loading from the golden image file to ensure that a known good design is loaded into the device. However, this implementation is a built-in feature of Xilinx 7 series FPGAs, primarily implemented through internal FPGA software, and is not universally applicable to FPGAs from other series and manufacturers. Summary of the Invention
[0004] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides a watchdog-based field-programmable gate array loading universal dual-guide switching circuit.
[0005] This disclosure provides a watchdog-based field-programmable gate array loading universal dual-boot switching circuit, including: a watchdog chip, a first memory chip, a second memory chip, a memory chip switching circuit, and a field-programmable gate array;
[0006] The first memory chip and the second memory chip are selectively connected to the field-programmable gate array via the memory chip switching circuit;
[0007] The watchdog chip is connected to the memory chip switching circuit and the field-programmable gate array, and is used to trigger the memory chip switching circuit to reload from the second memory chip when the first memory chip fails to load.
[0008] Optionally, the memory chip switching circuit includes: a dual AND gate, a D flip-flop, and a switch selection chip;
[0009] The watchdog chip is connected to the dual AND gate and is used to output a reset pulse signal to the dual AND gate when the first memory chip fails to load.
[0010] The first output terminal of the dual AND gate is connected to the first switching terminal of the D flip-flop to generate a switching signal, which triggers the output signal of the D flip-flop to flip.
[0011] The first output terminal of the D flip-flop is connected to the controlled terminal of the switch selection chip, and is used to control the switch selection chip to select whether to reload from the second memory chip or the first memory chip based on the flipped output signal.
[0012] Optionally, the second output terminal of the dual AND gate is connected to the reset trigger terminal of the field programmable gate array, the reset trigger terminal of the first memory chip, the reset trigger terminal of the second memory chip, and the set-to-1 terminal of the second channel of the D flip-flop;
[0013] The second output of the D flip-flop is connected to one input of the double AND gate.
[0014] Optionally, the first output terminal of the D flip-flop and the controlled terminal of the switch selection chip are both connected to the load state input terminal of the field-programmable gate array (FPGA) to transmit the load state based on the first memory chip or the second memory chip to the FPGA.
[0015] Optionally, the field-programmable gate array further includes a software control interface;
[0016] The software control interface is connected to the second switching terminal of the D flip-flop and is used to continuously send two pulse signals with a preset time interval to the second switching terminal in response to the target switching condition being triggered, thereby triggering the output signal of the D flip-flop to flip.
[0017] Optionally, the load state input terminal of the field-programmable gate array, the first output terminal of the D flip-flop, and the controlled terminal of the switch selection chip are all grounded through a resistor.
[0018] Optionally, the field-programmable gate array further includes a dog-feed signal output terminal;
[0019] The watchdog signal output terminal is connected to the input terminal of the watchdog chip and is used to output a watchdog abnormal signal to the watchdog chip when the first memory chip fails to load.
[0020] The watchdog chip outputs a reset pulse signal in response to the abnormal feeding signal.
[0021] Optionally, the first interactive terminal of the switch selection chip is connected to the first memory chip, the second interactive terminal of the switch selection chip is connected to the second memory chip, and the third interactive terminal of the switch selection chip is connected to the field-programmable gate array.
[0022] The switch selection chip responds to the output signal of the D flip-flop and uses internal logic to selectively connect the first memory chip and the second memory chip to the field-programmable gate array.
[0023] Optionally, the switch selection chip includes a QSPI switch;
[0024] The QSPI switch is connected to the field-programmable gate array via the QSPI bus.
[0025] Optionally, the watchdog-based field-programmable gate array loading universal dual-boot switching circuit further includes a hardware reset chip;
[0026] The hardware reset chip is connected to the other input terminal of the dual AND gate and is used to output a reset signal to the dual AND gate in response to a hardware reset signal input.
[0027] The technical solution provided in this disclosure has the following advantages compared with the prior art:
[0028] This disclosure provides a watchdog-based universal dual-boot switching circuit for loading field-programmable gate arrays (FPGAs), comprising: a watchdog chip, a first memory chip, a second memory chip, a memory chip switching circuit, and an FPGA. The first and second memory chips are selectively connected to the FPGA via the memory chip switching circuit. The watchdog chip, connected to both the memory chip switching circuit and the FPGA, is used to trigger the memory chip switching circuit to reload from the second memory chip when the first memory chip fails to load. Thus, by using a watchdog chip and the memory chip switching circuit for bootstrapping, and triggering the memory chip switching circuit to reload from the second memory chip when the first memory chip fails to load, the circuit's versatility with other series of watchdog FPGAs is improved, thereby enhancing the overall applicability of the circuit, while ensuring normal circuit loading. Attached Figure Description
[0029] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 A schematic diagram of a recoverable circuit for failed online FPGA program updates is provided for the present technology.
[0032] Figure 2 A schematic diagram of a watchdog-based field-programmable gate array loading universal dual-boot switching circuit is provided in an embodiment of this disclosure;
[0033] Figure 3 This is a schematic diagram of another watchdog-based field-gate array loading universal dual-guided switching circuit provided in an embodiment of this disclosure.
[0034] Among them, 01 is the host computer; 02 is the circuit board; 03 is the third auxiliary circuit; 04 is the first auxiliary circuit; 05 is the second auxiliary circuit; 06 is the FPGA (Field Programmable Gate Array); 07 is the first memory chip; 08 is the second memory chip; 110 is the watchdog chip; 120 is the memory chip switching circuit; 121 is the double AND gate; 122 is the D flip-flop; 123 is the switch selection chip; and 130 is the hardware reset chip. Detailed Implementation
[0035] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0036] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0037] First, in light of the relevant background, the deficiencies of the existing technology and the improvements of the embodiments of this disclosure will be explained. For example, Figure 1 This is a schematic diagram of a recoverable circuit for failed online FPGA program updates, provided as an example of existing technology. (Refer to...) Figure 1 , Figure 1The diagram shows a host computer 01, a circuit board 02, a third auxiliary circuit 03, a first auxiliary circuit 04, a second auxiliary circuit 05, an FPGA 06 with main control function, a first memory chip 07, and a second memory chip 08. The first auxiliary circuit 04, second auxiliary circuit 05, and third auxiliary circuit 03 are connected to the FPGA 06. A represents the IO2 pin, B represents the reset pin, and C represents the load configuration pin. The first auxiliary circuit 04 is connected to the IO2 pin and reset pin of the FPGA 06. One side of the second auxiliary circuit 05 is connected to the IO2 pin and load configuration pin of the FPGA 06, while the other side is connected to the first memory chip 07 and the second memory chip 08. One side of the third auxiliary circuit 03 is connected to the host computer 01 via an external communication interface (not shown in the diagram), while the other side is connected to the FPGA 06. Thus, the first auxiliary circuit 04 can execute the communication between the first memory chip 07, the second memory chip 08, and the FPGA. The connection and automatic switching of the loading configuration pin of FPGA06, the second auxiliary circuit 05 performs the reset of FPGA06 itself, and delays and saves the reset signal. Through the above settings, the program and state can be automatically restored after the online update of the FPGA program fails. Combined with... Figure 1 As can be seen from the connection relationship, this circuit only supports the upgrade and update of the program in the second memory chip 08. The program in the first memory chip 07 is a fixed program that does not support upgrades and updates. Therefore, switching to the first memory chip 07 for booting only when the second memory chip 08 fails to boot or update can easily lead to the circuit failing to load normally and reduce the applicability of the entire circuit. To address at least one of the above-mentioned defects, the watchdog-based field-programmable gate array loading universal dual-boot switching circuit proposed in this disclosure switches the booting based on the watchdog chip and the memory chip switching circuit. When the first memory chip fails to load, the memory chip switching circuit is triggered to reload from the second memory chip. While ensuring normal circuit loading, this improves the universality of field-programmable gate arrays with other watchdog series, thereby improving the applicability of the entire circuit. The watchdog-based field-programmable gate array loading universal dual-boot switching circuit provided in this disclosure will be described exemplarily below with reference to the accompanying drawings. Exemplarily, Figure 2 This is a schematic diagram of a watchdog-based field-programmable gate array (FPGA) loading universal dual-boot switching circuit provided in an embodiment of this disclosure. (Refer to...) Figure 2The circuit includes a watchdog chip 110, a first memory chip 07, a second memory chip 08, a memory chip switching circuit 120, and a field-programmable gate array 06. The first memory chip 07 and the second memory chip 08 are selectively connected to the field-programmable gate array 06 through the memory chip switching circuit 120. The watchdog chip 110 is connected to the memory chip switching circuit 120 and the field-programmable gate array 06, and is used to trigger the memory chip switching circuit 120 to reload from the second memory chip 08 when the first memory chip 07 fails to load. The first memory chip 07 and the second memory chip 08 are memory chips used to switch loading for different scenarios. Specifically, by default, the circuit loads from the first memory chip 07; if the first memory chip 07 fails to load (boot failure), the watchdog chip 110 and the memory chip switching circuit 120 trigger loading from the second memory chip 08. For example, the first memory chip 07 can also be referred to as Group A Flash, and the second memory chip 08 can also be referred to as Group B Flash; the specific models of the first memory chip 07 and the second memory chip 08 are not limited here. The field-programmable gate array (FPGA) 06 is used for selectively loading the first memory chip 07 and the second memory chip 08. Exemplarily, the FPGA 06 can be connected to the first memory chip 07 and the second memory chip 08 via relevant switches within the memory chip switching circuit 120. The internal logic of these switches allows for selective connection of the first memory chip 07 and the second memory chip 08 to the FPGA 06, thereby enabling selective loading of the first memory chip 07 and the second memory chip 08 by the FPGA 06. The specific working process will be explained later. The memory chip switching circuit 120 is used to select the corresponding memory chip (first memory chip 07 or second memory chip 08) to connect to and load by the FPGA 06 based on the input and output states of its internal structure. Specifically, based on the connection between the memory chip switching circuit 120 and the watchdog chip 110, when the entire circuit defaults to loading from the first memory chip 07, if the first memory chip 07 fails to load, the watchdog chip 110 will send a relevant signal, such as a reset pulse signal, to the memory chip switching circuit 120. This reset pulse signal will be used to further change the input and output states of the internal structure of the memory chip switching circuit 120, so that the relevant switch selects the second memory chip 08 to connect with the field programmable gate array 06 and reloads it. The specific working process will be described in the following description.It is easy to understand that when the first memory chip 07 fails to load, the field-programmable gate array 06 provided in this embodiment does not rely on its internal software to select to reload from the second memory chip 08. Instead, it can utilize the watchdog chip 110 and the memory chip switching circuit 120 in the circuit to enable the field-programmable gate array 06 to reload the second memory chip 08. It is only necessary to ensure that the field-programmable gate array 06 has a relevant interface. For example, this relevant interface can be a Serial Peripheral Interface (SPI) interface or a 6-wire SPI (Quad SPI, QSPI) interface. The field-programmable gate array 06 can be a Xilinx ZYNQ 7000 series or other series of field-programmable gate arrays. The specific type of the relevant interface and the series of the field-programmable gate array 06 are not limited here. For example, the watchdog chip 110 can be a TPS3823-33-Q1 model or other models of watchdog chips, which are not limited here. This disclosure provides a watchdog-based universal dual-boot switching circuit for loading a field-programmable gate array (FPGA), comprising: a watchdog chip 110, a first memory chip 07, a second memory chip 08, a memory chip switching circuit 120, and an FPGA 06. The first memory chip 07 and the second memory chip 08 are selectively connected to the FPGA 06 via the memory chip switching circuit 120. The watchdog chip 110 is connected to both the memory chip switching circuit 120 and the FPGA 06, and is used to trigger the memory chip switching circuit 120 to reload from the second memory chip 08 when the first memory chip 07 fails to load. Thus, by using the watchdog chip and the memory chip switching circuit for boot switching, and triggering the memory chip switching circuit 120 to reload from the second memory chip 08 when the first memory chip 07 fails to load, the configuration of the FPGA 06 is facilitated smoothly, avoiding hardware downtime. Simultaneously, it improves the versatility of FPGAs with other watchdog series, thereby enhancing the overall applicability of the circuit. In some embodiments, ... Figure 3 This is a schematic diagram of another watchdog-based field-gate array-loaded universal dual-boot switching circuit provided in an embodiment of this disclosure. Figure 2 Based on, refer to Figure 3The memory chip switching circuit includes: a dual AND gate 121, a D flip-flop 122, and a switch selection chip 123; a watchdog chip 110 is connected to the dual AND gate 121 and is used to output a reset pulse signal to the dual AND gate 121 when the first memory chip 07 fails to load; the first output terminal AND2 of the dual AND gate 121 is connected to the first switching terminal of the D flip-flop 122 and is used to generate a transition signal to trigger the output signal of the D flip-flop 122 to flip; the first output terminal of the D flip-flop 122 is connected to the controlled terminal of the switch selection chip 123 and is used to control the switch selection chip 123 to select whether to reload from the second memory chip 08 or the first memory chip 07 based on the flipped output signal. The dual AND gate 121 is a structure including two AND gate circuits. For example, the dual AND gate 121 includes a first output terminal AND2 and a second output terminal AND1, corresponding to the two AND gate circuits respectively. The D flip-flop 122 is a structure used to change the switching state of the switch selection chip 123 through its own output state. For example, the D flip-flop 122 can be... Figure 3 The dual-channel falling-edge trigger shown, or a preset number of single-channel falling-edge triggers, can be of model SN74HCS72 or other models; furthermore, it is easy to understand that, with Figure 3 Taking the structure as an example, the D flip-flop 122 can also be configured as two single-channel falling-edge flip-flops, as long as the ports shared by the two single-channel falling-edge flip-flops are the same as the ports of the dual-channel falling-edge flip-flop; there are no limitations here. For example, taking... Figure 3Taking the connection relationship shown as an example, the D flip-flop 122 is a dual falling edge flip-flop. In the first falling edge flip-flop, the CLR1 terminal (representing the Clear terminal) and the CP1 terminal (i.e., the first switching terminal, also called the trigger interface) are the input terminals, the D1 terminal is also an input terminal, and the Q1* terminal and the Q1 terminal (i.e., the first output terminal) are the output terminals. When the trigger interface CP1 is valid, the signal output by Q1 is equal to the signal input by D1. In the second falling edge flip-flop, the CP2 terminal and the PRE2 terminal (representing the Set terminal) are the input terminals, the D2 terminal is also an input terminal, and the Q2* terminal and the Q2 terminal are the output terminals. Similarly, when the signal at the CP2 terminal is valid, the signal output by Q2 is equal to the signal input by D2. In the Field Programmable Gate Array (FPGA) 06, the PS_POR_B and QSPI terminals are inputs, and the WDI and SOFT_SPI_SEL terminals are outputs. Specifically: the output of the watchdog chip 110 is connected to the two AND gates in the dual AND gate 121; the CP1 terminal is connected to the output of AND2; the output of AND1 is connected to both the PS_POR_B and PRE2 terminals; the QSPI and Q1 terminals are connected to the switch selection chip 123; the WDI terminal is connected to the input of the watchdog chip 110; and the SOFT_SPI_SEL terminal is connected to the CP2 terminal. It should be noted that the PS_POR_B terminal of the FPGA 06 is used to receive a reset signal; the WDI terminal is used to output a normal feed signal to the watchdog chip 110 when the FPGA 06 is normally loading the first memory chip 07; and the SOFT_SPI_SEL terminal is used to achieve switching loading (or mirror switching) between the two memory chips via software control. Figure 3Specifically, during power-up or in the presence of a hardware reset input, the field-programmable gate array 06 defaults to loading from the first memory chip 07. If loading from the first memory chip 07 fails, the field-programmable gate array 06 fails to boot, thus not sending a normal feed signal to the watchdog chip 110. When the watchdog chip 110 does not receive a normal feed signal for an extended period, its output, such as the RESET* terminal (not shown in the figure), will output a low-level active reset pulse signal, such as the WD_RESET# signal. At this time, the output of the AND gate circuit AND1 is 0, meaning the field-programmable gate array 06 is not activated. When the PS_POR_B terminal of the programmable gate array 06 receives a reset signal of 0, the field-programmable gate array 06 is reset when the reset signal is low. Simultaneously, the PRE2 terminal receives a 0, making the Q2 terminal 1. Based on this, since the reset pulse signal is 0, the AND2 output is 0, generating an SPI_CLK_SEL signal that transitions from high to low (from 1 to 0). This triggers the output signal corresponding to the Q1 terminal of the D flip-flop 122 to flip, i.e., the flipped output signal becomes 1, causing the switch selection chip 123 to switch to reloading from the second memory chip 08. For example, the duration of the WD_RESET# signal can be 200ms. In other embodiments, other duration values can be set according to the reset requirements of the watchdog chip 110, which are not limited here. In some embodiments, refer to... Figure 3 The second output terminal AND1 of the dual AND gate 121 is connected to the reset trigger terminal of the field-programmable gate array 06, the reset trigger terminal of the first memory chip 07, the reset trigger terminal of the second memory chip 08, and the set terminal of the second channel of the D flip-flop 122; the second output terminal of the D flip-flop 122 is connected to one input terminal of the dual AND gate 121. Specifically, based on the above operating procedure, the reset trigger terminal of the field-programmable gate array 06 is the PS_POR_B terminal, the set terminal of the D flip-flop 122 is the PRE2 terminal, and the second output terminal of the D flip-flop 122 is the Q2 terminal. It should be noted that, based on the connection between the second output terminal AND1 of the dual AND gate 121 and the corresponding reset trigger terminal, the PS_POR_B terminal is used to receive the reset signal for the field-programmable gate array 06. When the reset signal received by the field-programmable gate array 06, such as the PS_POR_B signal, is low (corresponding to 0), the field-programmable gate array 06 is triggered to reset. At the same time, the reset trigger terminals of the first memory chip 07 and the second memory chip 08 will also receive low-level reset signals, thereby triggering the first memory chip 07 and the second memory chip 08 to reset. The specific working principle of the PRE2 and Q2 terminals can be understood by referring to the above, and will not be repeated here. In some embodiments, refer to Figure 3The first output of the D flip-flop 122 and the controlled terminal of the switch selection chip 123 are both connected to the load state input of the field-programmable gate array 06, used to transmit the load state based on the first memory chip 07 or the second memory chip 08 to the field-programmable gate array 06. Specifically, in accordance with the above operating process, the first output of the D flip-flop 122 is the Q1 terminal, and the load state input of the field-programmable gate array 06 is the QSPI terminal. It should be noted that when the Q1 output of the D flip-flop 122 is high (corresponding to 1), the switch selection chip 123 selects to load from the second memory chip 08; when the Q1 output of the D flip-flop 122 is low (corresponding to 0), the switch selection chip 123 selects to load from the first memory chip 07, thereby changing the switching state of the switch selection chip 123. Based on this, the first output of the D flip-flop 122 and the controlled terminal of the switch selection chip 123 can transmit the loading state of the corresponding memory chip to the QSPI terminal, so that the field-programmable gate array 06 can obtain the specific loading status of the first memory chip 07 or the second memory chip 08. It is easy to understand that, based on the above connection relationship between the watchdog chip 110, the memory chip switching circuit 120, and the field-programmable gate array 06, the field-programmable gate array 06 can also be configured as other programmable devices with QSPI or SPI terminals to achieve mirror switching through the QSPI or SPI terminals. The type of device is not limited here. In some embodiments, refer to Figure 3The field-programmable gate array 06 also includes a software control interface. This software control interface is connected to the second switching terminal of the D flip-flop 122 and is used to continuously send two pulse signals with a preset time interval to the second switching terminal in response to the triggering of the target switching condition, thus triggering the output signal of the D flip-flop 122 to flip. Specifically, in conjunction with the above working process, the software control interface is the SOFT_SPI_SEL terminal, and the second switching terminal of the D flip-flop 122 is the CP2 terminal. For example, the target switching condition can be a user-defined switching condition, such as a software program that periodically checks the loading status of the corresponding memory chip and switches the memory chip, or other switching conditions, which are not limited here. Specifically, when the target switching condition is triggered, the host computer can control the SOFT_SPI_SEL terminal of the field-programmable gate array 06 to output a low-level pulse signal, for example, by continuously sending two pulse signals with an interval of 100ms and a duration of 10ms for each pulse signal, thereby causing the output signal of the D flip-flop 122 to flip, such as to 1 or 0, to activate the switching operation of the field-programmable gate array 06, that is, to realize the switching loading of the field-programmable gate array 06 from two memory chips. Here, the interval and duration of the pulse signal are not limited. For example, the interval can also be 90ms, 110ms or other durations, and the duration can also be 9ms, 11ms or other durations. For example, if the current field-programmable gate array 06 is loaded from the first memory chip 07, it is known that the BOOT_SPI_SEL signal corresponding to the controlled terminal of the switch selection chip 123 is 0 at this time. After two low-level pulse signals are output at the SOFT_SPI_SEL terminal, the Q2 terminal will be 0, thereby the output of the AND gate circuit AND2 will be 0, generating an SPI_CLK_SEL signal that jumps from high level to low level (from 1 to 0). This indicates that the SPI_CLK_SEL signal has generated a falling edge, which can trigger the output signal corresponding to the Q1 terminal of the D flip-flop 122 to flip, that is, the flipped output signal is 1, and then the switch selection chip 123 switches to reloading from the second memory chip 08. In some embodiments, refer to Figure 3 The load state input terminal of the field-programmable gate array 06, the first output terminal of the D flip-flop 122, and the controlled terminal of the switch selection chip 123 are all grounded through a resistor 140. Exemplarily, the resistance value of resistor 140 can be 4.7kΩ. In other embodiments, the resistance value of resistor 140 can be set to other values according to the circuit design requirements, and is not limited here. In some embodiments, refer to... Figure 3The field-programmable gate array 06 also includes a watchdog signal output terminal; the watchdog signal output terminal is connected to the input terminal of the watchdog chip 110, and is used to output a watchdog abnormality signal to the watchdog chip 110 when the first memory chip 07 fails to load; the watchdog chip 110 outputs a reset pulse signal in response to the watchdog abnormality signal. It should be noted that the watchdog abnormality signal here can be a no-feed signal, that is, when loading is normal, the watchdog operation will be performed normally; when loading is abnormal, the watchdog will not be fed, thereby triggering a reset. In other embodiments, the watchdog abnormality signal can also be another signal that can be sent to the watchdog chip 110 and is distinguishable from the normal watchdog signal. In the above working process, the watchdog signal output terminal is the WDI terminal. Specifically, when the first memory chip 07 fails to load, the watchdog signal output terminal can output a watchdog abnormality signal to indicate that normal watchdog feeding is not possible. Specifically, this watchdog abnormality signal means no watchdog feeding, equivalent to the watchdog chip 110 not receiving a normal watchdog signal for an extended period. For example, if the watchdog chip 110 does not receive a normal watchdog signal within 1.6 seconds, a reset pulse signal is output after the 1.6-second internal timer of the watchdog chip 110 finishes counting down. This causes the switch selection chip 123 to switch to reloading from the second memory chip 08. The specific working process after outputting the reset pulse signal can be understood as described above and will not be repeated here. In some embodiments, refer to... Figure 3The first interactive terminal of the switch selection chip 123 is connected to the first memory chip 07, the second interactive terminal of the switch selection chip 123 is connected to the second memory chip 08, and the third interactive terminal of the switch selection chip 123 is connected to the field programmable gate array 06. The switch selection chip 123 responds to the output signal of the D flip-flop 122 and achieves selective connection of the first memory chip 07 and the second memory chip 08 to the field programmable gate array 06 through internal logic switching. Specifically, when the output signal corresponding to the Q1 terminal of the D flip-flop 122 is 1, that is, the BOOT_SPI_SE L signal corresponding to the controlled terminal of the switch selection chip 123 is 1, the BOOT_SPI_SE L signal is used as the control input signal of the switch selection chip 123 and is input to the controlled terminal of the switch selection chip 123. Since the switch selection chip 123 includes two sub-switch selection chips, the controlled terminal may include a first controlled terminal (such as the IN1 terminal) and a second controlled terminal (such as the IN2 terminal). According to the control logic inside the switch selection chip 123, when both the first controlled terminal IN1 and the second controlled terminal IN2 are at a high level, that is, both are 1, the field programmable gate array 06 selects to load from the second memory chip 08. Based on the internal logic switching process of the switch selection chip 123 described above, when the output signal corresponding to the Q1 terminal of the D flip-flop 122 is 0, that is, the BOOT_SPI_SEL signal corresponding to the controlled terminal of the switch selection chip 123 is 0, it can also be known from the internal control logic of the switch selection chip 123 that when both the first controlled terminal IN1 and the second controlled terminal IN2 are at a low level (i.e., both are 0), the field-programmable gate array 06 selects to load from the first memory chip 07. It is easy to understand that the first, second, and third interactive terminals of the switch selection chip 123 have bidirectional signal transmission capabilities, that is, they can satisfy both external signal input and internal signal output, thereby achieving bidirectional interaction with the first memory chip 07, the second memory chip 08, and the field-programmable gate array 06. In some embodiments, refer to... Figure 3The switch selection chip 123 includes a QSPI switch; the QSPI switch is connected to the field-programmable gate array 06 via a QSPI bus. Specifically, in accordance with the above operating procedure, when the switch selection chip 123 is a QSPI switch, the first interactive terminal of the QSPI switch is connected to the QSPI terminal of the first memory chip 07, the second interactive terminal of the QSPI switch is connected to the QSPI terminal of the second memory chip 08, and the third interactive terminal of the QSPI switch is connected to the field-programmable gate array 06 via the QSPI bus (D represents the QSPI bus), so that the first memory chip 07 and the second memory chip 08 can be selectively connected to the field-programmable gate array 06. For example, the QSPI switch model can be TS3A27518EIPWR; in other embodiments, it can also be other models of QSPI switches with the above switching function known to those skilled in the art, which are not limited here. In some embodiments, refer to... Figure 3The watchdog-based field-programmable gate array loading general dual-boot switching circuit also includes a hardware reset chip 130; the hardware reset chip 130 is connected to another input terminal of the dual AND gate 121 and is used to output a reset signal to the dual AND gate 121 in response to the hardware reset signal input. Specifically, when the circuit is powered on or when a hardware reset input is present (i.e., when the circuit is normally loaded), the hardware reset chip 130 receives an external hardware reset signal and outputs a low-level reset signal, such as HW_RESET#, to AND1. When HW_RESET# is 0, AND1 outputs 0, meaning the PS_POR_B signal received by the field-programmable gate array 06 is 0, thus triggering the reset of the field-programmable gate array 06, the first memory chip 07, and the second memory chip 08. Simultaneously, the PRE2 terminal of the D flip-flop 122 is 0, making the Q2 terminal 1. At this time, the watchdog chip 110 can feed the watchdog normally, so the RESET* terminal of the watchdog chip 110 is 1, and the AND2 output is 1. In addition, the HW_RESET# signal is also transmitted to the CLR1 terminal, making the Q1 terminal 0, and the BOOT_SPI_SE corresponding to the controlled terminal of the switch selection chip 123 is 0. When the L signal is 0, according to the control logic inside the switch selection chip 123, when both the first and second controlled terminals are at a low level (i.e., both are 0), the field-programmable gate array 06 selects to load from the first memory chip 07. For example, the duration of the HW_RESET# signal can be 200ms. In other embodiments, other duration values can be set according to the reset requirements of the hardware reset chip 130, which are not limited here. Furthermore, in conjunction with the above hardware reset input, this embodiment can also implement the process of switching the currently loaded image through a software control interface. Specifically, if the field-programmable gate array 06 loads the second memory chip 08, the BOOT_SPI_SEL signal corresponding to the controlled terminal of the switch selection chip 123 is 1. After outputting two low-level pulse signals at the SOFT_SPI_SEL terminal, the Q2 terminal will be 0, thus the output of the AND gate circuit AND2 will be 0, generating the SPI_CLK_SEL signal that jumps from high level to low level (from 1 to 0). This indicates that the SPI_CLK_SEL signal has generated a falling edge, which can trigger the output signal corresponding to the Q1 terminal of the D flip-flop 122 to flip, that is, the flipped output signal is 0. Then the switch selection chip 123 switches to reloading from the first memory chip 07. It should be noted that, for the case where the software control interface is used to switch the currently loaded image, the circuit will transmit the status of the BOOT_SPI_SE L signal corresponding to the controlled terminal of the switch selection chip 123 to the host computer (not shown in the figure). The host computer will obtain the specific loading status of the first storage chip 07 or the second storage chip 08 based on the status of the BOOT_SPI_SE L signal being 1 or 0.To address this, the watchdog-based field-programmable gate array (FPGA) loading universal dual-boot switching circuit provided in this disclosure only requires a simple watchdog-feeding operation to automatically switch to another Flash group for loading when one Flash group fails to load, or to easily achieve free switching between the two Flash groups by continuously sending two pulse signals with a preset time interval through the software control interface, forming a simple and fast software control method. This achieves a stable and reliable switching mechanism, greatly improving the versatility of the entire circuit. It should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A watchdog-based field-programmable gate array (FPGA) loading universal dual-guided switching circuit, characterized in that, include: Watchdog chip, first memory chip, second memory chip, memory chip switching circuit, and field-programmable gate array; The first memory chip and the second memory chip are selectively connected to the field-programmable gate array via the memory chip switching circuit; The watchdog chip is connected to the memory chip switching circuit and the field-programmable gate array, and is used to trigger the memory chip switching circuit to reload from the second memory chip when the first memory chip fails to load.
2. The watchdog-based field-programmable gate array loading universal dual-guide switching circuit according to claim 1, characterized in that, The memory chip switching circuit includes: a dual AND gate, a D flip-flop, and a switch selection chip; The watchdog chip is connected to the dual AND gate and is used to output a reset pulse signal to the dual AND gate when the first memory chip fails to load. The first output terminal of the dual AND gate is connected to the first switching terminal of the D flip-flop to generate a switching signal, which triggers the output signal of the D flip-flop to flip. The first output terminal of the D flip-flop is connected to the controlled terminal of the switch selection chip, and is used to control the switch selection chip to select whether to reload from the second memory chip or the first memory chip based on the flipped output signal.
3. The watchdog-based field-programmable gate array loading universal dual-guide switching circuit according to claim 2, characterized in that, The second output terminal of the dual AND gate is connected to the reset trigger terminal of the field programmable gate array, the reset trigger terminal of the first memory chip, the reset trigger terminal of the second memory chip, and the set terminal of the second channel of the D flip-flop. The second output of the D flip-flop is connected to one input of the double AND gate.
4. The universal dual-boot switching circuit for loading a field-programmable gate array based on a watchdog timer as described in claim 2, characterized in that, The first output terminal of the D flip-flop and the controlled terminal of the switch selection chip are both connected to the load state input terminal of the field-programmable gate array (FPGA) to transmit the load state based on the first memory chip or the second memory chip to the FPGA.
5. The universal dual-boot switching circuit for loading a field-programmable gate array based on a watchdog timer according to claim 4, characterized in that, The field-programmable gate array also includes a software control interface; The software control interface is connected to the second switching terminal of the D flip-flop and is used to continuously send two pulse signals with a preset time interval to the second switching terminal in response to the target switching condition being triggered, thereby triggering the output signal of the D flip-flop to flip.
6. The universal dual-boot switching circuit for loading a field-programmable gate array based on a watchdog timer according to claim 2, characterized in that, The load state input terminal of the field-programmable gate array, the first output terminal of the D flip-flop, and the controlled terminal of the switch selection chip are all grounded through a resistor.
7. The universal dual-boot switching circuit for loading a field-programmable gate array based on a watchdog timer according to claim 2, characterized in that, The field-programmable gate array also includes a dog feed signal output terminal; The watchdog signal output terminal is connected to the input terminal of the watchdog chip and is used to output a watchdog abnormal signal to the watchdog chip when the first memory chip fails to load. The watchdog chip outputs a reset pulse signal in response to the abnormal feeding signal.
8. The watchdog-based field-programmable gate array loading universal dual-boot switching circuit according to claim 2, characterized in that, The first interactive terminal of the switch selection chip is connected to the first memory chip, the second interactive terminal of the switch selection chip is connected to the second memory chip, and the third interactive terminal of the switch selection chip is connected to the field programmable gate array. The switch selection chip responds to the output signal of the D flip-flop and uses internal logic to selectively connect the first memory chip and the second memory chip to the field-programmable gate array.
9. The watchdog-based field-programmable gate array loading universal dual-boot switching circuit according to claim 8, characterized in that, The switch selection chip includes a QSPI switch; The QSPI switch is connected to the field-programmable gate array via the QSPI bus.
10. The watchdog-based field-programmable gate array loading universal dual-guide switching circuit according to claim 2, characterized in that, It also includes a hardware reset chip; The hardware reset chip is connected to the other input terminal of the dual AND gate and is used to output a reset signal to the dual AND gate in response to a hardware reset signal input.