A GaN-based CMOS device combining metal polarity and nitrogen polarity and a method for preparing the same

Abstract

A GaN-based CMOS device combining metal polarity and nitrogen polarity and a preparation method thereof belong to the technical field of semiconductor electronic devices. The device integrates a PMOS device and an NMOS device on the same substrate, and each device structure is composed of a substrate, an AlN buffer layer, a high-resistance GaN layer, an AlGaN barrier layer, a GaN channel layer, a polarization induction layer, an insulating layer, a passivation layer, and a gate electrode, a source electrode, and a drain electrode. The main structure of the device is prepared by an MOCVD method, and the preparation process also involves processes such as magnetron sputtering and photolithography. The present invention reduces the system volume and the complexity of the system design by monolithically integrating PMOS and NMOS devices, which is beneficial to reducing the parasitic effects between different devices and improving the efficiency of the circuit system; in addition, the synchronous growth of metal polarity and nitrogen polarity devices can obtain PMOS and NMOS structures by epitaxy at one time, which is beneficial to shortening the process flow and reducing production costs.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor electronic devices, and in particular relates to a GaN-based CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device combining metal polarity with nitrogen polarity and a preparation method thereof. Background Art

[0002] Wide bandgap semiconductor GaN material has the advantages of wide bandgap width, strong breakdown electric field and high saturation electron velocity. It can be used to prepare high-frequency and high-power electronic devices and is applied in civil and military fields such as new generation mobile communications and military radar.

[0003] However, when discrete GaN-based electronic devices are applied to traditional integrated circuits, parasitic inductance and parasitic resistance will be generated at the electrode bonding point; at the same time, the wiring of the printed circuit board will generate additional capacitance, which causes the device to generate large losses during the switching process. The monolithic integration of GaN-based electronic devices is an effective way to reduce parasitic inductance and can effectively improve circuit efficiency. For monolithic integrated GaN-based CMOS devices, this can be achieved through the method of selective etching plus secondary epitaxy, but this method has a long process flow, and the secondary epitaxy will have an adverse effect on the quality of PMOS (P-channel field effect transistor). Summary of the invention

[0004] The present invention proposes a GaN-based CMOS device combining metal polarity and nitrogen polarity and a preparation method thereof. On the one hand, the present invention integrates a P-channel field effect transistor (PMOS for short) and an N-channel field effect transistor (NMOS for short) into a GaN-based CMOS device, thereby reducing the parasitic effects between different devices and improving the working efficiency of the circuit system; on the other hand, the present invention realizes the synchronous in-situ growth of metal polarity and nitrogen polarity GaN-based devices on a substrate wafer by a method of pre-sputtering and selective growth, thereby simplifying the device process flow and avoiding the adverse effects of secondary epitaxy on device performance.

[0005] The present invention discloses a GaN-based CMOS device combining metal polarity and nitrogen polarity, characterized in that the CMOS device is composed of a metal polarity PMOS device and a nitrogen polarity NMOS device (see attached Figure 1, the metal polarity PMOS device is composed of a substrate 1, a metal polarity AlN preparation layer 2, a metal polarity AlN buffer layer 4, a metal polarity high resistance GaN layer 6, a metal polarity AlGaN barrier layer 8, a metal polarity GaN channel layer 10, a metal polarity polarization inducing layer 12 and a passivation layer 14 from bottom to top; the passivation layer 14 and the metal polarity polarization inducing layer 12 are etched along the middle area to expose the metal polarity GaN channel layer 10 to form a PMOS gate electrode groove; after etching An insulating layer 15 is prepared on the surface of the passivation layer 14 and the exposed surface of the metal polarity GaN channel layer 10; the insulating layer 15 and the passivation layer 14 are further etched along the left and right end regions to expose the metal polarity polarization inducing layer 12, forming a PMOS source electrode groove and a PMOS drain electrode groove; a PMOS source electrode 16 and a PMOS drain electrode 17 are respectively prepared in the PMOS source electrode groove and the PMOS drain electrode groove, and a PMOS gate electrode 20 is prepared in the PMOS gate electrode groove; a nitrogen polarity NMOS The device structure is composed of a substrate 1, a nitrogen-polarity AlN buffer layer 5, a nitrogen-polarity high-resistance GaN layer 7, a nitrogen-polarity AlGaN barrier layer 9, a nitrogen-polarity GaN channel layer 11, a nitrogen-polarity polarization inducing layer 13 and a passivation layer 14 from bottom to top; the passivation layer 14 and the nitrogen-polarity polarization inducing layer 13 are etched along the middle region to expose the nitrogen-polarity GaN channel layer 11 to form an NMOS gate electrode groove; an insulating layer 15 is prepared on the surface of the etched passivation layer 14 and the exposed surface of the nitrogen-polarity GaN channel layer 11 ; The insulating layer 15 and the passivation layer 14 are further etched along the left and right end regions to expose the nitrogen polarization inducing layer 13, forming an NMOS source electrode groove and an NMOS drain electrode groove; an NMOS source electrode 18 and an NMOS drain electrode 19 are respectively prepared in the NMOS source electrode groove and the NMOS drain electrode groove, and an NMOS gate electrode 21 is prepared in the NMOS gate electrode groove; the metal polarity PMOS device and the nitrogen polarity NMOS device share the same substrate 1, and their structures are separated by an isolation layer 3.

[0006] The CMOS device can also be composed of a metal polarity NMOS device and a nitrogen polarity PMOS device (see Appendix Figure 2and the accompanying drawings), the metal polarity NMOS device is composed of a substrate 1, a metal polarity AlN preparation layer 2, a metal polarity AlN buffer layer 4, a metal polarity high resistance GaN layer 6, a metal polarity GaN channel layer 10, a metal polarity AlGaN barrier layer 8, a metal polarity polarization inducing layer 12 and a passivation layer 14 from bottom to top; the passivation layer 14 and the metal polarity polarization inducing layer 12 are etched along the middle area to expose the metal polarity AlGaN barrier layer 8 to form an NMOS gate electrode groove; in An insulating layer 15 is prepared on the surface of the etched passivation layer 14 and the exposed metal polarity AlGaN barrier layer 8; the insulating layer 15 and the passivation layer 14 are etched along the left and right end regions to expose the metal polarity polarization induction layer 12 to form an NMOS source electrode groove and an NMOS drain electrode groove; an NMOS source electrode 18 and an NMOS drain electrode 19 are prepared in the NMOS source electrode groove and the NMOS drain electrode groove, and an NMOS gate electrode 21 is prepared in the NMOS gate electrode groove; a nitrogen polarity PMOS The device structure is composed of a substrate 1, a nitrogen-polarity AlN buffer layer 5, a nitrogen-polarity high-resistance GaN layer 7, a nitrogen-polarity GaN channel layer 11, a nitrogen-polarity AlGaN barrier layer 9, a nitrogen-polarity polarization inducing layer 13 and a passivation layer 14 from bottom to top; the passivation layer 14 and the nitrogen-polarity polarization inducing layer 13 are etched along the middle region to expose the nitrogen-polarity AlGaN barrier layer 9 to form a PMOS gate electrode groove; an insulating layer is prepared on the surface of the etched passivation layer 14 and the exposed nitrogen-polarity AlGaN barrier layer 9 15; the insulating layer 15 and the passivation layer 14 are etched along the left and right end regions to expose the nitrogen polarization inducing layer 13 to form a PMOS source electrode groove and a PMOS drain electrode groove; a PMOS source electrode 16 and a PMOS drain electrode 17 are prepared in the PMOS source electrode groove and the PMOS drain electrode groove, and a PMOS gate electrode 20 is prepared in the PMOS gate electrode groove; the metal polarity NMOS device and the nitrogen polarity PMOS device share the same substrate 1, and their structures are separated by an isolation layer 3.

[0007] The present invention prepares metal polarity and nitrogen polarity GaN / AlGaN or AlGaN / GaN heterojunctions (metal polarity GaN / AlGaN heterojunctions correspond to Figure 1 The metal polarity GaN channel layer 10 / metal polarity AlGaN barrier layer 8 structure in the nitrogen polarity GaN / AlGaN heterojunction corresponds to Figure 1 The nitrogen-polarity GaN channel layer 11 / nitrogen-polarity AlGaN barrier layer 9 structure in the metal-polarity AlGaN / GaN heterojunction corresponds to Figure 2 The metal polarity AlGaN barrier layer 8 / metal polarity GaN channel layer 10 structure in the nitrogen polarity AlGaN / GaN heterojunction corresponds to Figure 2The structure of nitrogen-polar AlGaN barrier layer 9 / nitrogen-polar GaN channel layer 11 in the heterojunction is prepared by using two-dimensional hole gas and two-dimensional electron gas at the heterojunction interface to prepare PMOS and NMOS structures, thereby realizing the monolithic integration of GaN-based CMOS devices, which is conducive to reducing parasitic effects between devices and improving the efficiency of the circuit system. Through polarity control, metal polarity and nitrogen polarity device structures can be obtained simultaneously by one epitaxy, avoiding secondary epitaxy, which is conducive to improving the crystal quality of epitaxial thin films, shortening the device preparation cycle and reducing device costs.

[0008] A GaN-based CMOS device combining metal polarity and nitrogen polarity as described above is characterized in that the substrate 1 can be a sapphire substrate, a carbon-faced SiC substrate, a Si substrate or other single crystal substrates that can be used for nitride epitaxial growth. The polarity of each layer of material on the substrate 1 can be regulated by the substrate surface pretreatment process, such as a metal polarity PMOS or NMOS structure can be obtained on a sapphire, carbon-faced SiC substrate or Si substrate that has been pre-sputtered with an AlN buffer layer and high-temperature annealing (temperature is 1500°C to 1700°C, annealing time is between 5min and 20min); a nitrogen polarity PMOS or NMOS structure can be obtained on a sapphire, carbon-faced SiC substrate or Si substrate that has been subjected to ammonia nitridation treatment under high temperature and high V / III ratio conditions (temperature>1100°C, V / III ratio>6000). Since the metal polarity and nitrogen polarity devices share the same substrate 1, in order to obtain PMOS or NMOS structures of different polarities, different regions of the same substrate must be treated differently.

[0009] The GaN-based CMOS device combining metal polarity and nitrogen polarity as described above is characterized in that: the thickness of the metal polarity AlN preparation layer 2 is 10-200nm, the thickness of the metal polarity AlN buffer layer 4 is 100-200nm; the thickness of the nitrogen polarity AlN buffer layer 5 is 100-200nm.

[0010] The GaN-based CMOS device combining metal polarity and nitrogen polarity as described above is characterized in that: the metal polarity high-resistance GaN layer 6 and the nitrogen polarity high-resistance GaN layer 7 are doped with compensating acceptor elements such as Fe to form high-resistance characteristics, and the square resistance is 10 5 ~10 9 Ω / □, with a thickness of 1 to 2 μm; the Al component of the metal polarity AlGaN barrier layer 8 and the nitrogen polarity AlGaN barrier layer 9 is 15% to 40% (molar amount), and the thickness is 15 to 30 nm; the thickness of the metal polarity GaN channel layer 10 and the nitrogen polarity GaN channel layer 11 is 20 to 30 nm.

[0011] The GaN-based CMOS device combining metal polarity and nitrogen polarity as described above is characterized in that: the CMOS device is composed of a metal polarity PMOS and a nitrogen polarity NMOS, wherein the composition of the metal polarity polarization induction layer 12 of the metal polarity PMOS is gradually changed to In x Ga 1-x The In component x of N increases from x along the epitaxial growth direction. 1 Gradient to x 2 , satisfying 0≤x 1 <x 2 ≤1(from In x1 Ga 1-x1 N→In x2 Ga 1-x2 N), with a thickness of 50 to 150 nm; wherein the composition of the nitrogen polarity polarization induction layer 13 of the nitrogen polarity NMOS is gradually changed to In x Ga 1-x The In component x of N increases from x along the epitaxial growth direction. 1 Gradient to x 2 , satisfying 0≤x 1 <x 2 ≤1, thickness is 50~150nm. Due to the polarization effect of GaN-based materials, the metal polarity GaN / AlGaN heterojunction interface will produce high concentration of two-dimensional hole gas to form a hole channel, and the nitrogen polarity GaN / AlGaN heterojunction interface will produce high concentration of two-dimensional electron gas to form an electron channel; high concentration of three-dimensional hole gas and three-dimensional electron gas will be produced in the metal polarity polarization induction layer 12 and the nitrogen polarity polarization induction layer 13, respectively, to provide channel holes and channel electrons for the metal polarity PMOS and nitrogen polarity NMOS.

[0012] The GaN-based CMOS device combining metal polarity and nitrogen polarity as described above is characterized in that: the CMOS device is composed of a metal polarity NMOS and a nitrogen polarity PMOS, wherein the composition of the metal polarity polarization induction layer 12 of the metal polarity NMOS is gradually changed to In x Ga 1-x The In component x of N increases from x along the epitaxial growth direction. 1 Gradient to x 2 , satisfying 1≥x 1 >x 2 ≥0, with a thickness of 50-150 nm. The composition of the nitrogen-polarity PMOS nitrogen-polarity polarization induction layer 13 is gradually changed to In x Ga 1-x The In component x of N increases from x along the epitaxial growth direction. 1 Gradient to x 2 , full 1 ≥ x 1 >x 2≥0, thickness is 50~150nm. Due to the polarization effect of GaN-based materials, the metal polarity AlGaN / GaN heterojunction interface will produce a high concentration of two-dimensional electron gas to form an electron channel, and the nitrogen polarity AlGaN / GaN heterojunction interface will produce a high concentration of two-dimensional hole gas to form a hole channel; the metal polarity polarization induction layer 12 and the nitrogen polarity polarization induction layer 13 will produce high concentrations of three-dimensional electron gas and three-dimensional hole gas, respectively, to provide channel electrons and channel holes for the metal polarity NMOS and nitrogen polarity PMOS.

[0013] The method for preparing a GaN-based CMOS device combining metal polarity and nitrogen polarity as described above comprises the following steps:

[0014] (1) The preparation steps of CMOS devices composed of metal polarity PMOS and nitrogen polarity NMOS are as follows:

[0015] After the substrate 1 is cleaned, the substrate 1 is divided into three regions, one region is used to prepare the metal polarity PMOS, and one region is used to prepare the SiO 2 Isolation layer 3, a region for preparing nitrogen polarity NMOS;

[0016] The substrate region for preparing the metal polarity PMOS is subjected to photoresist spin coating, pre-baking, exposure, development and post-baking operations to form a photolithography pattern of the metal polarity AlN preparation layer 2 on the substrate 1; after sputtering the AlN layer on the substrate 1 by a magnetron sputtering method, the remaining photoresist on the surface is removed; the sputtered AlN layer is subjected to high temperature annealing to prepare the metal polarity AlN preparation layer 2 (see attached Figure 3 and accompanying drawings); wherein the growth temperature of the metal polar AlN preparation layer 2 is 500-600°C, the growth pressure is 100-400mbar, the thickness is 10-200nm, the sputtering uses an Al target, and the gas atmosphere is nitrogen; the annealing temperature is 1500-1700°C, and the annealing time is 5min-20min;

[0017] For the preparation of SiO 2 The substrate region of the isolation layer 3 is subjected to the steps of photoresist spin coating, pre-baking, exposure, development and post-baking to form SiO 2 The photolithography pattern of the isolation layer 3 is used to prepare SiO on the substrate 1 by chemical vapor deposition (CVD) method. 2 After the layer is formed, the remaining photoresist on the surface is removed to obtain SiO 2 Isolation layer 3 (see attached Figure 4 and the accompanying drawings), with a thickness of 10 to 20 nm, for isolation preparation of the PMOS and NMOS devices to be prepared subsequently;

[0018] For the substrate region used to prepare the nitrogen-polar NMOS, a nitrogen-polar AlN buffer layer 5 is prepared by a metal organic chemical vapor deposition (MOCVD) method, with a growth temperature of 1100-1200° C., a growth pressure of 100-400 mbar, a reaction chamber V / III ratio of 6000-12000, a thickness of 100-200 nm, and a growth source of trimethylaluminum and high-purity ammonia. While preparing the nitrogen-polar AlN buffer layer 5, a metal-polar AlN buffer layer 4 is epitaxially formed on the metal-polar AlN preparation layer 2 (see attached Figure 5 and the accompanying drawings); continuing to use the MOCVD method to sequentially epitaxially grow a metal polarity high resistance GaN layer 6 and a nitrogen polarity high resistance GaN layer 7, a metal polarity AlGaN barrier layer 8 and a nitrogen polarity AlGaN barrier layer 9, a metal polarity GaN channel layer 10 and a nitrogen polarity GaN channel layer 11, a metal polarity polarization induction layer 12 and a nitrogen polarity polarization induction layer 13 on the metal polarity AlN buffer layer 4 and the nitrogen polarity AlN buffer layer 5; wherein the growth of the metal polarity AlN buffer layer 4 and the nitrogen polarity AlN buffer layer 5 The temperature is 1100-1200°C, the growth pressure is 100-400 mbar, the reaction chamber V / III ratio is 6000-12000, the thickness is 100-200 nm, and the growth source is trimethylaluminum and high-purity ammonia; the growth temperature of the metal polarity high-resistance GaN layer 6 and the nitrogen polarity high-resistance GaN layer 7 is 1000-1100°C, the growth pressure is 100-400 mbar, the thickness is 1000-2000 nm, the growth source is trimethylgallium and high-purity ammonia, and the doping source is ferrocene (Cp 2 Fe), the doping concentration is 10 17 ~10 20 / cm 3The growth temperature of the metal polarity AlGaN barrier layer 8 and the nitrogen polarity AlGaN barrier layer 9 is 1100-1250°C, the growth pressure is 100-400mbar, the thickness is 15-30nm, the Al component is 15%-40%, and the growth sources are trimethylaluminum, trimethylgallium and high-purity ammonia. The Al component can be controlled by adjusting the flow rate of the three growth sources; the growth temperature of the metal polarity GaN channel layer 10 and the nitrogen polarity GaN channel layer 11 is 1000-1100°C, the growth pressure is 100-400mbar, the thickness is 20-30nm, and the growth sources are trimethylgallium and high-purity Ammonia; the growth temperature of the metal polarity polarization inducing layer 12 and the nitrogen polarity polarization inducing layer 13 is 600-800°C, the growth pressure is 100-400mbar, the thickness is 50-150nm, the growth sources are trimethyl indium, triethyl gallium and high-purity ammonia, and the composition gradient can be achieved by gradually changing the source flow rate or the growth temperature during the growth process. For example, the linear increase of the In component can be achieved by linearly increasing the trimethyl indium flow rate (or linearly reducing the growth temperature) during the growth process; conversely, the linear reduction of the In component can be achieved by linearly reducing the trimethyl indium flow rate (or linearly increasing the growth temperature) during the growth process;

[0019] Separate SiN layers are prepared on the metal polarization inducing layer 12 and the nitrogen polarization inducing layer 13 by using a CVD method. x The passivation layer 14 has a thickness of 50 to 100 nm. The discrete SiN x The passivation layer 14 is etched along the respective middle regions to the surfaces of the metal polarity GaN channel layer 10 and the nitrogen polarity GaN channel layer 11 to obtain a metal polarity PMOS gate electrode groove and a nitrogen polarity NMOS gate electrode groove (see attached Figure 6 and accompanying drawings); using CVD method to separate the etched SiN x A separate insulating layer 15 is prepared on the passivation layer 14, the metal polarity PMOS gate electrode groove and the nitrogen polarity NMOS gate electrode groove structure (see attached Figure 7 The thickness of the insulating layer 15 is 10-50 nm, and the material may be SiO 2 or Al 2 O 3The invention discloses a method for preparing a PMOS gate electrode 20 (with a thickness of 150 to 300 nm) in a PMOS gate electrode groove by using a CVD method and combining photolithography technology. The material of the PMOS gate electrode 20 can be a binary alloy composite material such as Ti-Al and Ti-Au, a ternary alloy composite material such as Ti-Al-Ni, Ti-Al-Au, and Ti-Ni-Ni, or a quaternary composite material such as Ti-Al-Ni-Au. The invention discloses a method for preparing a NMOS gate electrode 21 (with a thickness of 150 to 300 nm) in a NMOS gate electrode groove by using a CVD method and combining photolithography technology. The material of the NMOS gate electrode 21 can be a single layer material such as Au, Ti, or Ni, or a binary alloy composite material such as Ti-Al, Ti-Au, or Ni-Au. The invention discloses a method for preparing a PMOS gate electrode 20 (with a thickness of 150 to 300 nm) in a P ... an ICP method and combining photolithography technology. x The passivation layer 14 is etched along the left and right end regions to the surfaces of the metal polarization induction layer 12 and the nitrogen polarization induction layer 13 to obtain a PMOS source electrode groove, a PMOS drain electrode groove and an NMOS source electrode groove, and an NMOS drain electrode groove (see attached Figure 8 and the accompanying drawings); a PMOS source electrode 16 and a PMOS drain electrode 17 (thickness 50-200 nm) are prepared in the PMOS source electrode groove and the PMOS drain electrode groove respectively by a CVD method, and the materials of the PMOS source electrode 16 and the drain electrode 17 can be Ni-Al, Ni-Au and other alloy composite materials; a NMOS source electrode 18 and a NMOS drain electrode 19 (thickness 50-200 nm) are prepared in the NMOS source electrode groove and the NMOS drain electrode groove respectively by a CVD method, and the materials of the NMOS source electrode 18 and the drain electrode 19 can be Ti-Al, Ti-Au and other binary alloy composite materials, Ti-Al-Ni, Ti-Al-Au, Ti-Ni-Ni and other ternary alloy composite materials, Ti-Al-Ni-Au and other quaternary composite materials.

[0020] (2) The preparation steps of the CMOS device composed of metal polarity NMOS and nitrogen polarity PMOS are as follows:

[0021] After the substrate 1 is cleaned, the substrate 1 is divided into three regions, one region is used to prepare the metal polarity NMOS, and one region is used to prepare the SiO 2 Isolation layer 3, one area is used to prepare nitrogen polarity PMOS;

[0022] The substrate region for preparing the metal polarity NMOS is subjected to the steps of photoresist spin coating, pre-baking, exposure, development and post-baking to form a photolithography pattern of the metal polarity AlN preparation layer 2 on the substrate 1; after sputtering the AlN layer on the substrate 1 by a magnetron sputtering method, the remaining photoresist on the surface is removed; the sputtered AlN layer is subjected to high temperature annealing to prepare the metal polarity AlN preparation layer 2 (see attached Figure 3and accompanying drawings); wherein the growth temperature of the metal polar AlN preparation layer 2 is 500-600°C, the growth pressure is 100-400mbar, the thickness is 10-200nm, the sputtering uses an Al target, and the gas atmosphere is nitrogen; the annealing temperature is 1500-1700°C, and the annealing time is 5min-20min;

[0023] For the preparation of SiO 2 The substrate region of the isolation layer 3 is subjected to the steps of photoresist spin coating, pre-baking, exposure, development and post-baking to form SiO 2 The photolithography pattern of the isolation layer 3; SiO is prepared on the substrate 1 by the CVD method 2 After the layer is formed, the remaining photoresist on the surface is removed to obtain SiO 2 Isolation layer 3 (see attached Figure 4 and the accompanying drawings), with a thickness of 10 to 20 nm, for isolation preparation of the PMOS and NMOS devices to be prepared subsequently;

[0024] For the substrate region used to prepare the nitrogen-polar PMOS, the nitrogen-polar AlN buffer layer 5 is prepared by the MOCVD method, the growth temperature is 1100-1200°C, the growth pressure is 100-400 mbar, the reaction chamber V / III ratio is 6000-12000, the thickness is 100-200 nm, and the growth source is trimethylaluminum and high-purity ammonia; while preparing the nitrogen-polar AlN buffer layer 5, a metal-polar AlN buffer layer 4 is epitaxially formed on the metal-polar AlN preparation layer 2 (see attached Figure 5 and the accompanying drawings); continuing to use the MOCVD method to sequentially epitaxially form a metal polarity high-resistance GaN layer 6 and a nitrogen polarity high-resistance GaN layer 7, a metal polarity GaN channel layer 10 and a nitrogen polarity GaN channel layer 11, a metal polarity AlGaN barrier layer 8 and a nitrogen polarity AlGaN barrier layer 9, a metal polarity polarization inducing layer 12 and a nitrogen polarity polarization inducing layer 13 on the metal polarity AlN buffer layer 4 and the nitrogen polarity AlN buffer layer 5; wherein the metal polarity AlN buffer layer 4 and the nitrogen polarity AlN buffer layer 5 The growth temperature is 1100-1200°C, the growth pressure is 100-400 mbar, the reaction chamber V / III ratio is 6000-12000, the thickness is 100-200 nm, and the growth source is trimethyl aluminum and high-purity ammonia; the growth temperature of the metal polarity high-resistance GaN layer 6 and the nitrogen polarity high-resistance GaN layer 7 is 1000-1100°C, the growth pressure is 100-400 mbar, the thickness is 1000-2000 nm, the growth source is trimethyl gallium and high-purity ammonia, and the doping source is Cp 2 Fe, doping concentration is 10 17 ~10 20 / cm 3The growth temperature of the metal polarity GaN channel layer 10 and the nitrogen polarity GaN channel layer 11 is 1000-1100°C, the growth pressure is 100-400 mbar, the thickness is 20-30 nm, and the growth sources are trimethyl gallium and high-purity ammonia; the growth temperature of the metal polarity AlGaN barrier layer 8 and the nitrogen polarity AlGaN barrier layer 9 is 1100-1250°C, the growth pressure is 100-400 mbar, the thickness is 15-30 nm, the Al component is 15%-40%, and the growth sources are trimethyl aluminum, trimethyl gallium and high-purity ammonia. The Al component can be adjusted by adjusting the flow rate of the three growth sources. Control; the growth temperature of the metal polarity polarization induction layer 12 and the nitrogen polarity polarization induction layer 13 is 600-800°C, the growth pressure is 100-400mbar, the thickness is 50-150nm, the growth source is trimethylindium, triethylgallium and high-purity ammonia, and the component gradient can be achieved by gradually changing the source flow or growth temperature during the growth process. For example, the linear increase of the In component can be achieved by linearly increasing the trimethylindium flow (or linearly reducing the growth temperature) during the growth process; conversely, the linear reduction of the In component can be achieved by linearly reducing the trimethylindium flow (or linearly increasing the growth temperature) during the growth process;

[0025] Separate SiN layers are prepared on the metal polarization inducing layer 12 and the nitrogen polarization inducing layer 13 by using a CVD method. x The passivation layer 14 has a thickness of 50 to 100 nm. The discrete SiN x The passivation layer 14 is etched along the respective middle regions to the surfaces of the metal polarity AlGaN barrier layer 8 and the nitrogen polarity AlGaN barrier layer 9 to obtain metal polarity NMOS gate electrode grooves and nitrogen polarity PMOS gate electrode grooves; the CVD method is used to separate the etched SiN x A separate insulating layer 15 is prepared on the passivation layer 14, the metal polarity NMOS gate electrode groove and the nitrogen polarity PMOS gate electrode groove structure. The insulating layer 15 has a thickness of 10 to 50 nm and can be made of SiO 2 or Al 2 O 3The invention discloses a method for preparing an NMOS gate electrode 21 (with a thickness of 150 to 300 nm) in the NMOS gate electrode groove by using a CVD method and combining photolithography technology. The material of the NMOS gate electrode 21 can be a single layer material such as Au, Ti, Ni, or a binary alloy composite material such as Ti-Al, Ti-Au, or Ni-Au. The invention discloses a method for preparing an NMOS gate electrode 21 (with a thickness of 150 to 300 nm) in the NMOS gate electrode groove by using a CVD method and combining photolithography technology. The material of the PMOS gate electrode 20 can be a binary alloy composite material such as Ti-Al, Ti-Au, or a ternary alloy composite material such as Ti-Al-Ni, Ti-Al-Au, or Ti-Ni-Ni. The material of the PMOS gate electrode 20 can be a quaternary composite material such as Ti-Al-Ni-Au. The ICP method and combining photolithography technology are used to separate the insulating layer 15 and the SiN x The passivation layer 14 is etched along the left and right end regions to the surfaces of the metal polarization inducing layer 12 and the nitrogen polarization inducing layer 13 to obtain NMOS source electrode grooves, NMOS drain electrode grooves and PMOS source electrode grooves, PMOS drain electrode grooves; the NMOS source electrode 18 and the NMOS drain electrode 19 (thickness 50-200nm) are prepared in the NMOS source electrode groove and the NMOS drain electrode groove respectively by the CVD method, and the materials of the NMOS source electrode 18 and the NMOS drain electrode 19 can be binary alloy composite materials such as Ti-Al and Ti-Au, ternary alloy composite materials such as Ti-Al-Ni, Ti-Al-Au, Ti-Ni-Ni, and quaternary composite materials such as Ti-Al-Ni-Au; the PMOS source electrode 16 and the PMOS drain electrode 17 (thickness 50-200nm) are prepared in the PMOS source electrode groove and the PMOS drain electrode groove respectively by the CVD method, and the materials of the PMOS source electrode 16 and the PMOS drain electrode 17 can be alloy composite materials such as Ni-Al and Ni-Au.

[0026] Effects and benefits of the present invention:

[0027] (1) Compared with the method of using traditional discrete devices to form a CMOS drive circuit, the present invention reduces the system volume and the complexity of system design by integrating PMOS and NMOS on a single chip, reduces the parasitic effects between different devices, and improves the efficiency of the circuit system;

[0028] (2) The present invention can obtain PMOS and NMOS structures by epitaxy at one time by synchronously growing metal polarity and nitrogen polarity devices, without the need for additional device etching, thereby reducing the process flow and cost.

[0029] (3) The in-situ epitaxial growth of metal-polar and nitrogen-polar structures on a single chip is achieved through the method of pre-sputtering and selective growth, which reduces the epitaxial growth cycle and avoids the adverse effects of secondary epitaxy. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 : Schematic diagram of the structure of the GaN-based CMOS device combining the metal polarity PMOS and the nitrogen polarity NMOS described in the present invention.

[0031] Figure 2 : Schematic diagram of the structure of the GaN-based CMOS device combining the metal polarity NMOS and the nitrogen polarity PMOS described in the present invention.

[0032] Figure 3 : Schematic diagram of the preparation of the metal polarity AlN preparation layer of the GaN-based CMOS device combining the metal polarity PMOS and the nitrogen polarity NMOS (GaN-based CMOS device combining the metal polarity NMOS and the nitrogen polarity PMOS) of the present invention.

[0033] Figure 4 : Schematic diagram of the preparation of the isolation layer of the GaN-based CMOS device combining the metal polarity PMOS and the nitrogen polarity NMOS (GaN-based CMOS device combining the metal polarity NMOS and the nitrogen polarity PMOS) of the present invention.

[0034] Figure 5 : Schematic diagram of the preparation of the metal polarity AlN buffer layer and the nitrogen polarity AlN buffer layer of the GaN-based CMOS device combining the metal polarity PMOS and the nitrogen polarity NMOS (GaN-based CMOS device combining the metal polarity NMOS and the nitrogen polarity PMOS) of the present invention.

[0035] Figure 6 : Schematic diagram of the preparation of PMOS gate electrode groove and NMOS gate electrode groove of the GaN-based CMOS device combining metal polarity PMOS and nitrogen polarity NMOS described in the present invention.

[0036] Figure 7 : Schematic diagram of the preparation of the PMOS source electrode groove, PMOS drain electrode groove and NMOS source electrode groove, NMOS drain electrode groove of the GaN-based CMOS device combining the metal polarity PMOS and the nitrogen polarity NMOS according to the present invention.

[0037] Figure 8 : Schematic diagram of the preparation of the insulating layer of the GaN-based CMOS device combining the metal polarity PMOS and the nitrogen polarity NMOS described in the present invention.

[0038] Fig. 9: The valence band structure near the heterojunction interface of (a) the GaN channel layer / AlGaN barrier layer of the metal polarity PMOS device and (b) the conduction band structure near the heterojunction interface of the GaN channel layer / AlGaN barrier layer of the nitrogen polarity NMOS device in the device prepared in Example 1 obtained by simulation using Crosslight's Advanced Physical Models of Semiconductor Devices (APSYS) software.

[0039] Fig.10 : The hole concentration near the heterojunction interface of (a) the GaN channel layer / AlGaN barrier layer of the metal polarity PMOS device and the electron concentration near the heterojunction interface of (b) the GaN channel layer / AlGaN barrier layer of the nitrogen polarity NMOS device in the device prepared in Example 1 obtained by APSYS software simulation.

[0040] Fig.11 : Output characteristic curves of (a) metal polarity PMOS and (b) nitrogen polarity NMOS devices in the device prepared in Example 1 obtained by APSYS software simulation.

[0041] Fig.12 : The valence band structure of (a) the nitrogen-polarity PMOS device AlGaN barrier layer / GaN channel layer heterojunction interface and (b) the conduction band structure of the metal-polarity NMOS device AlGaN barrier layer / GaN channel layer heterojunction interface in the device prepared in Example 2 obtained by APSYS software simulation.

[0042] Fig.13 : The hole concentration near the heterojunction interface of (a) the AlGaN barrier layer / GaN channel layer of the nitrogen-polar PMOS device and the electron concentration near the heterojunction interface of (b) the AlGaN barrier layer / GaN channel layer of the metal-polar NMOS device in the device prepared in Example 2 obtained by simulation with APSYS software.

[0043] Fig.14 : Output characteristic curves of (a) nitrogen polarity PMOS and (b) metal polarity NMOS devices in the device prepared in Example 2 obtained by APSYS software simulation.

[0044] Markings in the figure: 1 is the substrate, 2 is the metal polarity AlN preparation layer, 3 is the isolation layer, 4 is the metal polarity AlN buffer layer, 5 is the nitrogen polarity AlN buffer layer, 6 is the metal polarity high resistance GaN layer, 7 is the nitrogen polarity high resistance GaN layer, 8 is the metal polarity AlGaN barrier layer, 9 is the nitrogen polarity AlGaN barrier layer, 10 is the metal polarity GaN channel layer, 11 is the nitrogen polarity GaN channel layer, 12 is the metal polarity polarization inducing layer, 13 is the nitrogen polarity polarization inducing layer, 14 is the passivation layer, 15 is the insulating layer, 16 is the PMOS source electrode, 17 is the PMOS drain electrode, 18 is the NMOS source electrode, 19 is the NMOS drain electrode, 20 is the PMOS gate electrode, and 21 is the NMOS gate electrode. DETAILED DESCRIPTION

[0045] The specific embodiments of the present invention are described in detail below in combination with the technical solutions and the accompanying drawings.

[0046] Embodiment 1:

[0047] like Figure 1 As shown, a method for preparing a GaN-based CMOS device combining a metal polarity PMOS and a nitrogen polarity NMOS is shown, and the specific steps are: a 2° beveled (0001) surface sapphire substrate 1 is ultrasonically cleaned for 5 minutes by toluene, acetone, ethanol and deionized water respectively, and then the substrate is blown dry with a nitrogen gun. The substrate 1 is divided into three areas, one area is used to prepare the metal polarity PMOS, and the other area is used to prepare the SiO 2 Isolation layer 3, a region for preparing nitrogen polarity NMOS;

[0048] 1. Prepare metal polar device patterns on a 2° beveled (0001) sapphire substrate by photolithography. Prepare a 100nm metal polar AlN preparation layer 2 by sputtering on the photolithography pattern using a magnetron sputtering method. A nitrogen atmosphere is used during the sputtering process. The sputtering target material is an Al target material. The sputtering temperature is 600°C and the pressure is 100mbar. Anneal the metal polar AlN preparation layer 2 at 1500°C for 10 minutes. Prepare an isolation layer pattern on a sapphire substrate by photolithography. Combine photolithography with plasma enhanced chemical vapor deposition (PECVD) to deposit SiO on the isolation layer pattern. 2 Isolation layer 3, SiH 4As Si source, the flow rate is 15μmol / min; oxygen is used as O source, the flow rate is 1.5μmol / min; during the deposition process, the pressure is 100mbar, the temperature is 250℃, and the thickness is 15nm. Metal polarity PMOS and nitrogen polarity NMOS structures are epitaxially prepared on the metal polarity AlN preparation layer 2 and the remaining sapphire substrate, respectively. The specific structure is as follows: on the metal polarity AlN preparation layer 2, a metal polarity AlN buffer layer 4 (thickness is 100nm), a metal polarity high resistance GaN layer 6 (thickness is 1500nm, Fe doping concentration is 1×10 18 / cm 3 , the sheet resistance is 1×10 9 Ω / □), metal polarity AlGaN barrier layer 8 (Al composition is 0.3, thickness is 30nm, undoped), metal polarity GaN channel layer 10 (thickness is 30nm, undoped) and metal polarity polarization inducing layer 12 (In x Ga 1-x The In component in N is from x 1 =0 linear gradient to x 2 =0.2, thickness is 100nm, during the growth process, the flow rate of ammonia and triethylgallium is kept constant, the flow rate of trimethylindium source is linearly increased from 0μmol / min to 12.7μmol / min, and the growth time is 1800s); at the same time, a nitrogen-polar AlN buffer layer 5 (thickness is 100nm), a nitrogen-polar high-resistance GaN layer 7 (thickness is 1500nm, Fe doping concentration is 1×10 18 / cm 3 , the sheet resistance is 1×10 9 Ω / □), nitrogen-polar AlGaN barrier layer 9 (Al composition is 0.3, thickness is 30nm, undoped), nitrogen-polar GaN channel layer 11 (thickness is 30nm, undoped) and nitrogen-polar polarization inducing layer 13 (In x Ga 1-x The In component in N is from x 1 =0 linear gradient to x 2 =0.2, thickness is 100 nm, during the growth process, the flow rate of ammonia and triethylgallium is kept constant, the flow rate of trimethylindium source is linearly increased from 0 μmol / min to 12.7 μmol / min, and the growth time is 1800 s). The specific growth parameters of each layer of the device are shown in Table 1.

[0049] Table 1 Growth parameters of each epitaxial layer grown by MOCVD in Example 1

[0050]

[0051]

[0052] Note: TMGa stands for trimethylgallium; TEGa stands for triethylgallium; TMAl stands for trimethylaluminum; TMIn stands for trimethylindium; NH 3 Stands for high-purity ammonia; Cp 2 Fe stands for ferrocene.

[0053] 2. Using the PECVD method to prepare separate SiN on the metal polarization induction layer 12 and the nitrogen polarization induction layer 13 x The passivation layer 14 is deposited using SiH 4 As Si source, the flow rate is 20μmol / min; ammonia is used as N source, the flow rate is 2μmol / min; the pressure during deposition is 100mbar, the temperature is 300℃, and the thickness is 50nm. The metal polarity PMOS gate electrode groove and the nitrogen polarity NMOS gate electrode groove are obtained by etching from the passivation layer 14 to the metal polarity GaN channel layer 10 and the nitrogen polarity GaN channel layer 11 by photolithography combined with ICP method (boron chloride and chlorine with a gas flow ratio of 1:9, and the plate power is 100W); SiO is prepared on the metal polarity PMOS and nitrogen polarity NMOS structures by PECVD method. 2Insulating layer 15 (thickness 50nm, preparation conditions are the same as those of isolation layer 3). Electron beam evaporation is used to prepare metal polarity PMOS gate electrode 20 in the metal polarity PMOS gate electrode groove (electrode structure is Ti / Al / Ni / Au, thickness of each layer is 40nm, 150nm, 20nm, 50nm, evaporation sources are Ti metal, Al metal, Ni metal and Au metal). Electron beam evaporation is used to prepare nitrogen polarity NMOS gate electrode 21 in the nitrogen polarity NMOS gate electrode groove (electrode structure is Ni / Au, thickness of each layer is 20nm and 50nm, evaporation sources are Ni metal and Au metal). By using a photolithography method combined with an ICP method, etching is performed from the insulating layer 15 to the metal polarization inducing layer 12 and the nitrogen polarization inducing layer 13 to obtain a PMOS source electrode groove, a PMOS drain electrode groove, and an NMOS source electrode groove, and an NMOS drain electrode groove; an electron beam evaporation method is used to prepare a PMOS source electrode 16 and a PMOS drain electrode 17 in the PMOS source electrode groove and the PMOS drain electrode groove (the electrode structure is Ni / Au, the thickness of each layer is 25nm and 100nm respectively, and the evaporation sources are Ni metal and Au metal respectively); an NMOS source electrode 18 and an NMOS drain electrode 19 are prepared in the NMOS source electrode groove and the NMOS drain electrode groove (the electrode structure is Ti / Al / Ti / Au, the thickness of each layer is 40nm, 100nm, 20nm, 100nm respectively, and the evaporation sources are Ti metal, Al metal and Au metal respectively), thereby obtaining a GaN-based CMOS device combining a metal polarity PMOS and a nitrogen polarity NMOS. The specific electrode preparation process is shown in Table 2.

[0054] Table 2: Device electrode preparation process parameters

[0055]

[0056] Fig. 9 The valence band structure near the heterojunction interface of (a) the GaN channel layer / AlGaN barrier layer of the PMOS device and the conduction band structure near the heterojunction interface of the GaN channel layer / AlGaN barrier layer of the NMOS device in the device prepared in Example 1 obtained by APSYS simulation.

[0057] Fig.10 The following are the hole concentrations near the heterojunction interface of (a) the GaN channel layer / AlGaN barrier layer of the PMOS device and the electron concentrations near the heterojunction interface of (b) the GaN channel layer / AlGaN barrier layer of the NMOS device in the device prepared in Example 1 obtained by APSYS simulation.

[0058] Combination Fig. 9 and Fig.10It can be seen that the valence band (conduction band) on the GaN side of the PMOS (NMOS) device close to the GaN / AlGaN interface (corresponding to the horizontal axis 0.03μm) forms a triangular potential well caused by the difference in polarization strength and bandgap width of the two materials, thereby generating a high concentration of two-dimensional hole (electron) gas at the interface.

[0059] Fig.11 The output characteristic curves of (a) PMOS and (b) NMOS devices in the device prepared in Example 1 obtained by APSYS simulation. As can be seen from the figure, the output characteristic curves of the two devices have clear linear regions and saturation regions, and the gate voltage can effectively regulate the size of the leakage current, which can achieve a good MOS field effect transistor function. Therefore, after the two devices are integrated on the same substrate to form the CMOS device in Example 1, the expected logic control function can be achieved in the circuit.

[0060] Embodiment 2:

[0061] like Figure 2 As shown in the figure, a method for preparing a GaN-based CMOS device combining a metal polarity NMOS and a nitrogen polarity PMOS is provided. The specific steps are as follows: a 2° beveled (0001) surface sapphire substrate 1 is ultrasonically cleaned for 5 minutes by using toluene, acetone, ethanol and deionized water respectively, and then the substrate is blown dry by a nitrogen gun. The substrate 1 is divided into three regions, one region is used to prepare a metal polarity NMOS, and one region is used to prepare a SiO 2 Isolation layer 3, one area is used to prepare nitrogen polarity PMOS;

[0062] 1. Prepare metal polar device patterns on a 2° beveled (0001) surface sapphire substrate using photolithography technology. Prepare a 100nm metal polar AlN preparation layer 2 on the photolithography pattern by sputtering using a magnetron sputtering method. A nitrogen atmosphere is used during the sputtering process. The sputtering target material is an Al target material. The sputtering temperature is 600°C and the pressure is 100mbar. Anneal the metal polar AlN preparation layer 2 at 1500°C for 10 minutes. Prepare an isolation layer pattern on a sapphire substrate using photolithography technology. Combine photolithography with PECVD method to deposit SiO on the isolation layer pattern. 2 Isolation layer 3, SiH 4As Si source, the flow rate is 15μmol / min; oxygen is used as O source, the flow rate is 1.5μmol / min; during the deposition process, the pressure is 100mbar, the temperature is 250℃, and the thickness is 15nm. Metal polarity NMOS and nitrogen polarity PMOS structures are epitaxially prepared on the metal polarity AlN preparation layer 2 and the remaining sapphire substrate, respectively. The specific structure is as follows: on the metal polarity AlN preparation layer 2, a metal polarity AlN buffer layer 4 (thickness is 100nm), a metal polarity high resistance GaN layer 6 (thickness is 1500nm, Fe doping concentration is 1×10 18 / cm 3 , the sheet resistance is 1×10 9 Ω / □), metal polarity GaN channel layer 10 (thickness 30nm, undoped), metal polarity AlGaN barrier layer 8 (Al composition 0.3, thickness 30nm, undoped) and metal polarity polarization inducing layer 12 (In x Ga 1-x The In component in N is from x 1 =0.2 linear gradient to x 2 =0, thickness is 100nm, the ammonia flow rate and triethylgallium flow rate are kept unchanged during the growth process, the trimethylindium source flow rate is linearly reduced from 12.7μmol / min to 0μmol / min, and the growth time is 1800s); at the same time, a nitrogen-polar AlN buffer layer 5 (thickness is 100nm), a nitrogen-polar high-resistance GaN layer 7 (thickness is 1500nm, Fe doping concentration is 1×10 18 / cm 3 , the sheet resistance is 1×10 9 Ω / □), nitrogen-polar GaN channel layer 11 (thickness 30nm, undoped), nitrogen-polar AlGaN barrier layer 9 (Al composition 0.3, thickness 30nm, undoped) and nitrogen-polar polarization inducing layer 13 (In x Ga 1-x The In component in N is from x 1 =0.2 linear gradient to x 2 =0, thickness is 100nm, during the growth process, the flow rate of ammonia and triethylgallium is kept constant, the flow rate of trimethylindium source is linearly reduced from 12.7μmol / min to 0μmol / min, and the growth time is 1800s). The specific growth parameters of each layer of the device are shown in Table 3.

[0063] Table 3: Growth parameters of each epitaxial layer grown by MOCVD in Example 2

[0064]

[0065]

[0066] Note: TMGa stands for trimethylgallium; TEGa stands for triethylgallium; TMAl stands for trimethylaluminum; TMIn stands for trimethylindium; NH 3 Stands for high-purity ammonia; Cp 2 Fe stands for ferrocene.

[0067] 2. Using the PECVD method to prepare separate SiN on the metal polarization induction layer 12 and the nitrogen polarization induction layer 13 x The passivation layer 14 is deposited using SiH 4 As Si source, the flow rate is 20μmol / min; ammonia is used as N source, the flow rate is 2μmol / min; the pressure during deposition is 100mbar, the temperature is 300℃, and the thickness is 50nm. The passivation layer 14 is etched to the metal polarity AlGaN barrier layer 12 and the nitrogen polarity AlGaN barrier layer 13 by photolithography combined with ICP method (boron chloride and chlorine with a gas flow ratio of 1:9, and the plate power is 100W) to obtain metal polarity NMOS gate electrode grooves and nitrogen polarity PMOS gate electrode grooves; SiO is prepared on the metal polarity NMOS and nitrogen polarity PMOS structures by PECVD method. 2Insulating layer 15 (thickness 50nm, preparation conditions are the same as those of isolation layer 3). Electron beam evaporation is used to prepare a metal polarity NMOS gate electrode 21 in the metal polarity NMOS gate electrode groove (the electrode structure is Ni / Au, the thickness of each layer is 20nm and 50nm respectively, and the evaporation sources are Ni metal and Au metal respectively). Electron beam evaporation is used to prepare a nitrogen polarity PMOS gate electrode 20 in the nitrogen polarity PMOS gate electrode groove (the electrode structure is Ti / Al / Ni / Au, the thickness of each layer is 40nm, 150nm, 20nm, 50nm respectively, and the evaporation sources are Ti metal, Al metal, Ni metal and Au metal respectively). Etching from the insulating layer 15 to the metal polarization inducing layer 12 and the nitrogen polarization inducing layer 13 is performed by a photolithography method combined with an ICP method to obtain an NMOS source electrode groove, an NMOS drain electrode groove, and a PMOS source electrode groove, and a PMOS drain electrode groove; an NMOS source electrode 18 and an NMOS drain electrode 19 are prepared in the NMOS source electrode groove and the NMOS drain electrode groove by an electron beam evaporation method (the electrode structure is Ti / Al / Ti / Au, the thickness of each layer is 40nm, 100nm, 20nm, and 100nm, respectively, and the evaporation sources are Ti metal, Al metal, and Au metal, respectively); a PMOS source electrode 16 and a PMOS drain electrode 17 are prepared in the PMOS source electrode groove and the PMOS drain electrode groove (the electrode structure is Ni / Au, the thickness of each layer is 25nm and 100nm, respectively, and the evaporation sources are Ni metal and Au metal, respectively), thereby obtaining a GaN-based CMOS device combining a metal polarity NMOS and a nitrogen polarity PMOS. The specific electrode preparation process is shown in Table 4.

[0068] Table 4: Device electrode preparation process parameters

[0069]

[0070]

[0071] Fig.12 The valence band structure near the heterojunction interface of (a) the AlGaN barrier layer / GaN channel layer of the PMOS device and the conduction band structure near the heterojunction interface of the AlGaN barrier layer / GaN channel layer of the NMOS device in the device prepared in Example 2 obtained by APSYS simulation.

[0072] Fig.13 The following are the hole concentrations near the heterojunction interface of (a) the AlGaN barrier layer / GaN channel layer of the PMOS device and the electron concentrations near the heterojunction interface of (b) the AlGaN barrier layer / GaN channel layer of the NMOS device in the device prepared in Example 2 obtained by APSYS simulation.

[0073] Combination Fig.12 and Fig.13 It can be seen that the valence band (conduction band) on the GaN side of the PMOS (NMOS) device close to the AlGaN / GaN interface (corresponding to the horizontal axis 0.03μm) forms a triangular potential well caused by the difference in polarization strength and bandgap width of the two materials, thereby generating a high concentration of two-dimensional hole (electron) gas at the interface.

[0074] Fig.14 The output characteristic curves of (a) PMOS and (b) NMOS devices in the device prepared in Example 2 obtained by APSYS simulation. As can be seen from the figure, the output characteristic curves of the two devices have clear linear regions and saturation regions, and the gate voltage can effectively regulate the size of the leakage current, which can achieve a good MOS field effect transistor function. Therefore, after the two devices are integrated on the same substrate to form the CMOS device in Example 2, the expected logic control function can be achieved in the circuit.

Claims

1. A GaN-based CMOS device combining metal polarity and nitrogen polarity, characterized in that: The CMOS device is composed of a metal polarity PMOS device and a nitrogen polarity NMOS device. The metal polarity PMOS device is composed of a substrate (1), a metal polarity AlN preparation layer (2), a metal polarity AlN buffer layer (4), a metal polarity high resistance GaN layer (6), a metal polarity AlGaN barrier layer (8), a metal polarity GaN channel layer (10), a metal polarity polarization induction layer (12) and a passivation layer (14) from bottom to top. The passivation layer (14) and the metal polarity polarization induction layer (12) are etched along the middle region to expose the metal polarity GaN channel layer (10) to form a PMMOS. OS gate electrode groove; preparing an insulating layer (15) on the surface of the etched passivation layer (14) and the exposed surface of the metal polarity GaN channel layer (10); etching the insulating layer (15) and the passivation layer (14) along the left and right end regions to expose the metal polarity polarization induction layer (12) to form a PMOS source electrode groove and a PMOS drain electrode groove; preparing a PMOS source electrode (16) and a PMOS drain electrode (17) in the PMOS source electrode groove and the PMOS drain electrode groove, respectively, and preparing a PMOS gate electrode (20) in the PMOS gate electrode groove; the nitrogen polarity NMOS device structure is changed from The invention is composed of a substrate (1), a nitrogen-polarity AlN buffer layer (5), a nitrogen-polarity high-resistance GaN layer (7), a nitrogen-polarity AlGaN barrier layer (9), a nitrogen-polarity GaN channel layer (11), a nitrogen-polarity polarization induction layer (13), and a passivation layer (14) in order from bottom to top; the passivation layer (14) and the nitrogen-polarity polarization induction layer (13) are etched along the middle region to expose the nitrogen-polarity GaN channel layer (11) and form an NMOS gate electrode groove; an insulating layer (15) is prepared on the surface of the etched passivation layer (14) and the exposed surface of the nitrogen-polarity GaN channel layer (11); the insulating layer (15) and the passivation layer are etched (14) Etching is then performed along the left and right end regions to expose the nitrogen polarity polarization induction layer (13) to form an NMOS source electrode groove and an NMOS drain electrode groove; an NMOS source electrode (18) and an NMOS drain electrode (19) are respectively prepared in the NMOS source electrode groove and the NMOS drain electrode groove, and an NMOS gate electrode (21) is prepared in the NMOS gate electrode groove; the metal polarity PMOS device and the nitrogen polarity NMOS device share the same substrate (1), and their structures are separated by an isolation layer (3); wherein the composition of the metal polarity polarization induction layer (12) of the metal polarity PMOS is gradually changed to In x Ga 1-x The In component x of N changes gradually from x1 to x2 along the epitaxial growth direction, satisfying 0≤x1<x2≤1, and the thickness is 50~150nm; the component of the nitrogen polarity polarization induction layer (13) of the nitrogen polarity NMOS changes gradually from x1 to x2. x Ga 1-x The In component x of N changes gradually from x1 to x2 along the epitaxial growth direction, satisfying 0≤x1<x2≤1, and the thickness is 50~150nm.

2. A GaN-based CMOS device combining metal polarity and nitrogen polarity as claimed in claim 1, characterized in that: The substrate (1) is a sapphire substrate, a carbon-surface SiC substrate or a Si substrate; a metal polarity PMOS structure is obtained on a sapphire substrate, a carbon-surface SiC substrate or a Si substrate that has been pre-sputtered with an AlN buffer layer and annealed at high temperature; and a nitrogen polarity NMOS structure is obtained on a sapphire substrate, a carbon-surface SiC substrate or a Si substrate that has been nitrided with ammonia gas under high temperature and high V / III ratio conditions.

3. A GaN-based CMOS device combining metal polarity and nitrogen polarity as claimed in claim 1, characterized in that: The thickness of the metal polar AlN preparation layer (2) is 10-200 nm, the thickness of the metal polar AlN buffer layer (4) is 100-200 nm; the thickness of the nitrogen polar AlN buffer layer (5) is 100-200 nm; the metal polar high resistance GaN layer (6) and the nitrogen polar high resistance GaN layer (7) are doped with Fe compensation acceptor elements to form high resistance characteristics, and the sheet resistance is 10 5 ~ 10 9 Ω / □, thickness is 1~2 μm; The Al composition of the metal polarity AlGaN barrier layer (8) and the nitrogen polarity AlGaN barrier layer (9) is 15% to 40% and the thickness is 15 to 30 nm; the thickness of the metal polarity GaN channel layer (10) and the nitrogen polarity GaN channel layer (11) is 20 to 30 nm.

4. A GaN-based CMOS device combining metal polarity and nitrogen polarity, characterized in that: The CMOS device is composed of a metal polarity NMOS device and a nitrogen polarity PMOS device. The metal polarity NMOS device is composed of a substrate (1), a metal polarity AlN preparation layer (2), a metal polarity AlN buffer layer (4), a metal polarity high resistance GaN layer (6), a metal polarity GaN channel layer (10), a metal polarity AlGaN barrier layer (8), a metal polarity polarization induction layer (12) and a passivation layer (14) from bottom to top. The passivation layer (14) and the metal polarity polarization induction layer (12) are etched along the middle region to expose the metal polarity AlGaN barrier layer (8), thereby forming a passivation layer. An NMOS gate electrode groove is formed; an insulating layer (15) is prepared on the surface of the etched passivation layer (14) and the exposed metal polarity AlGaN barrier layer (8); the insulating layer (15) and the passivation layer (14) are etched along the left and right end regions to expose the metal polarity polarization induction layer (12) to form an NMOS source electrode groove and an NMOS drain electrode groove; an NMOS source electrode (18) and an NMOS drain electrode (19) are prepared in the NMOS source electrode groove and the NMOS drain electrode groove, and an NMOS gate electrode (21) is prepared in the NMOS gate electrode groove; the nitrogen polarity PMOS device structure is The invention is composed of a substrate (1), a nitrogen-polar AlN buffer layer (5), a nitrogen-polar high-resistance GaN layer (7), a nitrogen-polar GaN channel layer (11), a nitrogen-polar AlGaN barrier layer (9), a nitrogen-polar polarization induction layer (13) and a passivation layer (14) in order from bottom to top; the passivation layer (14) and the nitrogen-polarity polarization induction layer (13) are etched along the middle region to expose the nitrogen-polarity AlGaN barrier layer (9) to form a PMOS gate electrode groove; an insulating layer (15) is prepared on the surface of the etched passivation layer (14) and the exposed nitrogen-polarity AlGaN barrier layer (9); the insulating layer (15) and the passivation layer are etched and the passivation layer (14) is etched and the passivation layer (13) is etched and the passivation layer (14 ... The metal polarity NMOS device and the nitrogen polarity PMOS device share the same substrate (1), and the structures are separated by an isolation layer (3); wherein the composition of the metal polarity polarization induction layer (12) of the metal polarity NMOS is gradually changed to In. x Ga 1-x The In component x of N changes gradually from x1 to x2 along the epitaxial growth direction, satisfying 1≥x1>x2≥0, and the thickness is 50~150nm; the component of the nitrogen polarity polarization induction layer (13) of the nitrogen polarity PMOS changes gradually from x1 to x2 x Ga 1-x The In component x of N changes gradually from x1 to x2 along the epitaxial growth direction, with 1≥x1>x2≥0, and the thickness is 50~150nm.

5. A GaN-based CMOS device combining metal polarity and nitrogen polarity as claimed in claim 4, characterized in that: The substrate (1) is a sapphire substrate, a carbon-surface SiC substrate or a Si substrate; a metal polarity NMOS structure is obtained on the sapphire, carbon-surface SiC substrate or Si substrate after a pre-sputtered AlN buffer layer and high-temperature annealing; a nitrogen polarity PMOS structure is obtained on the sapphire, carbon-surface SiC substrate or Si substrate after ammonia nitridation treatment under high temperature and high V / III ratio conditions.

6. A GaN-based CMOS device combining metal polarity and nitrogen polarity as claimed in claim 4, characterized in that: The thickness of the metal polar AlN preparation layer (2) is 10-200 nm, the thickness of the metal polar AlN buffer layer (4) is 100-200 nm; the thickness of the nitrogen polar AlN buffer layer (5) is 100-200 nm; the metal polar high resistance GaN layer (6) and the nitrogen polar high resistance GaN layer (7) are doped with Fe compensation acceptor elements to form high resistance characteristics, and the sheet resistance is 10 5 ~ 10 9 Ω / □, thickness is 1~2 μm; The Al composition of the metal polarity AlGaN barrier layer (8) and the nitrogen polarity AlGaN barrier layer (9) is 15% to 40% and the thickness is 15 to 30 nm; the thickness of the metal polarity GaN channel layer (10) and the nitrogen polarity GaN channel layer (11) is 20 to 30 nm.

7. The method for preparing a GaN-based CMOS device combining metal polarity and nitrogen polarity as claimed in claim 1, wherein the steps are as follows: After the substrate (1) is cleaned, the substrate (1) is divided into three regions, one region is used to prepare a metal polarity PMOS, one region is used to prepare a SiO2 isolation layer (3), and one region is used to prepare a nitrogen polarity NMOS; Performing photoresist spin coating, pre-baking, exposure, development and post-baking operations on a substrate region for preparing a metal polarity PMOS, thereby forming a photolithographic pattern of a metal polarity AlN preparation layer (2) on the substrate (1); After sputtering an AlN layer on a substrate (1) by a magnetron sputtering method, the remaining photoresist on the surface is removed; the sputtered AlN layer is subjected to a high-temperature annealing treatment to prepare a metal polar AlN preparation layer (2); The growth temperature of the metal polar AlN preparation layer (2) is 500-600°C, the growth pressure is 100-400 mbar, the thickness is 10-200 nm, the sputtering uses an Al target, and the gas atmosphere is nitrogen; the annealing temperature is 1500-1700°C, and the annealing time is 5 min-20 min; The substrate region for preparing the SiO2 isolation layer (3) is subjected to the steps of photoresist spin coating, pre-baking, exposure, development and post-baking to form a photolithographic pattern of the SiO2 isolation layer (3) on the substrate (1); after preparing the SiO2 layer on the substrate (1) by chemical vapor deposition, the remaining photoresist on the surface is removed to obtain the SiO2 isolation layer (3) with a thickness of 10 to 20 nm; For the substrate region used to prepare the nitrogen-polar NMOS, a nitrogen-polar AlN buffer layer (5) is prepared by a metal organic compound chemical vapor deposition method, with a growth temperature of 1100-1200° C. and a growth pressure of 100-400° C. mbar, the V / III ratio of the reaction chamber is 6000-12000, the thickness is 100-200nm, and the growth source is trimethylaluminum and high-purity ammonia; while preparing the nitrogen-polar AlN buffer layer (5), epitaxially forming a metal-polar AlN buffer layer (4) on the metal-polar AlN preparation layer (2); continuously epitaxially forming a metal-polar high-resistance GaN layer (6) and a nitrogen-polar high-resistance GaN layer (7), a metal-polar AlGaN barrier layer (8) and a nitrogen-polar AlGaN barrier layer (9), a metal-polar GaN channel layer (10) and a nitrogen-polar GaN channel layer (11), a metal-polar polarization induction layer (12) and a nitrogen-polarity polarization induction layer (13) on the metal-polar AlN buffer layer (4) and the nitrogen-polarity AlN buffer layer (5); wherein the growth temperature of the metal-polar AlN buffer layer (4) and the nitrogen-polarity AlN buffer layer (5) is 1100-1200 ℃, growth pressure 100~400mbar, reaction chamber V / III ratio 6000~12000, thickness 100~200nm, growth source trimethylaluminum and high-purity ammonia; the growth temperature of the metal polar high-resistance GaN layer (6) and the nitrogen polar high-resistance GaN layer (7) is 1000~1100℃, the growth pressure is 100~400mbar, the thickness is 1000~2000nm, the growth source is trimethylgallium and high-purity ammonia, the doping source is ferrocene, the doping concentration is 10 17 ~10 20 / cm 3 ; The growth temperature of the metal polarity AlGaN barrier layer (8) and the nitrogen polarity AlGaN barrier layer (9) is 1100-1250°C, the growth pressure is 100-400 mbar, the thickness is 15-30 nm, the Al component is 15%-40%, the growth sources are trimethylaluminum, trimethylgallium and high-purity ammonia, and the Al component is controlled by adjusting the flow rates of the three growth sources; the growth temperature of the metal polarity GaN channel layer (10) and the nitrogen polarity GaN channel layer (11) is 100 0~1100°C, growth pressure is 100~400mbar, thickness is 20~30nm, and growth sources are trimethylgallium and high-purity ammonia; the growth temperature of the metal polarization induction layer (12) and the nitrogen polarization induction layer (13) is 600~800°C, the growth pressure is 100~400mbar, the thickness is 50~150nm, and the growth sources are trimethylindium, triethylgallium and high-purity ammonia, and the composition gradient is achieved by gradually changing the source flow rate or the growth temperature during the growth process; Separate SiN layers are prepared on the metal polarity polarization inducing layer (12) and the nitrogen polarity polarization inducing layer (13) by using a CVD method. x The passivation layer (14) has a thickness of 50 to 100 nm; the discrete SiN x The passivation layer (14) is etched along the respective middle regions to the surfaces of the metal polarity GaN channel layer (10) and the nitrogen polarity GaN channel layer (11) to obtain a metal polarity PMOS gate electrode groove and a nitrogen polarity NMOS gate electrode groove; a CVD method is used to form a metal polarity PMOS gate electrode groove on the separated etched SiN x A separate insulating layer (15) is prepared on the passivation layer (14), the metal polarity PMOS gate electrode groove and the nitrogen polarity NMOS gate electrode groove structure, the insulating layer (15) has a thickness of 10-50 nm and is made of SiO2 or Al2O3; a PMOS gate electrode (20) is prepared in the PMOS gate electrode groove by using a CVD method and in combination with a photolithography technique, the material of the PMOS gate electrode (20) is one of Ti-Al, Ti-Au, Ti-Al-Ni, Ti-Al-Au, Ti-Ni-Ni, and Ti-Al-Ni-Au quaternary composite materials; an NMOS gate electrode (21) is prepared in the NMOS gate electrode groove by using a CVD method and in combination with a photolithography technique, the thickness of the NMOS gate electrode (21) is 150-300 nm, the material of the NMOS gate electrode (21) is one of Au, Ti, Ni, Ti-Al, Ti-Au, and Ni-Au; an ICP method and in combination with a photolithography technique is used to separate the separate insulating layer (15) and SiN x The passivation layer (14) is etched along the left and right end regions to the surfaces of the metal polarization induction layer (12) and the nitrogen polarization induction layer (13), thereby obtaining a PMOS source electrode groove, a PMOS drain electrode groove, and an NMOS source electrode groove, and an NMOS drain electrode groove; a PMOS source electrode (16) and a PMOS drain electrode (17) are respectively prepared in the PMOS source electrode groove and the PMOS drain electrode groove by a CVD method, with a thickness of 50 to 200 nm, and the material of the PMOS source electrode (16) and the drain electrode (17) is Ni-Al or Ni-Au; and a NMOS source electrode (18) and a NMOS drain electrode (19) are respectively prepared in the NMOS source electrode groove and the NMOS drain electrode groove by a CVD method, with a thickness of 50 to 200 nm, and the material of the NMOS source electrode (18) and the drain electrode (19) is one of Ti-Al, Ti-Au, Ti-Al-Ni, Ti-Al-Au, Ti-Ni-Ni, and Ti-Al-Ni-Au.

8. The method for preparing a GaN-based CMOS device combining metal polarity and nitrogen polarity as claimed in claim 4, wherein the steps are as follows: After the substrate (1) is cleaned, the substrate (1) is divided into three regions, one region for preparing a metal polarity NMOS, one region for preparing a SiO2 isolation layer (3), and one region for preparing a nitrogen polarity PMOS; The substrate region for preparing the metal polarity PMOS is subjected to the steps of photoresist spin coating, pre-baking, exposure, development and post-baking to form a photolithographic pattern of a metal polarity AlN preparation layer (2) on the substrate (1); After sputtering an AlN layer on a substrate (1) by a magnetron sputtering method, the remaining photoresist on the surface is removed; the sputtered AlN layer is subjected to a high-temperature annealing treatment to prepare a metal polar AlN preparation layer (2); The growth temperature of the metal polar AlN preparation layer (2) is 500-600°C, the growth pressure is 100-400 mbar, the thickness is 10-200 nm, the sputtering uses an Al target, and the gas atmosphere is nitrogen; the annealing temperature is 1500-1700°C, and the annealing time is 5 min-20 min; The substrate region for preparing the SiO2 isolation layer (3) is subjected to the steps of photoresist spin coating, pre-baking, exposure, development and post-baking to form a photolithography pattern of the SiO2 isolation layer (3) on the substrate (1); after preparing the SiO2 layer on the substrate (1) by a CVD method, the remaining photoresist on the surface is removed to obtain the SiO2 isolation layer (3) with a thickness of 10 to 20 nm; For a substrate region used to prepare a nitrogen-polarity PMOS, a nitrogen-polarity AlN buffer layer (5) is prepared by an MOCVD method, the growth temperature is 1100-1200°C, the growth pressure is 100-400 mbar, the V / III ratio of the reaction chamber is 6000-12000, the thickness is 100-200 nm, and the growth source is trimethylaluminum and high-purity ammonia. While preparing the nitrogen-polarity AlN buffer layer (5), a metal-polarity AlN buffer layer (4) is epitaxially formed on the metal-polarity AlN preparation layer (2); and the metal-polarity high-carbon AlN buffer layer (4) is epitaxially formed on the metal-polarity AlN buffer layer (4) and the nitrogen-polarity AlN buffer layer (5) in sequence by continuing to use the MOCVD method. The present invention relates to a GaN layer (6) and a nitrogen-polarity high-resistance GaN layer (7), a metal-polarity GaN channel layer (10) and a nitrogen-polarity GaN channel layer (11), a metal-polarity AlGaN barrier layer (8) and a nitrogen-polarity AlGaN barrier layer (9), a metal-polarity polarization induction layer (12) and a nitrogen-polarity polarization induction layer (13); wherein the growth temperature of the metal-polarity AlN buffer layer (4) and the nitrogen-polarity AlN buffer layer (5) is 1100-1200 °C. ℃, growth pressure 100~400 mbar, reaction chamber V / III ratio 6000~12000, thickness 100~200nm, growth source trimethylaluminum and high-purity ammonia; the growth temperature of the metal polar high-resistance GaN layer (6) and the nitrogen polar high-resistance GaN layer (7) is 1000~1100℃, the growth pressure is 100~400 mbar, the thickness is 1000~2000nm, the growth source is trimethylgallium and high-purity ammonia, the doping source is Cp2Fe, the doping concentration is 10 17 ~10 20 / cm 3 ; The growth temperature of the metal polarity GaN channel layer (10) and the nitrogen polarity GaN channel layer (11) is 1000-1100°C, the growth pressure is 100-400 mbar, the thickness is 20-30 nm, and the growth sources are trimethyl gallium and high-purity ammonia; the growth temperature of the metal polarity AlGaN barrier layer (8) and the nitrogen polarity AlGaN barrier layer (9) is 1100-1250°C, the growth pressure is 100-400 mbar, the thickness is 15-30 nm, and the Al component The growth sources are trimethylaluminum, trimethylgallium and high-purity ammonia, and the Al component is controlled by adjusting the flow rates of the three growth sources; the growth temperature of the metal polarization induction layer (12) and the nitrogen polarization induction layer (13) is 600-800°C, the growth pressure is 100-400 mbar, the thickness is 50-150 nm, and the growth sources are trimethylindium, triethylgallium and high-purity ammonia. The component gradient is achieved by gradually changing the source flow rate or the growth temperature during the growth process; Separate SiN layers are prepared on the metal polarity polarization inducing layer (12) and the nitrogen polarity polarization inducing layer (13) by using a CVD method. x The passivation layer (14) has a thickness of 50-100 nm; the discrete SiN x The passivation layer (14) is etched along the respective middle regions to the surfaces of the metal polarity AlGaN barrier layer (8) and the nitrogen polarity AlGaN barrier layer (9) to obtain a metal polarity NMOS gate electrode groove and a nitrogen polarity PMOS gate electrode groove; a CVD method is used to separate the etched SiN x A separate insulating layer (15) is prepared on the passivation layer (14), the metal polarity NMOS gate electrode groove and the nitrogen polarity PMOS gate electrode groove structure, wherein the insulating layer (15) has a thickness of 10-50 nm and is made of SiO2 or Al2O3; a NMOS gate electrode (21) is prepared in the NMOS gate electrode groove by using a CVD method and a photolithography technique, wherein the thickness of the NMOS gate electrode (21) is 150-300 nm, and the material of the NMOS gate electrode (21) is one of Au, Ti, Ni, Ti-Al, Ti-Au or Ni-Au; a PMOS gate electrode (20) is prepared in the PMOS gate electrode groove by using a CVD method and a photolithography technique, wherein the thickness of the PMOS gate electrode (20) is 150-300 nm, and the material of the PMOS gate electrode (20) is one of Ti-Al, Ti-Au, Ti-Al-Ni, Ti-Al-Au, Ti-Ni-Ni or Ti-Al-Ni-Au; an ICP method and a photolithography technique are used to separate the separate insulating layer (15) and SiN x The passivation layer (14) is etched along the left and right end regions to the surfaces of the metal polarization induction layer (12) and the nitrogen polarization induction layer (13) to obtain an NMOS source electrode groove, an NMOS drain electrode groove, and a PMOS source electrode groove, and a PMOS drain electrode groove; a NMOS source electrode (18) and an NMOS drain electrode (19) are respectively prepared in the NMOS source electrode groove and the NMOS drain electrode groove by a CVD method, with a thickness of 50 to 200 nm, and the material of the NMOS source electrode (18) and the NMOS drain electrode (19) is one of Ti-Al, Ti-Au, Ti-Al-Ni, Ti-Al-Au, Ti-Ni-Ni or Ti-Al-Ni-Au; a PMOS source electrode (16) and a PMOS drain electrode (17) are respectively prepared in the PMOS source electrode groove and the PMOS drain electrode groove by a CVD method, with a thickness of 50 to 200 nm, and the material of the PMOS source electrode 16 and the PMOS drain electrode 17 is Ni-Al or Ni-Au.

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