A method for controlling optical transmission delay of radio frequency signals

Abstract

The present application relates to the field of optical fiber communication technology, and particularly relates to a radio frequency signal optical transmission delay control method, transmitter parameters are set by a transmitter, receiver parameters are set by a receiver; the transmitter sends a PPS measurement pulse to the receiver after starting up; the receiver carries out delay measurement on the PPS measurement pulse, and carries out arithmetic average to obtain a delay value; the FIFO reading pointer is adjusted based on the delay value, and the PPS measurement pulse signal is switched to a transmission radio frequency signal, so that radio frequency signal transmission delay is stabilized; the method transmits a PPS pulse before transmitting a radio frequency signal, measures the delay value of the transmitted PPS pulse relative to a local PPS pulse at the receiver, then adjusts the reading position of the receiver FIFO, so that the radio frequency transmission delay is adjusted to a set value, the purpose of adjusting the radio frequency transmission delay is achieved, the method is suitable for a radio frequency signal digital optical fiber transmission system, has good versatility, can automatically adjust the radio frequency signal transmission delay, and ensures the stability of the radio frequency signal transmission delay.

Description

Technical Field

[0001] This invention relates to the field of optical fiber communication technology, and in particular to a method for controlling the optical transmission delay of radio frequency signals. Background Technology

[0002] In a radio frequency signal fiber optic transmission system, transceiver equipment is installed at different transmission nodes to complete the sending and receiving of service signals.

[0003] In an analog fiber optic transmission system for radio frequency (RF) signals, the transmission link consists of amplifiers, electro-optical conversion lasers, optical-to-electrical conversion detectors, and optical cables. At the transmitter, the analog RF signal is converted into an optical signal by the laser and output, then transmitted through the optical fiber to the receiver. The receiver's photodetector converts the input optical signal back into an electrical signal, recovering the analog RF signal. No digital signal processing is performed during the entire transmission process. The RF signal transmission delay is determined by the physical characteristics of the transmission link components and depends on their operational stability. Under current manufacturing technology, the transmission delay stability of analog RF signals can reach the picosecond (ps) level.

[0004] In a digital fiber optic transmission system for radio frequency (RF) signals, the transmitter first performs analog-to-digital sampling to convert the analog RF signal into a digital signal. Then, it undergoes digital signal processing (including digital down-conversion, interpolation filtering, JESD204B encoding / decoding, insertion of time stamp data, multiplexing of high-speed data, and data line encoding) to package it into a high-speed digital signal. This signal is then converted into an optical signal by a digital optical module and transmitted via fiber optic cable to the receiver. The receiver's optical receiving module converts the input optical signal into a high-speed digital electrical signal, and performs further digital signal processing (data line decoding, high-speed data demultiplexing, extraction of time stamp data, RF sampling data, interpolation filtering, and digital up / down conversion). Finally, a DAC circuit converts the digital signal back into an analog RF signal for output. During transmission, the RF signal transmission delay varies depending on the initial state of the digital signal processing. Actual measurements show that after multiple power-on / off cycles, the maximum variation in RF delay is approximately 40ns, indicating a transmission delay stability of 40ns.

[0005] In radar systems, the transmission delay of radio frequency (RF) signals is related to the distance to the target being measured; good transmission delay stability results in high accuracy of the target distance. The noise figure (NF) of RF signal transmission via digital fiber optics is independent of the transmission distance, allowing for longer transmission distances compared to analog fiber optic transmission. To address the requirements for long-distance RF signal transmission, it is necessary to develop a circuit and method for controlling the transmission delay of RF signal data optical signals, thereby meeting the stability requirements of RF signal transmission delay. Summary of the Invention

[0006] The purpose of this invention is to provide a method for controlling the optical transmission delay of radio frequency signals, and to develop a circuit and method for controlling the optical transmission delay of radio frequency signals to meet the stability requirements of radio frequency signal transmission delay.

[0007] To achieve the above objectives, the present invention provides a method for controlling the optical transmission delay of radio frequency signals, comprising the following steps:

[0008] The transmitter parameters are set via the transmitter, and the receiver parameters are set via the receiver.

[0009] The transmitter is powered on and sends a PPS measurement pulse to the receiver;

[0010] The receiver measures the delay of the PPS measurement pulse and performs an arithmetic average to obtain the delay value.

[0011] The FIFO read pointer is adjusted based on the delay value, and the PPS measurement pulse signal is switched to a transmission radio frequency signal to achieve stable radio frequency signal transmission delay.

[0012] The transmitter includes an ADC module, a first FPGA module, an electro-optical conversion module, a first filter, and a first frequency synthesizer module. The first frequency synthesizer module is connected to both the ADC module and the first FPGA module. The filter is connected to both the ADC module and the first FPGA module. The electro-optical conversion module is connected to the first FPGA module.

[0013] The receiver includes an optical-to-electric conversion module, a second FPGA module, a DAC module, a second filter, a detection module, a shaping module, and a second frequency synthesizer module. The optical-to-electric conversion module is connected to the second FPGA module. The second FPGA module is connected to the shaping module, the second frequency synthesizer module, and the DAC module. The DAC module is connected to the second FPGA module, the second frequency synthesizer module, and the second filter. The detection module is connected to the second filter and the shaping module.

[0014] The transmitter parameter settings include ADC module parameter settings, first FPGA module parameter settings, electro-optical conversion module parameter settings, and first frequency synthesizer module parameters.

[0015] The receiver parameters include the settings for the second frequency synthesis module, the optical-to-electrical conversion module, the detection module, and the shaping module.

[0016] This invention discloses a method for controlling the optical transmission delay of radio frequency (RF) signals. The method involves setting transmitter parameters and receiver parameters; the transmitter, upon power-on, sends a PPS (Programmable Spectrum) measurement pulse to the receiver; the receiver measures the delay of the PPS measurement pulse and performs an arithmetic average to obtain a delay value; based on the delay value, the FIFO readout pointer is adjusted, and the PPS measurement pulse signal is switched to transmit an RF signal, thereby stabilizing the RF signal transmission delay. This method transmits a PPS pulse before transmitting the RF signal, measures the delay of the transmitted PPS pulse relative to the local PPS pulse at the receiver, and then adjusts the FIFO readout position to adjust the RF transmission delay to the set value, achieving the purpose of adjusting the RF transmission delay. It is applicable to digital fiber optic transmission systems for RF signals, has good versatility, can automatically adjust the RF signal transmission delay, maintains a transmission delay stability of ≤5ns, ensures stable RF signal transmission delay, is simple to set up, has good maintainability, and is simple and practical. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a connection diagram of a radio frequency signal optical transmission delay control system provided by the present invention.

[0019] Figure 2 This is a schematic diagram of the working process of the optical transmitter of the present invention.

[0020] Figure 3 This is a schematic diagram of receiver FIFO delay adjustment.

[0021] Figure 4 This is a flowchart of the receiver's workflow.

[0022] Figure 5 This is a flowchart of a radio frequency signal optical transmission delay control method provided by the present invention. Detailed Implementation

[0023] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0024] Please see Figures 1 to 5This invention provides a method for controlling the optical transmission delay of radio frequency signals, comprising the following steps:

[0025] S1 sets the transmitter parameters via the transmitter and the receiver parameters via the receiver;

[0026] Specifically, the transmitter includes an ADC module, a first FPGA module (FPGA module 1), an electro-optical conversion module (FPGA module 1), a first filter (filter 1), and a first frequency synthesizer module (frequency synthesizer module 1). ADC module CH1 is connected to the output of filter 1, CH2 is connected to the external RF signal input, ADCCLK is connected to frequency synthesizer module 1, and the output of the ADC module is connected to FPGA module 1. FPGA module 1 is connected to the SPI, 250MHz clock, input of filter 1, and external PPST input of frequency synthesizer module 1. The GTX output of FPGA module 1 is connected to the input of the electro-optical conversion module. The input of filter 1 is connected to FPGA module 1, and its output is connected to the input of ADC module CH1. The input of the electro-optical conversion module is connected to the GTX output of FPGA module 1, and its output is connected to an external transmission optical cable. The input of frequency synthesizer module 1 is connected to an external 100MHz reference clock T, and its outputs are connected to the ADC module and FPGA module 1, respectively.

[0027] The receiver includes an optical-to-electric conversion module (optical-to-electric conversion module 2), a second FPGA module (FPGA module 2), a DAC module, a second filter (filter 2), a detection module, a shaping module, and a second frequency synthesizer module (second frequency synthesizer module). The input of the optical-to-electric conversion module is connected to an external optical cable, and the output is connected to the GTX input of the FPGA module 2. The FPGA module 2 is also connected to the SPI and 250MHz clock of the DAC module and the frequency synthesizer module 2. The data input of the DAC module is connected to the FPGA module 2, CH1 is connected to the input of the filter 2, and CH2 outputs radio frequency signals to the outside. The output of the filter 2 is connected to the input of the detection module, and the output of the detection module is connected to the input of the shaping module.

[0028] The ADC module is a dual-channel TXADC with a resolution of 14 bits, a maximum sampling frequency of 1.25 GHz, a full-power bandwidth of 2 GHz for analog input, and JESD204B (subtype) encoded serial digital output. The FPGA modules 1 and 2 use XC7K325T-2FFG900 as their main chip. Filters 1 and 2 are DC-475 MHz low-pass filters with a passband ripple of 0.5 dB, insertion loss ≤1.0 dB, and a rectangular coefficient of 1.25 for the -0.5 dB / -60 dB frequency bandwidth. The frequency synthesizer module is a ZERO DELAY phase-locked loop module with a reference frequency input range of DC-250 MHz, input levels of CMOS, LVDS, or LVPECL, and output levels of CMOS or LVPECL. The output frequency range is 0-1.5 GHz, with 12 output channels, output jitter ≤225 fs, and inter-channel output delay error ≤16 ps.

[0029] The electro-optical conversion module and the optical-electrical conversion module are DWDM CH34 channel standard wavelength (1550.12nm), with 1 channel, output optical power of -5dBm to 0dBm, receiving sensitivity ≤ -24dBm, saturated receiving power ≥ 0dBm, transmission data rate ≤ 11.3Gb / s, and maximum transmission distance of 100km.

[0030] The DAC module is a dual-channel TxDAC with a resolution of 16-bit, a conversion rate of 1600Mb / s, and selectable digital interpolation filters of no / 2X / 4X / 8X / 16V. The inherent delay difference of the TxDAC conversion is ≤2 DACCLK cycles.

[0031] The detection module is a microwave detector with an input frequency range of 0.01 to 4 GHz, in-band ripple ≤ ±0.3 dB, and low-level sensitivity (at -30 dBm) ≥ 0.5 mV.

[0032] The shaping module is a limiting amplifier with a -3dB frequency bandwidth of 500MHz, a gain of 20dB, an output level of 0-4V, and a rise rate of 1350V / us.

[0033] The parameter settings are as follows: For the transmitter's ADC module, the sampling clock ADCCLK frequency is 1000MHz, CH1 input is the PPS measurement pulse 1, CH2 input frequency range is 275MHz~475MHz with a maximum input level of +8dBm, and the output data is zero RF IQ data in JESD204B format. For the transmitter's first FPGA module, the data multiplexing / demultiplexing clock is 250MHz, PPST is the second pulse provided by the BeiDou system equipment, the PPS measurement pulse is the AND operation of PPST and a 300MHz clock, the output level is 2.5V CMOS level, and the GTX output data rate is 10Gb / s. For the transmitter's electro-optical conversion module, the output wavelength is 1550.12nm DWDM, the output optical power is 0~+2dBm, and the number of output channels is 1. For the transmitter and receiver's first frequency synthesizer module, the 100MHz clock T is the reference clock for the frequency synthesizer module, provided by the BeiDou system equipment, and the frequency synthesizer module uses a zero-delay PLL to generate ADCCLK and a 250MHz synchronization clock. The receiver's optical / electrical conversion module is configured with an input wavelength of 1550.12nm DWDM, an input optical power range of -24 to +1dBm, and one input channel. The receiver's FPGA module 2 is configured with a data multiplexing / demultiplexing clock of 250MHz, PPSR (Pulse Per Second) provided by the BeiDou system equipment, PPS measurement pulse 2 (recovered PPS measurement pulse from the transmitter), a GTX data rate of 10Gb / s, and the IQ data output from the FPGA module 2 to the DAC module is 16-bit wide, 250MHz zero-RF IQ data. The receiver's detection module is configured to use a microwave detector with DC-blocked input, a signal of 2Vp-p amplitude modulated at a 300MHz PPS measurement pulse, and a PPS pulse amplitude of 0–0.6V at the detector output. The receiver's shaping module is configured with an input PPS measurement pulse detector signal amplitude of 0–0.6V, and an output PPS measurement pulse 2 level of 0–4V with a rise rate of 1350V / µs. Filter 1 and Filter 2 settings: DC~475MHz low-pass filter, in-band ripple ≤0.5dB, insertion loss ≤1dB, input and output impedance 50 ohms, -60dB / -0.5dB frequency rectangularity factor 1.25.

[0034] S2 The transmitter is powered on and sends a PPS measurement pulse to the receiver;

[0035] Specifically, when the transmitter is powered on, it first continuously sends 10 seconds of PPS measurement pulses to the receiver.

[0036] The receiver in S3 performs a delay measurement on the PPS measurement pulse and performs an arithmetic average to obtain the delay value;

[0037] Specifically, the receiver uses the local PPS pulse as a reference to measure the delay of each received PPS measurement pulse, and then selects the six data with the closest delay values ​​to perform an arithmetic average. This average value is used as the delay value of the transmission link.

[0038] Link delay measurement

[0039] Upon power-on, the first frequency synthesizer module performs zero-delay synchronous phase-locked frequency multiplication on the externally input 100MHz reference, generating a 1GHz sampling clock (ADCCLK), a 1GHz conversion clock (DACCLK), and a 250MHz FPGA data processing clock that have a fixed phase relationship with the 100MHz reference.

[0040] When the transmitter is powered on, FPGA module 1 generates a 300MHz clock from the input 250MHz clock. Then, the 300MHz clock is ANDed with the externally input PPST pulse to obtain the PPS measurement pulse, which is a 300MHz FSK modulated signal with a period of 1 second.

[0041] Then, the PPS measurement pulse is input to CH1 of the ADC module for analog-to-digital conversion, which converts it into high-speed ADC data. After 375MHz downconversion and 4X interpolation filtering, it is converted into zero-IF IQ data, which is then transmitted to FPGA module 1 through the JESD204B high-speed interface.

[0042] FPGA module 1 decodes and multiplexes the JESD204B data sent by the ADC module, and converts it into a high-speed data stream after 8B10B encoding. The data is then output to the electro-optical conversion module using the GTX high-speed circuit.

[0043] The electro-optical conversion module converts the high-speed data stream into a single-mode optical signal with a wavelength of 1550nm. It is then transmitted through an optical fiber cable.

[0044] The second optical / electric receiving module performs photoelectric conversion on the input optical signal to recover the high-speed data stream electrical signal, and inputs it to FPGA module 2 through a differential circuit.

[0045] FPGA module 2 receives high-speed signals via the GTX interface, decodes them, recovers the IQ data, and then outputs it to the DAC module.

[0046] The DAC module performs interpolation filtering and digital quadrature upconversion on the input IQ data to convert the baseband signal into a 375MHz digital radio frequency signal. Then, the DAC module performs digital-to-analog conversion to output a PPS measurement pulse analog signal.

[0047] The PPS measurement pulse analog signal is filtered out by filter 2 to remove the image, and then input into the detection module for amplitude detection to recover the PPS pulse signal. After being shaped by the shaping module, the PPS measurement pulse is recovered.

[0048] PPS measurement pulse 2 is input to FPGA module 2 to perform delay measurement using the local PPSR pulse as the time reference. The transmitter sends PPS measurement pulse 1 for 10 seconds, sending a total of 10 PPS measurement pulses. The receiver measures the delay value of each pulse, and then selects the 6 delay values ​​with the closest delay values ​​and performs a mathematical average as the transmission delay value (Tpf) for this power-on.

[0049] The maximum distance between the transmitting and receiving stations (100km) is set with a delay value Tpf0 of 800us.

[0050] S4 adjusts the FIFO read pointer based on the delay value and switches the PPS measurement pulse signal to a transmission radio frequency signal to achieve stable radio frequency signal transmission delay.

[0051] Specifically, based on the calculated delay value, the FIFO read pointer of FPGA module 2 is adjusted to ensure that the delay after the IQ data output to the DAC module is converted into an RF signal meets the requirements. Then, the transmitter switches from transmitting the PPS measurement pulse signal to transmitting the RF signal, thus stabilizing the RF signal transmission delay. The 100MHz reference clock and PPS signal used by the device are both synchronous coherent signals provided by the BeiDou timing equipment.

[0052] Delay adjustment:

[0053] The required delay time ΔT = 800us - Tpf is adjusted. The FIFO read pointer of FPGA module 2 is adjusted according to ΔT to delay the link transmission to the set value.

[0054] Stop the PPS measurement pulse sampling of the ADC module, start the RF signal analog-to-digital sampling of the CH2 ADC module, convert it into high-speed RF ADC data, and then use the high-speed RF data to replace the high-speed PPS measurement pulse data for processing. The processing process is the same as the transmission and processing process of the PPS measurement pulse. Finally, the DAC module converts and outputs the RF analog signal.

[0055] Before FIFO adjustment, the delay Tpf of PPS measurement pulse 2 relative to PPSR is measured. Based on this measurement, the FIFO read pointer of FPGA module 2 is adjusted to delay PPS measurement pulse 2 to Tpf0. The value of Tpf0 is determined by the maximum transmission delay between the transmitter and receiver before adjustment (approximately 100ns) and the maximum fiber optic transmission distance (150km). Tpf0 should be ≥ 100ns + 100km * 5us / km = 600us; the device's Tpf0 is set to 800us. A schematic diagram of receiver FIFO delay adjustment is attached. Figure 3 As shown.

[0056] The above-disclosed embodiments are merely preferred embodiments of the radio frequency signal optical transmission delay control method of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art can understand that implementing all or part of the above embodiments and making equivalent changes in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A method for controlling the optical transmission delay of radio frequency signals, characterized in that, Includes the following steps: The transmitter parameters are set via the transmitter, and the receiver parameters are set via the receiver. The transmitter is powered on and sends a PPS measurement pulse to the receiver; The receiver measures the delay of the PPS measurement pulse and performs an arithmetic average to obtain the delay value. The FIFO read pointer is adjusted based on the delay value, and the PPS measurement pulse signal is switched to a transmission radio frequency signal to achieve stable radio frequency signal transmission delay. The transmitter includes an ADC module, a first FPGA module, an electro-optical conversion module, a first filter, and a first frequency synthesizer module. The first frequency synthesizer module is connected to both the ADC module and the first FPGA module. The filter is connected to both the ADC module and the first FPGA module. The electro-optical conversion module is connected to the first FPGA module. The receiver includes an optical-to-electrical conversion module, a second FPGA module, a DAC module, a second filter, a detection module, a shaping module, and a second frequency synthesizer module. The optical-to-electrical conversion module is connected to the second FPGA module. The second FPGA module is connected to both the shaping module and the second frequency synthesizer module. The DAC module is connected to the second FPGA module, the second frequency synthesizer module, and the second filter. The detection module is connected to both the second filter and the shaping module.

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