Branch prediction method and system, branch predictor, processor and storage medium

Abstract

The present application provides a branch prediction method and system, a branch predictor, a processor and a storage medium, which are applied to a branch predictor in a branch prediction system, wherein the system includes the branch predictor and a precision counter, and the method includes: using a first prediction pipeline to make predictions and obtain first branch prediction information; when a preset flushing condition is not met but a preset confidence condition is met, performing a self-increment operation of the precision counter; when the count of the precision counter reaches a preset value, activating a second prediction pipeline to use the first prediction pipeline and the second prediction pipeline to make predictions at the same time, and obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline. The present application uses a precision counter to count prediction accuracy, and can adaptively adjust the prediction bandwidth.

Description

Technical Field

[0001] The present application relates to the technical field of branch prediction and instruction extraction, and in particular to a branch prediction method, a branch predictor, a branch prediction system, a processor, and a computer-readable storage medium. Background Art

[0002] An out-of-order superscalar processor is a high-performance microprocessor that can execute multiple instructions in each clock cycle and does not need to change the processor state according to the order of the instructions. The forward-looking speculative execution of an out-of-order superscalar processor can improve the overall performance of the CPU, but when the speculation fails, there is both "waste" of power consumption and "pollution" of the predictor.

[0003] Based on this, the present application provides a branch prediction method, a branch predictor, a branch prediction system, a processor and a computer-readable storage medium to improve the relevant technology. Summary of the invention

[0004] The purpose of the present application is to provide a branch prediction method, a branch predictor, a branch prediction system, a processor and a computer-readable storage medium, which can adaptively adjust the prediction bandwidth by counting the prediction accuracy through a precision counter.

[0005] The purpose of this application is achieved by the following technical solutions:

[0006] In a first aspect, the present application provides a branch prediction method, which is applied to a branch predictor in a branch prediction system, wherein the system includes the branch predictor and a precision counter, and the method includes:

[0007] Using the first prediction pipeline to perform prediction, obtaining first branch prediction information;

[0008] When the preset line flushing condition is not met but the preset confidence condition is met, performing a self-increment operation of the precision counter;

[0009] When the count of the precision counter reaches a preset value, the second prediction pipeline is activated to use the first prediction pipeline and the second prediction pipeline to perform predictions simultaneously to obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline.

[0010] In a second aspect, the present application provides a branch predictor, wherein the branch predictor is configured to execute any one of the above branch prediction methods.

[0011] In a third aspect, the present application provides a branch prediction system, the system comprising a branch predictor, a precision counter, and an instruction fetch target queue;

[0012] The branch predictor is used to use the first prediction pipeline to make predictions and obtain first branch prediction information; when a preset flushing condition is not met but a preset confidence condition is met, perform a self-increment operation of the precision counter; when the count of the precision counter reaches a preset value, activate the second prediction pipeline to use the first prediction pipeline and the second prediction pipeline to make predictions at the same time, obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline; and write the branch target address in the branch prediction information into the instruction fetch target queue; the branch prediction information includes the first branch prediction information and the second branch prediction information;

[0013] The instruction fetch target queue is used to decouple the prediction pipeline and the instruction cache pipeline, and the prediction pipeline includes the first prediction pipeline and the second prediction pipeline.

[0014] In a fourth aspect, the present application provides a computing device, wherein the computing device comprises any one of the branch prediction systems described above.

[0015] In a fifth aspect, the present application provides a processor, comprising any one of the above-mentioned branch prediction systems.

[0016] In a sixth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions of any one of the above-mentioned branch prediction methods.

[0017] The branch prediction method, branch predictor, branch prediction system, processor and computer-readable storage medium provided by the present application use a precision counter to count the prediction accuracy and adaptively adjust the prediction bandwidth. When the flushing condition is not met but the confidence of the prediction meets the preset confidence condition, the precision counter will be added by one, so that the count of the precision counter gradually increases. Once the precision counter reaches the preset value, the second prediction pipeline will be activated. By using two prediction pipelines, namely the first prediction pipeline and the second prediction pipeline, two different branch prediction information can be obtained at the same time when predicting branch instructions, thereby increasing the prediction bandwidth to improve the prediction performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present application is further described below in conjunction with the accompanying drawings and specific implementation methods.

[0019] Figure 1 It is a flowchart of a branch prediction method provided in an embodiment of the present application.

[0020] Figure 2 It is a flow chart of a branch prediction method provided in an embodiment of the present application.

[0021] Figure 3It is a flow chart of statistical prediction accuracy provided in an embodiment of the present application.

[0022] Figure 4 It is a flowchart of selecting a predicted bandwidth provided in an embodiment of the present application.

[0023] Figure 5 It is a structural block diagram of a branch prediction system, an instruction cache module and a downstream processing module provided in an embodiment of the present application.

[0024] Figure 6 It is a structural block diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in this application to clearly and completely describe the technical solutions in the implementation mode of this application. Obviously, the described implementation mode is only a part of the implementation mode of this application, not all the implementation modes. Based on the implementation mode in this application, all other implementation modes obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0026] In the description of the embodiments of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0027] An out-of-order superscalar processor is a high-performance microprocessor that can execute multiple instructions in each clock cycle and does not need to change the processor state according to the order of the instructions. This technology can improve the instruction throughput and program execution speed, but it also requires more hardware resources and greater power consumption. The basic principle of an out-of-order superscalar processor is to use methods such as branch prediction, register renaming, and dynamic scheduling to solve problems such as data dependencies between instructions and pipeline levels. An out-of-order superscalar processor generally has one or more pipelines, each of which contains operations at different stages, such as instruction fetching, decoding, execution, and memory access. Some mechanisms are used to maintain data consistency and synchronization between pipelines. Compared with ordinary scalar processors, the biggest advantage of an out-of-order superscalar processor is that it fetches and submits multiple instructions per cycle, which improves instruction level parallelism (ILP) technology. ILP technology allows the processor to complete more computing tasks in one clock cycle, thereby improving program running efficiency. ILP technology can also be used in special fields or specific application scenarios, such as embedded systems, graphics processing, signal processing, etc.

[0028] The forward-looking speculative execution of out-of-order superscalar processors has greatly improved the overall performance of the CPU, but when the speculation fails, there is both "waste" of power consumption and "pollution" of the predictor. Specifically, when speculation fails, the CPU will perform operations such as "fetch-decode-execute-access" on the forward-looking error path, but they will eventually be cleared. The energy consumed at this time does not contribute to performance improvement at all, which is "waste" of power consumption. If the branch instruction on the wrong path is executed, the predictor cache will be replaced and updated, and useful information will be driven out of the cache, which will reduce the cover capability of the branch predictor and cause a decrease in the accuracy of subsequent branch predictions. This is "pollution" of the predictor.

[0029] The present application provides a branch prediction method, a branch predictor, a branch prediction system, a processor and a computer-readable storage medium to improve related technologies. The present application monitors the feedback of prediction accuracy through a precision counter and can adaptively adjust the prediction bandwidth.

[0030] It should be noted that, although the present application takes the branch prediction scenario as an example, the present application can be applied to other prediction scenarios and the present application is not limited to this.

[0031] See also Figure 1 , Figure 1 It is a flowchart of a branch prediction method provided in an embodiment of the present application.

[0032] An embodiment of the present application provides a branch prediction method, which is applied to a branch predictor. The method includes steps S101 to S103.

[0033] Step S101: using the first prediction pipeline to perform prediction and obtain first branch prediction information.

[0034] Step S102: When the preset line refresh condition is not met but the preset confidence condition is met, the precision counter is incremented.

[0035] Step S103: When the count of the precision counter reaches a preset value, activate the second prediction pipeline to use the first prediction pipeline and the second prediction pipeline to perform prediction simultaneously, and obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline.

[0036] Among them, the branch predictor may include, for example, a prediction control module and a prediction cache module, the prediction cache module is used to store branch information, the prediction control module is used to control the read and write access of the prediction cache module, read branch information from the prediction cache module, infer branch prediction information based on branch information, write the branch target address in the branch prediction information into the instruction fetch target queue, receive training data, context switch information and prediction accuracy of the corresponding branch target address fed back by the downstream processing module, etc. The prediction control module accesses the prediction cache module to obtain branch information, and the prediction control module can predict the direction (i.e. branch direction), type (i.e. branch type) and target address (i.e. branch target address) of the branch instruction execution as branch prediction information by further parsing the branch information. The branch predictor can not only predict the branch prediction information, but also obtain the confidence of the prediction.

[0037] The branch prediction information includes first branch prediction information and second branch prediction information, and each branch prediction information may include, for example, a branch direction, a branch type, a branch target address, etc. of the corresponding branch. The branch target address in the branch prediction information may be written into an instruction fetch target queue so that the instruction fetch target queue accesses the instruction cache module, so that the instruction cache module outputs the cached instruction to the downstream processing module.

[0038] Flushing is flushing the pipeline or flushing (i.e., flushing). Because the hardware mechanism that initiates the flush is generally distributed at the back end of the pipeline, when the flush is initiated, there are already erroneous instruction streams entering the front end pipeline for forward processing, so it is necessary to clear this part of the erroneous instruction stream from the pipeline, so it is called flushing (which includes clearing various queues, buffers, etc.).

[0039] In step S102, the flushing condition and the confidence condition are both pre-set conditions. Whether the corresponding conditions are met is judged to determine whether to perform the clearing operation of the instruction fetch target queue, whether to perform the self-increment operation of the precision counter, etc. The self-increment operation is to add one to the precision counter, making its count +1.

[0040] The precision counter is a counter used to count the number of predictions whose confidences meet the preset confidence conditions. After the precision counter reaches the preset value and activates the second prediction pipeline, the precision counter can keep the count unchanged, that is, always the preset value, until the flushing condition is met and a clearing operation is performed. Alternatively, the precision counter can continue to count and only count the number of predictions whose confidences meet the confidence conditions predicted by the first prediction pipeline. Alternatively, the precision counter can continue to count and not only count the number of predictions whose confidences meet the confidence conditions predicted by the first prediction pipeline, but also count the number of predictions whose confidences meet the confidence conditions predicted by the second prediction pipeline.

[0041] The embodiment of the present application does not limit the classification method of the confidence of the prediction, which can be classified into the first type of confidence and the second type of confidence, for example. The embodiment of the present application does not limit the confidence condition, and the confidence condition can include, for example: the confidence of the prediction is the first type of confidence. Among them, the embodiment of the present application does not limit the first type of confidence and the second type of confidence, the first type of confidence can be, for example, high confidence, and the second type of confidence can be, for example, non-high confidence, that is, the confidence of the prediction is classified into high confidence and non-high confidence.

[0042] Alternatively, the confidence level of the prediction may be classified into high confidence level, medium confidence level, low confidence level, etc. The confidence level condition may include, for example: the confidence level of the prediction is high confidence level.

[0043] Alternatively, the confidence of the prediction may be scored to obtain a confidence score of 100 or 10. The confidence condition may include, for example, that the confidence score of the prediction is greater than a preset score, wherein the preset score may be, for example, 60, 70, 80, 90, etc.

[0044] The embodiments of the present application do not limit the preset value, which may be, for example, 100, 500, 1000, 5000, 8000, 10000, 20000, etc. The count of the precision counter reaches the preset value, which means that the count of the precision counter gradually increases from 0 to the preset value. As an example, the preset value is 8000, and when the count of the precision counter reaches 8000, the second prediction pipeline is activated. The count reaches the preset value N, for example, which means that the precision counter with a count of N-1 performs a self-increment operation to make the count reach N.

[0045] In step S103, the specific operation of activating the second prediction pipeline may include, for example, enabling the hardware resources on which the second prediction pipeline depends, so that it can participate in the work normally. Similar to opening "another gate". On the basis of the simultaneous operation of the first prediction pipeline and the second prediction pipeline, the embodiment of the present application can continue to activate more prediction pipelines according to the needs of actual applications. For example, when the precision counter continues to count and simultaneously counts the number of predictions whose confidences of the predictions of the two prediction pipelines meet the confidence conditions and the count reaches a new threshold (the new threshold needs to be greater than the preset value), the third prediction pipeline can be activated. This application does not limit this.

[0046] In this embodiment, the prediction accuracy is calculated by using a precision counter to adaptively adjust the prediction bandwidth. The prediction bandwidth is used to describe the amount of data processed by the branch predictor per cycle. For example, a prediction bandwidth of 32B (Byte) means that 32 bytes of data are processed per cycle. When the flushing condition is not met but the confidence of the prediction meets the preset confidence condition (for example, the confidence of the prediction is high confidence), the precision counter will be added by one, so that the count of the precision counter gradually increases. Once the precision counter reaches the preset value, the second prediction pipeline will be activated. Using two prediction pipelines, namely the first prediction pipeline and the second prediction pipeline, two different branch prediction information can be obtained at the same time when predicting branch instructions, thereby increasing the prediction bandwidth to improve the prediction performance. In other words, this adaptability can optimize the performance of the system according to the actual prediction quality and decide whether to activate the second prediction pipeline. In addition, the flushing condition and the confidence condition can be flexibly adjusted, allowing the preset flushing condition and confidence condition to be customized according to performance requirements and prediction quality, so that the system can be flexibly configured according to the requirements of different applications and workloads to achieve the best performance and energy efficiency balance.

[0047] The embodiments of the present application do not limit the line flushing conditions. In some embodiments, the branch prediction system may further include an instruction fetch target queue, the instruction fetch target queue is used to decouple the prediction pipeline and the instruction cache pipeline, and the prediction pipeline includes the first prediction pipeline and the second prediction pipeline. The line flushing conditions may include: the downstream processing module feedbacks misprediction and / or context switching. The method may further include: writing the branch target address in the branch prediction information into the instruction fetch target queue; the branch prediction information includes the first branch prediction information and the second branch prediction information.

[0048] In some embodiments, the method may further include: when the line flushing condition is met, clearing the precision counter.

[0049] Since the branch prediction information includes the first branch prediction information and the second branch prediction information, the branch target address in the branch prediction information includes the branch target address in the first branch prediction information and the branch target address in the second branch prediction information. Since the first prediction pipeline and the second prediction pipeline predict at the same time, the prediction speed is doubled compared to the case where a single prediction pipeline works, and twice the branch target addresses can be predicted and written into the instruction fetch target queue in the same time. The embodiment of the present application does not limit the type of the branch target address, which may be, for example, a virtual address or a physical address. When the branch target address is a virtual address, the instruction fetch target queue accesses one or more levels of instruction cache modules so that the lowest level instruction cache module outputs the cache instruction of the physical address corresponding to the virtual address to the downstream processing module. When the branch target address is a physical address, the instruction fetch target queue accesses the instruction cache module so that the instruction cache module outputs the cache instruction of the corresponding physical address to the downstream processing module. The embodiment of the present application does not limit the cache instruction output by the instruction cache module, which may be, for example, a cache line. A cache line is an instruction block or a cache line, which is a unit of cache operation.

[0050] In an embodiment of the present application, the instruction fetch target queue can decouple the prediction pipeline and the instruction cache pipeline, that is, the instruction fetch target queue is used to achieve decoupling between the first prediction pipeline and the instruction cache pipeline, and to achieve decoupling between the second prediction pipeline and the instruction cache pipeline. The prediction pipeline may, for example, include the following operations: the prediction control module accesses the prediction cache module to obtain branch information → the prediction control module predicts based on the branch information and obtains the branch prediction information → the prediction control module writes the branch target address into the instruction fetch target queue. The instruction cache pipeline may, for example, include the following operations: the read pointer reads a branch target address from the instruction fetch target queue and accesses the instruction cache module → the instruction cache module outputs the corresponding cached instruction to the downstream processing module.

[0051] The flushing condition may include, for example, feedback of misprediction and context switching by the downstream processing module. The embodiment of the present application does not limit the downstream processing module, which may include, for example, but is not limited to, an instruction decoding unit, an instruction dispatching unit, an instruction issuing unit, an instruction executing unit, an instruction submitting unit, etc.

[0052] When a branch instruction is executed by the branch execution unit in the downstream processing module, the actual result will be obtained, including the actual branch direction, branch type and branch target address. The branch execution unit compares whether the predicted branch direction, branch type and branch target address are consistent with the actual branch direction, branch type and branch target address. Any inconsistency in one or more items is called a misprediction. The downstream processing module can feed back the misprediction (or prediction error) to the branch predictor to train the branch predictor; if each item is consistent, the prediction can be correctly fed back to the branch predictor. It should be noted that the branch direction in the actual result refers to whether the branch instruction has a jump behavior when it is executed. The branch direction in the predicted result is the behavior of the branch jump or not inferred by the branch predictor before the branch instruction is executed.

[0053] In some embodiments, when misprediction or context switching occurs, the downstream processing module may notify the instruction fetch target queue to clear the instruction fetch target queue.

[0054] In some embodiments, the method may further include: performing a training operation on the branch predictor when the downstream processing module feeds back a misprediction.

[0055] In some embodiments, performing a training operation on the branch predictor may include: after comparing the actual result of the branch instruction with the branch prediction information, the branch execution unit in the downstream processing module performs a correction and update operation on the branch predictor. For example, if the branch execution unit finds that the direction prediction of a specific branch instruction is wrong, it will perform a direction correction operation on the branch predictor.

[0056] As an example, the downstream processing module is a collection of multiple functional modules, in which the branch execution unit is responsible for initiating the training of the branch predictor. By performing training operations when the downstream processing module feeds back mispredictions, such as correcting and updating the branch predictor, the prediction errors can be corrected in time, thereby improving the accuracy of branch predictions, helping to reduce the probability of mispredictions, and reducing the poor system performance caused by mispredictions. The system can quickly correct mispredictions when they occur, thereby improving the robustness and stability of the system. Reducing mispredictions can avoid unnecessary branch transfers and instruction fetch target queue clearing operations, can more effectively predict the execution path of branch instructions, reduce unnecessary calculation and storage overhead, avoid unnecessary waste of resources, thereby improving the utilization efficiency of system resources, and helping to improve overall performance.

[0057] The context information of the program includes but is not limited to the process number, exception level, etc. Branch prediction information under different processes or exception levels cannot be shared. For example, the branch prediction information cached by running program A cannot be shared with program B. When switching from one program to another, it is a context switch. After the context switch occurs, the cache of the branch predictor cannot provide high-precision prediction results at this time, and certain training is required. It is not advisable to set a large prediction bandwidth. Therefore, the error information entering the instruction fetch target queue before the switching process must be cleared first; secondly, the precision counter must be cleared to reduce the prediction bandwidth, and reduce the power consumption overhead and cache pollution caused by the prediction failure due to insufficient preheating of the new process.

[0058] As a result, the system can respond to misprediction and context switching events in a timely manner. By clearing the instruction fetch target queue and resetting the precision counter, it can effectively reduce unnecessary resource occupation and energy consumption, help improve the energy efficiency of the system, and manage resources more effectively. Writing the branch target address in the branch prediction information into the instruction fetch target queue helps improve the efficiency of instruction prefetching. The instruction fetch target queue can decouple the prediction pipeline and the instruction cache pipeline, and realize the decoupling between the branch predictor and the instruction cache module, thereby ensuring that the instruction fetch target address can effectively supply the instruction cache pipeline in the case of correct prediction, reducing the possibility of instruction cache misses blocking the branch predictor. In addition, through the flexible configuration of the flushing conditions, the stability and reliability of the system are improved, ensuring that the system can perform well under various workloads and application scenarios.

[0059] In some embodiments, the method may also include: when the refresh condition is met and the first prediction pipeline and the second prediction pipeline perform predictions at the same time: closing the second prediction pipeline to use the first prediction pipeline for prediction; or, closing the first prediction pipeline to use the second prediction pipeline for prediction.

[0060] That is, closing one of the first prediction pipeline and the second prediction pipeline to use the other of the first prediction pipeline and the second prediction pipeline for prediction can be divided into two cases.

[0061] In the first case, the second prediction pipeline is turned off, and the first prediction pipeline is retained for prediction. In this case, the first prediction pipeline is always in an activated state, and the evolution of the activated prediction pipeline can be expressed as "1→1+2→1→1+2→1..." For example, when the prediction resources and prediction performance of the first prediction pipeline are better than those of the second prediction pipeline, the prediction pipeline with the best prediction performance can be kept working to ensure that the lower limit of the system's prediction performance is always at a high level.

[0062] In the second case, the first prediction pipeline is turned off, and the second prediction pipeline is retained for prediction. When the count of the precision counter reaches the preset value again, the first prediction pipeline can be activated to use the two prediction pipelines for simultaneous prediction until the flushing condition is met again and the second prediction pipeline is turned off. Similarly, the evolution of the prediction pipeline in the activated state can be expressed as "1→1+2→2→1+2→1..." In this case, the first prediction pipeline and the second prediction pipeline can be alternately in the activated state and the inactivated state, and the prediction resources of the branch predictor are used more evenly.

[0063] In this embodiment, prediction resources refer to the hardware and software resources used by the prediction pipeline to perform prediction tasks, and prediction performance refers to the efficiency and accuracy of the prediction pipeline in predicting branch behavior. Specifically, prediction resources, for example, involve the hardware resources used by each prediction pipeline (such as cache size, type, access speed, etc.), as well as the prediction algorithm at the software level. The prediction resources and corresponding prediction performance used by two prediction pipelines may be the same or different. For example, the first prediction pipeline can use a larger or faster Branch History Table (Branch History Table, BHT) or Pattern History Table (Pattern History Table, PHT), which can provide richer historical information to make more accurate predictions.

[0064] The evolution pattern of "1→1+2→1→1+2→1..." indicates that in the first case, the first prediction pipeline always remains activated. When certain conditions are met, the second prediction pipeline is also activated (1+2), and when these conditions are no longer met, the system returns to the state of using only the first prediction pipeline (1). This method can dynamically optimize the prediction accuracy according to the runtime situation. In the case where the first prediction pipeline may have better prediction resources and performance than the second prediction pipeline, even when both pipelines are available, choosing to retain the first pipeline with better performance can ensure that the system's prediction performance will not fall below a certain level. By always keeping the first prediction pipeline with better performance running, it can be ensured that the system's prediction performance always remains at a relatively high level, even when the second prediction pipeline is not activated.

[0065] The evolution pattern of "1→1+2→2→1+2→1..." indicates that in the second case, the two prediction pipelines are activated and disabled alternately. The first prediction pipeline and the second prediction pipeline can be switched dynamically based on the actual prediction accuracy and other conditions. The precision counter is used to determine when to activate the prediction pipeline that is not currently activated, and the flush condition is used to determine when to shut down one of the prediction pipelines. In this way, the resources of the branch predictor can be used more evenly. Different prediction pipelines may perform better in different situations. Dynamic switching can ensure that better prediction results can be achieved in different execution stages, helping the processor adapt to changing program behaviors and improving overall prediction accuracy.

[0066] In some embodiments, the method may further include: when the line brushing condition and the confidence condition are not met, keeping the count of the precision counter unchanged.

[0067] In some embodiments, the method may further include: when the count of the precision counter is lower than the preset value, continuing to use the first prediction pipeline to perform prediction.

[0068] In this embodiment, each time a prediction occurs and the confidence of the prediction meets the preset confidence condition, the count of the precision counter is increased by one, that is, the self-increment operation of the precision counter is performed; if a prediction occurs but the confidence does not meet the confidence condition, the precision counter keeps the count unchanged; if a misprediction occurs or the context of the program is switched, the precision counter is cleared and the statistics are restarted. When the precision counter increases continuously until the threshold, it indicates that the confidence of the prediction is high and all are correct predictions (because a misprediction will perform a clearing operation), so the prediction accuracy is considered to be high, otherwise the prediction accuracy is considered to be low. Under the premise of an existing prediction pipeline, another prediction pipeline is selected to work by high prediction accuracy to increase the prediction bandwidth, and vice versa to block another prediction pipeline to reduce the prediction bandwidth, thereby achieving a doubling of the prediction bandwidth when the prediction accuracy is high to improve performance, and a halving of the prediction bandwidth when the prediction accuracy is low to reduce prediction power consumption and reduce cache pollution.

[0069] In some embodiments, the process of obtaining the confidence of the prediction corresponding to the first branch prediction information includes: using an N-bit saturated counter to record the branch directions of the branches corresponding to the first branch prediction information in the most recent N times to determine the confidence of the current prediction, where N is an integer greater than 1; or, the process of obtaining the confidence of the prediction corresponding to the first branch prediction information and the second branch prediction information includes: using an M-bit saturated counter to record the branch directions of the branches corresponding to the first branch prediction information and the second branch prediction information in the most recent M times to determine the confidence of the current prediction, where M is an integer greater than 1.

[0070] That is to say, there are two situations in which a saturated counter is used to determine the prediction confidence. In the first situation, an N-bit saturated counter is used to separately record the branch direction of a branch corresponding to the first prediction pipeline to determine the confidence of the current prediction of the branch corresponding to the first prediction pipeline. In the second situation, an M-bit saturated counter is used to simultaneously record the branch direction of a branch corresponding to two prediction pipelines (i.e., the first prediction pipeline and the second prediction pipeline) to determine the confidence of the current prediction of the branch corresponding to any one prediction pipeline. At this time, regardless of whether the branch direction recorded in the M-bit saturated counter corresponds to the same prediction pipeline or two prediction pipelines, and regardless of which prediction pipeline the current prediction corresponds to, the branch direction recorded in the M-bit saturated counter can be used to determine the confidence of the current prediction of the branch.

[0071] Saturated counters can capture patterns and trends in branch behavior. This historical behavior-based prediction method can improve the accuracy of branch prediction, especially for branches that show certain regularity. Saturated counters can implement a mechanism to dynamically evaluate prediction confidence. For example, multiple consecutive correct predictions can increase confidence, while incorrect predictions can reduce confidence. This dynamic adjustment enables the prediction system to self-correct based on real-time data. Saturated counters are a relatively simple implementation method that is easy to implement in hardware. Compared with more complex prediction algorithms, saturated counters are more efficient in terms of resources and energy consumption. In the second case, the same saturated counter is used to evaluate the confidence of the prediction of one branch corresponding to two prediction pipelines. This provides a unified way to evaluate the accuracy of the entire prediction process and reduces the complexity of the design, which is conducive to improving the performance of the overall branch prediction system. Sharing saturated counter data between different prediction pipelines can help the system better adapt to different prediction modes. For example, if the prediction modes of the two pipelines are similar, sharing data can improve prediction accuracy; if the modes are different, this method still provides valuable historical information for evaluating the current prediction confidence.

[0072] The embodiment of the present application does not limit the values ​​of M and N, which can be, for example, 2, 3, 4, etc.

[0073] The branch prediction information is the prediction result that the prediction control module further infers and outputs after accessing the prediction cache module to obtain the branch information, including the branch pattern history records, referred to as PHR (Pattern History Records), which can be recorded using a 2-bit or 3-bit saturated counter, for example.

[0074] In some embodiments, considering that the current direction of a branch is related to its previous two directions, a 2-bit saturated counter can be designed to record the past two directions of the branch for predicting the current branch direction. Taking a 2-bit saturated counter as an example, when PHR = 2'b11 or 2'b00, the predicted confidence is high confidence, and if PHR = 2'b10 or 2'b01, the predicted confidence is not high confidence. In the use and training of PHR, the PHR obtained by accessing the prediction cache can be any of the following 4 types.

[0075] ①, 2'b00: indicates that the prediction direction is no jump and has high confidence.

[0076] If the prediction is wrong, update PHR from 2'b00->2'b01.

[0077] If the prediction is correct, the PHR remains unchanged.

[0078] ②, 2'b01: Indicates that the prediction direction is not jumping and is not high confidence.

[0079] If the prediction is wrong, update PHR from 2'b01->2'b10.

[0080] If the prediction is correct, update PHR from 2'b01->2'b00.

[0081] ③, 2'b10: Indicates that the predicted direction is jump, and the confidence level is not high.

[0082] If the prediction is wrong, update PHR from 2'b10->2'b01.

[0083] If the prediction is correct, update PHR from 2'b10->2'b11.

[0084] ④, 2'b11: Indicates that the predicted direction is jump, and the confidence level is high.

[0085] If the prediction is wrong, update PHR from 2'b11->2'b10.

[0086] If the prediction is correct, the PHR remains unchanged.

[0087] The predicted direction refers to the predicted branch direction, that is, the branch direction in the branch prediction information. A prediction error, that is, a misprediction occurs, corresponds to a situation where at least one of the branch direction, branch type, and branch target address in the prediction result (that is, the branch prediction information) is inconsistent with the branch direction, branch type, and branch target address in the actual result. A correct prediction corresponds to a situation where the branch direction, branch type, and branch target address in the prediction result are consistent with each of the branch direction, branch type, and branch target address in the actual result.

[0088] It should be noted that in this embodiment, high confidence is not the same as or equivalent to correct prediction. High confidence is based on the premise of correct prediction, because once the wrong prediction accuracy counter is cleared, the clearing has the highest priority.

[0089] By using an N-bit saturated counter to record the most recent N directions of a branch, the current branch direction can be predicted more accurately. The saturated counter is updated based on whether the prediction result is correct or not, so that the branch prediction system can learn from previous errors and adjust itself. For example, if the prediction is wrong, the value of the saturated counter will be adjusted accordingly to reflect the recent changes in branch behavior. Compared with complex prediction algorithms, the method using a saturated counter is simpler and more direct to implement, more efficient in hardware implementation, and takes up fewer resources. Since the number of bits N of the N-bit saturated counter can be selected as needed (such as 2, 3, 4, etc.), it can balance the relationship between prediction accuracy and required resources.

[0090] In some embodiments, the method may further include: when the count of the precision counter reaches the preset value, increasing the number of instruction channels and / or the capacity of the cache structure of the computing device to facilitate prefetching instructions.

[0091] In some embodiments, the method may further include: when the flushing condition is met, reducing the number of instruction channels of the computing device and / or the capacity of a cache structure to suppress pre-fetching instructions.

[0092] The computing device may be, for example, a processor, and the processor may include, for example, an out-of-order superscalar processor.

[0093] In the branch prediction method, when the precision counter reaches a preset value, the number of instruction channels of the computing device and / or the capacity of the cache structure are increased. This dynamic adjustment enables the system to flexibly increase prediction resources to promote instruction prefetching according to the current prediction accuracy and performance requirements, which helps to process more complex instruction streams, especially when the prediction accuracy is high, and can more effectively utilize processor resources. When the downstream processing module feedbacks the situation of misprediction or context switching that meets the flushing conditions, the number of instruction channels of the computing device and / or the capacity of the cache structure are reduced, which helps to reduce unnecessary resource consumption caused by inaccurate prediction and reduce performance loss caused by prediction errors. By reducing prediction resources, the system can suppress unnecessary instruction prefetching, thereby improving overall efficiency. This method of dynamically adjusting the number of instruction channels and cache capacity can optimize resource usage according to real-time prediction performance and system status. When the prediction performance is good, the prediction resources are increased to increase the instruction prefetching speed; when the prediction performance is poor, the prediction resources are reduced to reduce power consumption waste, which is conducive to maximizing resource utilization efficiency while ensuring efficient prediction. Dynamically adjusting resources based on changes in prediction accuracy improves the system's adaptability to different workloads, allowing computing devices to handle different types of programs and tasks more flexibly, enhancing their scalability and effectiveness in changing application environments.

[0094] In some embodiments, the instruction channel may include a decoding bandwidth and / or a transmission bandwidth.

[0095] In some embodiments, the cache structure may include one or more of the instruction fetch target queue, the instruction queue, the issue queue, and the out-of-order resource.

[0096] In the branch prediction method, the instruction channel includes decoding bandwidth and emission bandwidth. The adaptive adjustment of decoding bandwidth is conducive to processing intensive instruction sequences, while the adjustment of emission bandwidth is conducive to optimizing the parallel execution of instructions. That is to say, in addition to the prediction bandwidth, which is the bandwidth of the predicted instruction channel, the method can also adaptively adjust the bandwidths of the other two instruction channels, namely the bandwidths of the decoding channel and the emission channel. The flexibility of this adaptive adjustment enables the computing device to handle different workloads more effectively and improve the overall performance. A variety of cache structures include instruction fetch target queues, instruction queues, emission queues, and out-of-order resources, etc., which provide more possibilities for optimizing pre-fetch instructions and execution processes, so that the computing device can be more accurately optimized for specific performance bottlenecks, whether in the instruction fetch, decoding, emission or execution stages. By dynamically adjusting the decoding bandwidth and the emission bandwidth, and reasonably configuring different cache structures, the performance of the computing device in different scenarios can be effectively improved. For example, when executing branch-intensive code, the instruction fetch target queue and the instruction queue can be enhanced first, while when executing parallel instruction-intensive code, the processing capabilities of the emission queue and out-of-order resources can be enhanced. When a prediction error occurs, reducing the decoding bandwidth and transmission bandwidth and reducing the capacity of the cache structure can help reduce resource waste and performance degradation caused by incorrect predictions. By dynamically adjusting the instruction channel and cache structure, resources can be used more efficiently at different execution stages. Flexible resource management helps improve the overall efficiency of computing devices, especially in the face of changing workloads and execution conditions.

[0097] See also Figures 2 to 4 , Figure 2 is a flow chart of a branch prediction method provided in an embodiment of the present application, Figure 3 is a flow chart of a statistical prediction accuracy provided by an embodiment of the present application, Figure 4 It is a flowchart of selecting a predicted bandwidth provided in an embodiment of the present application.

[0098] In a specific application scenario, the embodiment of the present application also provides a branch prediction method, which is applied to a branch predictor in a branch prediction system, wherein the system includes the branch predictor, a precision counter, and an instruction fetch target queue, such as Figure 2 As shown, the method includes:

[0099] Using the first prediction pipeline to make predictions, obtain first branch prediction information, and write the branch target address in the first branch prediction information into an instruction fetch target queue; the instruction fetch target queue is used to decouple the prediction pipeline and the instruction cache pipeline, and the prediction pipeline includes the first prediction pipeline and the second prediction pipeline;

[0100] When a preset flushing condition is met, the precision counter is cleared (i.e., the precision counter is cleared); the flushing condition includes: feedback of misprediction and / or context switching by a downstream processing module;

[0101] When the line brushing condition is not met and the preset confidence condition is not met, the count of the precision counter is kept unchanged (that is, the precision counter is maintained); the confidence condition includes: the predicted confidence is high confidence;

[0102] When the flushing condition is not met but the confidence condition is met, the precision counter is incremented (i.e., the precision counter is incremented);

[0103] When the count of the precision counter is lower than a preset value, continue to use the first prediction pipeline to perform prediction (that is, one prediction pipeline works);

[0104] When the count of the precision counter reaches a preset value, the second prediction pipeline is activated to use the first prediction pipeline and the second prediction pipeline to perform prediction simultaneously (i.e., two prediction pipelines work), obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline, and write the branch target address in the first branch prediction information and the branch target address in the second branch prediction information into the instruction fetch target queue; at the same time, the number of instruction channels of the computing device and / or the capacity of the cache structure are increased to facilitate prefetching instructions;

[0105] When the flush line condition is met and the first prediction pipeline and the second prediction pipeline perform predictions at the same time, the second prediction pipeline is closed to use the first prediction pipeline for prediction; and when the flush line condition is met, the number of instruction channels of the computing device and / or the capacity of the cache structure are reduced to suppress prefetching instructions.

[0106] The instruction channel includes a decoding bandwidth and / or an emission bandwidth; the cache structure includes one or more of the instruction fetch target queue, the instruction queue, the emission queue and the out-of-order resource.

[0107] Among them, the process of obtaining the confidence of the prediction corresponding to the first branch prediction information includes: using an N-bit saturated counter to record the branch directions of the branches corresponding to the first branch prediction information in the most recent N times to determine the confidence of the current prediction, where N is an integer greater than 1; or, the process of obtaining the confidence of the prediction corresponding to the first branch prediction information and the second branch prediction information includes: using an M-bit saturated counter to record the branch directions of the branches corresponding to the first branch prediction information and the second branch prediction information in the most recent M times to determine the confidence of the current prediction, where M is an integer greater than 1.

[0108] In this embodiment, if Figure 3 As shown, the precision counter is updated each time a prediction is completed, and the specific update operation depends on the situation.

[0109] The first step is to check whether a wrong prediction or context switch has occurred (hereinafter referred to as condition 1). If condition 1 is met, the precision counter is cleared and the process ends; if condition 1 is not met, the second step is entered.

[0110] The second step is to check the confidence of the prediction result (hereinafter referred to as condition 2). If condition 2 is high confidence, the precision counter is incremented and the process ends; if condition 2 is not high confidence, the precision counter is maintained and the process ends.

[0111] Please combine Figure 2 and 4 Before each prediction starts, the second prediction pipeline will be activated based on whether the precision counter reaches the threshold. The first prediction pipeline is not affected and can be regarded as a constant activation state.

[0112] The first step is to check whether the precision counter reaches the preset value (hereinafter referred to as condition 3). If condition 3 is met, the second prediction pipeline is "activated", two prediction pipelines work, and the process ends; if condition 3 is not met, the second prediction pipeline is not "activated", one prediction pipeline is kept working, and the process ends.

[0113] It can be seen that in this embodiment, each time a prediction occurs and the confidence of the prediction is high, the count of the precision counter is +1; if a prediction occurs but the confidence is not high or the count of the precision counter has reached the maximum value (i.e., a preset value, which can be used as a threshold), the precision counter is maintained; if a wrong prediction occurs or the context of the program is switched, the precision counter is cleared and the statistics are restarted. When the precision counter increases continuously until the threshold, it indicates that the confidence of the prediction is high and all are correct predictions in the past period of time, then the prediction accuracy is considered to be high, otherwise the prediction accuracy is considered to be low. Among them, the past period of time can be the time period in which the precision counter increases continuously until the threshold, and the application does not set a limit on the length of this time period. As an example, the value of a period of time is measured based on the number of predictions, which is related to the capacity of the prediction cache module. For example, the prediction cache module can accommodate 8,000 branch records, so the "period of time" can be set to the duration of 8,000 predictions, or a duration parameter can be selected based on performance exploration data.

[0114] On the premise of the original prediction pipeline (i.e., the first prediction pipeline), the prediction accuracy is high to enable another prediction pipeline (i.e., the second prediction pipeline) to increase the prediction bandwidth, and vice versa to block the other prediction pipeline (i.e., the second prediction pipeline) to reduce the prediction bandwidth, thereby doubling the prediction bandwidth when the prediction accuracy is high to improve the prediction performance, and halving the prediction bandwidth when the prediction accuracy is low to reduce the prediction power consumption and reduce cache pollution.

[0115] An embodiment of the present application also provides a branch predictor, which is configured to execute any one of the above branch prediction methods.

[0116] In some embodiments, the branch predictor may include a prediction control module and a prediction cache module, the prediction cache module is used to store branch information, the prediction control module is used to control the read and write access of the prediction cache module, read the branch information from the prediction cache module, infer branch prediction information based on the branch information, write the branch target address in the branch prediction information into the instruction target queue, and receive training data, context switching information and prediction accuracy corresponding to the branch target address fed back by the downstream processing module.

[0117] An embodiment of the present application also provides a branch prediction system, which includes a branch predictor, a precision counter, and an instruction fetch target queue.

[0118] The branch predictor is used to use the first prediction pipeline to make predictions and obtain first branch prediction information; when a preset flush condition is not met but a preset confidence condition is met, perform the self-increment operation of the precision counter; when the count of the precision counter reaches a preset value, activate the second prediction pipeline to use the first prediction pipeline and the second prediction pipeline to make predictions at the same time, obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline; and write the branch target address in the branch prediction information into the instruction fetch target queue; the branch prediction information includes the first branch prediction information and the second branch prediction information.

[0119] The instruction fetch target queue is used to decouple the prediction pipeline and the instruction cache pipeline, and the prediction pipeline includes the first prediction pipeline and the second prediction pipeline.

[0120] In some embodiments, the precision counter is a separate module. In other embodiments, the precision counter is part of the branch predictor.

[0121] See also Figure 5 , Figure 5 It is a structural block diagram of a branch prediction system, an instruction cache module and a downstream processing module provided in an embodiment of the present application.

[0122] In a specific application scenario, the present application embodiment also provides a branch prediction system, such as Figure 5 As shown, the branch prediction system includes a branch predictor, a precision counter (not shown in the figure) and an instruction fetch target queue.

[0123] The branch predictor includes a prediction control module 100 and a prediction cache module 101 .

[0124] The prediction buffer module 101 is a memory body of the predictor and is a module with high power consumption. The prediction buffer module 101 is used to store branch information executed by the branch execution unit in the downstream processing module, including branch direction, branch type and branch target address (eg, virtual address).

[0125] The prediction control module 100 controls the read and write access of the predictor cache module 101, collects prediction results, writes the instruction fetch target queue 200, and receives feedback from the downstream processing module 300 to perform prediction accuracy statistics. Specifically, the prediction control module 100 is used to use the first prediction pipeline to make predictions, obtain the first branch prediction information, and write the branch target address in the first branch prediction information into the instruction fetch target queue 200; when the flush line condition is met, the precision counter is cleared; when the flush line condition is not met and the preset confidence condition is not met, the count of the precision counter is kept unchanged; when the flush line condition is not met but the confidence condition is met, the precision counter is incremented; when the count of the precision counter is lower than the preset value, the first prediction pipeline is continued to be used for prediction; when the count of the precision counter reaches the preset value, the second prediction pipeline is activated to use the first prediction pipeline and the second prediction pipeline to make predictions simultaneously, The first branch prediction information corresponding to the first prediction pipeline and the second branch prediction information corresponding to the second prediction pipeline are obtained, and the branch target address in the first branch prediction information and the branch target address in the second branch prediction information are written into the instruction fetch target queue 200; at the same time, the number of instruction channels of the computing device and / or the capacity of the cache structure are increased to promote prefetching instructions; when the downstream processing module 300 feeds back a misprediction and the first prediction pipeline and the second prediction pipeline make predictions at the same time, the second prediction pipeline is closed to make use of the first prediction pipeline for prediction; and, when the downstream processing module 300 feeds back a misprediction or context switching, the number of instruction channels of the computing device and / or the capacity of the cache structure are reduced to suppress prefetching instructions. 102 is the prediction control module 100 using the first prediction pipeline to access the prediction buffer module 101, 103 is the prediction control module 100 using the second prediction pipeline to access the prediction buffer module 101, 104 is the result of the prediction control module 100 using the first prediction pipeline to access the prediction buffer module 101, and 105 is the result of the prediction control module 100 using the second prediction pipeline to access the prediction buffer module 101. 106 is the prediction control module 100 using the first prediction pipeline to write the branch target address in the first branch prediction information into the instruction fetch target queue 200, and 107 is the prediction control module 100 using the second prediction pipeline to write the branch target address in the second branch prediction information into the instruction fetch target queue 200.

[0126] The instruction fetch target queue 200 is an instruction fetch target buffer, which is used to decouple the prediction pipeline and the instruction cache pipeline. The instruction fetch target queue 200 stores the branch target address obtained and provided by the prediction control module 100 for accessing the subsequent instruction cache module 201.

[0127] The instruction cache module 201 is a storage body for storing cache lines (ie, instructions) and is a module with high power consumption. 202 is the instruction fetch target queue 200 initiating access to the instruction cache module 201, and 203 is the instruction cache module 201 delivering the cache line after the instruction hit to the downstream processing module 300.

[0128] The downstream processing module 300 covers multiple functions such as decoding, dispatching, transmitting, executing, submitting, etc., and provides prediction accuracy, training after misprediction, and context switching information to the prediction control module 100. The downstream processing module 300 can also feedback misprediction and / or context switching to the instruction fetch module queue 200. Among them, the prediction accuracy fed back by the downstream processing module 300 can be divided into two types: correct prediction and wrong prediction (prediction error, i.e., wrong prediction). The present application does not limit the representation method of the prediction accuracy, which can be represented by one or more of Chinese, letters, numbers, symbols, and graphics. For example, "correct", "Y", "1", "√" can be used to indicate a correct prediction, and "wrong", "N", "0", "×" can be used to indicate a wrong prediction.

[0129] 301 indicates that the downstream processing module 300 finds a misprediction, feeds back the prediction control module 100 to train the branch predictor (including operations such as allocation, update, and correction), notifies the prediction control module 100 to perform prediction accuracy statistics so that the prediction control module 100 updates the PHR, and notifies the instruction target queue 200 to flush the line.

[0130] 302 is when the downstream processing module 300 discovers the context switch, notifies the prediction control module 100 to perform prediction accuracy statistics, and notifies the instruction fetch target queue 200 to flush the line.

[0131] In actual applications, after the hardware is powered on and reset, the downstream processing module 300 will notify the prediction control module 100 to start up to load the instruction of the first branch target address.

[0132] The prediction control module 100 initiates access to the prediction buffer module 101 . At this time, because the precision counter has not reached the threshold (ie, the preset value), only the access to 102 is activated, and the access to 103 is not activated.

[0133] The prediction buffer module 101 feeds back the prediction result 104 accessed by 102 to the prediction control module 100 . Since 103 is not activated, there is no feedback for 105 .

[0134] The prediction control module 100 receives the result fed back by 104 and updates the state of the precision counter, that is, checks the confidence level corresponding to the prediction result. If the confidence level is high, the precision counter increments; if the confidence level is not high, the precision counter remains. At the same time, the branch target address in the prediction result is written to the instruction fetch target queue 200 through 106 (because 103 is not activated, 107 is also not activated); at the same time, the predicted branch target address drives the prediction control module 100 itself again to enter the next cycle of access.

[0135] The instruction fetch target queue 200 sends the branch target addresses stored in it to the instruction cache module 201 in order for instruction fetch operation, parses the instructions of the cache line, and delivers them to the downstream processing module 300 through 203. After the downstream processing module 300 executes the branch instruction, it will notify the prediction control module 100 through 301, train the prediction control module 100, and update the precision counter at the same time. When the downstream processing module 300 needs to perform a context switch, it will notify the prediction control module 100 through 302 to update the precision counter.

[0136] Repeatedly, after a period of training, when the prediction cache module 101 has accumulated a lot of branch information and can give a high-precision prediction of the branch target address, the precision counter of the prediction control module 100 begins to approach the threshold.

[0137] Once the threshold is met, the prediction control module 100 activates the second prediction pipeline 103, and the paths 105 and 107 are activated synchronously. At this time, two prediction blocks will be processed per cycle, that is, the prediction control module 100 reads two branch information from the prediction cache module 101 per cycle, and the prediction control module 100 writes two branch target addresses to the instruction fetch target queue 200 per cycle. At this time, the prediction speed is doubled compared to the previous one.

[0138] After the two prediction pipelines have been working for a period of time, assuming that a misprediction occurs, the downstream processing module 300 will notify the prediction control module 100 to adjust the precision counter and shut down the second prediction pipeline. Because the prediction accuracy will decrease at this time, if no adjustment is made, the fast instruction fetch will send more instructions on the wrong path to the downstream processing module 300 for execution, and the branch execution of the wrong path may train the prediction cache module 101 in advance, causing pollution and deterioration of accuracy; at the same time, if it causes an instruction cache miss, the cache line on the wrong path will be backfilled, polluting the instruction cache module 201, causing an increase in the cache miss rate; what's more, the execution of instructions on the wrong path will also cause power consumption waste of the downstream processing module 300.

[0139] In this embodiment, prediction accuracy statistics are achieved through precision counters, and prediction bandwidth adaptation can be performed on this basis. In addition, it is also applicable to scenarios such as instruction fetch target queue adaptation, instruction fetch bandwidth adaptation, instruction queue adaptation, decoding bandwidth adaptation, transmission bandwidth adaptation, transmission queue adaptation, and out-of-order resource adaptation, to achieve adaptive adjustment of relevant parameters of corresponding resources based on prediction accuracy statistics, and this application does not impose any restrictions on this.

[0140] An embodiment of the present application further provides a processor, which includes any one of the above-mentioned branch prediction systems.

[0141] See also Figure 6 , Figure 6 It is a structural block diagram of a computing device provided in an embodiment of the present application.

[0142] An embodiment of the present application further provides a computing device, which includes any one of the above-mentioned branch prediction systems.

[0143] The embodiments of the present application do not limit the computing device, which may be, for example, a computer server, a cloud server, a distributed server, etc. The processor may include, for example, an out-of-order superscalar processor, etc.

[0144] In an optional embodiment, the computing device may include the branch prediction system described above. Figure 6 As shown, the computing device may include: a memory 110, a processor 120, and a communication interface 130. The memory 110, the processor 120, and the communication interface 130 are connected via an internal connection path.

[0145] The memory 110 is used to store instructions and codes. In some implementations, the codes may be codes for implementing the methods of the embodiments of the present application.

[0146] The processor 120 is used to execute the instructions and codes stored in the memory 110 to control the communication interface 130 to receive input data and information and output data such as operation results. In some implementations, when the solution of the embodiment of the present application is implemented by software or firmware, the code used to implement the solution of the embodiment of the present application can be stored in the processor 120 and executed by the processor 120.

[0147] The memory 110 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory 110 described herein is intended to include, but is not limited to, any memory of these and other suitable types. As an example, the memory 110 includes a random access memory (RAM), a cache memory and a read-only memory (ROM). Among them, the memory 110 stores a computer program, and the computer program can be executed by the processor 120 so that the processor 120 implements the steps of any of the above methods.

[0148] The processor 120 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor 120 may be any conventional processor, etc.

[0149] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 120 or an instruction in the form of software. The method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in the processor 120 for execution. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 110, and the processor 120 reads the information in the memory 110 and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0150] In some implementations, in addition to the hardware units described above, the computing device may also include software modules, where the software modules may be, for example, an operating system, a basic input output system (BIOS), application software, etc.

[0151] The operating system is used to manage the hardware and / or software resources of a computing device and is the core and cornerstone of a computing device. The operating system needs to handle basic tasks such as managing and configuring memory, determining the priority of system resource supply and demand, controlling input and output devices, operating the network, and managing the file system. In order to facilitate user operation, most operating systems provide an operating interface for users to interact with the system.

[0152] BIOS is used to run hardware initialization during the power-on boot phase and provide runtime services for the operating system and application programs. In some implementations, BIOS can also monitor and display processor temperature and execute functions such as adjusting temperature protection strategies.

[0153] Application software, also known as application program, can be understood as software written for a specific application purpose of the user. It is one of the main categories of computer software. For example, application software can be a program for achieving purposes such as power control and temperature management.

[0154] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions of any of the above-mentioned branch prediction methods.

[0155] An embodiment of the present application also provides a computer program product, which includes instructions of any of the above-mentioned branch prediction methods.

[0156] The computer program product may be a portable compact disk read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the computer program product of the present application is not limited thereto, and the computer program product may be any combination of one or more computer readable media.

[0157] The user information or user account information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, etc.) involved in multiple implementation methods of this specification are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws and standards of relevant countries and regions, and provide corresponding instruction entrances for users to choose to authorize or refuse.

[0158] It should be understood that the specific examples in this specification are only intended to help those skilled in the art to better understand the implementation methods of the present application, rather than to limit the scope of protection of the present application.

[0159] It is understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application.

[0160] It can be understood that the various implementation modes described in this specification can be implemented individually or in combination, and this application is not limited to this.

[0161] Unless otherwise specified, all technical and scientific terms used in this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0162] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this specification.

[0163] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of each embodiment described above can refer to the corresponding process in other embodiments and will not be repeated here.

[0164] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0165] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the technical solution of the present application.

[0166] In addition, each functional unit in each embodiment of the present specification may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0167] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of this specification. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0168] The above are only specific implementations of this specification, but the protection scope of this application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of this application should be based on the protection scope of the claims.

Claims

1. A branch prediction method, characterized in that: A branch predictor applied to a branch prediction system, the system comprising the branch predictor and a precision counter, the method comprising: Using the first prediction pipeline to perform prediction, obtaining first branch prediction information; When the preset line flushing condition is not met but the preset confidence condition is met, performing a self-increment operation of the precision counter; When the count of the precision counter reaches a preset value, activating the second prediction pipeline to simultaneously perform prediction using the first prediction pipeline and the second prediction pipeline to obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline; Among them, the line brushing conditions include: the downstream processing module feedbacks misprediction and / or context switching; the confidence conditions include any one of the following: the predicted confidence is the first type of confidence; the predicted confidence is high confidence; the predicted confidence score is greater than the preset score.

2. The branch prediction method according to claim 1, characterized in that: The branch prediction system further includes an instruction fetch target queue, the instruction fetch target queue is used to decouple the prediction pipeline and the instruction cache pipeline, the prediction pipeline includes the first prediction pipeline and the second prediction pipeline; The method further comprises: The branch target address in the branch prediction information is written into the instruction fetch target queue; the branch prediction information includes the first branch prediction information and the second branch prediction information.

3. The branch prediction method according to claim 1 or 2, characterized in that: The method further comprises: When the line flushing condition is met, the precision counter is cleared.

4. The branch prediction method according to claim 1 or 2, characterized in that: The method further comprises: When the flushing condition is met and the first prediction pipeline and the second prediction pipeline perform predictions at the same time: closing the second prediction pipeline to use the first prediction pipeline for prediction; or, The first prediction pipeline is closed to use the second prediction pipeline for prediction.

5. The branch prediction method according to claim 1, characterized in that: The method further comprises: When the line brushing condition and the confidence condition are not met, keeping the count of the precision counter unchanged; and / or, When the count of the precision counter is lower than the preset value, the first prediction pipeline continues to be used for prediction.

6. The branch prediction method according to claim 1, characterized in that: The process of obtaining the confidence level of the prediction corresponding to the first branch prediction information includes: using an N-bit saturated counter to record the branch directions of the branch corresponding to the first branch prediction information in the most recent N times to determine the confidence level of the current prediction, where N is an integer greater than 1; or The process of obtaining the confidence level of the prediction corresponding to the first branch prediction information and the second branch prediction information includes: using an M-bit saturated counter to record the branch directions of the branches corresponding to the first branch prediction information and the second branch prediction information in the most recent M times to determine the confidence level of the current prediction, where M is an integer greater than 1.

7. The branch prediction method according to claim 1, characterized in that: The method further comprises: When the count of the precision counter reaches the preset value, the number of instruction channels of the computing device and / or the capacity of the cache structure are increased to facilitate prefetching instructions; or, When the flushing condition is met, the number of instruction channels of the computing device and / or the capacity of the cache structure are reduced to suppress pre-fetching instructions.

8. The branch prediction method according to claim 7, characterized in that: The instruction channel includes a decoding bandwidth and / or a transmission bandwidth; and / or, The cache structure includes one or more of an instruction fetch target queue, an instruction queue, an issue queue and out-of-order resources.

9. A branch predictor, characterized in that: The branch predictor is configured to execute the branch prediction method according to any one of claims 1 to 8.

10. The branch predictor according to claim 9, characterized in that: The branch predictor includes a prediction control module and a prediction cache module, the prediction cache module is used to store branch information, the prediction control module is used to control the read and write access of the prediction cache module, read the branch information from the prediction cache module, infer branch prediction information based on the branch information, write the branch target address in the branch prediction information into the instruction fetch target queue, and receive training data, context switching information and prediction accuracy corresponding to the branch target address fed back by a downstream processing module.

11. A branch prediction system, characterized in that: The system includes a branch predictor, a precision counter, and an instruction fetch target queue; The branch predictor is used to use the first prediction pipeline to make predictions and obtain first branch prediction information; when a preset flushing condition is not met but a preset confidence condition is met, the precision counter is incremented; when the count of the precision counter reaches a preset value, the second prediction pipeline is activated to use the first prediction pipeline and the second prediction pipeline to make predictions at the same time, and obtain first branch prediction information corresponding to the first prediction pipeline and second branch prediction information corresponding to the second prediction pipeline; and, writing the branch target address in the branch prediction information into the instruction fetch target queue; the branch prediction information includes the first branch prediction information and the second branch prediction information; The instruction fetch target queue is used to decouple the prediction pipeline and the instruction cache pipeline, and the prediction pipeline includes the first prediction pipeline and the second prediction pipeline; Among them, the line brushing conditions include: the downstream processing module feedbacks misprediction and / or context switching; the confidence conditions include any one of the following: the predicted confidence is the first type of confidence; the predicted confidence is high confidence; the predicted confidence score is greater than the preset score.

12. A processor, characterized in that: The processor comprises the branch prediction system of claim 11.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions of the branch prediction method according to any one of claims 1 to 8.

Images