Display driving apparatus, display control apparatus thereof, and operation method thereof

Abstract

This invention provides a display driving device, a display control device, and an operating method thereof. The display control device includes a data analysis circuit and a data compensation circuit. The data analysis circuit performs arithmetic operations on multiple sub-pixel data output by the target driving channel of the source driver in the current frame to obtain the result value corresponding to the target driving channel. The data compensation circuit determines at least one compensated grayscale value corresponding to the result value. The compensated grayscale value is displayed by the target driving channel during a vertical blank period in the frame period, during which the current frame is displayed. The target driving channel of the source driver outputs at least one compensated voltage corresponding to the at least one compensated grayscale value during the vertical blank period in the frame period.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a display driving device, a display control device and an operating method thereof. Background Technology

[0002] For example, liquid crystal display (LCD) panels are widely used in current display devices. Inevitably, each pixel circuit in a display panel experiences leakage current. The lower the frame rate, the greater the leakage current in the pixel circuit. When the duration of each frame is the same, that is, when the frame rate is fixed, the leakage current of the same pixel circuit is approximately the same across different frames. Therefore, the leakage current in the pixel circuit is insufficient to cause flickering or color shift (or, the slight flickering or color shift caused by leakage current is tolerable).

[0003] When a display panel operates in variable refresh rate (VRR) mode, the duration of each frame may vary. When the frame rate dynamically changes, the leakage current of the same pixel circuit differs across frames, causing unacceptable flickering or color shift, thus affecting the image quality of the display panel. Improving the flickering or color shift caused by pixel circuit leakage is one of the many technical challenges in this field. Summary of the Invention

[0004] This invention provides a display driving device, a display control device, and an operating method thereof. The display control device is used to control the driving operation of the source driver on the display panel to improve flickering or color shift caused by leakage current in the pixel circuit.

[0005] In an embodiment of the present invention, the display control device includes a data analysis circuit and a data compensation circuit. The data analysis circuit performs arithmetic operations on a plurality of sub-pixel data output by the target drive channel of the source driver in the current frame to obtain a result value corresponding to the target drive channel. The data compensation circuit is coupled to the data analysis circuit to receive the result value. The data compensation circuit determines at least one compensated grayscale value corresponding to the result value, wherein the compensated grayscale value will be displayed by the target drive channel during a vertical blank period of the frame, during which the current frame is displayed. The target drive channel of the source driver outputs at least one compensated voltage corresponding to the at least one compensated grayscale value during the vertical blank period of the frame.

[0006] In an embodiment of the present invention, the above-described operation method includes: performing arithmetic operations on a plurality of sub-pixel data output by a target driving channel of a source driver in the current frame by a data analysis circuit of a display control device to obtain a result value corresponding to the target driving channel; and determining at least one compensated grayscale value corresponding to the result value by a data compensation circuit of the display control device. The compensated grayscale value is displayed by the target driving channel during a vertical blank period in the frame period, during which the current frame is displayed. The target driving channel of the source driver outputs at least one compensated voltage corresponding to the at least one compensated grayscale value during the vertical blank period in the frame period.

[0007] In an embodiment of the present invention, the display driving device includes a source driver and a display control device. The display control device is coupled to the source driver and is used to control the driving operation of the source driver. The display control device performs arithmetic operations on a plurality of sub-pixel data output by the target driving channel of the source driver in the current frame to obtain a result value corresponding to the target driving channel. The display control device determines at least one compensated grayscale value corresponding to the result value. The compensated grayscale value is displayed by the target driving channel during a vertical blank period of the frame period, during which the current frame is displayed. The target driving channel of the source driver outputs at least one compensated voltage corresponding to the at least one compensated grayscale value during the vertical blank period of the frame period.

[0008] Based on the above, the display control device described in the embodiments of the present invention can perform arithmetic operations on multiple sub-pixel data output by a target driving channel in the current frame to determine the compensation grayscale value corresponding to the target driving channel. During the vertical blank period of a frame period displaying the current frame, the target driving channel can output a compensation voltage corresponding to the compensation grayscale value to the display panel to minimize the leakage current of the sub-pixel circuit of the display panel. Therefore, the display control device can improve the flickering or color shift phenomenon caused by leakage current in the sub-pixel circuit. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention.

[0010] Figure 2 This is a circuit block diagram of a display control device according to an embodiment of the present invention.

[0011] Figure 3 This is a flowchart illustrating the operation method of a display control device according to an embodiment of the present invention.

[0012] Figure 4This is a circuit block diagram of a display control device according to another embodiment of the present invention.

[0013] Figure 5 This is a timing diagram illustrating, according to an embodiment of the present invention, the data compensation circuit changes the compensation grayscale value during the vertical blank period based on the change of frame rate.

[0014] Explanation of reference numerals in the attached figures

[0015] 10: Display panel

[0016] 100: Display driver

[0017] 110: Display control device

[0018] 111, 114: Data Analysis Circuits

[0019] 112, 115: Data compensation circuit

[0020] 113: Frame Rate Detection Circuit

[0021] 120: Source Driver

[0022] A1, A2, A3: Valid data period

[0023] F1, F2, F3: During the frame

[0024] Ga1, Ga2, Gb1, Gb2, Gb3, Gb4, Gb5: Compensation grayscale values

[0025] S310, S320, S330: Steps

[0026] t11, t21, t22, t23, t24, t25: Time points

[0027] VB1, VB2, VB3: Vertical Blank Period Detailed Implementation

[0028] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0029] The term "coupled (or connected)" as used throughout this application (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this application (including the claims) are used to name components or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments can be referred to mutually in the relevant descriptions.

[0030] Figure 1 This is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention. Figure 1 The illustrated display device includes a display panel 10 and a display driving device 100. This embodiment does not limit the implementation details of the display panel 10. Depending on the actual design, in some embodiments, the display panel 10 may include a liquid crystal display (LCD) panel or other display panels. The display driving device 100 is coupled to the display panel 10. The display driving device 100 can drive the display panel 10 to display images.

[0031] exist Figure 1 In the illustrated embodiment, the display driving device 100 may include a display control device 110 and a source driver 120. The display control device 110 is coupled to the source driver 120. The display control device 110 can control the source driver 120 to drive the display panel 10. This embodiment does not limit the implementation details of the operation of the source driver 120 driving the display panel 10. Depending on the actual design, in some embodiments, the source driver 120 may include a general source driver or other source drivers. In conjunction with the scanning timing of the display panel 10, the source driver 120 can drive the display panel 10 to display images.

[0032] Generally, the source driver 120 has multiple drive channels. Each of these drive channels is coupled to at least one corresponding data line of the display panel 10. For ease of explanation, one of these drive channels of the source driver 120 (hereinafter referred to as the target drive channel) will be used as an example below. The other drive channels of the source driver 120 can be described by analogy with the relevant description of the target drive channel, and will not be described in detail here.

[0033] The display control device 110 can perform arithmetic operations on multiple sub-pixel data output by a target driving channel of the source driver 120 in the current frame to obtain a result value corresponding to the target driving channel. For example, assuming a display panel with a 4K resolution (3840*2160 pixels), the target driving channel outputs 2160 sub-pixel data in the current frame. In some embodiments, the display control device 110 can perform one of the following arithmetic operations on these 2160 sub-pixel data output by the target driving channel in the current frame: an average operation, a median operation, or a root mean square operation, to obtain an average value, a median, or a root mean square value as the result value. Alternatively, the display control device 110 can select the maximum (or minimum) value from these 2160 sub-pixel data output by the target driving channel in the current frame as the result value.

[0034] The display control device 110 can determine at least one compensated grayscale value corresponding to the result value. The display control device 110 can output the at least one compensated grayscale value to the source driver 120 during a vertical blank period within a frame period of the current frame. The at least one compensated grayscale value will be displayed by the target drive channel during the vertical blank period of the frame period. The target drive channel of the source driver 120 can output at least one compensated voltage corresponding to the at least one compensated grayscale value to the display panel 10 during the vertical blank period.

[0035] Depending on different design requirements, the aforementioned display control device 110 can be implemented in hardware, firmware, software (i.e., program), or a combination of the above three. In hardware form, the display control device 110 can be implemented as logic circuits on an integrated circuit. The relevant functions of the display control device 110 can be implemented as hardware using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages. For example, the relevant functions of the display control device 110 can be implemented in various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or other processing units.

[0036] In software and / or firmware form, the functions of the display control device 110 can be implemented as programming codes. For example, the display control device 110 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored on a non-transitory readable medium. In some embodiments, the non-transitory readable medium includes, for example, semiconductor memory, programmable logic circuits, and / or storage devices. A central processing unit (CPU), controller, microcontroller, or microprocessor can read and execute the programming code from the non-transitory readable medium to implement the functions of the display control device 110.

[0037] Figure 2 This is a circuit block diagram of a display control device 110 according to an embodiment of the present invention. The display control device 110 is used to control the driving operation of the source driver 120. Figure 2 The display panel 10, display control device 110, and source driver 120 shown can be referenced. Figure 1 The descriptions of the display panel 10, display control device 110, and source driver 120 shown are omitted here. Figure 2In the illustrated embodiment, the display control device 110 includes a data analysis circuit 111 and a data compensation circuit 112.

[0038] Figure 3 This is a flowchart illustrating an operation method of a display control device according to an embodiment of the present invention. Please refer to... Figure 2 and Figure 3 In step S310, the data analysis circuit 111 can perform arithmetic operations on multiple sub-pixel data output by the target driving channel of the source driver 120 in the current frame to obtain the result value corresponding to the target driving channel. For example, suppose there are 2160 sub-pixel data output by the target driving channel in the current frame. In some embodiments, the data analysis circuit 111 can perform one of the following arithmetic operations on these 2160 sub-pixel data output by the target driving channel in the current frame: averaging, median, or root mean square (RMS) operation, to obtain the average, median, or RMS value as the result value. Alternatively, the data analysis circuit 111 can select the maximum (or minimum) value from these 2160 sub-pixel data output by the target driving channel in the current frame as the result value.

[0039] Data compensation circuit 112 is coupled to data analysis circuit 111 to receive the result value. In step S320, data compensation circuit 112 can determine at least one compensated grayscale value corresponding to the result value. The at least one compensated grayscale value will be displayed by the target drive channel of source driver 120 during a vertical blank period of a frame period displaying the current frame. In step S330, the target drive channel of source driver 120 outputs at least one compensation voltage corresponding to the at least one compensated grayscale value to display panel 10 during the vertical blank period of the frame period.

[0040] Based on the above, Figure 2 The display control device 110 can perform arithmetic operations on a target drive channel of the source driver 120 to determine at least one compensated grayscale value corresponding to the target drive channel. During the vertical blank period of a frame period displaying the current frame, the target drive channel of the source driver 120 can output at least one compensated voltage corresponding to the compensated grayscale value to the display panel 10 to minimize leakage current in the sub-pixel circuits of the display panel 10. Therefore, the display control device 110 can improve flickering or color shift caused by leakage current in the sub-pixel circuits of the display panel 10.

[0041] Figure 4 This is a circuit block diagram of a display control device 110 according to another embodiment of the present invention. The display control device 110 is used to control the driving operation of the source driver 120. Figure 4 The display panel 10, display control device 110, and source driver 120 shown can be referenced. Figure 1 The descriptions of the display panel 10, display control device 110, and source driver 120 shown are omitted here. Figure 4 In the illustrated embodiment, the display control device 110 includes a frame rate detection circuit 113, a data analysis circuit 114, and a data compensation circuit 115. Figure 4 The data analysis circuit 114 and data compensation circuit 115 shown can be referred to Figure 2 The relevant descriptions of the data analysis circuit 111 and the data compensation circuit 112 shown are provided, and analogies can be drawn from them. Alternatively, Figure 2 The data analysis circuit 111 and / or data compensation circuit 112 shown can be referred to Figure 4 The relevant descriptions of the data analysis circuit 114 and / or the data compensation circuit 115 shown are provided and can be extrapolated from there.

[0042] exist Figure 4 In the illustrated embodiment, the frame rate detection circuit 113 is coupled to the data compensation circuit 115. The frame rate detection circuit 113 can detect the frame rate. In other words, the frame rate detection circuit 113 can detect the length of the vertical blank period during a frame period of the currently displayed frame. The detection details of the frame rate detection circuit 113 are not limited here. According to practical design, in some embodiments, the frame rate detection circuit 113 can detect the period of the vertical synchronization signal to determine the frame rate. In other embodiments, the frame rate detection circuit 113 can detect the start time and end time of the vertical blank period to determine the length of the current vertical blank period, and then determine the frame rate based on the information of the length of the active data period (or display period) and the length of the current vertical blank period.

[0043] The frame rate detection circuit 113 provides the detection result (i.e., the frame rate) to the data compensation circuit 115. The data compensation circuit 115 determines whether the at least one compensated grayscale value is a single compensated grayscale value or multiple compensated grayscale values ​​based on the frame rate (as the detection result of the frame rate detection circuit 113). When the data compensation circuit 115 outputs a single compensated grayscale value to the source driver 120, the target drive channel of the source driver 120 outputs a grayscale voltage corresponding to the single compensated grayscale value to the display panel 10 during the blank period of the frame period. Furthermore, when the data compensation circuit 115 outputs multiple compensated grayscale values ​​to the source driver 120, the target drive channel of the source driver 120 outputs multiple compensated grayscale voltages corresponding to these compensated grayscale values ​​to the display panel 10 at different time points during the vertical blank period of the frame period. These different time points can be defined by the number of different line periods elapsed from the end of the valid data period (or the start time of the vertical blank period).

[0044] Figure 5 This is a timing diagram illustrating, according to an embodiment of the present invention, how the data compensation circuit 115 changes the compensation grayscale value during the vertical blank period based on the change of frame rate. Figure 5 The horizontal axis represents time. Figure 5 The diagram illustrates three frame periods, F1, F2, and F3. Frame period F1 includes a valid data period (or display period) A1 and a vertical blanking period VB1; frame period F2 includes a valid data period A2 and a vertical blanking period VB2; and frame period F3 includes a valid data period A3 and a vertical blanking period VB3. Figure 5 In the illustrated embodiment, the display panel 10 operates in variable refresh rate (VRR) mode, so the duration of different frames may be different, that is, the duration of the vertical blank period during different frames may be different.

[0045] Please refer to Figure 4 and Figure 5Assuming frame period F1 is the current frame, data analysis circuit 114 can perform arithmetic operations on multiple sub-pixel data output by the target drive channel of source driver 120 during the effective data period A1 of frame period F1 to obtain the result value corresponding to the target drive channel during the effective data period A1. Based on the result value corresponding to the effective data period A1, data compensation circuit 115 can determine the compensation grayscale value Ga1 corresponding to the result value of the effective data period A1, and provide the compensation grayscale value Ga1 to source driver 120. After the effective data period A1 ends, based on the compensation grayscale value Ga1 provided by data compensation circuit 115, the target drive channel of source driver 120 can output the compensation voltage corresponding to the compensation grayscale value Ga1 to display panel 10 during the vertical blank period (vertical blank period VB1) of frame period F1. Frame rate detection circuit 113 can provide the position of the pre-configured time point in the vertical blank period VB1 to data compensation circuit 115. When the time reaches point t11 ​​in the vertical blank period VB1, the data compensation circuit 115 can generate a compensation grayscale value Ga2 and provide the compensation grayscale value Ga2 to the source driver 120, so that the target drive channel of the source driver 120 can output the compensation voltage corresponding to the compensation grayscale value Ga2 to the display panel 10 after point t11, until the vertical blank period VB1 ends.

[0046] Similarly, assuming frame period F2 is the current frame, data analysis circuit 114 can perform arithmetic operations on multiple sub-pixel data output by the target driving channel of source driver 120 during the effective data period A2 of frame period F2 to obtain the result value corresponding to the target driving channel during the effective data period A2. Based on the result value corresponding to the effective data period A2, data compensation circuit 115 can determine the compensation grayscale value Gb1 corresponding to the result value of the effective data period A2, and provide the compensation grayscale value Gb1 to source driver 120. After the effective data period A2 ends, based on the compensation grayscale value Gb1 provided by data compensation circuit 115, the target driving channel of source driver 120 can output the compensation voltage corresponding to the compensation grayscale value Gb1 to display panel 10 during the vertical blank period VB2 of frame period F2.

[0047] The frame rate detection circuit 113 can provide the data compensation circuit 115 with the positions of multiple reconfiguration time points (e.g., t21-t24) during the vertical blank period VB2. When the time reaches time point t21 within the vertical blank period VB2, the data compensation circuit 115 can generate a compensation grayscale value Gb2 and provide the compensation grayscale value Gb2 to the source driver 120, so that the target drive channel of the source driver 120 can output the compensation voltage corresponding to the compensation grayscale value Gb2 to the display panel 10 after time point t21. When the time reaches time point t22 within the vertical blank period VB2, the data compensation circuit 115 can generate a compensation grayscale value Gb3 and provide the compensation grayscale value Gb3 to the source driver 120, so that the target drive channel of the source driver 120 can output the compensation voltage corresponding to the compensation grayscale value Gb3 to the display panel 10 after time point t22. When the time reaches point t23 within the vertical blank period VB2, the data compensation circuit 115 generates a compensation grayscale value Gb4 and provides it to the source driver 120. This allows the target drive channel of the source driver 120 to output a compensation voltage corresponding to the compensation grayscale value Gb4 to the display panel 10 after point t23. When the time reaches point t24 within the vertical blank period VB2, the data compensation circuit 115 generates a compensation grayscale value Gb5 and provides it to the source driver 120. This allows the target drive channel of the source driver 120 to output a compensation voltage corresponding to the compensation grayscale value Gb5 to the display panel 10 after point t24, until the vertical blank period VB2 ends. The longer the vertical blank period within the frame, the more compensation steps (achieved by the compensation grayscale value) the display control device can provide.

[0048] This embodiment does not limit the way the data compensation circuit 115 generates the compensation grayscale value. For example, in some embodiments, the data compensation circuit 115 can multiply the compensation grayscale value Gb1 by a coefficient g to generate the compensation grayscale value Gb2, that is, Gb2 = Gb1 * g. The coefficient g can be a real number determined according to the actual design. Similarly, the compensation grayscale value Gb3 can be the product of the compensation grayscale value Gb2 and the coefficient g, the compensation grayscale value Gb4 can be the product of the compensation grayscale value Gb3 and the coefficient g, and the compensation grayscale value Gb5 can be the product of the compensation grayscale value Gb4 and the coefficient g. In another embodiment, each of the compensation grayscale values ​​Gb2-Gb4 can be the product of the compensation grayscale value Gb1 and the corresponding coefficient.

[0049] In other embodiments, the data compensation circuit 115 can subtract (or add) a real number d from the compensation grayscale value Gb1 to generate the compensation grayscale value Gb2. The real number d can be determined according to the actual design. Similarly, the compensation grayscale value Gb3 can be the difference between the compensation grayscale value Gb2 and the real number d (or the sum of the compensation grayscale value Gb2 and the real number d), the compensation grayscale value Gb4 can be the difference between the compensation grayscale value Gb3 and the real number d (or the sum of the compensation grayscale value Gb3 and the real number d), and the compensation grayscale value Gb5 can be the difference between the compensation grayscale value Gb4 and the real number d (or the sum of the compensation grayscale value Gb4 and the real number d).

[0050] In some embodiments, the data compensation circuit 115 can look up the corresponding difference from a lookup table based on the position of a preset time point within the vertical blank period. For example, the lookup table may contain different differences for different time points. These differences in the lookup table can be multiple real numbers determined according to the actual design. Taking the vertical blank period VB2 as an example, when the current time point falls between time point t21 and time point t22, the data compensation circuit 115 can obtain the difference D1 from the lookup table. The data compensation circuit 115 can subtract (or add) the difference D1 to the compensation grayscale value Gb1 to generate the compensation grayscale value Gb2. When the current time point falls between time point t22 and time point t23, the data compensation circuit 115 can obtain the difference D2 from the lookup table. The compensation grayscale value Gb3 can be the difference between the compensation grayscale value Gb1 and the difference D2 (or the sum of the compensation grayscale value Gb1 and the difference D2). When the current time point falls between time point t23 and time point t24, the data compensation circuit 115 can obtain the difference D3 from the lookup table. The compensated grayscale value Gb4 can be the difference between the compensated grayscale value Gb1 and the difference D3 (or the sum of the compensated grayscale value Gb1 and the difference D3). When the current time point falls between time point t24 and time point t25, the data compensation circuit 115 can obtain the difference D4 from the lookup table. The compensated grayscale value Gb5 can be the difference between the compensated grayscale value Gb1 and the difference D4 (or the sum of the compensated grayscale value Gb1 and the difference D4).

[0051] In some embodiments, different time periods within a vertical blank period can have the same compensated grayscale value. Taking the vertical blank period VB2 as an example, the compensated grayscale values ​​Gb1, Gb2, Gb3, Gb4, and Gb5 can be the same for each other.

[0052] In summary, the display control device 110 described in the above embodiments can perform arithmetic operations on multiple sub-pixel data output by a target driving channel of the source driver 120 in the current frame to determine one (or more) compensation grayscale values ​​corresponding to this target driving channel. During the vertical blank period of the current frame, this target driving channel of the source driver 120 can output one (or more) compensation voltages corresponding to the compensation grayscale values ​​to the display panel 10 to minimize the leakage current of the sub-pixel circuit of the display panel 10. Therefore, the display control device 110 can improve the flickering or color shift phenomenon caused by the leakage current phenomenon of the sub-pixel circuit of the display panel 10.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display control device for controlling the driving operation of a source driver on a display panel, characterized in that, The display control device includes: A data analysis circuit is used to perform arithmetic operations on multiple sub-pixel data output by the target driving channel of the source driver in the current frame to obtain the result value corresponding to the target driving channel; and A data compensation circuit, coupled to the data analysis circuit to receive the result value, is used to determine a first compensation grayscale value corresponding to the result value and generate a second compensation grayscale value based on the first compensation grayscale value, causing the target driving channel of the source driver to output a compensation voltage corresponding to the first compensation grayscale value at a first time point during the vertical blank period of the frame in the current frame, and to output a compensation voltage corresponding to the second compensation grayscale value at a second time point later than the first time point during the vertical blank period.

2. The display control device according to claim 1, characterized in that, The data analysis circuit performs one of the following arithmetic operations on the multiple sub-pixel data output by the target driving channel in the current frame: averaging, median, or root mean square (RMS) operation, to obtain the average, median, or RMS value as the result value. Alternatively, the data analysis circuit selects the maximum or minimum value from the multiple sub-pixel data output by the target driving channel in the current frame as the result value.

3. The display control device according to claim 1, characterized in that, The display control device further includes: A frame rate detection circuit, coupled to the data compensation circuit, is used to detect the frame rate; The data compensation circuit determines, based on the frame rate, whether to generate only the first compensated grayscale value as a single compensated grayscale value or to generate multiple compensated grayscale values ​​including the first compensated grayscale value and the second compensated grayscale value.

4. The display control device according to claim 3, characterized in that, The frame rate detection circuit detects the period of the vertical synchronization signal to determine the frame rate.

5. The display control device according to claim 3, characterized in that, The frame rate detection circuit detects the start time and end time of the vertical blank period to determine the frame rate.

6. A method for operating a display control device, characterized in that, The operation method includes: The data analysis circuit of the display control device performs arithmetic operations on multiple sub-pixel data output by the target drive channel of the source driver in the current frame to obtain the result value corresponding to the target drive channel; and The data compensation circuit of the display control device determines the first compensation grayscale value corresponding to the result value, and generates a second compensation grayscale value based on the first compensation grayscale value. The source driver's target drive channel outputs the compensation voltage corresponding to the first compensation grayscale value at a first point in the vertical blank period during the current frame, and outputs the compensation voltage corresponding to the second compensation grayscale value at a second point in the vertical blank period later than the first point.

7. The operating method according to claim 6, characterized in that, The operation method further includes: The arithmetic operation is performed on the plurality of sub-pixel data output by the target driving channel in the current frame. One of the following operations—averaging, median, or root mean square (RMS)—is used as the arithmetic operation to obtain the average, median, or RMS value as the result value. The maximum or minimum value is selected from the plurality of sub-pixel data output by the target driving channel in the current frame as the result value.

8. The operating method according to claim 6, characterized in that, The operation method further includes: The frame rate is detected by the frame rate detection circuit of the display control device; and Based on the frame rate, it is determined whether to generate only the first compensated grayscale value as a single compensated grayscale value or to generate multiple compensated grayscale values ​​including the first compensated grayscale value and the second compensated grayscale value.

9. The operating method according to claim 8, characterized in that, The operation method further includes: The period of the vertical synchronization signal is detected to determine the frame rate.

10. The operating method according to claim 8, characterized in that, The operation method further includes: The start time and end time of the vertical blank period are detected to determine the frame rate.

11. A display driving device, characterized in that, The display driving device includes: Source driver; and A display control device, coupled to the source driver, is used to control the driving operation of the source driver on the display panel. The display control device performs arithmetic operations on multiple sub-pixel data output by the target driving channel of the source driver in the current frame to obtain a result value corresponding to the target driving channel. The display control device determines a first compensation grayscale value corresponding to the result value and generates a second compensation grayscale value based on the first compensation grayscale value. This causes the target driving channel of the source driver to output a compensation voltage corresponding to the first compensation grayscale value at a first time point during the vertical blank period of the frame in the current frame, and outputs a compensation voltage corresponding to the second compensation grayscale value at a second time point later than the first time point during the vertical blank period.

12. The display driving device according to claim 11, characterized in that, The display control device includes: A data analysis circuit is configured to perform the arithmetic operation on the plurality of sub-pixel data output by the target driving channel in the current frame to obtain the result value; and A data compensation circuit, coupled to the data analysis circuit, receives the result value and determines at least one compensation grayscale value corresponding to the result value.

13. The display driving device according to claim 12, characterized in that, The data analysis circuit performs one of the following arithmetic operations on the multiple sub-pixel data output by the target driving channel in the current frame: averaging, median, or root mean square (RMS) operation, to obtain the average, median, or RMS value as the result value. Alternatively, the data analysis circuit selects the maximum or minimum value from the multiple sub-pixel data output by the target driving channel in the current frame as the result value.

14. The display driving device according to claim 12, characterized in that, The display control device further includes: A frame rate detection circuit, coupled to the data compensation circuit, is used to detect the frame rate; The data compensation circuit determines, based on the frame rate, whether to generate only the first compensated grayscale value as a single compensated grayscale value or to generate multiple compensated grayscale values ​​including the first compensated grayscale value and the second compensated grayscale value.

15. The display driving device according to claim 14, characterized in that, The frame rate detection circuit detects the current period of the vertical synchronization signal to determine the frame rate.

16. The display driving device according to claim 14, characterized in that, The frame rate detection circuit detects the start time and end time of the vertical blank period to determine the frame rate.

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