A method of fabricating a vertical channel metal oxide transistor

Abstract

The application discloses a method for preparing a vertical channel metal oxide semiconductor transistor and belongs to the technical field of semiconductors. Firstly, a silicon oxide isolation layer is etched by RIE to form a groove, and then a source electrode, a drain electrode, an active layer, a gate dielectric layer and a metal gate electrode are prepared respectively to obtain a series connection vertical channel oxide transistor controlled by a gate electrode located in the groove. The application can avoid the generation of a source-drain overlapping area and the parasitic capacitance caused by the source-drain overlapping area, and can form the series connection of two transistors through one-time photolithography.

Description

Technical Field

[0001] This invention relates to a method for fabricating vertical channel metal-oxide-semiconductor transistors, belonging to the semiconductor industry and semiconductor process field. Background Technology

[0002] As the feature size of advanced semiconductor processes continues to shrink to the physical limits of both practice and theory, how to extend Moore's Law (manufacturing higher integration density at lower costs) has become a crucial topic of concern in the integrated circuit industry. According to the International Device and System Roadmap (IRDS), More Moore, More than Moore, and Beyond CMOS will be the future development and research directions for the integrated circuit industry and academia. Monolithic heterogeneous integration of different functions such as memory, sensing, and logic computing is one of the main contents of the "More than Moore" direction. A possible specific implementation direction for monolithic heterogeneous integration is functional integration in the back end of the line. Metal-oxide-semiconductor (MOSFET) technology, represented by IGZO, has the advantages of low fabrication temperature and low leakage current. Its fabrication temperature of less than 300 degrees Celsius is compatible with copper-interconnect-based back end processes. Therefore, back end compatible MOSFET transistors have become a research focus for both academia and industry. Compared to planar vertical channel transistors, they have advantages such as "higher aspect ratio", "feature size not limited by photolithography conditions", and "easy to integrate in three dimensions", making them one of the research objects in academia. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a vertical channel oxide transistor, which has the advantage of being three-dimensionally integrated.

[0004] The technical solution of the present invention is as follows:

[0005] A method for fabricating a vertical channel oxide transistor specifically includes the following steps:

[0006] 1) A silicon oxide isolation layer is formed on the surface of a single-crystal silicon by photolithography lift-off;

[0007] 2) Spin-coat photoresist onto the surface of the silicon oxide isolation layer, use the photoresist as a mask, and etch the silicon oxide isolation layer with RIE to form a trench. The trench has the same depth as the silicon oxide isolation layers on both sides, and the width of the trench is 100nm to 10μm; the length is 50nm to 10μm, and the ratio of the length of the silicon oxide isolation layers on both sides to the length of the trench is 5:1 to 100:1.

[0008] 3) Sputter-grow metal layers on the trenches and the silicon oxide isolation layers on both sides;

[0009] 4) Reactive ion etching (RIE) is used to etch the metal layer to ensure that no metal remains on the trench sidewalls. The metal layers on the bottom of the trench and the silicon oxide isolation layers on both sides serve as source / drain electrodes.

[0010] 5) The active layer film is grown by ALD and then photolithographically stripped to cover the entire trench and the metal layer covering the silicon oxide isolation layers on both sides.

[0011] 6) The gate dielectric layer film is grown by ALD and then covered on the active layer film by photolithography stripping.

[0012] 7) A metal gate electrode layer is sputtered and then photolithographically stripped to cover the gate dielectric layer, thereby forming a series vertical channel oxide transistor located on both sides of the gate control in the trench.

[0013] Further, in step 1), a silicon oxide isolation layer is generated by PECVD. The material of the silicon oxide isolation layer is silicon oxide, silicon nitride, or silicon oxynitride, and its thickness determines the channel length, with a thickness range of 50 nm to 1 μm.

[0014] Furthermore, the reactive ion etching (RIE) gas in step 2) is SF6 or CHF3.

[0015] Furthermore, in step 3), PVD sputtering is used, and the metal layer material can be molybdenum, tungsten, titanium, gold, titanium nitride, etc., with a thickness ranging from 20 nm to 100 nm.

[0016] Furthermore, the reactive ion etching (RIE) gas in step 4) is SF6 or CHF3, and the thickness of the remaining metal layer at the bottom of the trench and on the upper side of the silicon oxide isolation layer ranges from 10 nm to 50 nm.

[0017] Furthermore, the active layer grown by ALD in step 5) can be a metal oxide semiconductor such as IGZO, ITO, IZO, or AZO, with a thickness ranging from 5 nm to 50 nm.

[0018] Furthermore, the gate dielectric material grown by ALD in step 6) can be HfO2, Al2O3, SiO2, etc., with a thickness ranging from 5nm to 50nm.

[0019] Further, in step 7), PVD sputtering is used, and the sputtered metal electrode can be molybdenum, tungsten, titanium, gold, titanium nitride, etc., with a thickness ranging from 20 to 100 nm.

[0020] The beneficial effects of this invention are as follows:

[0021] This invention can form two transistors in series in a single photolithography process, and form a series vertical channel oxide transistor on both sides of the gate control by trench filling and etching, which can avoid the generation of source-drain overlap region and the resulting source-drain parasitic capacitance. Attached Figure Description

[0022] Figure 1 — Figure 7 This is a schematic diagram of the process flow of the present invention;

[0023] Wherein, 1—source / drain electrode; 2—silicon oxide isolation layer; 3—active layer thin film; 4—gate dielectric layer thin film; 5—gate electrode layer. Detailed Implementation

[0024] The present invention will be further described below with reference to the accompanying drawings and examples. It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

[0025] The method for fabricating a vertical channel oxide transistor provided by this invention specifically includes the following steps:

[0026] 1) A silicon oxide isolation layer is formed on the surface of single-crystal silicon by photolithography lift-off, such as... Figure 1 As shown; its thickness determines the channel length, and the thickness ranges from 50 nm to 1 μm;

[0027] 2) Spin-coat photoresist onto the silicon oxide surface, and use the photoresist as a mask to etch trenches into the silicon oxide using RIE (Reverse Etching). Figure 2 As shown; the width of the trench is 100nm to 10μm; the length is 50nm to 10μm; the depth of the trench is consistent with that of the silicon oxide isolation layers on both sides; and the ratio of the width of the silicon oxide isolation layers on both sides to the width of the trench is 5:1 to 100:1.

[0028] 3) The sputtered metal layer partially fills the trench, such as... Figure 3 As shown; the metal layer material can be molybdenum, tungsten, titanium, gold, titanium nitride, etc., and its thickness ranges from 20nm to 100nm;

[0029] 4) Reactive ion etching (RIE) of metal: Ensuring no metal residue remains on the trench sidewalls, a metal layer (10nm–50nm thick) is placed at the bottom of the trench and on the silicon oxide isolation layers on both sides, serving as the source / drain electrodes. Figure 4 As shown;

[0030] 5) An active layer thin film is grown using ALD, with a thickness ranging from 5 nm to 50 nm. This active layer thin film covers the silicon oxide isolation layers inside the trench and on both sides of the trench, such as... Figure 5 As shown, after photolithography stripping, the active layer film covers the entire trench and the metal layer covering the silicon oxide isolation layers on both sides;

[0031] 6) An ALD-grown gate dielectric film, with a thickness ranging from 5 nm to 50 nm, covers the silicon oxide isolation layers inside the trench and on both sides of the trench, such as... Figure 6 As shown, after photolithography stripping, the gate dielectric layer film is covered on the active layer film;

[0032] 7) A metal gate electrode layer with a thickness ranging from 20 to 100 nm is sputtered and grown on the silicon oxide isolation layers on both sides of the trench, such as... Figure 7 As shown, after photolithography stripping, the metal gate electrode layer is covered with a thin film of the gate dielectric layer, thereby forming a series vertical channel oxide transistor located on both sides of the gate control in the trench.

[0033] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a vertical channel oxide transistor, characterized in that, Specifically, the following steps are included: 1) A silicon oxide isolation layer is formed on the surface of a single-crystal silicon by photolithography lift-off; 2) Spin-coat photoresist onto the surface of the silicon oxide isolation layer, use the photoresist as a mask, and etch the silicon oxide isolation layer with RIE to form a trench. The trench has the same depth as the silicon oxide isolation layers on both sides, and the width of the trench is 100nm to 10μm; the length is 50nm to 10μm, and the ratio of the length of the silicon oxide isolation layers on both sides to the length of the trench is 5:1 to 100:

1. 3) Sputter-grow metal layers on the trenches and the silicon oxide isolation layers on both sides; 4) Reactive ion etching (RIE) is used to etch the metal layer to ensure that no metal remains on the trench sidewalls. The metal layers on the bottom of the trench and the silicon oxide isolation layers on both sides serve as source / drain electrodes. 5) The active layer film is grown by ALD and then photolithographically stripped to cover the entire trench and the metal layer covering the silicon oxide isolation layers on both sides. 6) The gate dielectric layer film is grown by ALD and then covered on the active layer film by photolithography stripping. 7) A metal gate electrode layer is sputtered and then photolithographically stripped to cover the gate dielectric layer, thereby forming a series vertical channel oxide transistor located on both sides of the gate control in the trench.

2. The method for fabricating a vertical channel oxide transistor as described in claim 1, characterized in that, Step 1) A silicon oxide isolation layer is generated by PECVD. The material of the silicon oxide isolation layer is silicon oxide, silicon nitride or silicon oxynitride, and its thickness determines the channel length. The thickness range is 50nm to 1μm.

3. The method for fabricating a vertical channel oxide transistor as described in claim 1, characterized in that, The gases used in the reactive ion etching (RIE) step 2) are SF6 and CHF3.

4. The method for fabricating a vertical channel oxide transistor as described in claim 1, characterized in that, Step 3) Use PVD sputtering, with the metal layer material being molybdenum, tungsten, titanium, gold, or titanium nitride, and its thickness ranging from 20 nm to 100 nm.

5. The method for fabricating a vertical channel oxide transistor as described in claim 1, characterized in that, Step 4) The gases used in the reactive ion etching are SF6 and CHF3, and the thickness of the remaining metal layer at the bottom of the trench and on the upper side of the silicon oxide isolation layer ranges from 10 nm to 50 nm.

6. The method for fabricating a vertical channel oxide transistor as described in claim 1, characterized in that, Step 5) The active layer film grown by ALD is IGZO, ITO, IZO or AZO metal oxide semiconductor, and its thickness ranges from 5nm to 50nm.

7. The method for fabricating a vertical channel oxide transistor as described in claim 1, characterized in that, Step 6) The gate dielectric layer film grown by ALD is HfO2, Al2O3 or SiO2, and its thickness ranges from 5nm to 50nm.

8. The method for fabricating a vertical channel oxide transistor as described in claim 1, characterized in that, Step 7) Use PVD sputtering. The metal gate electrode layer material is molybdenum, tungsten, titanium, gold or titanium nitride, and its thickness ranges from 20 to 100 nm.

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