Devices including vertical transistors and related methods

Abstract

This application relates to an apparatus and related methods comprising a vertical transistor. An apparatus includes a first conductive line and a vertical transistor above the first conductive line. The vertical transistor includes: a gate electrode; a gate dielectric material overlying a side of the gate electrode; and a channel region on the side of the gate dielectric material, the gate dielectric material being positioned between the channel region and the gate electrode. The apparatus further includes a second conductive line overlying conductive contacts of the at least one vertical transistor. Related apparatus and methods for forming the apparatus are also disclosed.

Description

[0001] Divisional application information

[0002] This application is a divisional application of the application for patent having application number 201980071020.9, filed on October 8, 2019, entitled “Semiconductor Devices Including Vertical Transistors, and Related Methods.”

[0003] Priority claim

[0004] This application claims the benefit of the filing date of U.S. Provisional Patent Application Serial No. 62 / 743,078, filed on October 9, 2018, for “Semiconductor Devices Including Vertical Transistors, and Related Methods.” TECHNICAL FIELD

[0005] Embodiments disclosed herein relate to semiconductor devices including vertical transistors and related methods. More particularly, embodiments of the invention relate to semiconductor devices including vertical transistors and related methods, the vertical transistors including gate electrodes surrounded by gate dielectric material and having channel regions disposed on sides of the gate dielectric material, the gate electrodes being located between the channel regions. BACKGROUND

[0006] Manufacture of semiconductor devices includes forming transistors that can be used to access memory components of memory cells of, for example, semiconductor devices. The transistors include channel regions comprising semiconductor material formulated and configured to conduct current in response to an applied threshold voltage and impede current flow in the absence of the threshold voltage.

[0007] In semiconductor devices including vertical memory cells, transistors associated with the vertical memory cells can be vertical. Forming such transistors includes stacking materials that will eventually form the vertical memory cells, the materials including source and drain contacts, channel regions, and gate electrode material. The stacked materials are patterned to form pillars including the stack of materials.

[0008] Channel regions of vertical transistors include semiconductor material. Forming pillars including semiconductor material of channel regions can include patterning the semiconductor material, for example, by exposing the semiconductor material to one or more etching chemistries. However, some semiconductor materials conventionally used in vertical transistors exhibit high off-current (Ioff) that can affect charge retention, current flow, and other electrical properties of adjacent vertical transistors. offFor example, when accessing an adjacent vertical transistor, the high off-state current of a vertical transistor can affect (e.g., disturb) conditions of the adjacent vertical transistor.

[0009] Replacements of conventional semiconductor materials in the channel region have proven difficult. For example, some semiconductor materials are sensitive to exposure to hydrogen and degrade in response to exposure to hydrogen-containing materials. Thus, exposing such semiconductor materials to one or more etch chemistries that include hydrogen-containing materials can have undesirable negative effects on the electrical and material properties of the semiconductor materials. Exposure of semiconductor materials to etch chemistries, such as hydrogen-containing plasmas, can affect the electrical properties of the semiconductor materials, thereby affecting current flow through the channel material formed of the semiconductor material, and ultimately affecting the performance of the associated transistor. Additionally, such semiconductor materials can also exhibit low threshold voltages (V t) , and thus require large negative voltages when the transistor is in an off state.

[0010] Additionally, conventional processes of forming memory cells often include performing a hydrogen anneal process in which one or more features of the fabricated memory cell are exposed to hydrogen while annealing at a low temperature (e.g., less than 450 °C). However, during the hydrogen anneal process, hydrogen can diffuse into the channel region of the access device of the memory cell, thereby degrading the performance and / or reliability of the resulting memory device. SUMMARY

[0011] Embodiments disclosed herein relate to devices including vertical transistors and related methods. For example, according to one embodiment, a device includes a first conductive line, a vertical transistor over the first conductive line, and a second conductive line overlying a conductive contact of the vertical transistor. The vertical transistor includes a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on a side of the gate dielectric material, the gate dielectric material positioned between the channel region and the gate electrode.

[0012] According to an additional embodiment, a method of forming a semiconductor device includes forming a first conductive line, forming a vertical transistor over the first conductive line, and forming a second conductive line over the vertical transistor. Forming the vertical transistor includes forming a gate electrode extending in a direction, forming a gate dielectric material adjacent to a first side of the gate electrode and adjacent to a second side of the gate electrode, and forming a channel region adjacent to the gate dielectric material adjacent to the first side of the gate electrode and adjacent to the gate dielectric material adjacent to the second side of the gate electrode after forming the gate electrode.

[0013] Further embodiments include a device including a vertical transistor, the vertical transistor comprising: a gate electrode; a first channel region on a first side of the gate electrode; a second channel region on a second side of the gate electrode, the second side opposite the first side; and a gate dielectric between the first channel region and the gate electrode and between the second channel region and the gate electrode. The device further includes a conductive material on sides of the first channel region and the second channel region, the conductive material electrically isolated from the first channel region and the second channel region by an electrically insulative material.

[0014] Still other embodiments relate to a method of operating a device. The method includes applying a bias voltage to a gate electrode of a device including a vertical transistor and applying another bias voltage to a conductive material located between the transistor and at least another transistor of the device. The vertical transistor includes a gate electrode, a gate dielectric material on at least opposite sides of the gate electrode, and a channel material on sides of the gate dielectric material, the gate electrode located between different portions of the channel material.

[0015] Additional embodiments include an electronic device comprising: at least one input device; at least one output device; at least one processor device operably coupled to the at least one input device and the at least one output device; and a device operably coupled to the at least one processor device. The device includes an array of vertical transistors. At least one of the vertical transistors of the array of vertical transistors includes: a gate electrode separated from an underlying conductive contact by a gate dielectric material overlying sidewalls of the gate electrode; a first channel region on a lateral side of the gate dielectric material; and a second channel region on a lateral side of the gate dielectric material opposite the lateral side of the first channel region, the gate electrode located between the first channel region and the second channel region. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1A is a simplified cross-sectional perspective view of a semiconductor device including a vertical transistor according to embodiments of the present disclosure;

[0017] Figure 1B is a simplified cross-sectional perspective view of a semiconductor device including a vertical transistor according to embodiments of the present disclosure; Figure 1A is a simplified cross-sectional perspective view of a semiconductor device including a vertical transistor according to embodiments of the present disclosure; Figure 1A is a simplified top cross-sectional view of a semiconductor device including a vertical transistor according to embodiments of the present disclosure;

[0018] Figure 1C is a simplified cross-sectional view of a channel region according to embodiments of the present disclosure;

[0019] Figures 2A to 2K A method of forming a semiconductor device is described in accordance with embodiments of the application; and

[0020] Figure 3 is a schematic block diagram of an electronic system in accordance with embodiments of the application. DETAILED DESCRIPTION

[0021] The description contained herein does not intend to be an actual view of any particular system, semiconductor structure, or semiconductor device, but is merely a conceptualized representation used to describe the embodiments herein. Commonly shared elements and features in the figures can retain the same numerical designation, except where: for ease of following the description, for the most part, element symbols begin with the number of the figure on which the element is introduced or most fully described.

[0022] The following description provides specific details, such as material types, material thicknesses, and processing conditions, in order to provide a thorough description of the embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein can be practiced without employing these specific details. Indeed, the embodiments can be practiced in conjunction with conventional manufacturing techniques employed in the semiconductor industry. Additionally, the description provided herein does not form a complete description of a vertical transistor, a semiconductor device including a vertical transistor, or a complete description of a process flow for fabricating such a vertical transistor or semiconductor device. The structures described below do not form a complete semiconductor device structure. Only the process acts and structures needed to understand the embodiments described herein are described in detail below. Additional acts to form a complete semiconductor device or vertical transistor can be performed by conventional techniques.

[0023] As used herein, the terms "longitudinal," "vertical," "lateral," and "horizontal" relate to a major plane of a substrate (e.g., base material, base structure, base configuration, etc.) in or on which one or more structures and / or features are formed and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate that has a relatively large area compared to other surfaces of the substrate.

[0024] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes to an extent that a person of ordinary skill in the art would understand that the given parameter, property, or condition is met to a degree of divergence (e.g., within acceptable tolerances). By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition can be met at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0025] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and a degree of variance from the numerical value that would be appreciated by one of ordinary skill in the art in the pertinent art as being within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value can include additional numerical values within a range of 90.0% to 110.0% of the numerical value, such as within a range of 95.0% to 105.0% of the numerical value, within a range of 97.5% to 102.5% of the numerical value, within a range of 99.0% to 101.0% of the numerical value, within a range of 99.5% to 100.5% of the numerical value, or within a range of 99.9% to 100.1% of the numerical value.

[0026] As used herein, spatially relative terms, such as "beneath", "below", "lower", "bottom", "above", "upper", "top", "front", "rear", "left", "right", and the like, can be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the drawings. For example, if a material in the figures is inverted, then an element described as "below" or "beneath" or "lower" of other elements or features would then be oriented "above" or "upper" relative to the other elements or features. Thus, a material can be oriented in any direction and terms used herein to describe such an orientation, such as "below", can encompass various orientations of materials unless otherwise specified or unless the context of the description dictates otherwise. The materials can be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptions used herein interpreted accordingly.

[0027] As used herein, the term "electrically conductive material" means and includes: a material comprising tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, a metal alloy; a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide); a material comprising at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof; an electrically conductive doped semiconductor material (e.g., electrically conductive doped silicon, electrically conductive doped germanium, electrically conductive doped silicon germanium, etc.); polysilicon; other materials that exhibit electrical conductivity; or combinations thereof.

[0028] According to embodiments described herein, a semiconductor device includes an array of vertical transistors. The vertical transistors include vertically oriented channel regions positioned on a side of a gate electrode. In other words, a gate electrode of a vertical transistor can be positioned between vertically oriented channel regions of the vertical transistor. A gate dielectric material is positioned between each of the channel regions and the gate electrode. In some embodiments, the gate electrode is positioned at a laterally central location of the vertical transistor. Because the gate electrode is positioned in the center of the channel regions, the gate electrode has a relatively large thickness compared to a transistor having channel regions positioned in the center of the vertical transistor for the same pitch of the vertical transistor. Because the gate electrode has a larger thickness than a conventional vertical transistor having the same pitch, the gate electrode can exhibit a reduced resistivity. Thus, the vertical transistor can exhibit a reduced RC (e.g., the product of the resistance of a word line and the capacitance of the word line (e.g., inter-word line capacitance)) value, which can be inversely proportional to the switching speed of the vertical transistor. In some embodiments, the vertical transistor exhibits an RC value that is about 1.8 times smaller than the RC value of a conventional vertical transistor having the same pitch as the vertical transistor disclosed herein. Thus, the vertical transistor can exhibit a switching speed that is about 1.8 times faster than the switching speed of a conventional vertical transistor. In some embodiments, a conductive material can be positioned between adjacent vertical transistors and can be configured to be electrically biased. Biasing the conductive material can reduce or prevent so-called "word line interference," in which the gate electrode (e.g., word line) of one vertical transistor affects the gate electrode of an adjacent vertical transistor when a voltage is applied to the word line of the one vertical transistor. Additionally, a voltage applied to the conductive material can affect the threshold voltage of an adjacent vertical memory cell.

[0029] Figure 1A is a simplified cross-sectional perspective view of a semiconductor device 100 according to embodiments of the present disclosure. Figure 1B is a simplified plan cross-sectional view of the semiconductor device 100 of Figure 1A taken along cross-sectional line B-B of Figure 1A is a simplified plan cross-sectional view of the semiconductor device 100 of The substrate 102 can be a base material or structure on which additional materials are formed. The substrate 102 can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate on which one or more layers, structures, or regions are formed. The substrate 102 can be a conventional silicon substrate or other bulk substrate that includes a layer of semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates (such as a sapphire-on-silicon ("SOS") substrate and a glass-on-silicon ("SOG") substrate), an epitaxial layer of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials (such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). The substrate 102 can be doped or undoped.

[0030] Referring Figure 1A and Figure 1B , the vertical transistors 110 can be arranged in rows (e.g., extending in the x-direction) and columns (e.g., extending in the y-direction). In some embodiments, the rows can be substantially perpendicular to the columns. However, the disclosure is not so limited and the vertical transistors 110 can be arranged in a pattern other than that illustrated in Figure 1A and Figure 1B . Although Figure 1B only six vertical transistors are illustrated, the disclosure is not so limited. For example, the semiconductor device 100 can include any number of vertical transistors 110, such as about 1,000 or more vertical transistors 110, about 10,000 or more vertical transistors 110, or about 100,000 or more vertical transistors 110.

[0031] As shown in Figure 1A , the vertical transistors 110 can include a first conductive line 104 over at least a portion of the substrate 102. In some embodiments, the first conductive line 104 can be arranged in rows extending in a first direction (e.g., the x-direction) along the substrate 102. In some such embodiments, each of the first conductive lines 104 can be in electrical communication with the vertical transistors 110 of a row of vertical transistors 110. In some embodiments, the first conductive lines 104 can be referred to herein as digit lines. In other embodiments, the first conductive lines 104 can be referred to as source lines.

[0032] The first conductive lines 104 can include tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, a metal alloy; a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide); a material including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), an alloy thereof; a conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.); polysilicon; other materials that exhibit electrical conductivity; or combinations thereof. In some embodiments, the first conductive lines 104 comprise tungsten. In other embodiments, the first conductive lines 104 comprise ruthenium.

[0033] The first conductive lines 104 of adjacent rows can be electrically isolated from one another, e.g., by an electrically insulative material 128, e.g., the electrically insulative material 128 can include: a phosphosilicate glass, a borosilicate glass, a borophosphosilicate glass (BPSG), a fluorosilicate glass, silicon dioxide, a nitride material (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride), a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), a dielectric carbonoxynitride material (e.g., silicon carbonoxynitride (SiOCN)), a high-k dielectric material (e.g., aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), titanium oxide (TiO2)), another material, or a combination thereof. In some embodiments, the electrically insulative material 128 includes silicon dioxide.

[0034] The vertical transistors 110 can include a lower conductive contact 105, e.g., the lower conductive contact 105 can include one of a source contact or a drain contact of the vertical transistor 110. The lower conductive contact 105 of the vertical transistor 110 can be in electrical communication with the respective first conductive line 104. The lower conductive contact 105 can include an electrically conductive material. In some embodiments, the lower conductive contact 105 includes the same material as the first conductive line 104.

[0035] In some embodiments, the electrically insulative material 124 can electrically isolate the lower conductive contact 105 of a vertical transistor 110 from the lower conductive contact 105 of an adjacent vertical transistor 110. For example, the electrically insulative material 124 can include: a phosphosilicate glass, a borosilicate glass, a borophosphosilicate glass (BPSG), a fluorosilicate glass, silicon dioxide, a nitride material (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride), another dielectric material, a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), a dielectric carbonoxynitride material (e.g., silicon carbonoxynitride (SiOCN)), a high-k dielectric material (e.g., aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), titanium oxide (TiO2)), another material, or a combination thereof. In other embodiments, the semiconductor device 100 can not include the electrically insulative material 124 and adjacent vertical transistors 110 can be sufficiently electrically isolated, e.g., by the electrically insulative material 106 as will be described herein.

[0036] Each vertical transistor 110 can include a gate electrode 108 surrounded on at least some sides thereof by a gate dielectric material 112. The gate electrode 108 can also be referred to herein as a word line of the vertical transistor 110. Referring to Figure 1B , the gate electrode 108 can extend as a line extending in, e.g., the y-direction.

[0037] The gate electrodes 108 can include an electrically conductive material, such as, for example, tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys; metal- containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); materials including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof; electrically conductive doped semiconductor materials (e.g., electrically conductive doped silicon, electrically conductive doped germanium, electrically conductive doped silicon germanium, etc.); polysilicon; other materials that exhibit electrical conductivity; or combinations thereof.

[0038] The thickness T1 of the gate electrodes 108 can be between about and about , such as between about and about , between about and about , between about and about , or between about and about .

[0039] The semiconductor device 100 can include electrically conductive contacts 109 Figure 1B in electrical communication with the gate electrodes 108. In some embodiments, each column of vertical transistors 110 Figure 1A may include at least one electrically conductive contact 109 in electrical communication with the gate electrodes 108 of its corresponding column. The electrically conductive contacts 109 can include an electrically conductive material, such as, for example, tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys; metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); materials including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof; electrically conductive doped semiconductor materials (e.g., electrically conductive doped silicon, electrically conductive doped germanium, electrically conductive doped silicon germanium, etc.); polysilicon; other materials that exhibit electrical conductivity; or combinations thereof. In some embodiments, the electrically conductive contacts 109 include the same material as the gate electrodes 108. In other embodiments, the electrically conductive contacts 109 include a different material than the material of the gate electrodes 108.

[0040] In some embodiments, the electrically conductive contacts 109 are in electrical communication with a voltage source configured to provide a suitable voltage (e.g., a bias voltage) to the gate electrodes 108 associated with the electrically conductive contacts 109.

[0041] A gate dielectric material 112 can be disposed around at least some sides of the gate electrode 108. The gate dielectric material 112 can extend along and adjacent to the gate electrode 108. In some embodiments, the gate dielectric material 112 extends linearly adjacent to the gate electrode 108. The gate dielectric material 112 can be positioned on at least one side of the gate electrode 108. In some embodiments, the gate dielectric material 112 can be positioned adjacent to the gate electrode 108 at opposite sides thereof. In some embodiments and with reference to Figure 1A and Figure 1B , the gate dielectric material 112 can be positioned above and below the gate electrode 108 Figure 1A and on at least two lateral sides (e.g., sides in the x-direction) of the gate electrode 108. As will be described herein, in some embodiments, an electrically insulative material 106, which can comprise the same material as the gate dielectric material 112, can be disposed on at least two other lateral sides (e.g., sides in the y-direction) of the gate electrode 108. In some such embodiments, the gate electrode 108 can be substantially surrounded by dielectric material on all sides thereof (e.g., above, below, left, right, front, back, etc.).

[0042] The gate dielectric material 112 can comprise one or more electrically insulative materials, such as, for example, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride), another gate dielectric material, a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), a dielectric carbonoxynitride material (e.g., silicon carbonoxynitride (SiOCN)), another material, or a combination thereof. In some embodiments, the gate dielectric material 112 comprises silicon dioxide.

[0043] The gate dielectric material 112 can have a thickness T2 between about and about (e.g., between about and about , between about and about , between about and about , or between about and about . In some embodiments, the distance between the upper surface of the gate electrode 108 and the upper surface of the channel region 118 can be tailored by adjusting the thickness of the gate dielectric material 112.

[0044] The vertical transistor 110 can further include an upper conductive contact 114 overlying the gate electrode 108 and the gate dielectric material 112. In some embodiments, the upper conductive contact 114 can include one of a source contact or a drain contact of the vertical transistor 110 (while the lower conductive contact 105 comprises the other of the source contact or the drain contact). The upper conductive contact 114 can include a conductive material. In some embodiments, the upper conductive contact 114 can comprise the same material as the lower conductive contact 105. In other embodiments, the upper conductive contact 114 comprises a different material than the lower conductive contact 105.

[0045] The upper conductive contact 114 can be in electrical communication with the second conductive line 126. Figure 1A Only a portion of the second conductive line 126 is illustrated, but it will be understood that, in at least some embodiments, the second conductive line 126 extends in a second direction (e.g., the y-direction) different from a first direction along which the first conductive line 104 extends. The second conductive line 126 can comprise a conductive material, such as, for example, tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys; metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); materials including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof; conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.); polysilicon; other materials that exhibit electrical conductivity; or combinations thereof. In some embodiments, the second conductive line 126 comprises tungsten or ruthenium. In some embodiments, the second conductive line 126 comprises the same material as the first conductive line 104. In other embodiments, the second conductive line 126 comprises a different material than the first conductive line 104.

[0046] The channel region 118 can be positioned adjacent to the gate dielectric material 112 (e.g., overlying a sidewall of the gate dielectric material 112). The channel region 118 can comprise a semiconductor material that is configured and arranged to exhibit electrical conductivity in response to the application of a suitable voltage (e.g., a threshold voltage V t ) to the vertical transistor 110 (e.g., between the gate electrode 108 and a source region (e.g., the first conductive line 104)). In some embodiments, the channel region 118 can directly contact the lower conductive contact 105 and extend along a sidewall of the gate dielectric material 112 to contact the upper conductive contact 114. Thus, the channel region 118 can directly contact each of the lower conductive contact 105 and the upper conductive contact 114. In some such embodiments, the channel region 118 can be in electrical communication with each of a source region and a drain region of the vertical transistor 110 associated with the channel region 118.

[0047] In some embodiments, each vertical transistor 110 can include two distinct channel regions 118 and a single gate electrode 108. The channel regions 118 can surround the gate electrode 108 and can be positioned adjacent to the gate electrode 108 (e.g., such as at the sides of the gate electrode 108). In other words, the gate electrode 108 can be positioned centrally (e.g., laterally central) between the two channel regions 118 of the vertical transistor 110. Although Figure 1A and Figure 1B Although illustrated and described as including two channel regions 118, the present disclosure is not so limited. In other embodiments, the vertical transistor 110 includes only one channel region 118.

[0048] The channel regions 118 can comprise a material formulated to conduct current in response to application of a suitable voltage (e.g., threshold voltage, set bias voltage, read bias voltage) to the vertical transistor 110. The channel regions 118 can comprise a semiconducting material having a bandgap greater than that of polysilicon (e.g., a bandgap greater than about 1.65 electron volts (eV)) and can be referred to herein as a so-called “large bandgap material.” For example, the channel regions 118 can comprise an oxide semiconductor material, such as one or more of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconium zinc tin oxide (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO), indium tungsten oxide (IWO), combinations thereof, and other similar materials. In some embodiments, channel region 118 comprises IGZO. In some embodiments, channel region 118 may have an In:Ga:Zn:O ratio of 1:1:1:4, an In₂O₃:Ga₂O₃:ZnO ratio of 2:2:1, or may be represented by the formula InGaO₃(ZnO)₅. In additional embodiments, channel region 118 comprises IGZO and IGSO. Channel region 118 may comprise a ternary oxide comprising atoms of two different elements and an oxygen atom. In other embodiments, channel region 118 comprises a quaternary oxide comprising atoms of three different elements and an oxygen atom. As will be described herein, in some embodiments, channel region 118 may comprise a composite structure comprising one or more discrete portions of one or more of the materials described above.

[0049] In some embodiments, gallium can constitute about 20 atomic percent to about 60 atomic percent (e.g., about 35 atomic percent to about 55 atomic percent) of the channel region 118, based on non-oxide elements (i.e., based on other elements of the channel region 118 (i.e., not including oxygen atoms)). Zinc can constitute about 20 atomic percent to about 60 atomic percent (e.g., about 20 atomic percent to about 40 atomic percent) of the channel region 118, based on non-oxide elements of the channel region 118. Indium can constitute about 20 atomic percent to about 60 atomic percent (e.g., about 20 atomic percent to about 40 atomic percent) of the channel region 118, based on non-oxide elements of the channel region 118. However, the disclosure is not limited thereto and the channel region 118 can have a composition different from that described above.

[0050] The channel region 118 can have a thickness T3 between about and about (e.g., between about and about , between about and about , between about and about , or between about and about .

[0051] In some embodiments, the channel region 118 includes a single material having a substantially uniform composition. In other embodiments, the channel region 118 can include a composite structure including more than one type of semiconductor material (e.g., an oxide semiconductor material). Figure 1C is a simplified cross-sectional view of a portion of one of the channel regions 118, e.g., showing a portion of the channel region 118 of block C of Figure 1A . For example, the channel region 118 can include a first semiconductor material 130, a second semiconductor material 132 on a side of the first semiconductor material 130, and a third semiconductor material 134 on an opposite side of the second semiconductor material 132. The second semiconductor material 132 can be positioned between the first semiconductor material 130 and the third semiconductor material 134. Figure 1C The channel region 118 of may also be referred to herein as a so-called “multi-layer” channel region, as the channel region 118 includes more than one semiconductor material (e.g., the first semiconductor material 130, the second semiconductor material 132, and the third semiconductor material 134).

[0052] The first semiconductor material 130, the second semiconductor material 132, and the third semiconductor material 134 can each independently be selected from the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO xindium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium tungsten oxide (IWO), or combinations thereof. x x x y z x y z x y z x y z a x y z a x y z a x y z a x y z a d x y z a x y z x y z a x y z a x y z a indium gallium silicon oxide (IGSO), indium tungsten oxide (IWO), or combinations thereof.

[0053] ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​In some embodiments, the first semiconductor material 130 and the third semiconductor material 134 comprise the same material and the second semiconductor material 132 comprises a material different from the first semiconductor material 130 and the third semiconductor material 134. In other embodiments, each of the first semiconductor material 130, the second semiconductor material 132, and the third semiconductor material 134 comprises a different material. In some embodiments, the first semiconductor material 130 and the third semiconductor material 134 comprise IGSO and the second semiconductor material 132 comprises IGZO, such that the channel region 118 comprises an IGSO / IGZO / IGSO composite structure. Although Figure 1C Although the channel region 118 is described as comprising three distinct semiconductor materials, the disclosure is not so limited. In other embodiments, the channel region 118 comprises two different semiconductor materials, four semiconductor materials, five semiconductor materials, etc. As one example, in some embodiments, the semiconductor structure channel region 118 comprises a first semiconductor material 130 and a second semiconductor material 132 adjacent to the first semiconductor material 130. The first semiconductor material 130 and the second semiconductor material 132 can comprise IGZO, but can have different compositions. For example, the first semiconductor material 130 can exhibit a different atomic percentage of one or more of indium, gallium, and zirconium than the second semiconductor material 132. In other words, the second semiconductor material 132 can comprise the same elements as the first semiconductor material 130, but can exhibit a different stoichiometric ratio (and composition) than the first semiconductor material 130.

[0054] Forming the channel region 118 as a composite structure can facilitate forming a channel region 118 that exhibits one or more desired properties, such as, for example, hydrogen resistance. In some embodiments, hydrogen does not substantially diffuse into the channel region 118 and the channel region 118 can form a hydrogen barrier. As one example, a channel region 118 comprising an IGSO / IGZO / IGSO composite structure can exhibit resistance to hydrogen and reduce or prevent hydrogen from diffusing into the composite structure, which can otherwise diffuse into a channel region and negatively affect the electrical properties of the channel region.

[0055] Referring again to Figure 1A and Figure 1B , the individual vertical transistors 110 can be separated from one another by an electrically insulating material 106. The electrically insulating material 106 can electrically isolate adjacent rows of vertical transistors 110 and adjacent columns of vertical transistors 110.

[0056] For example, the electrical insulating material 106 may comprise phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, a nitride material (e.g., silicon nitride (Si3N4)), a nitrogen oxide (e.g., silicon oxynitride), another dielectric material, a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), a dielectric carbonitride oxide material (e.g., silicon carbonitride (SiOCN)), or a combination thereof. In some embodiments, the electrical insulating material 106 comprises silicon dioxide. In some embodiments, the electrical insulating material 106 comprises the same material as the gate dielectric material 112.

[0057] Shielding material 120 may be in one direction (e.g., Figure 1B It extends in a straight line in the y-direction and can be in a second direction (e.g., Figure 1B The transistors are arranged between adjacent vertical transistors 110 in the x-direction. Therefore, each vertical transistor 110 may include a shielding material 120 on its first side and another shielding material 120 on its second, opposite side. (See reference...) Figure 1B In some embodiments, the shielding material 120 may extend linearly along the semiconductor device 100 in a first direction (e.g., in the column direction). The shielding material 120 may be electrically isolated from the first conductive line 104 by at least electrically insulating materials 124 and 106. The shielding material 120 may be electrically isolated from the second conductive line 126 by at least electrically insulating material 106. Additionally, the shielding material 120 may be separated from the channel region 118 by at least electrically insulating material 106.

[0058] As will be described herein, shielding material 120 may be configured, arranged, and electrically biased to reduce or prevent word line capacitance between the gate electrodes 108 of adjacent vertical transistors 110. Therefore, shielding material 120 may be configured to reduce capacitance (e.g., word line capacitance) between the gate electrodes 108 of adjacent vertical transistors 110.

[0059] Shielding material 120 may have approximately With the agreement Between (e.g., in about) With the agreement Between, in the agreement With the agreement Between, in the agreement With the agreement Between or in the period With the agreement The thickness T4 between (between).

[0060] The distance D between the lower surface of the shielding material 120 and the lower surface of the channel region 118 can be between about 10 nm and about 50 nm, such as between about 10 nm and about 30 nm or between about 30 nm and about 50 nm. The distance D can be controlled by the thickness of the electrically insulating material 106.

[0061] The shielding material 120 can comprise an electrically conductive material. In some embodiments, the shielding material 120 comprises a material having P+ type conductivity and can be referred to as a P+ body region. In other embodiments, the shielding material 120 comprises an electrically conductive metal, such as, for example, tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys; a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide); a material including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof; an electrically conductive doped semiconductor material (e.g., electrically conductive doped silicon, electrically conductive doped germanium, electrically conductive doped silicon germanium, etc.); polysilicon; other materials that exhibit electrical conductivity; or combinations thereof. Suitable electrically conductive doped semiconductor materials can be doped with P-type dopants (such as boron, aluminum, gallium, or combinations thereof). In some embodiments, the shielding material 120 comprises tungsten. In other embodiments, the shielding material 120 comprises ruthenium. In some embodiments, the shielding material 120 comprises the same material as the first conductive line 104 and / or the second conductive line 126.

[0062] The shielding material 120 can be in electrical communication with an electrically conductive contact 122 Figure 1B ), which can be configured to provide a suitable bias to the shielding material 120. In some embodiments, the electrically conductive contact 122 is in electrical communication with a voltage source configured to bias the electrically conductive contact 122 and the associated shielding material 120. The voltage source in electrical communication with the electrically conductive contact 122 can be different than the voltage source in electrical communication with the electrically conductive contact 122 and the gate electrode 108.

[0063] In some embodiments, the electrically conductive contact 122 comprises the same material as the shielding material 120. In other embodiments, the electrically conductive contact 122 comprises a material that is different than the material of the shielding material 120. The electrically conductive contact 122 can comprise the same material as the electrically conductive contact 109.

[0064] In some embodiments, when the gate electrode 108 of at least one vertical transistor 110 adjacent to the shielding material 120 is selected (i.e., biased with a voltage), the shielding material 120 can be configured to be biased to a predetermined voltage. Without wishing to be bound by any particular theory, it is believed that when a switching voltage is applied to the gate electrode 108, because the channel region 118 is located outside (i.e., on the side of) the gate electrode 108 (rather than the gate electrode 108 being disposed around the channel region 118), the channel region 118 of one vertical transistor 110 can be affected by the gate electrode 108 of an adjacent vertical transistor 110. In some embodiments, applying a suitable bias voltage to the shielding material 120 can prevent or reduce the effect of the voltage applied to the gate electrode 108 of a vertical transistor 110 on the channel region 118 of an adjacent vertical transistor 110. Thus, the shielding material 120 can facilitate reducing or preventing so-called "word line to word line capacitance" between the word lines 108 of adjacent vertical transistors 110. In some embodiments, the word line capacitance of the semiconductor device 100 can be about 35% less than the word line capacitance of a conventional semiconductor device that does not include a shielding material 120.

[0065] In use and operation, the shielding material 120 can be biased with a voltage between about -2.0 V and about 2.0 V (e.g., between about -2.0 V and about -1.5 V, between about -1.5 V and about -1.0 V, between about -1.0 V and about -0.5 V, between about -0.5 V and about 0 V, between about 0 V and about 0.5 V, between about 0.5 V and about 1.0 V, between about 1.0 V and about 1.5 V, or between about 1.5 V and about 2.0 V). In some embodiments, the shielding material 120 is biased with a voltage between about 0 V and about 0.5 V. In some embodiments, e.g., where the shielding material 120 is configured to be biased, the shielding material 120 can be referred to as a so-called "back gate" of the semiconductor device 200.

[0066] In use and operation, a voltage can be applied to one or more word lines 108. In some embodiments, another voltage, which can be different from (e.g., have a different magnitude than) the voltage applied to the one or more word lines 108, can be applied to the shielding material 120 positioned adjacent to the word line 108 to which the voltage is applied. Applying another voltage to the shielding material 120 can reduce the word line to word line capacitance between adjacent vertical transistors 110.

[0067] Accordingly, each vertical transistor 110 of the array of vertical transistors 110 can include a gate electrode 108 that can be positioned at a central portion of its respective vertical transistor 110. The gate electrode 108 can be surrounded on one or more sides thereof by a gate dielectric material 112. The gate dielectric material 112 can be in contact with a channel region 118 on an opposite side from the gate electrode 108. In other words, the gate dielectric material 112 can be disposed between the gate electrode 108 and the channel region 118. The gate electrode 108 can include two channel regions 118 associated therewith. The channel regions 118 can comprise an oxide semiconductor material. In some embodiments, each gate electrode 108 can include two channel regions 118 associated therewith and can be laterally positioned between the two channel regions 118. Because the channel regions 118 are disposed outside of the centrally located gate electrode 108, the gate electrode 108 of each vertical transistor 110 can be formed to a greater thickness than a conventional vertical transistor, while the pitch of the vertical transistors 110 is the same as a conventional vertical transistor. The greater thickness of the gate electrode 108 increases its area, and thus, reduces its resistance. Accordingly, the RC (product of resistance and capacitance) of the vertical transistor 110 can be reduced, which can be related to an increase in switching speed of the vertical transistor 110. The vertical transistor 110 can deliver the same current (e.g., about 5 mA / Dev) as a conventional vertical transistor arranged at the same pitch.

[0068] As will be described herein, in some embodiments, the channel regions 118 can be formed of a material that is not etched (e.g., not etched) or at least a portion of the channel regions 118 are not etched after formation of the channel regions 118. Accordingly, the channel regions 118 can exhibit improved electrical properties compared to conventional channel materials that are exposed to various etching chemistries (e.g., hydrogen containing plasma). In some embodiments, the channel regions 118 can comprise a composite structure and hydrogen does not substantially diffuse into the channel regions 118. The vertical transistors 110 can exhibit a threshold voltage higher than a conventional vertical transistor and can also exhibit an off current Ioff lower than a conventional vertical transistor. offIn some embodiments, the vertical transistor 110 can be in an off state with about 0 V applied to the gate electrode 108. In other words, no negative voltage can be applied to the gate electrode 108 when the vertical transistor 110 is in an off state. In some embodiments, a bias voltage can be applied to the shielding material 120 while the vertical transistor 110 is in an off state. By comparison, a conventional vertical transistor that includes a channel material (e.g., including polysilicon) and does not include a conductive shielding material 120 can exhibit leakage current if a substantially negative voltage is not applied to the gate electrode when the vertical transistor is in an off state (e.g., an off voltage having a magnitude greater than about 1.0). In some embodiments, applying a voltage to the gate electrode 108 of one vertical transistor 110 can not affect the gate electrode 108 or the channel region 118 of an adjacent vertical transistor 110.

[0069] Thus, in at least some embodiments, a semiconductor device includes a first conductive line and a vertical transistor over the first conductive line. The vertical transistor includes a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on a side of the gate dielectric material, the gate dielectric material positioned between the channel region and the gate electrode. The semiconductor device further includes a second conductive line overlying a conductive contact of the vertical transistor.

[0070] Thus, in at least some embodiments, a semiconductor device includes a vertical transistor over a first conductive line, the vertical transistor including a gate electrode surrounded by a gate dielectric material, a first channel region on a first side of the gate electrode, the gate dielectric material positioned between the first channel region and the gate electrode, and a second channel region on a second side of the gate electrode, the gate dielectric material positioned between the second channel region and the gate electrode. The semiconductor device further includes a second conductive line over the vertical transistor, and a conductive material between channel regions of adjacent vertical transistors, the conductive material electrically isolated from the channel regions by an electrically insulative material.

[0071] Thus, in at least some other embodiments, a semiconductor device includes a vertical transistor, the vertical transistor including a gate electrode, a first channel region on a first side of the gate electrode, a second channel region on a second side of the gate electrode, the second side opposite the first side, and a gate dielectric between the first channel region and the gate electrode and between the second channel region and the gate electrode. The semiconductor device further includes a conductive material on a side of the first channel region and the second channel region, the conductive material electrically isolated from the first channel region and the second channel region by an electrically insulative material.

[0072] Thus, in at least some embodiments, a method of operating a semiconductor device includes applying a bias voltage to a gate electrode of a semiconductor device comprising a vertical transistor. The vertical transistor comprises a gate electrode, a gate dielectric material on at least opposite sides of the gate electrode, and a channel material on sides of the gate dielectric material, the gate electrode being located between different portions of the channel material. The method further includes applying another bias voltage to a conductive material located between the transistor and at least another transistor of the semiconductor device.

[0073] In some embodiments, semiconductor device 100 can include a stack of vertical transistors 110 (e.g., in a 3D memory structure, such as in a stacked DRAM array). In some such embodiments, semiconductor device 100 can include one or more levels of vertical transistors 110, each level being vertically offset from other levels of vertical transistors 110. Each level of vertical transistors 110 can be isolated from one another by insulating material extending therebetween. For example, referring to Figure 1A , electrically insulating material can be formed over second conductive line 126. A first conductive line 104 of another level of vertical transistors 110 can be formed over the electrically insulating material and a vertical transistor 110 can be formed over the first conductive line 104 of the level to form a structure comprising multiple levels (e.g., two levels, three levels, four levels, eight levels, etc.) of vertical transistors.

[0074] Figures 2A to 2K A method of forming semiconductor device 100 described above with reference to Figures 1A to 1C is described in accordance with some embodiments of the present disclosure. Figure 2A is a simplified perspective view of semiconductor device 200 and Figure 2B is a top view of semiconductor device 200. Semiconductor device 200 can include first conductive material 204 over substrate 202, lower conductive contact material 205 over first conductive material 204, electrically insulating material 206 over lower conductive contact material 205, and gate electrode 108 Figure 1A , Figure 1BThe gate electrode material 208 has lines 209, as described herein. A first conductive material 204 and a lower conductive contact material 205 may be patterned thereon before the formation of an electrically insulating material 206 and the gate electrode material. The first conductive material 204 and the lower conductive contact material 205 may include lines extending in a first direction (e.g., the x-direction). In some embodiments, the electrically insulating material 206 is formed over the lower conductive contact material 205 after the patterning of the first conductive material 204 and the lower conductive contact material 205. In some such embodiments, the electrically insulating material 206 may fill the space between the patterned portions (e.g., lines) of the first conductive material 204 and the lower conductive contact material 205, such as... Figure 2H As illustrated in the view.

[0075] Substrate 202 and first conductive material 204 can be respectively compared with the above reference. Figure 1A The substrate 102 and the first conductive line 104 described are substantially the same. The electrically insulating material 206 is the same as described above. Figure 1A and Figure 1B The gate dielectric material 112 described is substantially the same. The lower conductive contact material 205 may include the same material described above with reference to the lower conductive contact 105.

[0076] The line 209 of the gate electrode material 208 can be formed by: forming the gate electrode material 208 over an electrically insulating material 206; forming a mask over a portion of the gate electrode material 208; and exposing the portion of the gate electrode material 208 exposed through the mask to a suitable etchant to remove the exposed portion of the gate electrode material 208 and form the line 209. The line 209 of the gate electrode material 208 may extend in a first direction (e.g., in the y-direction). The gate electrode material 208 may include the gate electrode 108 referenced above (…). Figure 1A , Figure 1B The same material described herein. In some embodiments, the upper portion of the gate electrode material 208 may comprise a dielectric material 208a. The dielectric material 208a may also be referred to herein as a hard mask. In some embodiments, the dielectric material 208a comprises silicon nitride. As will be described herein, the dielectric material 208a can substantially protect the gate electrode material 208 from etchants during the patterning of the vertical transistor. Although Figures 2B to 2K The dielectric material 208a is not described herein, but it will be understood that in some embodiments, the dielectric material 208a may overlay the gate electrode material 208 and protect the gate electrode material 208 during subsequent etching operations, as referenced. Figure 2H As described.

[0077] refer to Figure 2CThe gate dielectric material 212 can be formed adjacent to (e.g., formed over) the lines 209 of the gate electrode material 208. The gate dielectric material 212 can include the same materials described above with reference to the gate dielectric material 112 Figure 1A , Figure 1B In some embodiments, the gate dielectric material 212 includes the same material as the electrically insulative material 206. Thus, the electrically insulative material 206 and the gate dielectric material 212 can include a unitary insulative material that can correspond to the gate dielectric material 112. Although Figures 2C to 2K The electrically insulative material 206 and the gate dielectric material 212 are illustrated as separate components, it will be understood that the electrically insulative material 206 and the gate dielectric material 212 can include a unitary structure that exhibits a substantially uniform composition (e.g., silicon dioxide).

[0078] The gate dielectric material 212 can be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), another deposition method, or a combination thereof. The gate dielectric material 212 can be formed conformally over the lines 209 of the gate electrode material 208. In some embodiments, the gate dielectric material 212 and the electrically insulative material 206 between adjacent lines 209 can be removed to expose portions of the underlying conductive contact material 205 between adjacent lines 209. In some embodiments, the gate dielectric material 212 and the electrically insulative material 206 between adjacent lines 209 are removed by exposing the gate dielectric material 212 and the electrically insulative material 206 between adjacent lines 209 to a suitable etching chemistry, such as a reactive ion etching chemistry that is formulated and configured to remove the gate dielectric material 212 and the electrically insulative material 206 without substantially removing the underlying conductive contact material 205. In some embodiments, a mask can be over the gate dielectric material 212 over the gate electrode material 208 such that the gate dielectric material 212 is not removed from over the surface of the gate electrode material 208. Thus, the gate dielectric material 212 and the electrically insulative material 206 can substantially enclose the gate electrode material 208.

[0079] Referring to Figure 2D The semiconductor material 218 can be formed (e.g., conformally formed) over the semiconductor device 200. The semiconductor material 218 can be formed over at least a surface (e.g., sidewall) of the gate dielectric material 212. The semiconductor material 218 can include the same materials described above with reference to the channel region 118 Figure 1AThe semiconductor material 218 can be formed by ALD, CVD, PVD, LPCVD, PECVD, another deposition method, or a combination thereof. In some embodiments, the semiconductor material 218 is formed by atomic layer deposition. In some embodiments, the semiconductor material 218 is formed at a low temperature (e.g., between about 15 °C and about 25 °C). Because the semiconductor material 218 is formed over the lines 209 of the gate electrode material 208 and the gate dielectric material 212, the semiconductor material 218 can be patterned in at least the first direction. Thus, the semiconductor material 218 can be etchless to pattern the semiconductor material 218 in the first direction and can be formed as lines extending in the same direction as the gate electrode material 208. In other words, the semiconductor material 218 adjacent to and on the surface of the gate dielectric material 212 can be arranged as lines without being exposed to etching chemistry for patterning the semiconductor material 218 as lines (e.g., without exposing the semiconductor material 218 to a hydrogen-containing plasma). In other words, in some embodiments, the semiconductor material 218 can be deposited as a patterned line.

[0080] In some embodiments, the semiconductor material 218 can be formed as a composite structure as described above with reference to Figure 1C In some embodiments, at least a first semiconductor material can be formed over a surface of the semiconductor device 200 (e.g., by atomic layer deposition) and at least a second semiconductor material can be formed over the first semiconductor material (e.g., by atomic layer deposition). In some embodiments, additional semiconductor materials can be formed over the second semiconductor material to form a composite structure that exhibits desired electrical and material properties (e.g., threshold voltage, leakage current, hydrogen tolerance, etc.).

[0081] In some embodiments, portions of the semiconductor material 218 formed over the gate dielectric material 212 and over the first conductive material 204 of the lines 209 are removed such that the semiconductor material 218 overlies only portions (e.g., sidewalls) of the gate dielectric material 212 on sidewalls of the lines 209. In some embodiments, the semiconductor device 200 is exposed to a reactive ion etch plasma (e.g., including CHF3, SF6, C4F8, CH3F, another gas, or combinations thereof) to remove the semiconductor material 218 from surfaces of the lower conductive contact material 205 between adjacent lines 209. In other embodiments, the semiconductor material 218 between adjacent lines 209 is removed by exposing the semiconductor material 218 on surfaces of the lower conductive contact material 205 between adjacent lines 209 to a wet etch chemistry. In some embodiments, an upper surface of the semiconductor material 218 can be substantially non-coplanar with an upper surface of the gate electrode material 208. In some such embodiments, the upper surface of the semiconductor material 218 can be positioned further from the substrate 202 than the upper surface of the gate electrode material 208. In some embodiments, the semiconductor material 218 on an upper surface of the gate dielectric material 212 is removed by chemical mechanical planarization.

[0082] Referring to Figure 2E The upper conductive contact material 214 can be formed over surfaces of the lines 209, e.g., over the gate dielectric material 212 on upper surfaces of the lines 209. The upper conductive contact material 214 can include the same materials described above with reference to the upper conductive contact 114 Figure 1A ) described above.

[0083] In some embodiments, the upper conductive contact material 214 can be formed over the lines 209 by filling spaces between the lines with a sacrificial material (e.g., photoresist, silicon, another material, etc.), forming a mask over the sacrificial material and exposing the lines 209 (i.e., the gate dielectric material 212) through the mask, forming the upper conductive contact material 214 through openings in the mask, and removing the mask and the sacrificial material. In other embodiments, the upper conductive contact material 214 can be formed at a later stage of fabrication of the semiconductor device 200.

[0084] Referring to Figure 2F A portion of the lower conductive contact material 205 between adjacent lines 209 can be removed to expose the first conductive material 204 between adjacent lines 209 and form discrete lower conductive contacts (e.g., the lower conductive contacts 105 Figure 1A ) each associated with a respective line 209. Although Figure 2F removing the lower conductive contact material 205 between adjacent lines 209 is described, the disclosure is not so limited and the lower conductive contact material 205 can be substantially coextensive with the first conductive material 204.

[0085] Figure 2G This is a top view of the semiconductor device 200 after the upper conductive contact material 214 has been formed and after the lower conductive contact material 205 between adjacent lines 209 has been removed.

[0086] refer to Figure 2H and Figure 2I The semiconductor device 200 can be patterned in a second direction. Figure 2H It is along Figure 2F A simplified cross-sectional view of the semiconductor device is obtained by the cross-sectional line HH. In some embodiments, a mask or resist material may be placed above line 209 in a first direction and the semiconductor device 200 may be patterned in a second direction. Portions of the conductive contact material 214, the gate dielectric material 212, and the semiconductor material 218 may be patterned to form a transistor structure 215. In some embodiments, the gate electrode material 208 may not be removed when the portion of the conductive contact material 214 and the semiconductor material 218 is patterned to form the transistor structure 215. For example, dielectric material 208a ( Figure 2A The lower gate electrode material 208 can be protected from various etchants during the patterning of the semiconductor device 200 in the second direction. In some embodiments, portions of the upper conductive contact material 214 and the semiconductor material 218 are removed by exposing the semiconductor material to wet etching chemicals. Therefore, in some embodiments, the transistor structure 215 is formed and the semiconductor material 218 is patterned in both the first and second directions without exposing the semiconductor material 218 to a dry etchant (e.g., a dry etchant including hydrogen). In other words, the transistor structure 215 can be formed and patterned in both the first and second directions without etching the semiconductor material 218 in at least one of the first and second directions and without exposing the semiconductor material 218 to a dry etching chemical.

[0087] After forming the transistor structure 215, the space between adjacent transistor structures 215 is filled with an electrically insulating material, which may include the same material described above with reference to electrically insulating material 106.

[0088] refer to Figure 2J Electrical insulating material 216 may be formed (e.g., conformally formed) over transistor structure 215. Electrical insulating material 216 may include the aforementioned reference electrical insulating material 106 (… Figure 1A , Figure 1B The same material as described. Electrically insulating material 216 can be formed by, for example, ALD, CVD, PVD, LPCVD, PECVD, another deposition method, or a combination thereof.

[0089] After forming the electrically insulative material 216, an electrically conductive material 220 can be formed (e.g., conformally formed) over the electrically insulative material 216. In some embodiments, the electrically conductive material 220 is formed to substantially fill the volume between adjacent transistor structures 215. In other words, the space between the electrically insulative material 216 of adjacent transistor structures 215 can be filled with the electrically conductive material 220.

[0090] The electrically conductive material 220 can include the same materials described above with reference to the shielding material 120 Figure 1A 、 Figure 1B ) In some embodiments, the electrically conductive material 220 includes the same material as the gate electrode material 208.

[0091] Referring to Figure 2K , the electrically conductive material 220 and the electrically insulative material 216 over the surface of the upper electrically conductive contact material 214 can be removed to form a substantially planar upper surface of the semiconductor device 200 and expose portions of the upper electrically conductive contact material 214.

[0092] After planarizing the semiconductor device 200, in some embodiments, another electrically conductive material can be patterned over the upper electrically conductive contact material 214 to form electrically conductive lines that extend in the y-direction. In some embodiments, the electrically conductive lines can extend in a direction different from the direction in which the lines 209 of the first electrically conductive material 204 extend. In some embodiments, the electrically conductive lines can be referred to as source lines. In other embodiments, the electrically conductive lines can be referred to as digit lines, bit lines, or access lines.

[0093] Although Figures 2A to 2K the different components of the semiconductor device 200 have been described as being formed in a particular order, the disclosure is not so limited. For example, although the upper electrically conductive contact material 214 has been described as being formed after the semiconductor material 218 is formed, the disclosure is not so limited to the particular order in which the components of the semiconductor device 200 are formed. In other embodiments, the upper electrically conductive contact material 214 can be formed after the electrically insulative material 216 and the electrically conductive material 220 are formed. In some such embodiments, the electrically conductive material 220 and the electrically insulative material 216 over the transistor structures 215 Figure 2J ) can be removed from over the surface of the transistor structures 215 to form openings in the electrically conductive material 220 and the electrically insulative material 216 and expose upper portions of the gate dielectric material 212. The upper electrically conductive contact material 214 can be formed in the openings. Thereafter, the upper electrically conductive contact material 214, the electrically conductive material 220, and the electrically insulative material 216 can be removed from the upper surface of the semiconductor device 200, e.g., by chemical mechanical planarization.

[0094] Accordingly, vertical transistors 210 can be formed of, and include, semiconductor material 218 positioned on sides of gate electrode material 208. In some embodiments, gate electrode material 208 of each vertical transistor 210 is positioned at a laterally-central location of the vertical transistor and semiconductor material 218 is positioned adjacent to gate electrode material 208 (e.g., on opposite sides (e.g., lateral sides) of gate electrode material 208). A vertical length (i.e., in the z-direction) of semiconductor material 218 can be greater than a vertical length of gate electrode material 208. In some embodiments, semiconductor material 218 can be formed and patterned without exposing semiconductor material 218 to various etch chemistries (e.g., dry etch chemistries). For example, semiconductor material 218 (e.g., semiconductor material 218 on sidewalls of gate dielectric material 212) forming channel regions 118 Figure 1A ) after semiconductor material 218 is formed can be substantially free of exposure to dry etch chemistries. Accordingly, in some such embodiments, semiconductor material 218 can be considered to comprise “virgin” or “as-deposited” material and can exhibit improved electrical properties relative to channel regions of conventional vertical transistors.

[0095] In some embodiments, semiconductor material 218 can be formed as a composite structure, e.g., when semiconductor material 218 is formed by atomic layer deposition. In some such embodiments, semiconductor material 218 can be formulated and configured to exhibit hydrogen resistance (e.g., substantially reduce or prevent diffusion of hydrogen therein).

[0096] In some embodiments, after semiconductor device 200 is formed, semiconductor device 200 can be subjected to a hydrogen anneal process, e.g., by exposing semiconductor device 200 to a temperature of at least about 400 °C (e.g., at least about 450 °C, at least about 500 °C, or at least about 600 °C). During the hydrogen anneal process, semiconductor material 218 can include a composite structure that can be formulated and configured to exhibit immunity to hydrogen and protected from penetration of hydrogen species into semiconductor material 218.

[0097] Accordingly, in at least some embodiments, a method of forming a semiconductor device includes forming a first conductive line and forming a vertical transistor over the first conductive line. Forming the vertical transistor includes forming a gate electrode, forming a gate dielectric material adjacent to a first side of the gate electrode and adjacent to a second side of the gate electrode, and forming a channel region adjacent to the gate dielectric material adjacent to the first side of the gate electrode and adjacent to the gate dielectric material adjacent to the second side of the gate electrode after forming the gate electrode. The method further includes forming a second conductive line over the vertical transistor.

[0098] Accordingly, the semiconductor devices (e.g., semiconductor devices 100, 200) of the present application can be formed using original channel regions (e.g., channel regions 118, semiconductor material 218 formed without etching its semiconductor material). The channel regions 118, semiconductor material 218 of the present application can exhibit improved properties relative to conventional semiconductor materials of conventional vertical transistors. For example, the channel regions 118, semiconductor material 218 of the present application can exhibit higher threshold voltages, reduced off-state currents, and greater electron carrier mobility relative to conventional semiconductor materials. In addition, the channel regions 118, semiconductor material 218 can exhibit resistance to hydrogen and can be formulated and configured to prevent hydrogen diffusion therein. The semiconductor devices 100, 200 can exhibit reduced wordline-to-wordline capacitance relative to conventional semiconductor devices, at least in part due to the conductive shield material 120, 220. In some embodiments, the semiconductor devices 100, 200 can exhibit improved switching speed relative to conventional semiconductor devices.

[0099] Semiconductor devices (e.g., semiconductor devices 100, 200) including channel regions (e.g., channel regions 118, semiconductor material 218) according to embodiments of the present application can be used in embodiments of electronic systems of the present application. For example, Figure 3 is a block diagram of an illustrative electronic system 303 according to embodiments of the present application. For example, the electronic system 303 can comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., such as an or tablet computer), an e-book, a navigation device, and the like. The electronic system 303 includes at least one memory device 305. The memory device 305 can include, for example, embodiments of the semiconductor devices (e.g., semiconductor devices 100, 200) previously described herein, in which a channel region (e.g., channel region 118, semiconductor material 218) comprises an original deposited material. The semiconductor devices can include at least one gate electrode (e.g., gate electrodes 108, 208) positioned centrally within the channel region (e.g., channel region 118, semiconductor material 218). In addition, the semiconductor devices can include a shield material (e.g., conductive shield material 120, 220) between adjacent vertical transistors (e.g., vertical transistors 110, 210), which can reduce the wordline-to-wordline capacitance of the semiconductor devices.

[0100] The electronic system 303 can further include at least one electronic signal processor device 307 (often referred to as a "microprocessor"). The electronic signal processor device 307 can optionally include embodiments of the semiconductor devices (e.g., semiconductor devices 100, 200) previously described herein. The electronic system 303 can further include one or more input devices 309 for inputting information into the electronic system 303 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, buttons, or control panels. The electronic system 303 can further include one or more output devices 311 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 309 and the output device 311 can comprise a single touch screen device that can be used both to input information into the electronic system 303 and to output visual information to a user. The input device 309 and the output device 311 can be in electrical communication with one or more of the memory device 305 and the electronic signal processor device 307.

[0101] Accordingly, according to embodiments of the present disclosure, an electronic device includes at least one input device, at least one output device, at least one processor device operably coupled to the at least one input device and the at least one output device, and a semiconductor device operably coupled to the at least one processor device. The semiconductor device includes a vertical transistor array. At least one vertical transistor of the vertical transistor array includes a gate electrode separated from a lower conductive contact by a gate dielectric material, the gate dielectric material overlying a sidewall of the gate electrode, a first channel region on a lateral side of the gate dielectric material, and a second channel region on a lateral side of the gate dielectric material opposite the lateral side of the first channel region, the gate electrode positioned between the first channel region and the second channel region.

[0102] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0103] Embodiment 1: A semiconductor device comprising: a first conductive line; a vertical transistor over the first conductive line, the vertical transistor comprising: a gate electrode; a gate dielectric material overlying a side of the gate electrode; and a channel region on a side of the gate dielectric material, the gate dielectric material positioned between the channel region and the gate electrode; and a second conductive line overlying a conductive contact of the vertical transistor.

[0104] Embodiment 2: The semiconductor device of embodiment 1, wherein the channel region comprises two distinct channel regions, one of the distinct channel regions is positioned on a first lateral side of the gate electrode and the other of the distinct channel regions is positioned on a second lateral side of the gate electrode.

[0105] Embodiment 3: The semiconductor device of embodiment 1 or embodiment 2, wherein the gate electrode is substantially surrounded on all sides thereof by the gate dielectric material.

[0106] Embodiment 4: The semiconductor device of any one of embodiments 1-3, wherein the channel region comprises an oxide semiconductor material.

[0107] Embodiment 5: The semiconductor device of any one of embodiments 1-4, wherein the channel region comprises ZTO, IZO, ZnO x , IGZO, IGSO, InO x , In2O3, SnO2, TiO x , Zn x O y N z , Mg x Zn y O z , In x Zn y O z , In x Ga y Zn z O a , Zr x In y Zn z O a , Hf x In y Zn z O a , Sn x In y Zn z O a , Al x Sn y In z Zn a O d , Si x In y Zn z O a , Zn x Sn y O z , Al x Zn y Sn z Oa Ga x Zn y Sn z O a Zr x Zn y Sn z O a InGaSiO or IWO.

[0108] Embodiment 6: The semiconductor device of any of embodiments 1-5, wherein the channel region comprises indium gallium zinc oxide material and indium gallium silicon oxide material on opposite sides of the indium gallium zinc oxide material.

[0109] Embodiment 7: The semiconductor device of any of embodiments 1-6, wherein the channel region comprises a multi-layer channel region.

[0110] Embodiment 8: The semiconductor device of any of embodiments 1-7, further comprising another conductive material between adjacent vertical transistors, the another conductive material electrically isolated from the channel regions of adjacent vertical transistors by an electrically insulative material.

[0111] Embodiment 9: The semiconductor device of embodiment 8, wherein the another conductive material is in electrical communication with a voltage source.

[0112] Embodiment 10: The semiconductor device of any of embodiments 1-9, wherein the channel region is formed by atomic layer deposition.

[0113] Embodiment 11: The semiconductor device of any of embodiments 1-10, wherein the channel region exhibits a bandgap greater than about 1.65 electron volts.

[0114] Embodiment 12: A method of forming a semiconductor device, the method comprising: forming a first conductive line; forming a vertical transistor over the first conductive line, forming the vertical transistor comprising: forming a gate electrode extending in a direction; forming a gate dielectric material adjacent to a first side of the gate electrode and to a second side of the gate electrode; and after forming the gate electrode, forming a channel region adjacent to the gate dielectric material adjacent to the first side of the gate electrode and to the gate dielectric material adjacent to the second side of the gate electrode; and forming a second conductive line over the vertical transistor.

[0115] Embodiment 13: The method of embodiment 12, further comprising removing portions of the channel region to form another vertical transistor adjacent to the vertical transistor.

[0116] Embodiment 14: The method of embodiment 12 or embodiment 13, wherein forming a channel region comprises forming a channel region material comprising a multi-layer channel material adjacent to the gate dielectric material, the multi-layer channel material forming a barrier to prevent diffusion of hydrogen into the channel region.

[0117] Embodiment 15: The method of any one of embodiments 12-14, wherein forming a channel region comprises: forming a first indium gallium silicon oxide material adjacent to the gate dielectric material; forming an indium gallium zinc oxide adjacent to the first indium gallium silicon oxide material; and forming a second indium gallium silicon oxide material adjacent to the indium gallium zinc oxide.

[0118] Embodiment 16: The method of any one of embodiments 12-15, further comprising forming a conductive material on a side of the channel region and separated from the channel region by an electrically insulating material.

[0119] Embodiment 17: The method of any one of embodiments 12-16, wherein forming the channel region comprises: forming at least a first oxide semiconductor material adjacent to the gate dielectric material; and forming at least a second oxide semiconductor material adjacent to the first oxide semiconductor material.

[0120] Embodiment 18: The method of any one of embodiments 12-17, wherein forming a channel region comprises forming the channel region by atomic layer deposition.

[0121] Embodiment 19: The method of any one of embodiments 12-18, wherein forming a channel region comprises forming the channel region without exposing the channel region to a dry etchant.

[0122] Embodiment 20: A semiconductor device comprising: a vertical transistor comprising: a gate electrode; a first channel region on a first side of the gate electrode; a second channel region on a second side of the gate electrode, the second side opposite the first side; and a gate dielectric between the first channel region and the gate electrode and between the second channel region and the gate electrode; and a conductive material on a side of the first channel region and the second channel region, the conductive material electrically isolated from the first channel region and the second channel region by an electrically insulating material.

[0123] Embodiment 21: The semiconductor device of embodiment 20, wherein the first channel region and the second channel region comprise an oxide semiconductor material.

[0124] Embodiment 22: The semiconductor device of Embodiment 20 or Embodiment 21, wherein the gate electrode is positioned centrally between the first and second channel regions.

[0125] Embodiment 23: The semiconductor device of any one of Embodiments 20-22, wherein the vertical transistor is positioned vertically between a first conductive line and a second conductive line.

[0126] Embodiment 24: The semiconductor device of Embodiment 23, further comprising a vertical transistor positioned above the first and second conductive lines.

[0127] Embodiment 25: The semiconductor device of Embodiment 23 or Embodiment 24, wherein the conductive material comprises a line extending in a same direction as one of the first and second conductive lines.

[0128] Embodiment 26: The semiconductor device of any one of Embodiments 20-23, wherein an upper portion of the conductive material is not coplanar with an upper portion of the gate electrode.

[0129] Embodiment 27: The semiconductor device of any one of Embodiments 20-26, wherein the first and second channel regions each comprise a composite structure comprising indium gallium zinc oxide and indium gallium silicon oxide on sides of the indium gallium zinc oxide.

[0130] Embodiment 28: A method of operating a semiconductor device, the method comprising: applying a bias voltage to a gate electrode of a semiconductor device comprising a vertical transistor, the vertical transistor comprising: a gate electrode; a gate dielectric material on at least opposing sides of the gate electrode; and a channel material on sides of the gate dielectric material, the gate electrode being positioned between different portions of the channel material; and applying another bias voltage to a conductive material positioned between the transistor and at least another transistor of the semiconductor device.

[0131] Embodiment 29: The method of Embodiment 28, wherein applying another bias voltage to a conductive material comprises applying another bias voltage to the conductive material having a magnitude different from the bias voltage applied to the gate electrode.

[0132] Embodiment 30: The method of Embodiment 28 or Embodiment 29, wherein applying another bias voltage to a conductive material comprises applying a bias voltage of between about -2.0 V and about 2.0 V to the conductive material while applying the bias voltage to the gate electrode.

[0133] Embodiment 31 : The method of any one of embodiments 28-30, wherein applying a bias voltage to the gate electrode includes applying a bias voltage of about 0 V to the gate electrode when the vertical transistor is in an off state.

[0134] Embodiment 32: The method of embodiment 31, wherein applying another bias voltage to the conductive material includes applying another bias voltage to the conductive material when the bias voltage of about 0 V is applied to the gate electrode.

[0135] Embodiment 33: An electronic device comprising: at least one input device; at least one output device; at least one processor device operably coupled to the at least one input device and the at least one output device; and a semiconductor device operably coupled to the at least one processor device, the semiconductor device comprising an array of vertical transistors, at least one vertical transistor of the array of vertical transistors comprising: a gate electrode separated from a lower conductive contact by a gate dielectric material, the gate dielectric material overlying sidewalls of the gate electrode; a first channel region on a lateral side of the gate dielectric material; and a second channel region on a lateral side of the gate dielectric material opposite the lateral side of the first channel region, the gate electrode positioned between the first channel region and the second channel region.

[0136] While particular illustrative embodiments have been described in connection with the drawings, those of ordinary skill in the art will recognize and appreciate the embodiments encompassed by the present application are not limited to the embodiments explicitly shown and described herein. That is, there are many additions, deletions, modifications and variations that can be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present application, e.g., the scope of the claims as set forth below, including legal equivalents. In addition, features from one disclosed embodiment can be combined with features of another disclosed embodiment while remaining within the scope of the present application.

Claims

1. A semiconductor device comprising: a vertical transistor overlying a base structure and comprising: an electrode extending vertically perpendicular to a major plane of the base structure; a dielectric material adjacent to the electrode; and a channel region adjacent to the dielectric material and extending vertically perpendicular to the major plane of the base structure, the channel region comprising a composite structure including at least two semiconductor materials; a shield material extending perpendicular to the major plane of the base structure and in a vertical direction, the shield material comprising an electrically conductive material; and an electrically insulating material extending parallel to the channel region and the shield material and in a vertical direction and disposed laterally adjacent to the channel region and the shield material, the electrically insulating material comprising a first sidewall and a second sidewall opposite the first sidewall, the first sidewall of the electrically insulating material is in physical contact with the channel region along an entire height of the channel region, and the second sidewall of the electrically insulating material is in physical contact with the shield material along an entire height of the shield material.

2. The semiconductor device of claim 1, wherein the channel region comprises at least two oxide semiconductor materials.

3. The semiconductor device of claim 1, wherein the composite structure comprises a first oxide semiconductor material located between portions of a second oxide semiconductor material, the second oxide semiconductor material having a different material composition than the first oxide semiconductor material.

4. The semiconductor device of claim 1, wherein the shield material is located between the vertical transistor and an adjacent vertical transistor.

5. The semiconductor device of claim 1, wherein the shield material comprises a material having a P+ type conductivity.

6. The semiconductor device of claim 1, wherein the shield material is coupled to an electrically conductive contact configured to bias the shield material to a different voltage than the channel region.

7. The semiconductor device of claim 1, wherein a lower surface of the shield material is vertically located above a lower surface of the channel region.

8. The semiconductor device of claim 1, wherein the channel region comprises indium gallium silicon oxide.

9. The semiconductor device of claim 1, wherein a thickness of the electrode is greater than a thickness of the channel region.

10. A semiconductor device comprising: vertical transistors overlying a base structure and horizontally adjacent to each other, each vertical transistor comprising: an electrode extending vertically perpendicular to a major plane of the base structure; and a channel region extending vertically perpendicular to the major plane of the base structure, the channel region comprising an oxide semiconductor material; and a dielectric material disposed between the electrode and the channel region; a shield material comprising an electrically conductive material and extending perpendicular to the major plane of the base structure and in a vertical direction, the shield material disposed between horizontally adjacent vertical transistors; and an electrically insulating material extending parallel to the channel region and the shield material and in a vertical direction and disposed laterally adjacent to the channel region and the shield material, the electrically insulating material comprising a first sidewall and a second sidewall opposite the first sidewall, the first sidewall of the electrically insulating material is in physical contact with the channel region along an entire height of the channel region, and the second sidewall of the electrically insulating material is in physical contact with the shield material along an entire height of the shield material. an electrically insulating material extending in a vertical direction parallel to the channel region and the shielding material and disposed laterally adjacent to the channel region and the shielding material, the electrically insulating material comprising a first sidewall and a second sidewall opposite the first sidewall, the first sidewall of the electrically insulating material is in physical contact with the channel region along an entire height of the channel region, and the second sidewall of the electrically insulating material is in physical contact with the shielding material along an entire height of the shielding material.

11. The semiconductor device of claim 10, wherein the shielding material is separated from the channel region of the horizontally adjacent vertical transistor by the electrically insulating material.

12. The semiconductor device of claim 10, wherein the oxide semiconductor material comprises a first oxide semiconductor material and at least a second oxide semiconductor material.

13. The semiconductor device of claim 10, wherein the oxide semiconductor material: a first oxide semiconductor material; a second oxide semiconductor material adjacent to the first oxide semiconductor material; and a third oxide semiconductor material adjacent to the second oxide semiconductor material, the second oxide semiconductor material being between the first oxide semiconductor material and the third oxide semiconductor material.

14. The semiconductor device of claim 13, wherein the first oxide semiconductor material and the third oxide semiconductor material comprise substantially the same material composition.

15. The semiconductor device of claim 10, wherein the oxide semiconductor material comprises zinc tin oxide (ZTO), indium zinc oxide (IZO), or zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), and indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂) x ), Zinc oxide (Zn) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconium indium zinc oxide (Zr) x In y Zn z O a ), Hafnium indium zinc oxide (Hf x In y Zn z O a ), Tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconium zinc tin oxide (Zr) x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (IWO), or any combination thereof.

16. A method of forming a semiconductor device, the method comprising: forming a vertical transistor overlying a base structure, the vertical transistor comprising: forming a dielectric material over an electrode material, the electrode material extending vertically perpendicular to a major plane of the base structure; and forming a channel region over sides of the dielectric material and extending vertically perpendicular to the major plane of the base structure, forming the channel region comprising forming a composite semiconductor material; forming an electrically insulating material over sides of the channel region of the vertical transistor, the electrically insulating material comprising a first sidewall and a second sidewall opposite the first sidewall, the first sidewall of the electrically insulating material being in physical contact with the channel region along an entire height of the channel region; and forming a shielding material extending in a vertical direction perpendicular to the major plane of the base structure, the second sidewall of the electrically insulating material being in physical contact with the shielding material along an entire height of the shielding material, the shielding material comprising a conductive material between the vertical transistor and an adjacent vertical transistor.

17. The method of claim 16, wherein forming a channel region comprising a composite semiconductor material comprises forming the channel region comprising a composite semiconductor material comprising an oxide semiconductor material.

18. The method of claim 16, wherein forming a channel region comprising a composite semiconductor material comprises forming the composite semiconductor material comprising a second semiconductor material between a first semiconductor material and a third semiconductor material.

19. The method of claim 16, wherein forming a dielectric material over an electrode material comprises forming the dielectric material on opposite sides of the electrode material.

20. The method of claim 16, wherein forming a channel region comprises forming the channel region by atomic layer deposition.

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