A method of operating a two-tap pixel to reduce fixed pattern noise

Abstract

Disclosed herein are fixed pattern noise (FPN) reduction techniques in image sensors operated with pulsed illumination. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to a first charge at a first floating diffusion, the first charge corresponding to a first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to a second charge at the second floating diffusion, the second charge corresponding to a second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 373,722, filed August 28, 2022, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to image sensors. For example, several embodiments of the present technology relate to methods of operating pixels to reduce fixed pattern noise in image sensors operated, for example, with pulsed illumination. BACKGROUND

[0004] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design as well as image acquisition processing.

[0005] A typical image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having light-sensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges after absorbing the image light. The image charges photo-generated by the pixels can be measured as an analog output image signal on a column bitline, which varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the column bitline and converted to a digital value to provide information representative of the external scene. SUMMARY

[0006] Embodiments of the present disclosure provide a method of operating a two-tap pixel to reduce fixed pattern noise, the method comprising: during a first sub-exposure period of a frame, operating a first tap of the two-tap pixel to capture a first signal corresponding to a first charge at a first floating diffusion portion corresponding to the first tap, wherein operating the first tap includes activating a first transfer transistor of the first tap to transfer the first charge to the first floating diffusion portion, and wherein the first charge is generated by a photosensor of the two-tap pixel in response to first light incident on the photosensor, and operating a second tap of the two-tap pixel to capture a first parasitic signal corresponding to fixed pattern noise (FPN) at a second floating diffusion portion corresponding to the second tap; and during a second sub-exposure period of the frame, operating the second tap to capture a second signal corresponding to a second charge at the second floating diffusion portion, wherein operating the second tap includes activating a second transfer transistor of the second tap to transfer the second charge to the second floating diffusion portion, and wherein the second charge is generated by the photosensor in response to second light incident on the photosensor, and operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion portion.

[0007] Another embodiment of the present disclosure provides a method of operating an image sensor to reduce fixed pattern noise, the image sensor including a pixel having: (a) a photosensor; (b) a first tap including a first transfer transistor coupling a first charge storage region to the photosensor; and (c) a second tap including a second transfer transistor coupling a second charge storage region to the photosensor, the method comprising: during a first sub-exposure period of a frame, capturing a first signal using the first tap of the pixel, wherein capturing the first signal includes activating the first transfer transistor such that (i) the first transfer transistor is activated at a first timing corresponding to a time at which a first light is emitted by an illuminator or a time at which a second light is incident on the photosensor and (ii) a first charge corresponding to the first light or the second light is transferred from the photosensor to the first charge storage region via the first transfer transistor, and capturing a first parasitic signal using the second tap of the pixel, the first parasitic signal corresponding to fixed pattern noise (FPN) at the second charge storage region; and during a second sub-exposure period of the frame, capturing a second signal using the second tap of the pixel, wherein capturing the second signal includes activating the second transfer transistor such that (i) the second transfer transistor is activated at a second timing corresponding to a time at which a third light is emitted by the illuminator or a time at which a fourth light is incident on the photosensor and (ii) a second charge corresponding to the third light or the fourth light is transferred from the photosensor to the second charge storage region via the second transfer transistor, and capturing a second parasitic signal using the first tap of the pixel, the second parasitic signal corresponding to FPN at the first charge storage region. BRIEF DESCRIPTION OF DRAWINGS

[0008] Non-limiting and non-exhaustive embodiments of the present technology are described with reference to the following figures, wherein like reference numerals are used to refer to like components throughout.

[0009] Figure 1 is a partial schematic circuit diagram of a pixel configured in accordance with various embodiments of the present technology.

[0010] Figure 2A and 2B is a timing diagram illustrating a method of operating a pixel in accordance with various embodiments of the present technology.

[0011] Figure 3A is a timing diagram illustrating a correlated double sampling method of operating a pixel in accordance with various embodiments of the present technology.

[0012] Figure 3B is a timing diagram illustrating a four sampling method of operating a pixel in accordance with various embodiments of the present technology.

[0013] Figure 3C is a timing diagram illustrating an alternative four-sampling method of operating a pixel according to various embodiments of the present technology.

[0014] Figure 4 is a partial schematic circuit diagram of another pixel configured according to various embodiments of the present technology.

[0015] Figure 4A is a partial schematic circuit diagram of a back-porch gate, storage gate, and transfer transistor configured according to various embodiments of the present technology.

[0016] Figure 4B is a partial schematic circuit diagram of a storage gate and transfer transistor configured according to various embodiments of the present technology.

[0017] Figure 4C is a partial schematic circuit diagram of a back-porch gate, storage diode, and transfer transistor configured according to various embodiments of the present technology.

[0018] Figure 5 is a partial schematic circuit diagram of another pixel configured according to various embodiments of the present technology.

[0019] Figure 6 is a partial schematic circuit diagram of yet another pixel configured according to various embodiments of the present technology.

[0020] Figure 6A is a partial schematic circuit diagram of an active differential amplifier configured according to various embodiments of the present technology.

[0021] Figure 7 is a partial schematic circuit diagram of yet another pixel configured according to various embodiments of the present technology.

[0022] Figure 7A is a partial schematic circuit diagram of a capacitor bank of a pixel configured according to various embodiments of the present technology. Figure 7

[0023] Figure 8 is a flowchart illustrating a method of operating a pixel according to various embodiments of the present technology. Figure 7

[0024] Figure 9 is a partial schematic circuit diagram of another pixel configured according to various embodiments of the present technology.

[0025] Figure 10 is a flowchart illustrating a method of operating a pixel according to various embodiments of the present technology. Figure 9

[0026] Figure 11 ​​​is a flowchart of a method of a pixel illustrating operation in accordance with various embodiments of the present technology Figure 9 is a flowchart of an alternative method of a pixel.

[0027] Figure 12 is a partial schematic circuit diagram of a further pixel configured in accordance with various embodiments of the present technology.

[0028] Figure 13 is a flowchart of a method of a pixel illustrating operation in accordance with various embodiments of the present technology Figure 12

[0029] Figure 14 is a partial schematic circuit diagram of a further pixel configured in accordance with various embodiments of the present technology.

[0030] Figure 15 is a flowchart of a method of a pixel illustrating operation in accordance with various embodiments of the present technology Figure 14

[0031] Figure 16 is a partial schematic circuit diagram of a further pixel configured in accordance with various embodiments of the present technology.

[0032] Figure 17 is a timing diagram of a method of a pixel illustrating operation in accordance with various embodiments of the present technology Figure 16

[0033] Figure 18 is a partial schematic circuit diagram of a further pixel configured in accordance with various embodiments of the present technology.

[0034] Figure 19 is a table of a method of a pixel illustrating operation in accordance with various embodiments of the present technology Figure 18

[0035] Figure 20 is a partial schematic circuit diagram of a further pixel configured in accordance with various embodiments of the present technology.

[0036] Figure 21 is a table of a method of a pixel illustrating operation in accordance with various embodiments of the present technology Figure 20

[0037] Figure 22 is a partial schematic circuit diagram of a further pixel configured in accordance with various embodiments of the present technology.

[0038] Figure 23 is a flowchart of a method of a pixel illustrating operation in accordance with various embodiments of the present technology Figure 22

[0039] ​​​​​​Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and that the actual implementation can be of a different composition and form. For example, the sizes and relative positions of the elements in the figures can be exaggerated or rendered larger in the figure for clarity. Additionally, some of the elements depicted in the figures can not be necessary for implementation of the various aspects described herein and the elements can be interchanged with similar devices or ones functioning similarly. Also, the figures are not drawn to scale, but are instead shown as idealized representations. DETAILED DESCRIPTION

[0040] The present disclosure relates to image sensors used in conjunction with pulsed illumination. For example, several embodiments of the present technology relate to pixels and associated methods of operating the pixels to reduce fixed pattern noise, such as dark current fixed pattern noise, ambient parasitic light sensitivity, and pulsed signal parasitic light sensitivity. Some of the methods described herein utilize correlated double sampling (CDS) techniques, while others of the methods described herein utilize four sampling techniques. In the following description, specific details are set forth to provide a thorough understanding of the aspects of the technology. However, persons skilled in the relevant art will recognize that the systems, apparatuses and techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the technology.

[0041] Reference throughout this specification to "example", "an example", or "embodiment" means that a particular feature, structure, or characteristic described in connection with the example or embodiment is included in at least one example or embodiment of the technology. Therefore, the appearances of the phrases "in example", "as an example", or "for example" in various places throughout this specification are not necessarily referring to the same example or embodiment, and are not necessarily mutually exclusive. Furthermore, the features, structures, or characteristics of the technology described throughout this specification can be combined in any suitable manner in different examples and embodiments of the technology.

[0042] For ease of description, spatial relative terms (e.g., “below,” “under,” “above,” “below,” “above,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like) may be used herein to describe the relationship of an element or feature relative to one or more other elements or features, as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of the device or system during use or operation. For example, if the device or system illustrated in the figures rotates, turns, or flips about a horizontal axis, then an element or feature described as “below,” “under,” or “below” one or more other elements or features may be oriented “above” one or more other elements or features. Therefore, the exemplary terms “below” or “below” are non-limiting and may cover both above and below orientations. Devices or systems may also be oriented in other ways than illustrated in the figures (e.g., rotated ninety degrees about a vertical axis or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly. In addition, it should be understood that when an element is referred to as being "between" two other elements, it may be the only element between the other two elements or there may be one or more intermediary elements.

[0043] Throughout this specification, several terms used in the field are employed. These terms have their general meanings in the field, unless specifically defined herein or indicated otherwise by the context in which they are used. It should be noted that element names and symbols (e.g., Si for silicon) are used interchangeably throughout this document; however, they have the same meaning.

[0044] A. SUMMARY

[0045] Image sensors are often used in conjunction with pulsed illumination for various applications (e.g., automotive applications, indirect time-of-flight (iTOF) applications, blood pressure measurement / monitoring applications, blood oxygen saturation measurement / monitoring applications, active stereo applications, structured light applications, laser scanning applications). For example, image sensors are often used in the automotive industry with pulsed illumination for safety systems, driver assistance systems, and in-vehicle monitors. As a particular example, image sensors are often used in a camera pointed forward of an automobile to detect objects (e.g., people, cars, traffic signs), capture speed measurements, detect road markings, and / or measure the distance between the automobile and another vehicle in front of the automobile. Such front-facing cameras often utilize gated imaging to address low-light or poor visibility conditions. For example, in the dark, the energy or intensity of active illumination (a) projected in front of the automobile and (b) received at a given location in front of the automobile is inversely proportional to the square of the distance between the given location and the light source. Thus, the illumination can be pulsed to enable adjustment of the image sensor exposure in the front-facing camera of the automobile and the distance the image sensor "sees" in front of the automobile (similar to high dynamic range techniques), where the number of light pulses projected in front of the automobile is positively correlated with the distance the image sensor "sees" in front of the automobile.

[0046] As another example, in poor driving conditions (e.g., fog), the illumination projected in front of the automobile is scattered to a large extent, and both (typically) short-wave infrared and thermal imaging are insufficient to provide sufficient visibility in such conditions. Thus, in these cases, the illumination projected in front of the automobile can be pulsed, and short-exposure time gating techniques can be utilized so that only the content within a depth slice in front of the automobile is captured by the image sensor in the front-facing camera of the automobile. Scattered light outside the selected depth slice can be suppressed and not captured by the image sensor.

[0047] Another automotive application in which image sensors with pulsed illumination are often utilized is in driver monitor systems. For example, infrared illuminators are often used in systems that monitor the driver to detect and reduce glare perceived by the driver. The infrared illumination can be pulsed to improve the signal-to-noise ratio of the illumination detected by the image sensor of the camera used in the monitoring system.

[0048] A common problem in several of the above applications is fixed pattern noise (FPN), including dark current FPN, ambient parasitic light sensitivity (PLS), and pulse signal PLS. PLS refers to the sensitivity of an image sensor to light outside of the exposure period (e.g., when the'shutter' is closed). In pulsed illumination applications, signal light can arrive at the image sensor too late or too early due to, for example, reflections from glass covering or protecting the image sensor, multi-path reflections in the external scene, scattering, etc. In several applications, signal light that arrives at the image sensor too late or too early and is detected by the image sensor can be undesired noise. Pulse signal PLS refers to this undesired noise.

[0049] Various techniques can be used to address FPN. For example, a 1-tap pixel can be operated to: (a) transfer first charges captured by a photosensor during a bright frame (e.g., a frame in which a light source emits a light pulse) to a floating diffusion; (b) read out a signal corresponding to the first charges at the end of the bright frame; (c) transfer second charges captured by the photosensor during a dark frame (e.g., a frame in which the light source does not emit a light pulse) to the floating diffusion; and (d) read out a reference signal corresponding to the second charges at the end of the dark frame. During the bright frame, the first charges can be transferred to the floating diffusion with a timing corresponding to the timing of the light pulse emitted by the light source. After readout, the reference signal from the dark frame can be used to subtract dark current FPN and ambient PLS from the signal corresponding to the bright frame. However, this technique does not account for pulse signal PLS. Additionally, the time multiplexing used in this technique limits the sampling frequency of the image sensor.

[0050] In a second technique, a 1-tap pixel can be operated to: (a) transfer first charges captured by a photosensor to a floating diffusion with a timing corresponding to the time at which a light source emits a first light pulse during a first bright frame; (b) read out a signal corresponding to the first charges at the end of the first bright frame; (c) transfer second charges captured by the photosensor to the floating diffusion with a timing prior to the light source emitting a second light pulse during a second bright frame; and (d) read out a reference signal corresponding to the second charges at the end of the second bright frame. The reference signal can then be used to subtract dark current FPN, ambient PLS, and pulse signal PLS from the signal corresponding to the first bright frame. However, this technique doubles the power consumed by the illuminator compared to the first technique discussed above. Additionally, similar to the first technique discussed above, the time multiplexing used in this second technique limits the sampling frequency of the image sensor.

[0051] In a third technique, a 2-tap pixel can be operated to: (a) transfer first charge captured by the photosensor to a first floating diffusion using a first transfer transistor and with a timing that is before a first light pulse is emitted by the light source during a first bright frame; (b) transfer second charge captured by the photosensor to a second floating diffusion using a second transfer transistor and with a timing that corresponds to a time at which the first pulse of light is emitted by the light source during the first bright frame; (c) read out a signal corresponding to the second charge at the end of the first bright frame; (d) transfer third charge captured by the photosensor to the first floating diffusion using the first transfer transistor and with a timing that is before a second light pulse is emitted by the light source during a second bright frame; (e) transfer fourth charge captured by the photosensor to the second floating diffusion using the second transfer transistor and with a timing that corresponds to a time at which the second pulse of light is emitted by the light source during the second bright frame; and (f) read out a reference signal corresponding to the first and third charges at the end of the second bright frame. The reference signal can then be used to tease out dark current FPN, ambient PLS, and pulsed signal PLS from the signal read out at the end of the first bright frame. However, in this technique there is a mismatch in PLS and dark current FPN captured in the signal and reference signal, which can cause residual errors. In addition, this third technique can suffer from residual errors from offset or gain errors between the different transfer transistors.

[0052] To address these concerns, the present technology involves 2-tap pixels and methods of operating 2-tap pixels that can be used to reduce FPN (e.g., dark current FPN, ambient PLS, and pulsed signal PLS) in image sensors operated with pulsed illumination. For example, several embodiments of the present technology involve 2-tap pixels in which: (a) during a first bright frame or sub-exposure, a first tap is operated to capture one or more first light pulses emitted by a light source and a second tap is operated to capture FPN at one or more timings when the light source is not emitting the one or more first light pulses; and (b) during a second (e.g., subsequent, immediate) bright frame or sub-exposure, the first tap is operated to capture FPN at one or more timings when the light source is not emitting one or more second light pulses and the second tap is operated to capture the one or more second light pulses emitted by the light source. Each tap can then be read out using CDS techniques or four-sampling techniques, and different signals read out from the first and second taps can be used to tease out FPN.

[0053] Because each light pulse emitted by the light source is captured during each frame or sub-exposure, the present technology does not utilize or require additional illuminator power. Additionally, the temporal multiplexing utilized by the present technology is not expected to significantly limit the sampling frequency. Moreover, the present technology is expected to avoid mismatch between the captured dark current FPN and the PLS. Thus, the present technology is expected to reduce residual errors that can arise due to mismatch. Furthermore, because both the first and second taps of a pixel are used to capture light pulses emitted by the light source as well as FPN, the present technology is expected to reduce or avoid residual errors that can arise due to offsets or gain errors between different transfer transistors of the taps.

[0054] B. Image sensors operated with pulsed illumination and selected embodiments of pixels and associated methods for reducing fixed pattern noise Figure 1

[0055] Figure 2A is a partial schematic circuit diagram of a pixel 100 configured in accordance with various embodiments of the present technology. As shown, the pixel 100 includes an overflow transistor 101, a photosensor 102 having an anode coupled to ground and a cathode coupled to the overflow transistor 101, and two taps each coupled to the overflow transistor 101 and the photosensor 102. A first of the taps includes a first transfer transistor 103, a floating diffusion FD A , a first resistive transistor 105, a first source follower buffer or transistor 107, and a first row select transistor 109. A second of the taps includes a second transfer transistor 104, a floating diffusion FD B , a second reset transistor 106, a second source follower buffer or transistor 108, and a second row select transistor 110. The first and second row select transistors 109 and 110 can be coupled to column readout circuitry 120 (e.g., sample and hold circuitry, pixel output buffers, etc.).

[0056] The photosensor 102 can be a photodiode. In other embodiments, the photosensor 102 can be any other suitable type of photosensor or photodetector (e.g., a metal-semiconductor-metal (MSM) photodetector, a phototransistor, a photoconductive detector, or a phototube). In operation, the photosensor 102 can be configured to photo generate electrical charges or photocurrents in response to incident light (e.g., light emitted (e.g., in one or more pulses) from a light source (not shown) and / or reflected to the photosensor 102).

[0057] Various signals are provided to the pixel 100 for controlling the operation of the pixel 100. For example, an overflow gate signal OFG can be supplied to the overflow transistor 101 to selectively activate and clear the charge generated or accumulated by the photosensor 102. The first transfer transistor 103 can be supplied with a transfer signal TxA, and the second transfer transistor 104 can be supplied with a transfer signal TxB. The transfer signal TxA can be configured to selectively activate the first transfer transistor 103 and transfer the charge generated or accumulated by the photosensor 102 to the floating diffusion FD A . Similarly, the transfer signal TxB can be configured to selectively activate the second transfer transistor 104 and transfer the charge generated or accumulated by the photosensor 102 to the floating diffusion FD B . The first and second reset transistors 105 and 106 are supplied with respective reset signals RST to selectively activate the reset transistors 105 and 106 and reset the corresponding floating diffusion FD A or FD B . The reset signals RST supplied to the first and second reset transistors 105 and 106 can be the same signal or different signals. The voltage at the floating diffusion FD A due to the charge at the floating diffusion FD A may be applied to the gate of the first source follower transistor 107. The first source follower transistor 107 is then configured to convert the charge at the floating diffusion FD A to a corresponding analog signal at the source of the first source follower transistor 107. The analog signal can be passed to the column readout circuitry 120 after assertion of a row select signal RS supplied to the gate of the first row select transistor 109. Similarly, the voltage at the floating diffusion FD B due to the charge at the floating diffusion FD B may be applied to the gate of the second source follower transistor 108. The second source follower transistor 108 is then configured to convert the charge at the floating diffusion FD B to a corresponding analog signal at the source of the second source follower transistor 108. The analog signal can be passed to the column readout circuitry 120 after assertion of a row select signal RS supplied to the gate of the second row select transistor 110. The row select signal RS applied to the gate of the second row select transistor 110 can be the same signal as the row select signal RS applied to the gate of the first row select transistor 109 or a different signal.

[0058] Figure 1 and 2B are respectively illustrative of the operation of a pixel (e.g., Figure 2AFIGS. 23 and 24 are timing diagrams 230 and 240, respectively, of a method of reading out a pixel 100, any of the other pixels discussed and illustrated herein, or another pixel of the present technology. Timing diagrams 230 and 240 each include a series of two frames, where each frame includes two sub-frames (e.g., sub-exposure periods, phases). As shown in timing diagram 230, the pixel 100 is configured to sample a first parasitic or noise signal (e.g., FPN) during a first sub-frame of a first frame. As shown in timing diagram 240, the pixel 100 is configured to sample a second parasitic or noise signal (e.g., PLS) during a second sub-frame of the first frame. As shown in both timing diagrams 230 and 240, the pixel 100 is configured to sample a third parasitic or noise signal (e.g., PLS) during a first sub-frame of a second frame. As shown in both timing diagrams 230 and 240, the pixel 100 is configured to sample a fourth parasitic or noise signal (e.g., PLS) during a second sub-frame of the second frame. Figure 1 As shown in timing diagrams 230 and 240, the illuminator or light source is configured to emit a single light pulse 232 in each sub-frame. For example, the illuminator emits a first light pulse 232a during a first sub-frame of a first frame, a second light pulse 232b during a second sub-frame of the first frame, a third light pulse 232c during a first sub-frame of a second frame, and a fourth light pulse 232d during a second sub-frame of the second frame. Additionally or alternatively, the pulses 232a-d can correspond to light power received by the pixel with the timing shown.

[0059] Referring to both Figure 2A and 2A , the transfer signal TxB supplied to the gate of the second transfer transistor 104 of the pixel 100 can be asserted with timing prior to the illuminator emitting the first light pulse 232a during the first sub-frame of the first frame and / or with timing when the pixel is not receiving a substantial amount of light power. Asserting the transfer signal TxB activates the second transfer transistor 104, allowing any charge generated or accumulated at the photosensor 102 to be transferred to the floating diffusion FD B Because the second transfer transistor 104 is activated with timing when the illuminator is not emitting a light pulse and / or with timing when the pixel is not receiving a substantial amount of light power, any charge transferred to the floating diffusion FD B when the second transfer transistor 104 is activated represents a dark current FPN, ambient PLS, and pulse signal PLS captured or generated by the pixel 100. In other words, the second tap of the pixel 100 is used to sample FPN (or a first parasitic or noise signal) during the first sub-frame of the first frame. The transfer signal TxB is then de-asserted during the first sub-frame of the first frame, and prior to the illuminator emitting the first light pulse 232a and / or prior to the pixel receiving a substantial amount of light power corresponding to the light pulse 232a. De-asserting the transfer signal TxB deactivates the second transfer transistor 104.

[0060] Subsequently, a transfer signal TxA supplied to the gate of the first transfer transistor 103 of the pixel 100 can correspond to a timing assertion of the time at which the illuminator emits the first light pulse 232a during the first sub-frame of the first frame (e.g., just prior to said time, contemporaneously with said time) and / or the time at which the pixel receives the first light pulse 232a during the first sub-frame. Asserting the transfer signal TxA activates the first transfer transistor 103, allowing any charge generated or accumulated at the photosensor 102 (e.g., in response to light corresponding to the first pulse 232a incident on the photosensor 102) to be transferred to the floating diffusion FD A Because the period of time during which the first transfer transistor 103 is activated during the first sub-frame of the first frame overlaps with the period of time when the illuminator emits the first light pulse 232a during the first sub-frame of the first frame and / or when the pixel receives a significant amount of optical power, the charge transferred to the floating diffusion FD A when the first transfer transistor 103 is activated represents a combination of the signal light, dark current FPN, ambient PLS, and pulse signal PLS captured or generated by the pixel 100. In other words, the first tap of the pixel 100 is used to sample a first signal or first signal voltage representing a combination of the signal light and FPN during the first sub-frame of the first frame. Next, the transfer signal TxA is de-asserted during the first sub-frame of the first frame (e.g., when or shortly after the illuminator stops emitting the first light pulse 232a) and before the end of the first sub-frame of the first frame. De-asserting the transfer signal TxA deactivates the first transfer transistor 103.

[0061] At the end of the first sub-frame of the first frame, row select signals RS applied to the gates of the first and second row select transistors 109 and 110 are asserted to activate the first and second row select transistors 109 and 110. Next, a signal S A corresponding to the voltage at the floating diffusion FD A-0 is read out of the pixel 100 to the column readout circuitry 120. In addition, a signal S B corresponding to the voltage at the floating diffusion FD B-1 is read out of the pixel 100 to the column readout circuitry 120. The signals S A-0 and S B-1 may be stored in the column readout circuitry 120 for further processing at the end of the first frame.

[0062] During the second sub-frame of the first frame, the transfer signal TxA supplied to the gate of the first transfer transistor 103 of the pixel 100 can be asserted at a timing prior to the timing at which the illuminator emits the second light pulse 232b during the second sub-frame of the first frame and / or at a timing at which the pixel does not receive a substantial amount of light power. Asserting the transfer signal TxA activates the first transfer transistor 103, allowing any charge generated or accumulated at the photosensor 102 to be transferred to the floating diffusion FD A Because the first transfer transistor 103 is activated at a timing at which the illuminator does not emit a light pulse and / or at a timing at which the pixel does not receive a substantial amount of light power, any charge transferred to the floating diffusion FD A when the first transfer transistor 103 is activated represents the dark current FPN, the ambient PLS, and the pulse signal PLS captured or generated by the pixel 100. In other words, the first tap of the pixel 100 is now used to sample the FPN (or second parasitic or noise signal) during the second sub-frame of the first frame (e.g., rather than being used to sample the combination of the signal light and the FPN as was done during the first sub-frame of the first frame). Then, during the second sub-frame of the first frame, and prior to the illuminator emitting the second light pulse 232b and / or prior to the pixel receiving a substantial amount of light power corresponding to the light pulse 232b, the transfer signal TxA is de-asserted. De-asserting the transfer signal TxA deactivates the first transfer transistor 103.

[0063] Subsequently, the transfer signal TxB supplied to the gate of the second transfer transistor 104 of the pixel 100 can be asserted at a timing corresponding to (e.g., just prior to, contemporaneous with) the time at which the illuminator emits the second light pulse 232b during the second sub-frame of the first frame and / or the time at which the pixel receives the second light pulse 232b during the second sub-frame. Asserting the transfer signal TxB activates the second transfer transistor 104, allowing any charge generated or accumulated at the photosensor 102 (e.g., in response to light corresponding to the second pulse 232b incident on the photosensor 102) to be transferred to the floating diffusion FD B Because the second transfer transistor 104 is activated for a period of time during the second sub-frame of the first frame that overlaps with the period of time when the illuminator emits the second light pulse 232b and / or when the pixel receives a substantial amount of light power during the second sub-frame of the first frame, any charge transferred to the floating diffusion FD Bthe combination of the signal light, the dark current FPN, the ambient PLS, and the pulsed signal PLS captured or generated by the pixel 100. In other words, the second tap of the pixel 100 is now used to sample a second signal or second signal voltage representing the combination of the signal light and the FPN during the second sub-frame of the first frame (e.g., instead of sampling only the FPN as was done during the first sub-frame of the first frame). Then, the transfer signal TxB is de-asserted during the second sub-frame of the first frame (e.g., at or shortly after the illuminator stops emitting the second light pulse 232b) and before the end of the second sub-frame of the first frame. De-asserting the transfer signal TxB deactivates the second transfer transistor 104.

[0064] At the end of the second sub-frame of the first frame (indicating the end of the first frame), the row select signals RS applied to the gates of the first and second row select transistors 109 and 110 are asserted to activate the first and second row select transistors 109 and 110. Then, at the end of the second sub-frame, the signal S A corresponding to the voltage at the floating diffusion FD A-1 and applied to the gate of the first source follower transistor 107 is read out from the pixel 100 to the column readout circuitry 120. In addition, at the end of the second sub-frame, the signal S B corresponding to the voltage at the floating diffusion FD B-0 and applied to the gate of the second source follower transistor 108 is read out from the pixel 100 to the column readout circuitry 120.

[0065] Then, the column readout circuitry 120 can subtract the signal S A-0 from the signal S A-1 to isolate the FPN (dark current FPN, ambient PLS, and pulsed signal PLS). In addition, the column readout circuitry 120 can subtract the signal S B-0 from the signal S B-1 to isolate the FPN (dark current FPN, ambient PLS, and pulsed signal PLS). Then, the column readout circuitry 120 can add the difference between (a) the signal S A-0 and S A-1 to (b) the difference between the signal S B-0 and S B-1 . The resulting sum can represent the sum of the signal light component captured by the pixel 100 during the first frame multiplied by the camera gain factors of the first and second taps of the pixel 100. The above process can be repeated for subsequent frames, including the second frame described in Figure 2B

[0066] Referring now to Figure 2A , the timing diagram 240 illustrates a process generally similar to that described by Figure 1 ​The method of the method illustrated by timing diagram 230. However, as shown in timing diagram 240, the illuminator emits several light pulses 242 per sub-frame of a given frame. More specifically, in the illustrated embodiment, the illuminator is configured to emit three light pulses 242a-242c during a first sub-frame of a first frame and three light pulses 242d-242f during a second sub-frame of the first frame. Here, the transfer signal TxA is pulsed three times during the first sub-frame at a timing corresponding to the times at which the illuminator emits the three light pulses 242a-242c and / or the times at which the pixel receives a large amount of optical power corresponding to the three pulses 242a-242c, and the transfer signal TxB is pulsed during the first sub-frame at times corresponding to when the illuminator does not emit light (e.g., at times shortly before the illuminator emits the pulses 242a-242c) and / or when the pixel does not receive a large amount of optical power corresponding to the three pulses 242a-242c. In other words, referring to both Figure 2B and 2B , the first tap of the pixel 100 including the first transfer transistor 103 and the floating diffusion FD A may be used during the first sub-frame to sample the combination of signal light and FPN from each of the three pulses 242a-242c, and the second tap of the pixel including the second transfer transistor 104 and the floating diffusion FD B may be used during the first sub-frame to sample the FPN.

[0067] At the end of the first sub-frame of the first frame, the row select signal RS applied to the gates of the first and second row select transistors 109 and 110 is asserted to activate the first and second row select transistors 109 and 110. Then, at the end of the first sub-frame, the signal S A corresponding to the voltage at the floating diffusion FD A-0 is read out from the pixel 100 to the column readout circuitry 120. In addition, at the end of the first sub-frame, the signal S B corresponding to the voltage at the floating diffusion FD B-1 is read out from the pixel 100 to the column readout circuitry 120. The signals S A-0 and S B-1 may be stored in the column readout circuitry 120 for further processing at the end of the first frame.

[0068] During the second sub-frame, the transfer signal TxA is pulsed at times corresponding to when the illuminator is not emitting light (e.g., times shortly before the illuminator emits each of the three pulses 242d through 242f) and / or when the pixel is not receiving a substantial amount of light power corresponding to the three pulses 242d through 242f, and the transfer signal TxB is pulsed at times corresponding to when the illuminator is emitting the pulses 242d through 242f and / or when the pixel is receiving a substantial amount of light power corresponding to the three pulses 242d through 242f. In other words, the first tap of the pixel 100 is used to sample FPN during the second sub-frame, and the second tap of the pixel 100 is used to sample the combination of signal light (corresponding to each of the three pulses 242d through 242f) and FPN during the second sub-frame.

[0069] At the end of the second sub-frame of the first frame (indicating the end of the first frame), the row select signal RS applied to the gates of the first and second row select transistors 109 and 110 is asserted to activate the first and second row select transistors 109 and 110. Then, at the end of the second sub-frame, the signal S A corresponding to the voltage at the floating diffusion FD A-1 and applied to the gate of the first source follower transistor 107 is read out from the pixel 100 to the column readout circuitry 120. In addition, at the end of the second sub-frame, the signal S B corresponding to the voltage at the floating diffusion FD B-0 and applied to the gate of the second source follower transistor 108 is read out from the pixel 100 to the column readout circuitry 120.

[0070] Then, the column readout circuitry 120 can subtract the signal S A-0 from the signal S A-1 to isolate FPN (dark current FPN, ambient PLS, and pulsed signal PLS). In addition, the column readout circuitry 120 can subtract the signal S B-0 from the signal S B-1 to isolate FPN (dark current FPN, ambient PLS, and pulsed signal PLS). Then, the column readout circuitry 120 can add the difference between (a) the signal S A-0 and S A-1 to the difference between (b) the signal S B-0 and S B-1 . The resulting sum can represent the sum of the signal light component captured by the pixel 100 during the first frame multiplied by the camera gain factors of the first and second taps of the pixel 100. The above process can be repeated for subsequent frames, including the second frame described in Figure 2A .

[0071] Although shown in the timing diagram 230 of Figure 2B with a single light pulse 232 per sub-frame andFigure 2A Each sub-frame in timing diagram 240 has three light pulses 242, but in other embodiments of the technology any number of light pulses 232, 242 (and thus any number of pulses of transfer signals TxA and TxB) can be used per sub-frame. Additionally, the number of light pulses 232, 242 in a given sub-frame can differ from the number of pulses of transfer signal TxA in the given sub-frame and / or the number of pulses of transfer signal TxB in the given sub-frame. Additionally or alternatively, the positions of light pulses 232, 242, the positions of pulses of transfer signal TxA, and / or the positions of pulses of transfer signal TxB can differ from the positions of light pulses 232, 242, the positions of pulses of transfer signal TxA, and / or the positions of pulses of transfer signal TxB, respectively, across two sub-frames of a single frame or corresponding sub-frames across two different frames (e.g., the first sub-frame of the first frame and the first sub-frame of the second frame or the second sub-frame of the first frame and the second sub-frame of the second frame).

[0072] In these and other embodiments, the order in which transfer signals TxA and TxB are pulsed across sub-frames or frames can differ from the order shown in Figure 3A and 2B . For example, transfer signal TxA can be pulsed for the first time during the first sub-frame and be misaligned with light pulses 232, 242 emitted from the luminaire; transfer signal TxB can be pulsed for the second time during the first sub-frame and be aligned (e.g., centered on) light pulses 232, 242 emitted from the luminaire; transfer signal TxB can be pulsed for the first time during the second sub-frame and be misaligned with light pulses 232, 242 emitted from the luminaire; and / or transfer signal TxA can be pulsed for the second time during the second sub-frame and be aligned (e.g., centered on) light pulses 232, 242 emitted from the luminaire. As another example, transfer signal TxB can be pulsed after (rather than before) light pulses 232, 242 are emitted by the luminaire during the first sub-frame and be misaligned with light pulses 232, 242; and / or transfer signal TxA can be pulsed after (rather than before) light pulses 232, 242 are emitted by the luminaire during the second sub-frame and be misaligned with light pulses 232, 242.

[0073] In these and yet other embodiments, the timing of the pulses of transfer signals TxA and TxB can differ from that shown in timing diagrams 230 and 240. For example, in timing diagrams 230 and 240, transfer signal TxA is pulsed during the first sub-frame at a timing that is aligned with (e.g., centered on) the times at which the luminaire emits light pulses 232, 242, and transfer signal TxB is pulsed during the first sub-frame so that transfer signal TxB is not asserted at any of the times at which the luminaire emits light pulses 232, 242. In other embodiments of the present technology, transfer signal TxA can be pulsed during the first sub-frame at a timing that is only partially aligned with (e.g., offset from the center of) the time periods during which the luminaire emits light pulses 232, 242, and / or transfer signal TxB can be pulsed during the first sub-frame so that transfer signal TxB partially overlaps the time periods during which the luminaire emits light pulses 232, 242. Generally, for ideal operation, (a) one of transfer signals TxA or TxB should be asserted during the first sub-frame so that one or more light pulses 232, 242 emitted by the luminaire or light source and / or a substantial amount of optical power corresponding to a desired distance or distance range is captured and transferred to the corresponding one of floating diffuser FD A or FD B (b) the other of transfer signals TxA or TxB should be asserted during the first sub-frame so that one or more light pulses 232, 242 emitted by the luminaire and / or a substantial amount of optical power corresponding to a desired distance or distance range is not captured and transferred to the other of floating diffuser FD A or FD B (c) the other of transfer signals TxA or TxB should be asserted during the second sub-frame so that one or more light pulses 232, 242 emitted by the luminaire and / or a substantial amount of optical power corresponding to a desired distance or distance range is captured and transferred to the other of floating diffuser FD A or FD B (d) one of transfer signals TxA or TxB should be asserted during the second sub-frame so that one or more light pulses 232, 242 emitted by the luminaire and / or a substantial amount of optical power corresponding to a desired distance or distance range is not captured and transferred to the corresponding one of floating diffuser FD A or FD B .

[0074] Figure 1 is a timing diagram 350 illustrating a CDS method for an operational pixel (e.g., pixel 100 of Figure 1 , any of the other pixels discussed and illustrated herein, or another pixel of the present technology) that can be utilized in connection with the FPN reduction methods described herein according to various embodiments of the present technology. Reference is made to Figure 2Aand 3A The method begins by asserting the overflow gate signal OFG and the reset signal RST at time tO. Asserting the overflow gate signal OFG activates the overflow transistor 101 of the pixel 100 and clears any charge generated and accumulated at the photosensor 102. Asserting the reset signal RST activates the first and second reset transistors 105 and 106 and clears any charge accumulated at the floating diffusion FD A and FD B . Thus, the voltage V A at the floating diffusion FD FDA and the voltage V B at the floating diffusion FD FDB are reset to a reference voltage (e.g., V DD or another positive power supply voltage) via the first and second reset transistors 105 and 106, respectively. Then, the reset signal RST is de-asserted at time tl while the overflow gate signal OFG remains asserted.

[0075] At time t2, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a first portion of the signal S A corresponding to the voltage V FDA at the floating diffusion FD A-0 (or a reference voltage for the signal S A-0 ) and (b) read out from the pixel 100 a first portion of the signal S B corresponding to the voltage V FDB at the floating diffusion FD B-1 (or a reference voltage for the signal S B-1 ). Time t2 can correspond to a timing at which an illuminator (not shown) does not emit a light pulse with it or one or more light pulses from the illuminator and a large amount of light power corresponding to a desired distance or distance range is not received by the pixel 100 and transferred to the floating diffusion FD A and / or FD B . As such, the first portions of the signals S A-0 and S B-1 may represent samples of FPN (dark current FPN, ambient PLS, and pulsed signal PLS) captured or generated by the pixel 100 at the floating diffusion FD A and FD B , respectively. The first portions of the signals S A-0 and S B-1 read out from the pixel at time t2 can be stored for further processing at a later time, e.g., in a sampling capacitor of the column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0076] From time t3 to time t4, the transfer signal TxA is asserted to activate the first transfer transistor 103 of the first tap of the pixel 100. The time period between time t3 and time t4 can correspond to the timing with which the illuminator (not shown) emits one or more light pulses or the timing with which a large amount of light power from one or more light pulses emitted by the illuminator and corresponding to a desired distance or distance range is received by the pixel 100 and transferred to the floating diffusion FD A Thus, the photosensor 102 of the pixel 100 photo-generates charge or photocurrent during this time period, which is transferred to the floating diffusion FD A via the first transfer transistor 103. As a result, the voltage V A at the floating diffusion FD FDA decreases between time t3 and time t4. At time t4, the transfer signal TxA can be de-asserted, thereby de-activating the first transfer transistor 103. In some embodiments, the overflow gate signal OFG can additionally be asserted to activate the overflow transistor 101 and clear any charge at the photosensor 102.

[0077] At time t5, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a second portion of the signal S A corresponding to the voltage V FDA at the floating diffusion FD A-0 (or the signal voltage of the signal S A-0 ) and (b) read out from the pixel 100 a second portion of the signal S B corresponding to the voltage V FDB at the floating diffusion FD B-1 (or the signal voltage of the signal S B-1 ). As discussed above, the voltage V FDA decreases from time t3 to time t4 at least in part due to the pixel 100 receiving light power from one or more light pulses emitted by the illuminator and corresponding to a desired distance or distance range. Thus, the signals S A-0 and / or the second portion of S B-1 read out from the pixel 100 at time t5 can represent samples of a combination of: (a) charge (if any) from the signal light received from the one or more light pulses reaching the floating diffusion FD A and / or FD B respectively; and (b) FPN (dark current FPN, ambient PLS, and pulsed signal PLS) at the floating diffusion FD A and / or FD B respectively. The signals S A-0 and S B-1The first portion of signal S B-0 may be stored for further processing at a later time, e.g., in a sampling capacitor of column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0078] At time t6, reset signal RST is asserted to activate first and second reset transistors 105 and 106. As discussed above, activation of first and second reset transistors 105 and 106 clears any charge accumulated at floating diffusion FD A and FD B . Thus, voltage V A at floating diffusion FD FDA and voltage V B at floating diffusion FD FDB are reset to a reference voltage (e.g., V DD or another positive power supply voltage) via first and second reset transistors 105 and 106, respectively. Then, reset signal RST is de-asserted at time t7 while overflow gate signal OFG remains asserted.

[0079] At time t8, row select signal RS is asserted to activate first and second row select transistors 109 and 110 of pixel 100 and (a) to read out from pixel 100 a first portion of signal S A-1 corresponding to voltage V A-1 at floating diffusion FD B (or a reference voltage for signal S FDB ) and (b) to read out from pixel 100 a first portion of signal S B-0 corresponding to voltage V B-0 at floating diffusion FD A (or a reference voltage for signal S B ). Time t8 can correspond to a timing at which an illuminator (not shown) does not emit a light pulse therewith or to a timing at which a light pulse or pulses emitted by the illuminator and corresponding to a desired distance or distance range do not have a substantial amount of light power received by pixel 100 and transferred to floating diffusions FD A-1 and FD B-0 . As such, the first portions of signals S A and S B may represent samples of FPN (dark current FPN, ambient PLS, and pulsed signal PLS) captured or generated by pixel 100 at floating diffusions FD A-1 and FD B-0 , respectively. The first portions of signals S B and S B read out from the pixel at time t8 can be stored for further processing at a later time, e.g., in a sampling capacitor of column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0080] From time t9 to time tlO, the transfer signal TxB is asserted to activate the second transfer transistor 104 of the second tap of the pixel 100. The time period between time t9 and time tlO can correspond to the timing at which the illuminator (not shown) emits one or more light pulses or the timing at which a substantial amount of light power from one or more light pulses emitted by the illuminator and corresponding to a desired distance or distance range is received by the pixel 100 and transferred to the floating diffusion FD B Thus, the photosensor 102 of the pixel 100 photo-generates charge or photocurrent during this time period, which is transferred to the floating diffusion FD B via the second transfer transistor 104. As a result, the voltage V B at the floating diffusion FD FDB decreases between time t9 and time tlO. At time tlO, the transfer signal TxB can be de-asserted, thereby de-activating the second transfer transistor 104. In addition, the overflow gate signal OFG can be asserted to activate the overflow transistor 101 and clear any charge at the photosensor 102.

[0081] At time tl l, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a second portion of the signal S A corresponding to the voltage V FDA at the floating diffusion FD A-1 (or the signal voltage of the signal S A-1 ) and (b) read out from the pixel 100 a second portion of the signal S B corresponding to the voltage V FDB at the floating diffusion FD B-0 (or the signal voltage of the signal S B-0 ). As discussed above, the voltage V FDB decreases from time t9 to time tlO at least in part due to the pixel 100 receiving light power from one or more light pulses emitted by the illuminator and corresponding to a desired distance or distance range. Thus, the signals S A-1 and / or the second portion of S B-0 read out from the pixel 100 at time tl l can represent samples of a combination of: (a) charge (if any) from the signal light received from the one or more light pulses reaching the floating diffusion FD A and / or FD B respectively; and (b) FPN (dark current FPN, ambient PLS, and pulsed signal PLS) at the floating diffusion FD A and / or FD B respectively. The signals S A-1 and SB-0 The second portions of the signals S

[0082] After obtaining the signals S A-0 , S A-1 , S B-0 , and S B-1 , the first and second portions of the signals S A-0 , S A-1 , S B-0 , and S B-1 may be processed to isolate the FPN (dark current FPN, ambient PLS, and pulse signal PLS). For example, the column readout circuitry 120 can: (a) determine the signal S A-0 as the difference between the second portion of the signal S A-0 and the first portion of the signal S A-0 ; (b) determine the signal S B-1 as the difference between the second portion of the signal S B-1 and the first portion of the signal S B-1 ; (c) determine the signal S A-1 as the difference between the second portion of the signal S A-1 and the first portion of the signal S A-1 ; and (d) determine the signal S B-0 as the difference between the second portion of the signal S B-0 and the first portion of the signal S B-0 . (As the exposure time is lengthened, the FPN components of the first and second portions of the signals S A-0 , S A-1 , S B-0 , and S B-1 may become less relevant and thus can not cancel each other out completely.) Consistent with the discussion above regarding Figure 3A and 2B , the column readout circuitry 120 can then determine: (i) a first difference between the signal S A-0 and the signal S A-1 ; (ii) a second difference between the signal S B-0 and the signal S B-1 ; and (iii) a sum of the first difference and the second difference. The sum can represent the signal light component captured by the pixel 100 during the frame with the FPN (dark current FPN, ambient PLS, and pulse signal PLS) subtracted, and multiplied by the sum of the known camera gain factors / constants of the pixel 100. The above process can be repeated for subsequent frames.

[0083] Although shown in timing diagram 350 as a reset of pixel 100 from time t6 to time t7, the CDS method of this technique can omit the reset of pixel 100 between the read at time t5 and the read at time t11. More specifically, assuming the floating diffuser FD A and FD B And / or if the full-well capacity of the photoelectric sensor 102 is large enough, then the signal S read from pixel 100 at time t5 will be sufficient. A-0 and S B-1 The second part can be used as the signal S read out at time t11. A-1 and S B-0 The first part is the reference signal. In other words, this type of CDS method can skip or omit the read performed at time t8 of timing diagram 350 to obtain signal S. A-1 and S B-0 The second part. Therefore, the number of reads performed during this type of CDS method can be less than the number of reads performed during the CDS method illustrated by timing diagram 350, which means that compared to the number of reads stored in... Figure 3B The signal S read from pixel 100 during the CDS method described in the text A-0 S A-1 S B-0 and S B-1 Compared to the number of sampling capacitors required for a portion of the signal S read from pixel 100 during this type of CDS method, the number of capacitors stored in the signal S is significantly greater. A-0 S A-1 S B-0 and S B-1 The number of sampling capacitors required for certain parts (e.g., in column readout circuitry 120 or in pixels) can also be reduced.

[0084] Figure 1 This describes the operational pixels (e.g., those that can be utilized in conjunction with the FPN reduction method described herein) according to various embodiments of the present technology. Figure 1 Timing diagram 360 for a four-sampling method (pixel 100, any of the other pixels discussed and described herein, or another pixel of this technique). See also: Figure 2A and 3B The method begins by asserting the overflow gate signal OFG and the reset signal RST at time t0. The assertion of the overflow gate signal OFG activates the overflow transistor 101 of pixel 100 and clears any charge generated and accumulated at photosensitive sensor 102. The assertion of the reset signal RST activates the first and second reset transistors 105 and 106 and clears the floating diffuser FD. A and FD B Any charge accumulated at that point. Therefore, the floating diffuser FD A Voltage V at point FDA and floating diffusion section FDB the voltage V FDB at the floating diffusion FD DD to a reference voltage (e.g., V

[0085] At time tl, while the reset signal RST and the overflow gate signal OFG remain asserted, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a signal S A the voltage V FDA at the floating diffusion FD DD (e.g., V A-0 + reset noise at time tl) of a first reset noise component (or a first reset noise voltage of the signal S A-0 (b) read out from the pixel 100 a signal S B the voltage V FDB at the floating diffusion FD DD (e.g., V B-1 + reset noise at time tl) of a first reset noise component (or a first reset noise voltage of the signal S B-1 Time tl can correspond to a timing at which an illuminator (not shown) does not emit a light pulse with it, or to a timing at which a light pulse or pulses emitted by the illuminator and corresponding to a desired distance or distance range do not have a substantial light power received by the pixel 100 and transferred to the floating diffusion FD A and FD B Thus, the first reset noise signal components of the signals S A-0 and S B-1 may represent samples of reset noise captured or generated by the pixel 100 at the floating diffusion FD A and FD B At time tl, the first reset noise signal components of the signals S A-0 and S B-1 read out from the pixel 100 can be stored for further processing at a later time, e.g., in a sampling capacitor of the column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below). Then, the reset signal RST is de-asserted at time t2 while the overflow gate signal OFG remains asserted.

[0086] At time t3, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a first portion of a signal S A the voltage V FDA at the floating diffusion FD A-0 (b) read out from the pixel 100 a second portion of the signal S A-0(a) the reference voltage) and (b) the reading from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB signal S B-1 The first part (or signal S) B-1 (reference voltage). Time t3 may correspond to the timing of the illuminator (not shown) not emitting its emitted light pulses or to one or more light pulses emitted by the illuminator and to a large amount of light power not received by pixel 100 and transferred to the floating diffuser FD at the desired distance or distance range. A and FD B The timing of the signal S. A-0 and S B-1 The first part can be represented by pixel 100 in the floating diffuser FD. A and FD B Samples of FPNs (dark current FPN, ambient PLS, and pulse signal PLS) captured or generated at the location. The signal S read from the pixel at time t3. A-0 and S B-1 The first part can be stored for further processing at a later time, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (discussed in more detail below).

[0087] From time t4 to time t5, the transfer signal TxA is asserted to activate the first transfer transistor 103 of the first tap of pixel 100. The time interval between time t4 and time t5 may correspond to the timing of an illuminator (not shown) emitting one or more light pulses, or to a large amount of light power from one or more light pulses emitted by the illuminator corresponding to a desired distance or range, which is received by pixel 100 and transferred to the floating diffuser FD. A The timing is such that, during this time period, the photoelectric sensor 102 of pixel 100 generates photocharge or photocurrent, which is transferred to the floating diffuser FD via the first transfer transistor 103. A Therefore, the floating diffuser FD A Voltage V at point FDA The signal decreases between time t4 and time t5. At time t5, the transfer signal TxA can be de-asserted, thereby deactivating the first transfer transistor 103. In some embodiments, the overflow gate signal OFG can be additionally asserted to activate the overflow transistor 101 and clear any charge at the photosensor 102.

[0088] At time t6, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the data corresponding to the floating diffuser FD is read from pixel 100. A Voltage V at point FDA signal S A-0The second part (or signal S) A-0 (a) Signal voltage) and (b) Read from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB signal S B-1 The second part (or signal S) B-1 (signal voltage). As discussed above, voltage V FDA From time t4 to time t5, the decrease is at least partly due to the reduction in light power received by pixel 100 from one or more light pulses emitted by the illuminator, corresponding to the desired distance or distance range. Therefore, the signal S read from pixel 100 at time t6... A-0 and / or S B-1 The second part can represent a sample of the following combination: (a) signal light received from one or more optical pulses arrives at the floating diffuser FD. A and / or FD B (a) the charge (if present); and (b) respectively, the floating diffuser FD A and / or FD B The FPN (dark current FPN, ambient PLS, and pulse signal PLS) at the location. The signal S read from pixel 100 at time t6. A-0 and S B-1 The second part can be stored for further processing at a later time, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (discussed in more detail below).

[0089] At time t7, the reset signal RST is asserted to activate the first and second reset transistors 105 and 106. As discussed above, activating the first and second reset transistors 105 and 106 clears the floating diffuser FD. A and FD B Any charge accumulated at that point. Therefore, the floating diffuser FD A Voltage V at point FDA and floating diffusion section FD B Voltage V at point FDB Reset to the reference voltage (e.g., V) via the first and second reset transistors 105 and 106 respectively. DD Or another positive power supply voltage).

[0090] At time t8, while the reset signal RST and the overflow gate signal OFG are asserted, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the data corresponding to the floating diffuser FD is read from pixel 100. A Voltage V at point FDA (For example, V) DD The signal S (+reset noise at time t8) A-0The second reset noise component (or signal S) A-0 (b) The second reset noise voltage) and the reading from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB (For example, V) DD The signal S (+reset noise at time t8) B-1 The second reset noise component (or signal S) B-1 The second reset noise voltage). Time t8 may correspond to the timing of the illuminator (not shown) not emitting its emitted light pulses or to one or more light pulses emitted by the illuminator and to a large amount of light power not received by pixel 100 and transferred to the floating diffuser FD at the desired distance or distance range. A and FD B The timing of the signal S. A-0 and S B-1 The second reset noise component can be represented by the pixel 100 in the floating diffuser FD. A and FD B Samples of reset noise captured or generated at that location. The signal S read from the pixel at time t8. A-0 and S B-1 The second reset noise component can be stored for further processing at a later time, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (discussed in more detail below).

[0091] At time t9, while the reset signal RST and the overflow gate signal OFG are still asserted, the row selection signal RS is asserted again to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the data corresponding to the floating diffuser FD is read from pixel 100. A Voltage V at point FDA (For example, V) DD The signal S (reset noise at time t9) A-1 The first reset noise component (or signal S) A-1 (a) The first reset noise voltage and (b) the reading from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB (For example, V) DD The signal S (reset noise at time t9) B-0 The first reset noise component (or signal S) B-0 The first reset noise voltage). Time t9 may correspond to the timing of the illuminator (not shown) not emitting its emitted light pulses or to one or more light pulses emitted by the illuminator and to a large amount of light power not received by pixel 100 and transferred to the floating diffuser FD at the desired distance or distance range. A and FD Bthe timing of the signals S A-1 and S B-0 The first reset noise components of the signals S A and S B may represent samples of reset noise captured or generated by the pixel 100 at the floating diffusion FD A-1 and FD B-0 at time t9 can be stored for further processing at a later time, e.g., in a sampling capacitor of the column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0092] If the duration of the time period between time t8 and time t9 is short, the read performed at time t8 to obtain the second reset noise components of the signals S A-0 and S B-1 may be merged with the read performed at time t9 to obtain the first reset noise components of the signals S A-1 and S B-0 (or the first reset noise voltages of the signals S A-1 and S B-0 ). For example, in some embodiments, the read performed at time t9 of the timing diagram 360 can be omitted, and the second reset noise components of the signals S A-0 and S B-1 (or the second reset noise voltages of the signals S A-0 and S B-1 ) can be used instead of the first reset noise components of the signals S A-1 and S B-0 (or the first reset noise voltages of the signals S A-1 and S B-0 ). Alternatively, in some embodiments, the read performed at time t8 of the timing diagram 360 can be omitted, and the first reset noise components of the signals S A-1 and S B-0 (or the first reset noise voltages of the signals S A-1 and S B-0 ) can be used instead of the second reset noise components of the signals S A-0 and S B-1 (or the second reset noise voltages of the signals S A-0 and S B-1 ). Reducing the number of reads can reduce the number of sampling capacitors needed to store the signals read from the pixel 100 (e.g., in the column readout circuitry 120 or in the pixel).

[0093] Referring again to the method illustrated in timing diagram 360, the reset signal RST can be deasserted at time t10, while the overflow gate signal OFG remains asserted. At time t11, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the data corresponding to the floating diffuser FD is read from pixel 100. A Voltage V at point FDA signal S A-1 The first part (or signal S) A-1 (a) the reference voltage) and (b) the reading from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB signal S B-0 The first part (or signal S) B-0 (reference voltage). Time t11 may correspond to the timing of the illuminator (not shown) not emitting its emitted light pulses or to one or more light pulses emitted by the illuminator and to a large amount of light power not received by pixel 100 and transferred to the floating diffuser FD at the desired distance or distance range. A and FD B The timing of the signal S. A-1 and S B-0 The first part can be represented by pixel 100 in the floating diffuser FD. A and FD B Samples of FPNs (dark current FPN, ambient PLS, and pulse signal PLS) captured or generated at the location. Signal S read from the pixel at time t11. A-1 and S B-0 The first part can be stored for further processing at a later time, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (discussed in more detail below).

[0094] From time t12 to time t13, the transfer signal TxB is asserted to activate the second transfer transistor 104 of the second tap of pixel 100. The time interval between time t12 and time t13 may correspond to the timing of an illuminator (not shown) emitting one or more light pulses, or to a large amount of light power from one or more light pulses emitted by the illuminator corresponding to a desired distance or range, which is received by pixel 100 and transferred to the floating diffuser FD. B The timing is such that, during this time period, the photoelectric sensor 102 of pixel 100 generates photocharge or photocurrent, which is transferred to the floating diffuser FD via the second transfer transistor 104. B Therefore, the floating diffuser FD B Voltage V at point FDBThe signal decreases between time t12 and time t13. At time t13, the transfer signal TxB can be de-asserted, thereby deactivating the second transfer transistor 104. In some embodiments, the overflow gate signal OFG can be additionally asserted to activate the overflow transistor 101 and clear any charge at the photosensor 102.

[0095] At time t14, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the corresponding floating diffuser FD is read from pixel 100. A Voltage V at point FDA signal S A-1 The second part (or signal S) A-1 (a) Signal voltage) and (b) Read from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB signal S B-0 The second part (or signal S) B-0 (signal voltage). As discussed above, voltage V FDB From time t12 to time t13, the light power received by pixel 100 from one or more light pulses emitted by the illuminator, corresponding to the desired distance or range, decreases at least in part. Therefore, the signal S read from pixel 100 at time t14... A-1 and / or S B-0 The second part can represent a sample of the following combination: (a) signal light received from one or more optical pulses arrives at the floating diffuser FD. A and / or FD B (a) the charge (if present); and (b) respectively, the floating diffuser FD A and / or FD B The FPN (dark current FPN, ambient PLS, and pulse signal PLS) at the location. The signal S read from pixel 100 at time t14. A-1 and S B-0 The second part can be stored for further processing, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (discussed in more detail below).

[0096] At time t15, the reset signal RST is asserted to activate the first and second reset transistors 105 and 106. As discussed above, activating the first and second reset transistors 105 and 106 clears the floating diffuser FD. A and FD B Any charge accumulated at that point. Therefore, the floating diffuser FD A Voltage V at point FDA and floating diffusion section FD B Voltage V at point FDBreset transistors 105 and 106 to a reference voltage (e.g., V DD or another positive power supply voltage).

[0097] At time t16, while the reset signal RST and the overflow gate signal OFG remain asserted, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a signal S A corresponding to the voltage V FDA at the floating diffusion FD DD (e.g., V A-1 + reset noise at time t16) plus a second reset noise component of the signal S A-1 (or a second reset noise voltage of the signal S B ) and (b) read out from the pixel 100 a signal S FDB corresponding to the voltage V DD at the floating diffusion FD B-0 (e.g., V B-0 + reset noise at time t16) plus a second reset noise component of the signal S A (or a second reset noise voltage of the signal S B ). The time t16 can correspond to a timing at which a light pulse is not emitted by an illuminator (not shown) or to a timing at which a light pulse or pulses emitted by an illuminator and corresponding to a desired distance or distance range are not received by the pixel 100 and transferred to the floating diffusions FD A-1 and FD B-0 . Thus, the second reset noise components of the signals S A and S B may represent samples of reset noise captured or generated by the pixel 100 at the floating diffusions FD A-1 and FD B-0 . The second reset noise components of the signals S A-0 and S A-1 read out from the pixel at time t16 can be stored for further processing, e.g., in a sampling capacitor of the column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0098] After obtaining the first and second portions of each of the signals S B-0 , S B-1 , S A-0 and the first and second reset noise components, the signals can be processed to tease out FPN. For example, the column readout circuitry 120 can: (a) determine a first difference by subtracting the first portion of the signal S A-0 from the first reset noise component of the signal S B-1the first reset noise component of the signal S B-1 the second difference; (c) determining a third difference by subtracting the signal S A-1 the first reset noise component of the signal S A-1 the fourth difference; (e) determining a fifth difference by subtracting the signal S B-0 the second portion of the signal S B-0 the second reset noise component of the signal S A-0 the second portion of the signal S A-0 the second reset noise component of the signal S B-1 the second portion of the signal S B-1 the second reset noise component of the signal S A-1 the second portion of the signal S A-1 the second reset noise component of the signal S B-0 the second portion of the signal S B-0 the second reset noise component of the signal S

[0099] Next, the column readout circuitry 120 can determine: (a) a first sum of the first difference and the fifth difference; (b) a second sum of the second difference and the sixth difference; (c) a third sum of the third difference and the seventh difference; and (d) a fourth sum of the fourth difference and the eighth difference. Assuming strong correlation among the noise components of the first through fourth sums, the noise components can cancel each other out to a large extent, leaving the signal light components captured on each tap during each pair of frames. Consistent with the discussion above regarding Figure 3A and 2B Next, the column readout circuitry 120 can: (i) determine a ninth difference by subtracting the third sum from the first sum; (ii) determine a tenth difference by subtracting the second sum from the fourth sum; and (iii) determine a fifth sum of the ninth difference and the tenth difference. The fifth sum can represent the sum of the signal light captured by the pixel 100 during the frame with the FPN (dark current FPN, ambient PLS, and pulsed signal PLS) subtracted, and multiplied by the known camera gain factor / constant of the pixel 100. The above process can be repeated for subsequent frames.

[0100] As discussed above with reference to Figure 3B the CDS method illustrated by the timing diagram 350 can be used to remove FPN and reset noise. However, at long exposures, the correlation between the noise read out at different times can be poor, resulting in high flicker noise measurements. By using the CDS method illustrated by the timing diagram 350, the noise components can be removed from the signal S Figure 3CThe timing diagram 360 illustrates a four-sampling method for capturing reset noise signals. The correlation between noise measurements captured at different times remains strong, allowing both reset noise and flicker noise to be largely extracted from the signal light measurement. Therefore, the main residual noise expected when using the four-sampling method of this technique is leakage current noise from the 3T readout node of pixel 100.

[0101] Figure 1 This describes the operational pixels (e.g., those that can be utilized in conjunction with the FPN reduction method described herein) according to various embodiments of the present technology. Figure 1 Timing diagram 370 for an alternative four-sampling method (pixel 100, any of the other pixels discussed and described herein, or another pixel of the present technique). See also: Figure 2A and 3C The method begins by asserting the overflow gate signal OFG and the reset signal RST at time t0. The assertion of the overflow gate signal OFG activates the overflow transistor 101 of pixel 100 and clears any charge generated and accumulated at photosensitive sensor 102. The assertion of the reset signal RST activates the first and second reset transistors 105 and 106 and clears the floating diffuser FD. A and FD B Any charge accumulated at that point. Therefore, the floating diffuser FD A Voltage V at point FDA and floating diffusion section FD B Voltage V at point FDB Reset to the reference voltage (e.g., V) via the first and second reset transistors 105 and 106 respectively. DD Or another positive power supply voltage).

[0102] At time t1, the overflow gate signal OFG is de-asserted (the overflow transistor 101 is deactivated), the transfer signal TxA is asserted (the first transfer transistor 103 of the first tap of pixel 100 is activated), and the reset signal RST remains asserted. As shown in timing diagram 370, the transfer signal TxA remains asserted until time t8.

[0103] At time t2, while the reset signal RST and the transfer signal TxA are asserted, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the data corresponding to the floating diffuser FD is read from pixel 100. A Voltage V at point FDA (For example, V) DD The signal S (including reset noise at time t2) A-0 The first reset noise component (or signal S) A-0 (a) The first reset noise voltage and (b) the reading from pixel 100 corresponding to the floating diffuser FDB the voltage V FDB at time t2 DD of the signal S B-1 the first reset noise component (or signal S B-1 of the first reset noise voltage) of the signal S A corresponds to the timing at which the illuminator (not shown) emits the light pulse or pulses from which the substantial amount of light power corresponding to the desired distance or distance range is received by the pixel 100 and transferred to the floating diffusion FD B and / or the timing at which the illuminator emits the light pulse or pulses from which the substantial amount of light power corresponding to the desired distance or distance range is received by the pixel 100 and transferred to the floating diffusion FD A but cleared from the floating diffusion FD A via the first reset transistor 105. In any case, the first reset noise component of the signal S A-0 and S B-1 may represent samples of the reset noise captured or generated by the pixel 100 at the floating diffusion FD A and FD B at time t2. The first reset noise component of the signal S A-0 and S B-1 read out from the pixel at time t2may be stored for further processing at a later time, e.g., in a sampling capacitor of the column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below). Then, the reset signal RST can be de-asserted at time t3while the transfer signal TxA remains asserted.

[0104] At time t4, while the transfer signal TxA remains asserted, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a first portion of the signal S A the voltage V FDA of the signal S A-0 (or reference voltage of the signal S A-0 ) corresponding to the voltage V B at the floating diffusion FD FDB of the signal S B-1 (or reference voltage of the signal S B-1 ). At least the first portion of the signal S B-1 may represent samples of the reset noise captured or generated by the pixel 100 at the floating diffusion FD BSamples of FPNs (dark current FPN, ambient PLS, and pulse signal PLS) captured or generated at the location. Signal S A-0 The first part can be represented by pixel 100 in the floating diffuser FD A A sample of FPN (dark current FPN, ambient PLS, and pulse signal PLS) captured or generated at the location, or a sample that can represent a combination of the following: (a) signal light received from one or more light pulses emitted from a free illuminator (not shown) reaching the floating diffuser FD. A (a) the charge (if present); and (b) the floating diffuser FD A The FPN (dark current FPN, ambient PLS, and pulse signal PLS) is located at the point. Because signal S... A-0 The first part is read out at time t4, while the transfer signal TxA remains asserted, thus the floating diffusion part FD A Voltage V at point FDA The signal S read from the pixel at time t4 can be freely changed (e.g., due to the optical power derived from one or more pulses received by pixel 100 after time t4). A-0 and S B-1 The first part can be stored for further processing at a later time, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (as described in more detail below).

[0105] The entirety or subset of the time interval between time t1 and time t7 (or the time interval between time t3 and time t6) may correspond to the timing of one or more light pulses emitted by the illuminator (not shown), or to a large amount of light power emitted by the illuminator at the desired distance or range, which is received by pixel 100 and transferred to the floating diffuser FD. A The timing is such that the photoelectric sensor 102 of pixel 100 can generate photocharge or photocurrent during this time period, and the charge can be transferred to the floating diffuser FD via the first transfer transistor 103. A Therefore, the floating diffuser FD A Voltage V at point FDA It decreases between time t3 and time t6 (between the assertions of the reset signal RST).

[0106] At time t5, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the corresponding floating diffuser FD is read from pixel 100. A Voltage V at point FDA signal S A-0 The second part (or signal S) A-0 (a) Signal voltage) and (b) Read from pixel 100 corresponding to the floating diffuser FDB the voltage V FDB the signal S B-1 the second portion (or signal S B-1 the signal voltage). As discussed above, the voltage V FDA decreases from time t3 to time t6 at least in part due to the pixel 100 receiving light power from one or more light pulses emitted by the illuminator and corresponding to the desired distance or distance range. Thus, the signal S A-0 and / or the second portion of S B-1 may represent samples of a combination of: (a) signal light received from the one or more light pulses reaching the floating diffusion FD A and / or the charge (if any) of FD B respectively; and (b) respectively, FPN (dark current FPN, ambient PLS, and pulsed signal PLS) at the floating diffusion FD A and / or FD B Because the second portion of the signal S A-0 is read out at time t5 while the transfer signal TxA remains asserted, the voltage V A at the floating diffusion FD FDA remains free to change (e.g., due to additional light power from one or more pulses received by the pixel 100 after time t5). The signal S A-0 and the second portion of S B-1 read out from the pixel 100 at time t5 can be stored for further processing at a later time, e.g., in a sampling capacitor of the column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0107] At time t6, the reset signal RST is asserted while the transfer signal TxA remains asserted. Asserting the reset signal RST activates the first and second reset transistors 105 and 106 and clears any charge accumulated at the floating diffusion FD A and FD B The voltage V A at the floating diffusion FD FDA and the voltage V B at the floating diffusion FD FDB are reset to a reference voltage (e.g., V DD or another positive supply voltage) via the first and second reset transistors 105 and 106 respectively.

[0108] At time t7, while the reset signal RST and the transfer signal TxA are asserted, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the data corresponding to the floating diffuser FD is read from pixel 100. A Voltage V at point FDA (For example, V) DD The signal S (reset noise at time t7) A-0 The second reset noise component (or signal S) A-0 (b) The second reset noise voltage) and the reading from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB (For example, V) DD The signal S (reset noise at time t7) B-1 The second reset noise component (or signal S) B-1 The second reset noise voltage). Time t7 may correspond to the timing of the illuminator (not shown) not emitting its emitted light pulses or to one or more light pulses emitted by the illuminator and to a large amount of light power not received by pixel 100 and transferred to the floating diffuser FD at the desired distance or distance range. A and / or FD B The timing. Alternatively, time t7 may correspond to the timing of the illuminator emitting one or more light pulses, or to a large amount of light power emitted by the illuminator at a desired distance or range, received by pixel 100 and transferred to the floating diffuser FD. A However, via the first reset transistor 105 from the floating diffuser FD A The timing of the clearing. In any case, signal S... A-0 and S B-1 The second reset noise component can be represented by the pixel 100 in the floating diffuser FD. A and FD B Samples of reset noise captured or generated at that location. The signal S read from the pixel at time t7. A-0 and S B-1 The second reset noise component can be stored for further processing at a later time, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (discussed in more detail below).

[0109] At time t8, the transfer signal TxA is de-asserted (deactivating the first transfer transistor 103), while the overflow gate signal OFG is asserted (activating the overflow transistor 101). Activating the overflow transistor 101 clears any charge generated and accumulated at the photodetector 102.

[0110] At time t9, the overflow gate signal OFG is de-asserted (deactivating the overflow transistor 101), the transfer signal TxB is asserted (activating the second transfer transistor 104 of the second tap of pixel 100), and the reset signal RST remains asserted. As shown in timing diagram 370, the transfer signal TxB remains asserted until time t16.

[0111] At time t10, while the reset signal RST and the transfer signal TxB are asserted, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the data corresponding to the floating diffuser FD is read from pixel 100. A Voltage V at point FDA (For example, V) DD The signal S (including reset noise at time t10) A-1 The first reset noise component (or signal S) A-1 (a) The first reset noise voltage and (b) the reading from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB (For example, V) DD The signal S (including reset noise at time t10) B-0 The first reset noise component (or signal S) B-0 The first reset noise voltage). Time t10 may correspond to the timing of the illuminator (not shown) not emitting its emitted light pulses or to one or more light pulses emitted by the illuminator and to a large amount of light power not received by pixel 100 and transferred to the floating diffuser FD at the desired distance or distance range. A and / or FD B The timing. Alternatively, time t10 may correspond to the timing of the illuminator emitting one or more light pulses, or to a large amount of light power emitted by the illuminator at a desired distance or range, which is received by pixel 100 and transferred to the floating diffuser FD. B However, via the second reset transistor 106 from the floating diffuser FD B The timing of the clearing. In any case, signal S... A-1 and S B-0 The first reset noise component can be represented by the pixel 100 in the floating diffuser FD. A and FD B Samples of reset noise captured or generated at that location. The signal S read from the pixel at time t10. A-1 and S B-0The first reset noise component can be stored for further processing at a later time, for example, in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (discussed in more detail below). Then, the reset signal RST can be deasserted at time t11, while the transfer signal TxB remains asserted.

[0112] If the time interval between time t7 and time t10 is short, then it can be combined at time t7 to obtain signal S. A-0 and S B-1 The second reset noise component (or signal S) A-0 and S B-1 The second reset noise voltage) is used to perform the read at time t10 in order to obtain signal S. A-1 and S B-0 The first reset noise component (or signal S) A-1 and S B-0 The read is performed using the first reset noise voltage. For example, in some embodiments, the read performed at time t10 of timing diagram 370 may be omitted, and signal S A-0 and S B-1 The second reset noise component (or signal S) A-0 and S B-1 The second reset noise voltage can replace signal S. A-1 and S B-0 The first reset noise component (or signal S) A-1 and S B-0 The first reset noise voltage is used. Alternatively, in some embodiments, the read performed at time t7 of timing diagram 370 may be omitted, and signal S A-1 and S B-0 The first reset noise component (or signal S) A-1 and S B-0 The first reset noise voltage can replace signal S A-0 and S B-1 The second reset noise component (or signal S) A-0 and S B-1 The second reset noise voltage is used. In yet another embodiment, a read performed at time t7 and a read performed at time t10 may be combined such that a single read is performed while (a) neither transfer signals TxA nor TxB is asserted or (b) both transfer signals TxA and TxB are asserted. The signal read from the first tap of the pixel during the single read can be used as signal S. A-0 The second reset noise component (or signal S) A-0 The second reset noise voltage and signal S A-1 The first reset noise component (or signal S) A-1the first reset noise voltage of the signal S B-1 the second reset noise component of the signal S B-1 the second reset noise voltage of the signal S B-0 the first reset noise component of the signal S B-0 the first reset noise voltage of the signal S A Reducing the number of times the signal is read can reduce the number of sample capacitors needed to store the signal read out from the pixel 100 (e.g., in the column readout circuitry 120 or in the pixel).

[0113] At time t12, while the transfer signal TxB remains asserted, the row select signal RS is asserted to activate the first and second row select transistors 109 and 110 of the pixel 100 and (a) read out from the pixel 100 a signal S A the voltage V FDA at the floating diffusion FD A-1 the first portion of the signal S A-1 the reference voltage of the signal S B (b) read out from the pixel 100 a signal S FDB the first portion of the signal S B-0 the reference voltage of the signal S B-0 At least the first portion of the signal S A-1 may represent a sample of FPN (dark current FPN, ambient PLS, and pulsed signal PLS) captured or generated by the pixel 100 at the floating diffusion FD A . The first portion of the signal S B-0 may represent a sample of FPN (dark current FPN, ambient PLS, and pulsed signal PLS) captured or generated by the pixel 100 at the floating diffusion FD B or can represent a sample of a combination of: (a) charge (if any) of signal light received at the floating diffusion FD B from one or more light pulses emitted from a free illuminator (not shown); and (b) FPN (dark current FPN, ambient PLS, and pulsed signal PLS) at the floating diffusion FD B . Because the first portion of the signal S B-0 is read out at time t12 while the transfer signal TxB remains asserted, the voltage V B at the floating diffusion FD FDB remains free to change (e.g., due to light power from one or more pulses received by the pixel 100 after time t12). The signals S A-1 and S B-0The first part can be stored for further processing at a later time, for example in the sampling capacitor of the column readout circuit system 120 or in the sampling capacitor of the pixel (as described in more detail below).

[0114] The entirety or a subset of the time interval between time t9 and time t16 (or the time interval between time t11 and time t14) may correspond to the timing of one or more light pulses emitted by the illuminator (not shown), or to a large amount of light power emitted by the illuminator at the desired distance or range, which is received by pixel 100 and transferred to the floating diffuser FD. B The timing is such that the photoelectric sensor 102 of pixel 100 can generate photocharge or photocurrent during this time period, and the charge can be transferred to the floating diffuser FD via the second transfer transistor 104. B Therefore, the floating diffuser FD A Voltage V at point FDB It decreases between time t11 and time t14 (between the assertions of the reset signal RST).

[0115] At time t13, the row selection signal RS is asserted to activate the first and second row selection transistors 109 and 110 of pixel 100, and (a) the corresponding floating diffuser FD is read from pixel 100. A Voltage V at point FDA signal S A-1 The second part (or signal S) A-1 (a) Signal voltage) and (b) Read from pixel 100 corresponding to the floating diffuser FD B Voltage V at point FDB signal S B-0 The second part (or signal S) B-0 (signal voltage). As discussed above, voltage V FDB From time t11 to time t14, the decrease is at least partly due to the reduction in light power received by pixel 100 from one or more light pulses emitted by the illuminator, corresponding to the desired distance or distance range. Therefore, the signal S read from pixel 100 at time t13... A-1 and / or S B-0 The second part can represent a sample of the following combination: (a) signal light received from one or more optical pulses arrives at the floating diffuser FD. A and / or FD B (a) the charge (if present); and (b) respectively, the floating diffuser FD A and / or FD B The FPN (dark current FPN, ambient PLS, and pulse signal PLS) is located at the point. Because signal S... B-0the second portion of signal S B at time t13 while transfer signal TxB remains asserted, so the voltage V FDB at floating diffusion FD A-1 remains free to change (e.g., due to additional light power from one or more pulses received by pixel 100 after time t13). The signal S B-0 read out from pixel 100 at time t13, and the second portion of signal S A may be stored for further processing at a later time, e.g., in a sampling capacitor of column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0116] At time t14, reset signal RST is asserted while transfer signal TxB remains asserted. Asserting reset signal RST activates first and second reset transistors 105 and 106 and clears any charge accumulated at floating diffusion FD A and FD B . Thus, the voltage V A at floating diffusion FD FDA and the voltage V B at floating diffusion FD FDB are reset to a reference voltage (e.g., V DD or another positive supply voltage) via first and second reset transistors 105 and 106, respectively.

[0117] At time t15, while reset signal RST and transfer signal TxB remain asserted, row select signal RS is asserted to activate first and second row select transistors 109 and 110 of pixel 100 and (a) read out from pixel 100 a signal S A corresponding to the voltage V FDA at floating diffusion FD DD (e.g., V A-1 + reset noise at time t15) plus a second reset noise component of signal S A-1 (or a second reset noise voltage of signal S B ) and (b) read out from pixel 100 a signal S FDB corresponding to the voltage V DD at floating diffusion FD B-0 (e.g., V B-0 + reset noise at time t15) plus a second reset noise component of signal S A (or a second reset noise voltage of signal S B . Time t15 can correspond to a time when an illuminator (not shown) is not emitting a light pulse with its timing or one or more light pulses emitted by the illuminator and a substantial amount of light power corresponding to a desired distance or distance range is not being received by pixel 100 and transferred to floating diffusion FD A and / or FD Bcorresponds to the timing at which the illuminator emits one or more light pulses or a substantial amount of light power from one or more light pulses emitted by the illuminator and corresponding to the desired distance or distance range is received by the pixel 100 and transferred to the floating diffusion FD B But via the second reset transistor 106 from the floating diffusion FD A the timing of the clearing. In any case, the signal S A-1 and S B-0 The second reset noise components of the signals S A and S B may represent samples of reset noise captured or generated by the pixel 100 at the floating diffusion FD A-1 and S B-0 at time t15 can be stored for further processing, e.g., in a sampling capacitor of the column readout circuitry 120 or in a sampling capacitor of the pixel (as discussed in more detail below).

[0118] After obtaining the first and second portions of each of the signals S A-0 , S A-1 , S B-0 , and S B-1 , as well as the first and second reset noise components, the signals can be processed to isolate the FPN. For example, the column readout circuitry 120 can: (a) determine a first difference by subtracting the first portion of the signal S A-0 from the first reset noise component of the signal S A-0 ; (b) determine a second difference by subtracting the first portion of the signal S B-1 from the first reset noise component of the signal S B-1 ; (c) determine a third difference by subtracting the first portion of the signal S A-1 from the first reset noise component of the signal S A-1 ; (d) determine a fourth difference by subtracting the first portion of the signal S B-0 from the first reset noise component of the signal S B-0 ; (e) determine a fifth difference by subtracting the second reset noise component of the signal S A-0 from the second portion of the signal S A-0 ; (f) determine a sixth difference by subtracting the second reset noise component of the signal S B-1 from the second portion of the signal S B-1 ; (g) determine a seventh difference by subtracting the second reset noise component of the signal S A-1 from the second portion of the signal S A-1 ; and (h) determine an eighth difference by subtracting the second reset noise component of the signal S B-0 from the second portion of the signal S B-0 .

[0119] Next, column readout circuitry 120 can determine: (a) a first sum of the first difference and the fifth difference; (b) a second sum of the second difference and the sixth difference; (c) a third sum of the third difference and the seventh difference; and (d) a fourth sum of the fourth difference and the eighth difference. Assuming strong correlation among the noise components of the first through fourth sums, the noise components can largely cancel each other, leaving behind the signal light components captured on each tap during each pair of frames. Consistent with the discussion above, column readout circuitry 120 can then: (i) determine a ninth difference by subtracting the third sum from the first sum; (ii) determine a tenth difference by subtracting the second sum from the fourth sum; and (iii) determine a fifth sum of the ninth difference and the tenth difference. The fifth sum can represent the signal light components captured by pixel 100 during the frames with FPN (dark current FPN, ambient PLS, and pulsed signal PLS) removed, and multiplied by the sum of the known camera gain factors / constants of pixel 100. The above process can be repeated for subsequent frames. Figure 4 and 2B Consistent with the discussion above, column readout circuitry 120 can then: (i) determine a ninth difference by subtracting the third sum from the first sum; (ii) determine a tenth difference by subtracting the second sum from the fourth sum; and (iii) determine a fifth sum of the ninth difference and the tenth difference. The fifth sum can represent the signal light components captured by pixel 100 during the frames with FPN (dark current FPN, ambient PLS, and pulsed signal PLS) removed, and multiplied by the sum of the known camera gain factors / constants of pixel 100. The above process can be repeated for subsequent frames.

[0120] Figure 1 is another pixel 400 configured in accordance with various embodiments of the present technology. As shown, pixel 400 is generally similar to pixel 100 of Figure 4 , except that pixel 400 is a charge mode storage pixel having (a) a first transfer transistor 403 coupled to a floating diffusion FD A of the first memory transistor 482a in a first tap of pixel 400 and (b) a second transfer transistor 404 coupled to a floating diffusion FD B of the second memory transistor 482b in a second tap of pixel 400. The first and second memory transistors 481a and 482b can be selectively activated via memory output signals MemoutA and MemoutB, respectively. In operation, the first and second transfer transistors 403 and 404 can be selectively activated using transfer signals TxA and TxB, respectively, to transfer charges generated by a photosensor of pixel 400 to the first and second memory transistors 482a and 482b, respectively, for storage at the first and second memory transistors 482a and 482b. The memory output signals MemoutA and MemoutB can be used to selectively activate the first and second memory transistors 482a and 482b, respectively, to transfer the charges stored at the first and second memory transistors 482a and 482b to the floating diffusions FD A and FD B , respectively. Figure 1 The remaining components described in Figure 4The corresponding components, which are explained and discussed in detail above, are omitted here for the sake of brevity. Figures 4A to 4C The remaining components are described in detail below. Pixel 400 can be operated using any of the FPN reduction techniques, CDS sampling methods, and / or quad-sampling methods described in detail above.

[0121] Figure 4 Description of various embodiments of the present technology Figures 4A to 4C An alternative implementation scheme with 400 pixels. More specifically, Figure 4 It is an operation 480 that can replace pixel 400. Figure 4A The schematic circuit diagrams 480a to 480c, which use one or both of these, are shown. Figure 4B As shown in Figure 480a, a storage gate 484a is included that couples an anti-overflow gate 483a to a transfer transistor 403a. Figure 4A Figure 480b and Figure 4C Similar to Figure 480a, Figure 480b includes a storage gate 484b coupled to the transfer transistor 403b. However, Figure 480b lacks an anti-overflow gate. Figure 4A Figure 480c is also similar Figure 5 Figure 480a is different from Figure 480c, which includes a storage diode 486 instead of a storage gate. The storage diode 486 includes a cathode coupled to an anti-overflow gate 483c and a transfer transistor 403c.

[0122] Figure 1 This is a partial schematic circuit diagram of another pixel 500 configured according to various embodiments of the present technology. Pixel 500 is generally similar to... Figure 1 The number of pixels is 100. Therefore, similar reference numbers are... Figure 1 and 5 The term "component" is used to identify components that are the same or at least substantially similar, and for the sake of brevity, a detailed discussion of these components is omitted here. Pixel 500 is downstream of the first and second source follower transistors 507 and 508 of pixel 500, which differs from... Figure 1The pixel 500 includes, with reference to the first tap of the pixel 500, a first enable transistor 591a having a gate supplied with an enable signal EN to selectively activate the first enable transistor 591a, a first current source 592a coupled between the first enable transistor 591a and ground, a first switch transistor 593a coupled to the first source follower transistor 507 and the first enable transistor 591a and having a gate supplied with a switch signal SW0 to selectively activate the first switch transistor 593a, a third source follower transistor 597a having a gate coupled to the first switch transistor 593a, a first sampling capacitor 595a coupled to the first switch transistor 593a and the gate of the third source follower transistor 597a, and a first row select transistor 509a coupled to the third source follower transistor 597a. The first tap of the pixel 500 further includes a second switch transistor 594a coupled to the first source follower transistor 507 and the first enable transistor 591a and having a gate supplied with a switch signal SW1 to selectively activate the second switch transistor 594a, a fourth source follower transistor 598a having a gate coupled to the second switch transistor 594a, a second sampling capacitor 596a coupled to the second switch transistor 594a and the gate of the fourth source follower transistor 598a, and a second row select transistor 509b coupled to the fourth source follower transistor 598a.

[0123] Referring now to the second tap of pixel 500, pixel 500 includes a second enable transistor 591b having a gate supplied with an enable signal EN to selectively activate the second enable transistor 591b. The enable signal EN supplied to the second enable transistor 591b can be the same signal as the enable signal EN applied to the first enable transistor 591a or a different signal. The second tap further includes a second current source 592b coupled between the second enable transistor 591b and ground, a third switch transistor 593b coupled to the second source follower transistor 508 and the second enable transistor 591b and having a gate supplied with a switch signal SWO to selectively activate the third switch transistor 593b, a fifth source follower transistor 597b having a gate coupled to the third switch transistor 593b, a third sampling capacitor 595b coupled to the third switch transistor 593b and the gate of the fifth source follower transistor 597b, and a third row select transistor 510a coupled to the fifth source follower transistor 597b. The switch signal SWO supplied to the gate of the third switch transistor 593b can be the same signal as the switch signal SWO supplied to the gate of the first switch transistor 593a of the first tap or can be a different signal than the switch signal SWO. The second tap of pixel 500 further includes a fourth switch transistor 594b coupled to the second source follower transistor 508 and the second enable transistor 591b and having a gate supplied with a switch signal SW1 to selectively activate the fourth switch transistor 594b, a sixth source follower transistor 598b having a gate coupled to the fourth switch transistor 594b, a fourth sampling capacitor 596b coupled to the fourth switch transistor 594b and the gate of the sixth source follower transistor 598b, and a fourth row select transistor 510b coupled to the sixth source follower transistor 598b. The switch signal SW1 supplied to the gate of the fourth switch transistor 594b can be the same signal as the switch signal SW1 supplied to the gate of the second switch transistor 594a of the first tap or can be a different signal than the switch signal SW1.

[0124] Pixel 500 can operate using any of the FPN reduction techniques, CDS sampling methods, and / or four-sampling methods described in detail above. In addition, the first enable transistor 591a and the first switch transistor 593a can be activated to sample the signal S A-0 onto the first sampling capacitor 595a; the first enable transistor 591a and the second switch transistor 594a can be activated to sample the signal S A-1 onto the second sampling capacitor 596a; the second enable transistor 591b and the third switch transistor 593b can be activated to sample the signal S B-0The signal is sampled onto the third sampling capacitor 595b; and the second enable transistor 591b and the fourth switch transistor 594b can be activated to transmit the signal S. B-1 The signal is sampled onto the fourth sampling capacitor 596b. A-0 S A-1 S B-0 S B-1 Each of the elements can be read from pixel 500 to column readout circuitry system 520 via a corresponding of row selection transistors 509a, 509b, 510a, and 510b. Column readout circuitry system 520 can, for example, use one or more differential analog-to-digital converters (ADCs) to calculate signal S. A-0 With S A-1 Between and signal S B-0 With S B-1 The difference between them.

[0125] although Figure 6 , 4 Pixels 100, 400, and 500 respectively directly read signals from the subframe to column readout circuitry systems 120, 420, and 520. However, other pixels configured according to various embodiments of the present technology can perform calculations for reducing FPN as discussed above. In other words, although column readout circuitry systems 120, 420, and 520 are configured to determine various differences and / or sums using signals read from pixels 100, 400, and 500 respectively, in some embodiments of the present technology, one or more of these difference and / or sum calculations can be performed within a pixel. Several of these embodiments are described in detail below.

[0126] For example, Figure 1 This is a partial schematic circuit diagram of a pixel 600 configured according to various embodiments of the present technology. The pixel 600 is generally similar to... Figure 1 The number of pixels is 100. Therefore, similar reference numbers are... Figure 1 and 6 The term "component" is used to identify components that are the same or at least substantially similar, and for the sake of brevity, a detailed discussion of these components is omitted here. Pixel 600 is downstream of the first and second source follower transistors 607 and 608 of pixel 600, which differs from... Figure 6AThe pixel 600 includes, with reference to the first tap of the pixel 600, a first enable transistor 691a coupled to the first source follower transistor 607 and having a gate supplied with an enable signal EN to selectively activate the first enable transistor 691a. The pixel 600 includes, with reference to the first tap of the pixel 600, a first current source 692a coupled between the first enable transistor 691a and ground. The pixel 600 includes, with reference to the first tap of the pixel 600, a first differential amplifier 630a having (a) inputs coupled to the first source follower transistor 607 and the first enable transistor 691a and (b) an output coupled to a gate of a third source follower transistor 697a. The third source follower transistor 697a is coupled to the first row select transistor 609 of the pixel 600.

[0127] The pixel 600 includes, with reference to the second tap of the pixel 600, a second enable transistor 691b coupled to the second source follower transistor 608 and having a gate supplied with an enable signal EN to selectively activate the second enable transistor 691b. The enable signal EN can be the same signal as the enable signal EN supplied to the gate of the first enable transistor 691a or a different signal. The pixel 600 includes, with reference to the second tap of the pixel 600, a second current source 692b coupled between the second enable transistor 691b and ground. The pixel 600 includes, with reference to the second tap of the pixel 600, a second differential amplifier 630b having (a) inputs coupled to the second source follower transistor 608 and the second enable transistor 691b and (b) an output coupled to a gate of a fourth source follower transistor 697b. The fourth source follower transistor 697b is coupled to the second row select transistor 610 of the pixel 600.

[0128] The first and second differential amplifiers 630a and 630b are passive differential detectors and are generally similar to each other. With reference to the first differential amplifier 630a as an example, the first differential amplifier 630a includes a first capacitor 631a having a capacitance CI, a second capacitor 632a having a capacitance C2, and a switch transistor 633a. The first capacitor 631a, the second capacitor 632a, and the switch transistor 633a are coupled to each other at a common node between the inputs and the output of the first differential amplifier 630a. More specifically, the first capacitor 631a is coupled between the input of the first differential amplifier 630a and the common node; the second capacitor 632a is coupled between ground (e.g., a negative supply rail or another reference voltage) and the common node; and the source of the switch transistor 633a is coupled to the common node. In the illustrated embodiment, the common node is directly coupled to the output of the first differential amplifier 630a. The drain of the switch transistor 633a is coupled to a reference voltage (e.g., VDD / 2) that is different than the common node. The gate of the switch transistor 633a is coupled to a control signal CTRL. The source of the switch transistor 633a is coupled to the common node. The drain of the switch transistor 633a is coupled to the reference voltage (e.g., VDD / 2) that is different than the common node. The gate of the switch transistor 633a is coupled to the control signal CTRL. DD(Positive supply voltage or another reference voltage). Switching transistor 633a is arranged as a reset switch for first differential amplifier 630a. More specifically, the gate of switching transistor 633a is configured to receive a switching signal SW, which, when asserted, activates switching transistor 633a and resets the voltage at the common node (and therefore the voltage at the output of first differential amplifier 630a). When the switching signal SW is not asserted, switching transistor 633a is deactivated, and first capacitor 631a and second capacitor 632a form a passive voltage divider circuit.

[0129] In operation, switching transistor 633a can be activated to reset the voltage at the common node of the first differential amplifier 630a to a reference voltage. Therefore, the voltage across the first capacitor 631a of the first differential amplifier 630a is brought to a level equivalent to the difference between the voltage output by the first source follower transistor 607 and the reference voltage. Then, as the voltage output by the first source follower transistor 607 depends at least partially on the floating diffuser FD... A Voltage V at point FDA As a result, the voltage at the common node of the first differential amplifier 630a may vary depending on the relative gain or attenuation of the capacitance C1 of the first capacitor 631a and the capacitance C2 of the second capacitor 632a. For example, the voltage at the common node may vary due to a capacitive voltage divider formed at least partially by the first capacitor 631a and the second capacitor 632a, resulting in a relative gain or attenuation given by dividing capacitance C1 by the sum of capacitances C1 and C2 (e.g., C1 / (C1+C2)).

[0130] This operation of the first differential amplifier 630a can be used to output a differential voltage to the gate of the third source follower transistor 697a. For example, when signal S... A-0 Based on floating diffusion part FD A Voltage V at point FDA When the first source follower transistor 607 outputs, the first enable transistor 691a can be activated by asserting the enable signal EN, and the switch transistor 633a can be activated by asserting the switch signal SW. This is done by setting the voltage across the first capacitor 631a to be equivalent to the signal S output by the first source follower transistor 607. A-0 The difference between the signal S and the reference voltage at the common node of the first differential amplifier 630a is used to convert the signal S A-0 The sample is applied to the first capacitor 631a. Then, the first enable transistor 691a and the switch transistor 633a can be deactivated respectively by the cancel assertion enable signal EN and the switch signal SW. Then, when signal S... A-1The first enable transistor 691a can be activated by asserting the enable signal EN, and the signal S A-0 The difference between the signals S A-1 appears as a voltage at a common node of the first differential amplifier 630a with a gain or attenuation dependent on the capacitances CI of the first capacitor 631a and C2 of the second capacitor 632a. The differential voltage is output by the first differential amplifier 630a to the gate of the third source follower transistor 697a, and a corresponding analog voltage signal can be read out from the pixel 600 via the first row select transistor 609 to the column readout circuitry 620. Thereafter, the column readout circuitry 620 can perform remaining calculations to reduce FPN. Thus, the pixel 600 can operate using any of the FPN reduction techniques, CDS sampling methods, and / or four-sampling methods described in detail above.

[0131] In some embodiments, in the second tap of the pixel 600, the switch signal SW supplied to the gate switch transistor 633a of the first differential amplifier 630a can be the same signal or a different signal than the switch signal SW supplied to the gate of the switch transistor 633b of the second differential amplifier 630b. Additionally, in some embodiments, the pixels and / or image sensors can be configured in a stacked configuration, e.g., using pixel-level hybrid bonding at various locations.

[0132] Figure 6A is a partial schematic circuit diagram of an alternative differential amplifier 630’ configured in accordance with various embodiments of the present technology. In some embodiments, Figure 6 The differential amplifier 630’ of Figure 6A may be used in place of the first differential amplifier 630a and / or the second differential amplifier 630b of the pixel 600 of Figure 6A The alternative differential amplifier 630’ of

[0133] Reference is made to Figure 7The differential amplifier 630' is an active differential amplifier having a first capacitor 634, an amplifier 635, a second capacitor 636, and a switch transistor 637. The first capacitor 634 is coupled to an input of the differential amplifier 630'. Additionally, the amplifier 635, the second capacitor 636, and the switch transistor 637 each couple the first capacitor 634 to an output of the differential amplifier 630'. More specifically, the amplifier 635, the second capacitor 636, and the switch transistor 637 are coupled in parallel with one another between the first capacitor 634 and the output of the differential amplifier 630'. The amplifier 635 of the differential amplifier 630' includes an input (e.g., an inverting input) and an output. In some embodiments, the amplifier 635 can be an inverter or an operational amplifier (opamp) and / or can further include another input (not shown) coupled to ground (e.g., a negative power rail or another reference voltage), such as a non-inverting input.

[0134] The switch transistor 637 is arranged as a reset switch and includes a gate configured to receive a switch signal SW. When the switch signal SW is asserted, the switch transistor 637 is activated, thereby shorting together the input and the input of the amplifier 635 via the switch transistor 637. This can automatically zero the amplifier 635, setting the voltage at the input of the amplifier 635 equal to the voltage at the output of the amplifier 635 and at an intermediate potential dependent on the characteristics of the amplifier 635. As the switch signal SW is de-asserted, the switch transistor 637 is deactivated and the voltage signal (e.g., S A-0 ) at the input of the differential amplifier 630' is sampled onto the first capacitor 634. Then, as the voltage at the input of the differential amplifier 630' changes (e.g., becomes S A-1 ), the difference between the voltage (e.g., S A-0 ) sampled onto the first capacitor 634 and the voltage (e.g., S A-1 ) at the input of the differential amplifier 630' is amplified and appears at the output of the differential amplifier 630'.

[0135] Figure 6 is a partial schematic circuit diagram of another pixel 700 configured in accordance with various embodiments of the present technology. The pixel 700 is generally similar to the pixel 600 of Figure 6 . Accordingly, detailed discussion of generally similar components between the pixel 600 and the pixel 700 is omitted here for brevity in view of the detailed discussion provided above. The pixel 700 differs from the pixel 600 downstream of first and second differential amplifiers 730a and 730b of the pixel 700. Figure 7Apixel 700 includes a fifth source follower transistor 761a having a gate coupled to an output of the first differential amplifier 730a, a third enable transistor 762a coupled to the fifth source follower transistor 761a and having a gate configured to receive the enable signal EN, a third current source 763a coupled between the third enable transistor 762a and ground, a first capacitor bank 740a, and a sixth source follower transistor 797a coupled to the first row select transistor 709 and having a gate coupled to an output of the first capacitor bank 740a. The enable signal EN supplied to the gate of the third enable transistor 762a can be the same signal as (a) the enable signal EN supplied to the gate of the enable transistor coupled to the input of the first differential amplifier 730a and / or (b) the enable signal EN supplied to the gate of the enable transistor coupled to the input of the second differential amplifier 730b, or a different signal.

[0136] Referring now to the second tap of the pixel 700, the pixel 700 includes a seventh source follower transistor 761b having a gate coupled to an output of the second differential amplifier 730b, a fourth enable transistor 762b coupled to the seventh source follower transistor 761b and having a gate configured to receive the enable signal EN, a fourth current source 763b coupled between the fourth enable transistor 762b and ground, a second capacitor bank 740b, and an eighth source follower transistor 797b coupled to the second row select transistor 710 and having a gate coupled to an output of the second capacitor bank 740b. The enable signal EN supplied to the gate of the fourth enable transistor 762a can be the same signal as (a) the enable signal EN supplied to the gate of the enable transistor coupled to the input of the second differential amplifier 730b, (b) the enable signal EN supplied to the gate of the enable transistor coupled to the input of the first differential amplifier 730a, and / or (c) the enable signal EN supplied to the gate of the third enable transistor 762a, or a different signal.

[0137] Figure 7 is Figure 7 a portion of the capacitor bank 740a. Figure 7A The capacitor bank 740b of the pixel 700 can have a structure similar to the capacitor bank 740a detailed in Figure 7A As detailed in Figure 7As shown, capacitor bank 740a includes first switches 741 to 744, second switches 761 to 764, capacitors 751 to 754, transistor 760, and capacitor 755. More specifically, capacitor bank 740a includes four circuit branches coupled in parallel to each other between the input and output of capacitor bank 740. Each branch includes a counterpart of the first switches 741 to 744, a counterpart of the sampling capacitors 751 to 754, and a counterpart of the second switches 761 to 764. For example, the first circuit branch of capacitor bank 740a includes first switch 741, sampling capacitor 751, and second switch 761. First switch 741 selectively couples the input of capacitor bank 740a to sampling capacitor 751 and second switch 761, and second switch 761 selectively couples first switch 741 and sampling capacitor 751 to the output of capacitor bank 740. Sampling capacitor 751 is coupled between (a) the first and second switches 741 and 761 and (b) ground. Transistor 760 is coupled to (a) V DD Alternatively, another reference voltage may be connected between (b) each of the second switches 761 to 764, the output of capacitor bank 740, and capacitor 755. Transistor 760 includes a gate configured to receive a signal PRE to selectively activate transistor 760. Capacitor 755 is coupled between (a) ground and (b) each of the second switches 761 to 764, the output of capacitor bank 740, and transistor 760. As discussed in more detail below, capacitor bank 740a may be used to sample and store various differential signals output from the first differential amplifier 730a or the second differential amplifier 730b and to calculate the sum of various signals stored in capacitor bank 740.

[0138] Refer again Figure 3B Differential amplifiers 730a and 730b can calculate the differences between various voltage signals generated by pixel 700. For example, see the attached image. Figure 7A and 7 The first differential amplifier 730a can calculate: (a) at time t1 based on the floating diffuser FD A Voltage V at point FDA The captured first reset noise signal and the floating diffuser FD at time t3 A Voltage V at point FDA The captured signal S A-0 (a) The first difference between them; (b) at time t6 based on the floating diffusion part FD A Voltage V at point FDA The captured signal S A-0 At time t8, based on the floating diffusion part FD A Voltage V at point FDA(c) The second difference between the captured second reset noise signal (or the third reset noise signal captured at time t9 if the duration between time t8 and t9 is short); A Voltage V at point FDA The captured third reset noise signal (or the second reset noise signal captured at time t8 if the duration between times t8 and t9 is short) and the reset noise signal captured at time t11 based on the floating diffusion part FD A Voltage V at point FDA The captured signal S A-1 The third difference between them; and (d) at time t14 based on the floating diffusion part FD A Voltage V at point FDA The captured signal S A-1 Compared with the floating diffusion part FD at time t16 A Voltage V at point FDA The fourth difference between the captured fourth reset noise signals.

[0139] The first differential amplifier output from the first differential amplifier 730a can be transmitted via the first switch 741 when the third enable transistor 762a is activated. Figure 7A The sampling capacitor 751 is selectively coupled to the fifth source follower transistor 761a, which is stored in the sampling capacitor 751 of the first capacitor bank 740a. Figure 7A The second differential amplifier output from the first differential amplifier 730a can be transmitted via the first switch 742 when the third enable transistor 762a is activated. Figure 7A The sampling capacitor 752 is selectively coupled to the fifth source follower transistor 761a and stored in the sampling capacitor 752 of the first capacitor bank 740a. Figure 7A The third differential output from the first differential amplifier 730a can be transmitted via the first switch 743 when the third enable transistor 762a is activated. Figure 7A The sampling capacitor 753 is selectively coupled to the fifth source follower transistor 761a and stored in the sampling capacitor 753 of the first capacitor bank 740a. Figure 7A ); and the fourth differential output from the first differential amplifier 730a can be transmitted via the first switch 744 when the third enable transistor 762a is activated. Figure 7A The sampling capacitor 754 is selectively coupled to the fifth source follower transistor 761a and stored in the sampling capacitor 754 of the first capacitor bank 740a. Figure 7 ).

[0140] After the differences are stored to the sampling capacitors 751-754 of the first capacitor bank 740a, the first capacitor bank 740a can be used to compute the sum of two or more of the signals stored in the first capacitor bank 740a by shorting the respective capacitors together. For example, referring to Figure 8 and 7A together, the first and second differences output from the first differential amplifier 730a and stored to the first capacitor bank 740a can be added together to compute a first sum by selectively coupling the sampling capacitor 751 to the sampling capacitor 752 via the second switch 761 and the second switch 762 when the transistor 760 is activated. Similarly, the third and fourth differences output from the first differential amplifier 730a and stored to the first capacitor bank 740a can be added together to compute a second sum by selectively coupling the sampling capacitor 753 to the sampling capacitor 754 via the second switch 763 and the second switch 764 when the transistor 760 is activated. The first and second sums are applied (at different times) to the gate of the sixth source follower transistor 797a at the output of the first capacitor bank 740a, and signals corresponding to the first and second sums can be read out from the pixel 700 to the column readout circuitry 720 via the first row select transistor 709.

[0141] The second capacitor bank 740b of the second tap of the pixel 700 can operate in substantially similar fashion to the first capacitor bank 740a discussed in detail above.

[0142] Figure 7 is a flowchart of a method 870 of a pixel 700 that illustrates the operation of various embodiments of the present technology Figure 7 Method 870 is illustrated as a series of steps or blocks. Blocks aligned on the left-hand side of the page correspond to the first tap of the pixel 700, and blocks aligned on the right-hand side of the page correspond to the second tap of the pixel 700. All or a subset of any one or more of the blocks can be performed according to the discussion above. For example, only a subset of the blocks is discussed below.

[0143] Referring to Figure 8 , 7A and 8, the method 870 begins at block 871 by (i) asserting a reset signal RST to reset the pixel 700 and (ii) sampling a first reset noise component (shown as “V1” in A-0 ) of the signal S Figure 8 At block 872, the method 870 continues by (i) de-asserting the reset signal RST and (ii) sampling a first portion (shown as “V2” in A-0 ) of the signal S Figure 8The sampling continues (shown as "V2" in the diagram). At box 873, method 870 calculates the signal S using a first differential amplifier 730a. A-0 The first reset noise component and signal S A-0 The process continues by the first difference (V1-V2) between the first portions. This difference can be stored on the first sampling capacitor 751 of the first capacitor bank 740a of pixel 700. At block 874, method 870 proceeds by adjusting the signal S... A-0 Part Two (in) Figure 8 The sampling continues (shown as "V3" in the image). Signal S A-0 The second part can be sampled onto the first differential amplifier 730a. At block 875, method 870 resets pixel 700 by (i) asserting the reset signal RST and (ii) adjusting the signal S. A-0 The second reset noise component (in) Figure 8 The sampling continues (shown as "V4" in the diagram). At box 875, method 870 calculates the signal S using a first differential amplifier 730a. A-0 The second part is related to signal S A-0 The second difference (V3-V4) between the second reset noise components continues. The difference can be stored on the sampling capacitor 752 of the first capacitor bank 740a of pixel 700.

[0144] like Figure 8 As shown in the diagram, method 870 may additionally include a method for signal S. B-1 S A-0 and S B-0 Each of these performs steps largely similar to those in boxes 871 to 876. More specifically, during the first subframe and / or in the same timing sequence, the signal S at the first tap of pixel 700 may be... A-0 Execution boxes 871 to 876, and can target the signal S on the second tap of pixel 700. B-1 The steps are largely similar to those in boxes 871 to 876. Subsequently, during the second subframe and / or in the same timing sequence, the signal S at the first tap of pixel 700 can be... A-1 The steps are largely similar to those in boxes 871 to 876, and can be applied to the signal S at the second tap of pixel 700. B-0 Perform steps that are largely similar to those in boxes 871 to 876.

[0145] At box 877, method 870 calculates signal S. A-0 And so on. More specifically, sampling capacitors 751 and 752 can be shorted together via the second switches 761 and 762 of the first capacitor bank 740a to combine signal S. A-0 The first difference (V1-V2) and signal SA-0 The second difference (V3-V4). Assuming the noise components are strongly correlated, the noise components can cancel each other, leaving the signal S A-0 The sum of the first difference and the second difference can be read out from the pixel 700 to the column readout circuitry 720 via the sixth source follower transistor 797a and the first row select transistor 709 of the pixel 700. As shown in Figure 9 , generally similar steps to block 877 can be performed: (i) using the other two sampling capacitors 753 and 754 of the first capacitor bank 740a and the second switches 763 and 764 for the signal S A-1 on the first tap of the pixel 700; and (ii) using the sampling capacitors of the second capacitor bank 740b of the pixel 700 and the second switches for the signal S B-0 and S B-1 on the second tap of the pixel 700.

[0146] Although the steps of the method 870 are discussed and illustrated in a particular order, the method 870 is not limited thereto. In other embodiments, the method 870 can be performed in a different order. In these and other embodiments, any of the steps of the method 870 can be performed before, during, and / or after any of the other steps of the method 870. Moreover, the method 870 can be modified and still remain within these and other embodiments of the technology. For example, in some embodiments, one or more steps of the method 870 can be omitted and / or repeated.

[0147] Figure 7 is a partial schematic circuit diagram of another pixel 900 configured in accordance with various embodiments of the technology. The pixel 900 is generally similar to the pixel 700 of Figure 7 . Thus, in the interest of brevity, detailed discussion of generally similar components between the pixel 700 and the pixel 900 is omitted here in view of the detailed discussion provided above. The pixel 900 differs from the pixel 700 of Figure 9 with respect to the first and second capacitor banks 940a and 940b of the pixel 900. With respect to the first tap of the pixel 900, the pixel 900 includes: a source follower transistor 981a having a gate coupled to an output of the first capacitor bank 940a; an enable transistor 982a coupled to the source follower transistor 981a and having a gate configured to receive an enable signal EN; a current source 983a coupled between the enable transistor 982a and ground; a third differential amplifier 930c having inputs coupled to the source follower transistor 981a and the enable transistor 982a; a source follower transistor 997a coupled to the first row select transistor 909 and having a gate coupled to an output of the third differential amplifier 930c. The enable signal EN supplied to the gate of the enable transistor 982a can be the same as the enable signal EN supplied to the gate of the enable transistor 982 of the pixel 700. Figure 10This refers to any one or more of the other enable signals EN described herein, or different signals. See below for reference. Figure 9 In more detail, the third differential detector 930c is used to calculate the signal S from the first subframe. A-0 With the signal S from the second subframe A-1 The difference between them.

[0148] Referring now to the second tap of pixel 900, pixel 900 includes: a source follower transistor 981b having a gate coupled to the output of a second capacitor bank 940b; an enable transistor 982b coupled to the source follower transistor 981b and having a gate configured to receive an enable signal EN; a current source 983b coupled between the enable transistor 982b and ground; a fourth differential amplifier 930d having an input coupled to the source follower transistor 981b and the enable transistor 982b; and a source follower transistor 997b coupled to a second row select transistor 910 and having a gate coupled to the output of the fourth differential amplifier 930d. The enable signal EN supplied to the gate of the enable transistor 982b can be... Figure 10 This refers to any one or more of the other enable signals EN described herein, or different signals. See below for reference. Figure 10 In more detail, the fourth differential detector 930d is used to calculate the signal S from the first subframe. B-0 With the signal S from the second subframe B-1 The difference between them.

[0149] Figure 9 This describes the operation of various embodiments according to the present technology. Figure 8 The flowchart of method 1020 for pixel 900 is provided. Method 1020 is described as a series of steps or boxes. The box aligned on the left side of the page corresponds to the first tap of pixel 900, and the box aligned on the right side of the page corresponds to the second tap of pixel 900. All or a subset of any one or more of the boxes may be performed as discussed above. As shown, boxes 1021 to 1027 are generally similar to those in... Figure 8 The method 870, which is described in detail above, is explained in boxes 871 to 877. Therefore, for the sake of brevity, a detailed discussion of boxes 1021 to 1027 is omitted here.

[0150] At box 1027, and Figure 11 Compared to block 877 of method 870, signal S A-0 S A-1 S B-0 and S B-1The sum of the first difference and the second difference is not read from pixel 900 into column readout circuit system 920. Instead, referring to the first tap of pixel 900, method 1020: (i) output signal S from the first capacitor bank 940a A-0 The sum of the first and second differences (which can be approximated by the signal S from the first subframe when the noise components are strongly correlated and largely cancel each other out) A-0 (i) to the gate of the source follower transistor 981a; and (ii) to sample the corresponding first signal onto the third differential amplifier 930c of the pixel 900. Next, method 1020: (i) output signal S from the first capacitor bank 940a. A-1 The sum of the first and second differences (which can be approximated by the signal S from the second subframe when the noise components are strongly correlated and largely cancel each other out) A-1 (i) inputting the second signal to the gate of the source follower transistor 981a; and (ii) inputting the corresponding second signal to the third differential amplifier 930c. Method 1020 for the signal S on the second tap of pixel 900 B-0 and S B-1 Perform a similar process.

[0151] At block 1028, method 1020 continues by calculating the difference between the corresponding first signal and the corresponding second signal using a third differential amplifier 930c. When the noise components are strongly correlated and largely cancel each other out, the difference output from the third differential amplifier 930c can represent signal S. A-0 With signal S A-1 The difference between them. The difference output from the third differential amplifier 930c is applied to the gate of the source follower transistor 997a, and the corresponding signal can be read from pixel 900 to column readout circuit system 920 via the first row select transistor 909. The method is for the signal S at the second tap of pixel 900. B-0 and S B-1 A similar process is performed using the fourth differential amplifier 930d.

[0152] Although the steps of method 1020 are described and illustrated in a specific order, method 1020 is not limited thereto. In other embodiments, method 1020 may be performed in a different order. In these and other embodiments, any of the steps of method 1020 may be performed before, during, and / or after any of the other steps of method 1020. Furthermore, method 1020 may be modified but remains within these and other embodiments of the present technology. For example, in some embodiments, one or more steps of method 1020 may be omitted and / or repeated.

[0153] In some embodiments, instead of (a) reading the difference from the output of the third differential amplifier 930c to the column readout circuit system 920 via the first row select transistor 909 and (b) reading the difference from the output of the fourth differential amplifier 930d to the column readout circuit system 920 via the second row select transistor 910, the outputs of source follower transistors 997a and 997b can be shorted together. For example, the bit line at the output of source follower transistor 997a can be shorted to the bit line at the output of source follower transistor 997b. When the values ​​of the difference from the outputs of the third and fourth differential amplifiers 930c and 930d are close, shorting the bit lines in this manner allows the sum of the difference from the output of the third differential amplifier 930c and the difference from the output of the fourth differential amplifier 930d to be calculated. When the noise components are strongly correlated and largely cancel each other out, the calculated sum can be represented as (S A-0 -S A-1 )+(S B-0 -S B-1 This sum can then be read out to column readout circuitry 920, for example, using a single row selection transistor (not shown). In other words, in some embodiments, pixel 900 may utilize single-ended readout.

[0154] Figure 9 This describes the operation of various embodiments according to the present technology. Figure 10 The flowchart for this alternative method 1120 for pixel 900 is provided. Method 1120 is described as a series of steps or boxes. The box aligned on the left side of the page corresponds to the first tap of pixel 900, and the box aligned on the right side of the page corresponds to the second tap of pixel 900. All or a subset of any one or more of the boxes may be performed as discussed above. As shown, boxes 1121 to 1128 are generally similar to those in Figure 10 Boxes 1021 to 1028 of method 1020, which are described in detail above, are used for explanation. Therefore, for the sake of brevity, a detailed discussion of boxes 1121 to 1128 is omitted here.

[0155] At box 1128, and Figure 12 Compared to block 1028 of method 1020, the signal S output from the third differential amplifier 930c is... A-0 With signal S A-1 The difference between the two is not read from pixel 900 into column readout circuitry 920. Additionally, the signal S output from the fourth differential amplifier 930d... B-0 With signal S B-1The difference between is not read out of the pixel 900 to the column readout circuitry 920. Instead, the difference is each applied to the corresponding gate of the source follower transistors 997a and 997b, and the method 1120 shorts the bit lines together at the outputs of the source follower transistors 997a and 997b at block 1129. Assuming the values of the differences output from the third and fourth differential amplifiers 930c and 930d are close, the shorting process performed at block 1129 calculates the sum of the differences. The sum of the differences can then be read out of the pixel 900 to the column readout circuitry 920. However, when the values of the differences output from the third and fourth differential amplifiers 930d and 930d are not close, shorting the bit lines in this manner can cause the circuit to act as a winner-take-it-all circuit.

[0156] Although the steps of the method 1120 are discussed and illustrated in a particular order, the method 1120 is not limited thereto. In other embodiments, the method 1120 can be performed in a different order. In these and other embodiments, any of the steps of the method 1120 can be performed before, during, and / or after any of the other steps of the method 1120. Moreover, the method 1120 can be modified and still remain within these and other embodiments of the technology. For example, in some embodiments, one or more steps of the method 1120 can be omitted and / or repeated.

[0157] Figure 9 is a partial schematic circuit diagram of yet another pixel 1200 configured in accordance with various embodiments of the technology. The pixel 1200 is generally similar to the pixel 900 of Figure 9 . Thus, in view of the detailed discussion provided above, detailed discussion of generally similar components between the pixel 900 and the pixel 1200 is omitted here for brevity. The pixel 1200 differs from the pixel 900 in terms of coupling. Figure 12Pixel 900. First, the first capacitor bank 1240a of the first tap of pixel 1200 is selectively shorted to the second capacitor bank 1240b of the second tap of pixel 1200 via a summing switch 1231. Second, the components downstream of the second capacitor bank 1240b are shared between the first and second taps of pixel 1200. More specifically, the first and second taps of the pixel share: (a) a source follower transistor 1281 having a gate coupled to the output of the second capacitor bank 1240b; (b) an enable transistor 1282 coupled to the source follower transistor 1281 and having a gate configured to receive an enable signal EN; (c) a current source 1283 coupled between the enable transistor 1282 and ground; (d) a third differential amplifier 1230c having an input coupled to the source follower transistor 1281 and the enable transistor 1282; (e) a source follower transistor 1297 having a gate coupled to the output of the third differential amplifier 1230c; and (f) a row select transistor 1210 coupled to the source follower transistor 1297. Therefore, it is possible to... Figure 9 The pixel count of 1200 is roughly similar to... Figure 12 The first capacitor bank 940a downstream of the first tap of pixel 900 is described as a component of the assembly, and pixel 1200 can be read out using a single-ended method. The enable signal EN supplied to the gate of enable transistor 1282 can be [missing information]. Figure 13 Any one or more of the other enable signals EN described herein, or different signals.

[0158] Figure 12 This describes the operation of various embodiments according to the present technology. Figure 10 The flowchart of method 1340 for pixel 1200 is provided. Method 1340 is described as a series of steps or boxes. The box aligned on the left side of the page corresponds to the first tap of pixel 1200, and the box aligned on the right side of the page corresponds to the second tap of pixel 1200. All or a subset of any one or more of the boxes may be performed as discussed above. As shown, boxes 1341 to 1347 are generally similar to those in... Figure 10 Boxes 1021 to 1027 of method 1020, which are described in detail above, are used for explanation. Therefore, for the sake of brevity, a detailed discussion of boxes 1341 to 1347 is omitted here.

[0159] At box 1348, method 1340 activates summation switch 1231 to short-circuit the outputs of first capacitor bank 1240a and second capacitor bank 1240b together. For example, although method 1340 is at box 1347: (a) using the corresponding second switch of first capacitor bank 1240a to short-circuit the two sampling capacitors of first capacitor bank 1240a together (e.g., to calculate (S A-0 ΔV12 )+(S A-0 ΔV 34 )) and (b) using the corresponding second switches of the second capacitor bank 1240b to short together two sample capacitors of the second capacitor bank 1240b (e.g., to compute (S B-0 ΔV 12 )+(S B-0 ΔV 34 )) but the method 1340 can activate the switch 1231 so that the outputs of the first and second capacitor banks 1240a and 1240b are shorted to compute a first sum (e.g., equivalent to (S A-0 ΔV 12 )+(S A-0 ΔV 34 )+(S B-0 ΔV 12 )+(S B-0 ΔV 34 )). As discussed above, when the noise components are strongly correlated and largely cancel each other out, the sum can be approximately equivalent to S A-0 +S B-0 . Then, the first sum can be output from the second capacitor bank 1240b and applied to the source follower transistor 1281 so that the first sum is sampled on the third differential amplifier 1230c.

[0160] Then, while the method 1340 at block 1347: (a) uses the corresponding second switches of the first capacitor bank 1240a to short together another two sample capacitors of the first capacitor bank 1240a (e.g., to compute (S A-1 ΔV 12 )+(S A-1 ΔV 34 )) and (b) uses the corresponding second switches of the second capacitor bank 1240b to short together another two sample capacitors of the second capacitor bank 1240b (e.g., to compute (S B-1 ΔV 12 )+(S B-1 ΔV 34 )) the method 1340 can activate the switch 1231 so that the outputs of the first and second capacitor banks 1240a and 1240b are shorted to compute a second sum (e.g., equivalent to (S A-1 ΔV 12 )+(S A-1 ΔV 34 )+(S B-1 ΔV 12 )+(S B-1 ΔV 34)). As discussed above, the second sum can be approximately equal to S A-1 + S B-1 The second sum can then be output from the second capacitor bank 1240b and applied to the source follower transistor 1281, such that a corresponding signal is provided to the input of the third differential amplifier 1230c.

[0161] At block 1349, the method 1340 continues by: (i) calculating a difference between the first sum and the second sum; and (ii) reading the difference out of the pixel 1200 to the column readout circuitry 1220 via the row select transistor 1210. The method 1340 can calculate the difference using the third differential amplifier 1230c. When the noise components are strongly correlated and largely cancel each other out, the difference calculated by the third differential amplifier 1230c can be approximately equal to (S A-0 + S B-0 ) - (S A-1 + S B-1 ) or AS A + AS B .

[0162] Although the steps of the method 1340 are discussed and illustrated in a particular order, the method 1340 is not limited thereto. In other embodiments, the method 1340 can be performed in a different order. In these and other embodiments, any of the steps of the method 1340 can be performed before, during, and / or after any of the other steps of the method 1340. Moreover, the method 1340 can be modified and still remain within these and other embodiments of the technology. For example, in some embodiments, one or more steps of the method 1340 can be omitted and / or repeated. As a particular example, the pixel 1200 can operate using a method similar to the method 1020 of Figure 10 As a particular example, the third differential amplifier 1230c can be used to sequentially perform the corresponding blocks on the right side of the method 1020 illustrated in blocks 1028 and Figure 14

[0163] Figure 9 is a partial schematic circuit diagram of yet another pixel 1400 configured in accordance with various embodiments of the technology. The pixel 1400 is generally similar to the pixel 900 of Figure 9 Accordingly, detailed discussion of generally similar components between the pixel 900 and the pixel 1400 is omitted here for brevity in view of the detailed discussion provided above. The pixel 1400 differs from the pixel 900 in terms of coupling. Figure 14 ​Pixel 900. First, the output of the third differential amplifier 1430c of the first tap of pixel 1400 is selectively shorted to the output of the fourth differential amplifier 1430d of the second tap of pixel 1400 via a summing transistor 1465, the summing transistor 1465 including a gate configured to receive a summing signal Σ. Second, components downstream of the third differential amplifier 1430c are shared between the first and second taps of pixel 1400. More specifically, the first and second taps of the pixel share: (a) a source follower transistor 1497 having a gate (via summing transistor 1465) coupled to the outputs of the third differential amplifier 1430c and the fourth differential amplifier 1430d; and (b) a row select transistor 1409 coupled to the source follower transistor 1497. Thus, it is possible to see from Figure 9 The 1400 pixels are roughly similar to... Figure 15 The components of the fourth differential amplifier 930d downstream of the second tap of pixel 900 are described, and pixel 1400 can be read out using a single-ended method.

[0164] Figure 14 This describes the operation of various embodiments according to the present technology. Figure 10 The flowchart of method 1570 for pixel 1400 is provided. Method 1570 is described as a series of steps or boxes. The box aligned on the left side of the page corresponds to the first tap of pixel 1400, and the box aligned on the right side of the page corresponds to the second tap of pixel 1400. All or a subset of any one or more of the boxes may be performed as discussed above. As shown, boxes 1571 to 1578 are generally similar to those in... Figure 16 Boxes 1021 to 1028 of method 1020, which is explained and discussed in detail above, are referenced here. Therefore, for the sake of brevity, a detailed discussion of boxes 1571 to 1578 is omitted here.

[0165] At box 1579, the signal S output from the third differential amplifier 1430c is... A-0 With signal S A-1 The difference between them and the signal S output from the fourth differential amplifier 1430d B-0 With signal S B-1 The difference between them is summed. More specifically, method 1570 activates the summing transistor 1465 by asserting the summing signal Σ to short-circuit the output of the third differential amplifier 1430c with the output of the fourth differential amplifier 1430d. (a) Signal S A-0 With signal S A-1 The difference between (b) and signal S B-0 With signal S B-1The sum of the differences is applied to the gate of the source follower transistor 1497, and the corresponding signal can be read out from the pixel 1400 via the row select transistor 1409 to the column readout circuitry 1420. The sum of the differences can represent ΔS A + ΔS B .

[0166] Although the steps of the method 1570 are discussed and illustrated in a particular order, the method 1570 is not limited thereto. In other embodiments, the method 1570 can be performed in a different order. In these and other embodiments, any of the steps of the method 1570 can be performed before, during, and / or after any of the other steps of the method 1570. Moreover, the method 1570 can be modified and still remain within the scope of these and other embodiments of the technology. For example, in some embodiments, one or more steps of the method 1570 can be omitted and / or repeated.

[0167] Figure 7 is a partial schematic circuit diagram of another pixel 1600 configured in accordance with various embodiments of the technology. The pixel 1600 is generally similar to the pixel 700 of Figure 7 . Accordingly, in view of the detailed discussion provided above, detailed discussion of generally similar components between the pixel 700 and the pixel 1600 is omitted here for brevity. The pixel 1600 and the pixel 700 are configured to operate in a similar manner as described above with respect to the pixel 700. Figure 17The pixel 1600 differs from the pixel 700 in that the first capacitor bank 1640a of the pixel 1600 contains fewer sampling capacitors than the first capacitor bank 740a of the pixel 700, and the second capacitor bank 1640b of the pixel 1600 contains fewer sampling capacitors than the second capacitor bank 740b of the pixel 700. More specifically, referring to the first tap of the pixel 1600 as an example, the first capacitor bank 1640a contains first switches 1641a and 1642a, second switches 1661a and 1662a, sampling capacitors 1651a and 1652a, a transistor 1660a, and a capacitor 1655a. More specifically, the first capacitor bank 1640a contains two circuit branches coupled in parallel with each other between the input and the output of the first capacitor bank 1640a (rather than the four utilized in the pixel 700). Each of the branches contains a corresponding one of the first switches 1641a and 1642a, a corresponding one of the sampling capacitors 1651a and 1652a, and a corresponding one of the second switches 1661a and 1662a. In other words, the first capacitor bank 1640a contains two fewer sampling capacitors and corresponding first and second switches than the first capacitor bank 740a of the pixel 700. All other components of the first capacitor bank 1640a are generally similar to those of the first capacitor bank 740a. The same applies to the second capacitor bank 1640b of the pixel 1600 as compared to the second capacitor bank 740b of the pixel 700. As discussed in more detail below, the use of fewer sampling capacitors in each of the first capacitor bank 1640a and the second capacitor bank 1640b is implemented using long exposure times and frame buffering: (a) to read past samples in a pipelined manner during exposure; and (b) to read past samples in a pipelined manner during exposure.

[0168] Figure 16 are illustrative of operations that can be utilized in connection with the FPN reduction methods described herein in accordance with various embodiments of the present technology Figure 16 is a timing diagram 1770 of a method of the pixel 1600. Referring to Figure 17 and 17 together, the method begins at time t0 by asserting the overflow gate signal OFG and the reset signal RST. Asserting the overflow gate signal OFG activates the overflow transistor 1601 of the pixel 1600 and clears any charge generated and accumulated at the photosensor 1602. Asserting the reset signal RST activates the first and second reset transistors 1605 and 1606 and clears any charge accumulated at the floating diffusion FD A and FD B . Thus, the voltage V A at the floating diffusion FD FDA and the voltage V B at the floating diffusion FD FDBReset to the reference voltage (e.g., V) via the first and second reset transistors 1605 and 1606 respectively. DD (or another positive power supply voltage). The switching signal SW can also be asserted to reset the voltage at the common node of the first and second differential amplifiers 1630a and 1630b. Then, the reset signal RST and / or the switching signal SW can be deasserted at time t1, while the overflow gate signal OFG remains asserted. Deasserting the switching signal SW will reset the signal S... A-0 The first reset noise component is sampled onto the first differential amplifier 1630a and / or the signal S is... B-1 The first reset noise component is sampled onto the second differential amplifier 1630b.

[0169] At time t2, the S output from the first differential amplifier 1630a A-0 ΔV 12 The signal S is sampled onto the sampling capacitor 1651a of the first capacitor bank 1640a via the first switch 1641a and output from the second differential amplifier 1630b. B-1 ΔV 12 The sample is fed to the sampling capacitor 1651b of the second capacitor bank 1640b via the first switch 1641b. In some embodiments, S A-0 ΔV 12 Equivalent to signal S at time t1 A-0 The first reset noise component and the signal S at time t2 A-0 The difference between the first parts. In these and other embodiments, S B-1 ΔV 12 Equivalent to signal S at time t1 B-1 The first reset noise component and the signal S at time t2 B-1 The difference between the first part.

[0170] From time t3 to time t5, the transfer signal TxA is asserted to activate the first transfer transistor 1603 of the first tap of pixel 1600. The time interval between time t3 and time t5 may correspond to the timing of an illuminator (not shown) emitting one or more light pulses, or to a large amount of light power from one or more light pulses emitted by the illuminator corresponding to a desired distance or range, which is received by pixel 1600 and transferred to the floating diffuser FD. A The timing is such that, during this time period, the photoelectric sensor 1602 of pixel 1600 generates photocharge or photocurrent, which is transferred to the floating diffuser FD via the first transfer transistor 1603. A Therefore, the floating diffuser FD A Voltage V at point FDA It decreases between time t3 and time t5.

[0171] At time t4, S is stored on the sampling capacitor 1651a of the first capacitor group 1640a of the first tap of pixel 1600. A-0 ΔV 12 The data is read from pixel 1600 to column readout circuitry 1620 via row selection transistor 1609 (e.g., by selectively coupling sampling capacitor 1651a to the gate of source follower transistor 1697a via second switch 1661a). Additionally, S is stored on the second sampling capacitor 1651b of the second capacitor bank 1640a of the second tap of pixel 1600. B-1 ΔV 12 The data is read from pixel 1600 to column readout circuitry 1620 via row selection transistor 1610 (e.g., by selectively coupling sampling capacitor 1651b to the gate of source follower transistor 1697b via second switch 1661b). Therefore, although samples are taken at time t2 onto the correspondings of the first and second capacitor banks 1640a and 1640b, S... A-0 ΔV 12 and S B-1 ΔV 12 It was not read from pixel 1600 until time t4.

[0172] At time t5, the transfer signal TxA can be de-asserted, thereby deactivating the first transfer transistor 1603. Additionally, the overflow gate signal OFG can be asserted to activate the overflow transistor 1601 and clear any charge at the photosensor 1602. The switching signal SW can also be pulsed to switch the signal S... A-0 The second part is sampled onto the first differential amplifier 1630a and / or the signal S is... B-1 The second part is sampled onto the second differential amplifier 1630b.

[0173] At time t6, the S output from the first differential amplifier 1630a A-0 ΔV 34 The signal S is sampled onto the sampling capacitor 1652a of the first capacitor bank 1640a via the first switch 1642a and output from the second differential amplifier 1630b. B-1 ΔV 34 The sampled signal is sent to the sampling capacitor 1652b of the second capacitor bank 1640b via the first switch 1642b. In some embodiments, S A-0 ΔV 34 Equivalent to signal S at time t5 A-0 The second part is related to the signal S at time t6. A-0 The difference between the second reset noise components. In these and other embodiments, S B-1 ΔV34 the second portion of signal S B-1 at time t6. B-1 the difference between the second reset noise component of signal S

[0174] At time t7, the reset signal RST is asserted to activate the first and second reset transistors 1605 and 1606. As discussed above, activating the first and second reset transistors 1605 and 1606 clears any charge accumulated at floating diffusion FD A and FD B . Accordingly, the voltage V A at floating diffusion FD FDA and the voltage V B at floating diffusion FD FDB are reset to a reference voltage (e.g., V DD or another positive supply voltage) via the first and second reset transistors 1605 and 1606, respectively. The switch signal SW can also be asserted to reset the voltage at the common node of the first and second differential amplifiers 1630a and 1630b. Then, the reset signal RST and / or the switch signal SW can be de-asserted at time t8, while the overflow gate signal OFG can remain asserted. De-asserting the switch signal SW can sample the first reset noise component of signal S A-1 onto the first differential amplifier 1630a and / or the first reset noise component of signal S B-0 onto the second differential amplifier 1630b.

[0175] At time t9, the AV A-1 of S 12 output from the first differential amplifier 1630a is sampled onto the sampling capacitor 1651a of the first capacitor bank 1640a via the first switch 1641a, and the AV B-0 of S 12 output from the second differential amplifier 1630b is sampled onto the sampling capacitor 1651b of the second capacitor bank 1640b via the first switch 1641b. In some embodiments, the AV A-1 of S 12 is equivalent to the difference between the first reset noise component of signal S A-1 at time t8 and the first portion of signal S A-1 at time t9. In these and other embodiments, the AV B-0 of S 12 is equivalent to the difference between the first reset noise component of signal S B-0 at time t8 and the first portion of signal S B-0 at time t9.

[0176] From time t10 to time ti l, the transfer signal TxB is asserted to activate the second transfer transistor 1604 of the second tap of the pixel 1600. The time period between time t10 and time ti l can correspond to the timing at which an illuminator (not shown) emits one or more light pulses or a large amount of light power corresponding to a desired distance or distance range from the one or more light pulses emitted by the illuminator to be received by the pixel 1600 and transferred to the floating diffusion FD B Thus, the photosensor 1602 of the pixel 1600 photo generates electrical charges or photocurrents during this time period, which are transferred to the floating diffusion FD B via the second transfer transistor 1604. As a result, the voltage V B at the floating diffusion FD FDB decreases between time t10 and time ti l.

[0177] At time ti l, the AV A-0 of S 34 stored on the sample capacitor 1652a of the first capacitor bank 1640a of the first tap of the pixel 1600 is read out from the pixel 1600 to the column readout circuitry 1620 via the row select transistor 1609 (e.g., by selectively coupling the sample capacitor 1652a to the gate of the source follower transistor 1697a via the second switch 1662a). In addition, the AV B-1 of S 34 stored on the second sample capacitor 1652b of the second capacitor bank 1640a of the second tap of the pixel 1600 is read out from the pixel 1600 to the column readout circuitry 1620 via the row select transistor 1610 (e.g., by selectively coupling the sample capacitor 1652b to the gate of the source follower transistor 1697b via the second switch 1662b). Thus, although sampled onto respective ones of the first and second capacitor banks 1640a and 1640b at time t6, the AV A-0 of S 34 and the AV B-1 of S 34 are not read out from the pixel 1600 until time ti l.

[0178] Also, at time ti l (or shortly before or after time ti l), the AV A-1 of S 12is read out of pixel 1600 via row select transistor 1609 to column readout circuitry 1620 (e.g., by selectively coupling sample capacitor 1651a to the gate of source follower transistor 1697a via second switch 1661a). Additionally, S B-0 ΔV 12 is read out of pixel 1600 via row select transistor 1610 to column readout circuitry 1620 (e.g., by selectively coupling sample capacitor 1651b to the gate of source follower transistor 1697b via second switch 1661b). Thus, although sampled onto respective ones of first and second capacitor banks 1640a and 1640b at time t9, ΔV A-1 ΔV 12 and ΔV B-0 of S 12 are not read out of pixel 1600 until time t11. ΔV A-1 of S 12 and ΔV B-0 of S 12 may be read out simultaneously with ΔV A-0 of S 34 and ΔV B-1 of S 34 for example by: (a) shorting sample capacitors 1651a and 1652a together via second switches 1661a and 1662a; and / or (b) shorting sample capacitors 1651b and 1652b together via second switches 1661b and 1662b. Alternatively, ΔV A-1 of S 12 and ΔV B-0 of S 12 may be read out sequentially with ΔV A-0 of S 34 and ΔV B-1 of S 34 .

[0179] At time t12, transfer signal TxB can be de-asserted, thereby deactivating second transfer transistor 1604. Additionally, overflow gate signal OFG can be asserted to activate overflow transistor 1601 and clear any charge at photosensor 1602. Switch signal SW can also be pulsed to couple signal S A-1to the first differential amplifier 1630a and / or a second portion of the signal S B-0 to the second differential amplifier 1630b.

[0180] At time t13, the ΔV A-1 of S 34 is sampled onto the sampling capacitor 1652a of the first capacitor bank 1640a via the first switch 1642a, and the ΔV B-0 of S 34 is sampled onto the sampling capacitor 1652b of the second capacitor bank 1640b via the first switch 1642b. In some embodiments, the ΔV A-0 of S 34 is equivalent to the difference between the second portion of the signal S A-1 at time t12 and the second reset noise component of the signal S A-1 at time t13. In these and other embodiments, the ΔV B-0 of S 34 is equivalent to the difference between the second portion of the signal S B-0 at time t12 and the second reset noise component of the signal S B-0 at time t13.

[0181] Although not shown in the timing diagram 1770 of S Figure 18 , the ΔV A-1 of S 34 may be read out of the pixel 1600 during the next subframe with timing corresponding to time t4 of the first subframe. More specifically, the ΔV A-1 of S 34 may be read out to the column readout circuitry 1620 via the row select transistor 1609 (e.g., by selectively coupling the sampling capacitor 1652a to the gate of the source follower transistor 1697a via the second switch 1662a). Similarly, the ΔV B-1 of S 34 may be read out of the pixel 1600 during the next subframe with timing corresponding to time t4 of the first subframe. More specifically, the ΔV B-1 of S 34The data can be read out to the column readout circuitry 1620 via the row selection transistor 1610 (e.g., by selectively coupling the sampling capacitor 1652b to the gate of the source follower transistor 1697b via the second switch 1662b). Therefore, although samples are taken at time t13 onto the correspondings of the first and second capacitor banks 1640a and 1640b, S... A-1 ΔV 34 and S B-0 ΔV 34 It was not read from pixel 1600 until later.

[0182] Although the steps of the method illustrated by timing diagram 1770 are discussed and described in a specific order, the method is not limited thereto. In other embodiments, the method illustrated by timing diagram 1770 may be performed in a different order. In these and other embodiments, any of the steps of the method may be performed before, during, and / or after any of the other steps of the method. Furthermore, the method illustrated by timing diagram 1770 may be modified but remains within these and other embodiments of the present technology. For example, in some embodiments, one or more steps of the method illustrated by timing diagram 1770 may be omitted and / or repeated.

[0183] Figure 12 This is a partial schematic circuit diagram of another pixel 1800 configured according to various embodiments of the present technology. Pixel 1800 is generally similar to... Figure 12 Pixel 1200. Therefore, given the detailed discussion provided above, for the sake of brevity, a detailed discussion of the generally similar components between pixel 1200 and pixel 1800 will be omitted here. Pixel 1800 differs in coupling from... Figure 18 Pixel 1200. First, instead of coupling the outputs of two different capacitor banks, pixel 1800 includes capacitor bank 1840, which is shared between the first tap and the second tap of pixel 1800 and arranged such that capacitors 1881 to 1886 can be programmed using the output of either or both of the first differential amplifier 1830a and / or the second differential amplifier 1830b. Second, the outputs of the first and second differential amplifiers 1830a and 1830b are coupled to the input of capacitor bank 1840 via first and second switches 1890a and 1890b, respectively. Third, the structure of capacitor bank 1840 and the total number of sampling capacitors in pixel 1800 are different from the structure of capacitor bank 1240 and the total number of sampling capacitors in pixel 1200.

[0184] like Figure 19As shown, capacitor bank 1840 includes switches 1891 to 1896, sampling capacitors 1881 to 1886, transistor 1860, and capacitor 1855. More specifically, capacitor bank 1840 includes six circuit branches, each selectively coupled to the input and output of capacitor bank 1840 via a corresponding one of switches 1891 to 1896. Each circuit branch includes a corresponding one of switches 1891 to 1896 and a corresponding one of sampling capacitors 1881 to 1886. For example, the first circuit branch includes switch 1891 and sampling capacitor 1881 coupled between ground and switch 1891. Switch 1891 selectively couples sampling capacitor 1881 to the input and output of capacitor bank 1840. As discussed in more detail below, the sampling capacitor can be used to selectively sample various differential signals output from the first differential amplifier 1830a and / or the second differential amplifier 1830b and to sum two or more of the differential signals together before outputting the sum to the third differential amplifier 1830c.

[0185] Figure 18 This describes the operation of various embodiments according to the present technology. Figure 18 Table 1920 shows the method for obtaining 1800 pixels. Please refer to it together. Figure 20 and 19 S output from the first differential amplifier 1830a A-0 ΔV 12 The signal can be sampled onto the sampling capacitor 1881 of the capacitor bank 1840 via the first switch 1890a and switch 1891. Additionally, the S signal output from the second differential amplifier 1830b... B-1 ΔV 12 The signal can be sampled onto the sampling capacitor 1882 of the capacitor bank 1840 via the second switch 1890b and switch 1892. Then, the S signal output from the first differential amplifier 1830a... A-0 ΔV 34 The signal can be sampled onto the sampling capacitor 1883 of the capacitor bank 1840 via the first switch 1890a and switch 1893. Furthermore, the S signal output from the second differential amplifier 1830b... B-1 ΔV 34 It can be sampled onto the sampling capacitor 1884 of the capacitor bank 1840 via the second switch 1890b and switch 1894.

[0186] Subsequently, S stored in sampling capacitor 1881 A-0 ΔV 12 and S stored in sampling capacitor 1883 A-0 ΔV 34It can be summed (e.g., by shorting sampling capacitors 1881 and 1883 together via switches 1891 and 1893). The sum (represented by S) A-0 The S can be stored in the sampling capacitor 1881 of the capacitor bank 1840. Additionally, the S stored in the sampling capacitor 1882... B-1 ΔV 12 and S stored in sampling capacitor 1884 B-1 ΔV 34 It can be summed (e.g., by shorting sampling capacitors 1882 and 1884 together via switches 1892 and 1894). The sum (represented by S) B-1 The voltage can be stored on the sampling capacitor 1882 of the capacitor bank 1840. In some embodiments, the voltage on the sampling capacitors 1883 and 1884 can then be reset by activating the transistor 1860 with the assertion signal PRE when the switches 1893 and 1894 are activated.

[0187] Next, the S output from the first differential amplifier 1830a A-1 ΔV 12 The signal can be sampled onto the sampling capacitor 1883 of the capacitor bank 1840 via the first switch 1890a and switch 1893. Additionally, the S signal output from the second differential amplifier 1830b... B-0 ΔV 12 The signal can be sampled onto the sampling capacitor 1884 of the capacitor bank 1840 via the second switch 1890b and switch 1894. Then, the SA signal output from the first differential amplifier 1830a... -1 ΔV 34 The signal can be sampled onto the sampling capacitor 1885 of the capacitor bank 1840 via the first switch 1890a and switch 1895. Furthermore, the S signal output from the second differential amplifier 1830b... B-0 ΔV 34 It can be sampled onto the sampling capacitor 1886 of the capacitor bank 1840 via the second switch 1890b and switch 1896.

[0188] Subsequently, S stored in sampling capacitor 1883 A-1 ΔV 12 and S stored in sampling capacitor 1885 A-1 ΔV 34 It can be summed (e.g., by shorting sampling capacitors 1883 and 1885 together via switches 1893 and 1895). The sum (represented by S) A-1 The S can be stored in the sampling capacitor 1883 of the capacitor bank 1840. Additionally, the S stored in the sampling capacitor 1884... B-0 ΔV12 and S stored in sampling capacitor 1886 B-0 ΔV 34 It can be summed (e.g., by shorting sampling capacitors 1884 and 1886 together via switches 1894 and 1896). The sum (represented by S) B-0 The voltage can be stored on the sampling capacitor 1884 of the capacitor bank 1840. In some embodiments, the voltage on the sampling capacitors 1885 and 1886 can then be reset by activating the transistor 1860 with the assertion signal PRE when the switches 1895 and 1896 are activated.

[0189] Next, S stored in sampling capacitor 1881 A-0 (representing S) A-0 ΔV 12 With S A-0 ΔV 34 The sum of (s) can be compared with S stored in the sampling capacitor 1884 B-0 (representing S) B-0 ΔV 12 With S B-0 ΔV 34 The sum is calculated by summing the samples (e.g., by shorting the sampling capacitors 1881 and 1884 together via switches 1891 and 1894). The resulting sum (representing S) is calculated by summing the samples (e.g., by shorting the sampling capacitors 1881 and 1884 together via switches 1891 and 1894). A-0 +S B-0 The S can be stored in the sampling capacitor 1881 of the capacitor bank 1840. Additionally, the S stored in the sampling capacitor 1883... A-1 (representing S) A-1 ΔV 12 With S A-1 ΔV 34 The sum of (S) can be compared with S stored in the sampling capacitor 1882 B-1 (representing S) B-1 ΔV 12 With S B-1 ΔV 34 The sum is calculated by summing the samples (e.g., by shorting the sampling capacitors 1883 and 1882 together via switches 1893 and 1892). The resulting sum (representing S) is calculated by summing the samples (e.g., by shorting the sampling capacitors 1883 and 1882 together via switches 1893 and 1892). A-1 +S B-1 The voltage can be stored on the sampling capacitor 1882 of the capacitor bank 1840. In some embodiments, the voltage on the sampling capacitors 1883 and 1884 can then be reset by activating the transistor 1860 with the assertion signal PRE when the switches 1893 and 1894 are activated.

[0190] Next, the third differential amplifier 1830c of the pixel 1800 can determine the difference between (a) the sum stored on the sampling capacitor 1881 of the capacitor bank 1840 (denoted S A-0 + S B-0 ) and (b) the sum stored on the sampling capacitor 1882 of the capacitor bank 1840 (denoted S A-1 + S B-1 ). For example, the sum stored on the sampling capacitor 1881 of the capacitor bank 1840 (denoted S A-0 + S B-0 ) can be read out from the capacitor bank 1840 via the switch 1891 and sampled onto the third differential amplifier 1830c. Next, the sum stored on the sampling capacitor 1882 of the capacitor bank 1840 (denoted S A-1 + S B-1 ) can be read out from the capacitor bank 1840 via the switch 1892 and input into the third differential amplifier 1830c. Next, the third differential amplifier 1830c can calculate the difference between the sums and output the difference to the gate of the source follower transistor 1897. Next, a signal corresponding to the difference applied to the gate of the source follower transistor 1897 can be read out from the pixel 1800 via the row select transistor 1810 to the column readout circuitry 1820.

[0191] Although the steps of the method illustrated by the table 1920 are discussed and illustrated in a particular order, the method is not so limited. In other embodiments, the method illustrated by the table 1920 can be performed in a different order. In these and other embodiments, any of the steps of the method can be performed before, during, and / or after any of the other steps of the method. Moreover, the method illustrated by the table 1920 can be altered and still remain within the scope of these and other embodiments of the technology. For example, in some embodiments, one or more steps of the method illustrated by the table 1920 can be omitted and / or repeated.

[0192] Figure 18 is a partial schematic circuit diagram of yet another pixel 2000 configured in accordance with various embodiments of the technology. The pixel 2000 is generally similar to the pixel 1800 of Figure 18 . Accordingly, detailed discussion of generally similar components between the pixel 1800 and the pixel 2000 is omitted here for brevity in view of the detailed discussion provided above. The pixel 2000 differs from the pixel 1800 of Figure 18 in coupling. First, the capacitor bank 2040 of the pixel 2000 includes ten circuit branches, which means that the capacitor bank 2040 includes (a) ten sampling capacitors 2080-2089 and (b) ten corresponding switches 2090-2099. Second, the pixel 2000 omits the first differential amplifier 1830a; the second differential amplifier 1830b; and the third differential amplifier 1830c is coupled to the gate of the source follower transistor 1897.Figure 20 The source follower transistor, enable transistor, and current source of the first and second differential amplifiers 1830a and 1830b of pixel 1800 are used. Therefore, instead of directly calculating S using differential amplifiers (e.g., the first differential amplifier 1830a and / or the second differential amplifier 1830b), the difference is calculated. A-0 S A-1 S B-0 and S B-1 ΔV of each of them 12 and ΔV 34 , Figure 21 2000 pixels can S A-0 S A-1 S B-0 and S B-1 Samples V1, V2, V3, and V4 are directly stored in one or more of sampling capacitors 1880 to 1881. In some embodiments, S A-0 S A-1 S B-0 and S B-1 V1 of each of them can represent the first reset noise component of the corresponding signal and can be provided by the following Equation 1; S A-0 S A-1 S B-0 and S B-1 V2 of each of them can represent the first part of the corresponding signal and can be provided by the following Equation 2; S A-0 S A-1 S B-0 and S B-1 V3 of each of them can represent the second part of the corresponding signal and can be provided by the following Equation 3; and S A-0 S A-1 S B-0 and S B-1 V4 of each of them can represent the second reset noise component of the corresponding signal and can be provided by the following Equation 4.

[0193] Equation 1: V1 = V DD +v n (t1, ω)

[0194] Equation 2: V2 = V DD -ΔV RST +v n (t2, ω)

[0195] Equation 3: V3 = V DD -S-ΔV RST +v n (t3, ω)

[0196] Equation 4: V4 = V DD +vn (t4, ω)

[0197] Figure 20 is illustrative of the operation of various embodiments of the present technology Figure 20 table 2140 of a four sampling method of a pixel of Figure 21 and 21 S A-0 of pixel 2000 can be sampled onto sampling capacitor 2081 of capacitor bank 2040 via first switch 2090a and switch 2091. Additionally, S B-1 of pixel 2000 can be sampled onto sampling capacitor 2082 of capacitor bank 2040 via second switch 2090b and switch 2092. Then, S A-0 of pixel 2000 can be sampled onto sampling capacitor 2083 of capacitor bank 2040 via first switch 2090a and switch 2093. Furthermore, S B-1 of pixel 2000 can be sampled onto sampling capacitor 2084 of capacitor bank 2040 via second switch 2090b and switch 2094. Additionally, S A-0 of pixel 2000 can be sampled onto sampling capacitor 2085 of capacitor bank 2040 via first switch 2090a and switch 2095. Then, S B-1 of pixel 2000 can be sampled onto sampling capacitor 2086 of capacitor bank 2040 via second switch 2090b and switch 2096.

[0198] Thereafter, S A-0 of pixel 2000 stored on sampling capacitor 2081 and S A-0 of pixel 2000 stored on sampling capacitor 2085 can be summed (e.g., by shorting sampling capacitor 2081 and sampling capacitor 2085 together via switch 2091 and switch 2095). The sum (representing (S A-0 of pixel 2000) + (S A-0 of pixel 2000) can be stored on sampling capacitor 2081 of capacitor bank 2040. Additionally, S B-1 of pixel 2000 stored on sampling capacitor 2082 and S B-1 of pixel 2000 stored on sampling capacitor 2086 can be summed (e.g., by shorting sampling capacitor 2082 and sampling capacitor 2086 together via switch 2092 and switch 2096). The sum (representing (S B-1 of pixel 2000) + (S B-1V2) can be stored on sample capacitor 2083 of capacitor bank 2040. In some embodiments, then, the voltages on sample capacitors 2085 and 2086 can be reset by asserting signal PRE to activate transistor 2060 when switches 2095 and 2096 are activated.

[0199] S A-0 V4) can be sampled onto sample capacitor 2085 of capacitor bank 2040 via first switch 2090a and switch 2095. Additionally, S B-1 V4) can be sampled onto sample capacitor 2086 of capacitor bank 2040 via second switch 2090b and switch 2096. Then, S

[0200] S A-0 V2) and S A-0 V4) can be summed (e.g., by shorting sample capacitor 2083 and sample capacitor 2085 together via switch 2093 and switch 2095). The sum (representing (S A-0 V2) + (S A-0 V4)) can be stored on sample capacitor 2083 of capacitor bank 2040. Additionally, S B-1 V2) and S B-1 V4) can be summed (e.g., by shorting sample capacitor 2084 and sample capacitor 2086 together via switch 2094 and switch 2096). The sum (representing (S B-1 V2) + (S B-1 V4)) can be stored on sample capacitor 2084 of capacitor bank 2040. In some embodiments, then, the voltages on sample capacitors 2085 and 2086 can be reset by asserting signal PRE to activate transistor 2060 when switches 2095 and 2096 are activated.

[0201] S A-1 V1) can be sampled onto sample capacitor 2085 of capacitor bank 2040 via first switch 2090a and switch 2095. Additionally, S B-0 V1) can be sampled onto sample capacitor 2086 of capacitor bank 2040 via second switch 2090b and switch 2096. Then, S A-1V2 of S can be sampled onto a sampling capacitor 2087 of capacitor bank 2040 via first switch 2090a and switch 2097. Further, S B-0 V2 of S can be sampled onto a sampling capacitor 2088 of capacitor bank 2040 via second switch 2090b and switch 2098. In addition, S A-1 V3 of S can be sampled onto a sampling capacitor 2089 of capacitor bank 2040 via first switch 2090a and switch 2099. Further, S B-0 V3 of S can be sampled onto a sampling capacitor 2080 of capacitor bank 2040 via second switch 2090b and switch 2090.

[0202] Next, the sum (representing (S A-1 V1 of S and the sum (representing (S A-1 V3 of S) stored on sampling capacitor 2089 can be summed (e.g., by shorting sampling capacitor 2085 and sampling capacitor 2089 together via switch 2095 and switch 2099). The sum (representing (S A-1 V1 of S) + (S A-1 V3 of S) can be stored on sampling capacitor 2085 of capacitor bank 2040. Further, S B-0 V1 of S and the sum (representing (S B-0 V3 of S) stored on sampling capacitor 2080 can be summed (e.g., by shorting sampling capacitor 2086 and sampling capacitor 2080 together via switch 2096 and switch 2090). The sum (representing (S B-0 V1 of S) + (S B-0 V3 of S) can be stored on sampling capacitor 2086 of capacitor bank 2040. In some embodiments, the voltages on sampling capacitors 2089 and 2080 can then be reset by asserting signal PRE to activate transistor 2060 when switches 2099 and 2090 are activated.

[0203] Next, the sum (representing (S A-0 V1 of S) + (S A-0 V3 of S) stored on sampling capacitor 2081 and the sum (representing (S B-0 V1 of S) + (S B-0 V3 of S) stored on sampling capacitor 2086 can be summed (e.g., by shorting sampling capacitor 2081 and sampling capacitor 2086 together via switch 2091 and switch 2096). The resulting sum (representing (S A-0 V1 of S) + (S A-0 V3 of S) + (SB-0 V1) + (S B-0 V3) can be stored on sample capacitor 2081 of capacitor bank 2040. Additionally, the sum (representing (S A-1 V1) + (S A-1 V3) sampled onto sample capacitor 2085 and the sum (representing (S B-1 V1) + (S B-1 V3) sampled onto sample capacitor 2082 can be summed (e.g., by shorting sample capacitor 2085 and sample capacitor 2082 together via switch 2095 and switch 2092). The resulting sum (representing (S A-1 V1) + (S A-1 V3) + (S B-1 V1) + (S B-1 V3) can be stored on sample capacitor 2082 of capacitor bank 2040. In some embodiments, then, the voltages on sample capacitors 2085 and 2086 can be reset by asserting signal PRE to activate transistor 2060 when switches 2095 and 2096 are activated.

[0204] Next, S A-1 V4 sampled by the first tap of pixel 2000 can be sampled onto sample capacitor 2089 of capacitor bank 2040 via first switch 2090a and switch 2099. Additionally, S B-0 V4 sampled by the second tap of pixel 2000 can be sampled onto sample capacitor 2080 of capacitor bank 2040 via second switch 2090b and switch 2090.

[0205] Next, S A-1 V2 stored on sample capacitor 2087 and S A-1 V4 stored on sample capacitor 2089 can be summed (e.g., by shorting sample capacitor 2087 and sample capacitor 2089 together via switch 2097 and switch 2099). The sum (representing (S A-1 V2) + (S A-1 V4) can be stored on sample capacitor 2087 of capacitor bank 2040. Additionally, S B-0 V2 stored on sample capacitor 2088 and S B-0 V4 stored on sample capacitor 2080 can be summed (e.g., by shorting sample capacitor 2088 and sample capacitor 2080 together via switch 2098 and switch 2090). The sum (representing (S B-0 V2) + (S B-0The voltage V4 can be stored on the sampling capacitor 2088 of the capacitor bank 2040. In some embodiments, the voltage on the sampling capacitors 2089 and 2080 can then be reset by activating the transistor 2060 with the assertion signal PRE when the switches 2099 and 2090 are activated.

[0206] Subsequently, the sum stored in the sampling capacitor 2083 (represented by (S) A-0 V2)+(S A-0 The sum of V4) and stored in sampling capacitor 2088 (representing (S) B-0 V2)+(S B-0 V4) can be summed (e.g., by shorting sampling capacitors 2083 and 2088 together via switches 2093 and 2098). The resulting sum (representing (S) A-0 V2)+(S A-0 (V4)+(S B-0 V2)+(S B-0 V4) can be stored on the sampling capacitor 2083 of the capacitor bank 2040. Additionally, the sum sampled onto the sampling capacitor 2087 (representing (S) A-1 V2)+(S A-1 The sum of V4) and the sampled onto the sampling capacitor 2084 (representing (S) B-1 V2)+(S B-1 V4) can be summed (e.g., by shorting sampling capacitors 2087 and 2084 together via switches 2097 and 2094). The resulting sum (representing (S) A-1 V2)+(S A-1 (V4)+(S B-1 V2)+(S B-1 The voltage V4 can be stored on the sampling capacitor 2084 of the capacitor bank 2040. In some embodiments, the voltage on the sampling capacitors 2087 and 2088 can then be reset by activating the transistor 2060 with the assertion signal PRE when the switches 2097 and 2098 are activated.

[0207] Next, the sum (S) stored in the sampling capacitors 2083 of the capacitor bank 2040 can be represented as (S A-0 V2)+(S A-0 (V4)+(S B-0 V2)+(S B-0 The sum of V4) added to the sampling capacitor 2084 stored in capacitor bank 2040 (representing (S) A-1 V2)+(S A-1 (V4)+(S B-1 V2)+(SB-1 V4) (e.g., by shorting sample capacitor 2083 and sample capacitor 2084 together via switch 2093 and switch 2094) to generate a first sum. The first sum can be read out from capacitor bank 2040 and sampled onto differential amplifier 2030. Then, the sum stored on sample capacitor 2081 of capacitor bank 2040 (representing (S A-0 V1) + (S A-0 V3) + (S B-0 V1) + (S B-0 V3)) can be added to the sum stored on sample capacitor 2082 of capacitor bank 2040 (representing (S A-1 V1) + (S A-1 V3) + (S B-1 V1) + (S B-1 V3)) (e.g., by shorting sample capacitor 2081 and sample capacitor 2082 together via switch 2091 and switch 2092) to generate a second sum. The second sum can be read out from capacitor bank 2040 and input into differential amplifier 2030. Then, differential amplifier 2030 can calculate the difference between the first and second sums and output the difference to the gate of source follower transistor 2097. Then, a signal corresponding to the difference can be read out from pixel 2000 via row select transistor 2010 to column readout circuitry 2020.

[0208] Although the steps of the method illustrated by table 2140 are discussed and illustrated in a particular order, the method is not limited thereto. In other embodiments, the method illustrated by table 2140 can be performed in a different order. In these and other embodiments, any of the steps of the method can be performed before, during, and / or after any of the other steps of the method. Moreover, the method illustrated by table 2140 can be altered and still remain within the scope of these and other embodiments of the technology. For example, in some embodiments, one or more steps of the method illustrated by table 2140 can be omitted and / or repeated. As another example, the order in which the particular ones of capacitors 2080-2089 of capacitor bank 2040 are used and / or the various signals / sums are stored into the particular ones of capacitors 2080-2089 can be different than that shown in Figure 21 and remain within the scope of the technology. Additionally or alternatively, the various calculations described with reference to Figure 21 may be altered and / or performed in a different order than that illustrated in Figure 22 .

[0209] Figure 1 is a partial schematic circuit diagram of another pixel 2200 and corresponding sample and hold circuitry 2220 each configured in accordance with various embodiments of the technology. Pixel 2200 is generally similar to pixel 2000, and like reference numbers are used to refer to like elements. In this example, sample and hold circuitry 2220 is configured to sample and hold the sum of the signals from the four sub-pixels of pixel 2200 (e.g., sub-pixel 2201, sub-pixel 2202, sub-pixel 2203, and sub-pixel 2204) onto sample capacitor 2221 of capacitor bank 2220. In this example, sample capacitor 2221 is configured to store the sum of the signals from the four sub-pixels of pixel 2200. In this example, the sum stored on sample capacitor 2221 is representative of (S Figure 22Pixel 100. Therefore, given the detailed discussion provided above, for the sake of brevity, a detailed discussion of the generally similar components between pixel 100 and pixel 2200 is omitted here. As shown, the sampling and holding circuit system 2220 includes multiple transistors and multiple sampling capacitors. For simplicity and clarity, in Figure 23 Only the connection between row select transistor 2210 and sample and hold circuitry 2220 is shown. A similar connection may be used between row select transistor 2209 and sample and hold circuitry 2220.

[0210] Figure 22 This describes the operation of various embodiments according to the present technology. Figure 22 The flowchart illustrates the method 2380 for pixel 2200 and the sampling and holding circuitry system 2220. Method 2350 is described as a series of steps or blocks. The block aligned on the left side of the page corresponds to the first tap of pixel 2200, and the block aligned on the right side of the page corresponds to the second tap of pixel 2200. All or a subset of any one or more of the blocks may be performed as described above.

[0211] Let's refer to each other. Figure 23 and 23 Method 2380 at block 2381 involves: (i) canceling the assertion applied to the reset signal RST of the reset transistor 2205; and (ii) setting the signal S... A-0 The reset signal section ( Figure 22 The sample (shown as "V1") is taken to the first sampling capacitor (e.g., in...). Figure 23 The sampling and holding circuit system 2220 begins by aligning the sampling capacitor marked A0 with the sampling capacitor marked R. At block 2382, method 2380 proceeds by passing the signal S... A-0 signal section ( Figure 22 The sample (shown as "V2") is sampled to the second sampling capacitor (e.g., in...). Figure 23 The sampling and holding circuit system 2220 continues on the sampling capacitor marked A0 and the sampling capacitor marked S. Figure 22 As shown in the diagram, method 2380 may additionally include a method for signal S. B-1 S A-0 and S B-0 Each of them performs steps largely similar to those in boxes 2381 and 2382. More specifically, during the first subframe and / or in the same or sequential timing, the signal S at the first tap of pixel 2200 can be... A-0 Execution boxes 2381 and 2382, and can target the signal S on the second tap of pixel 2200. B-1Perform steps largely similar to those in frames 2381 and 2382. Subsequently, during the second subframe and / or in the same or sequential timing sequence, the signal S at the first tap of pixel 2200 can be... A-1 Perform steps largely similar to those in boxes 2381 and 2382, and can target the signal S on the second tap of pixel 2200. B-0 Perform steps that are largely similar to those in boxes 2381 and 2382.

[0212] At box 2383, method 2380 calculates signal S. A-0 With signal S B-0 The sum continues. For example, stored separately in Figure 22 In the sampling and holding circuit system 2220, the sampling capacitors marked A0 and B0 are aligned with the sampling capacitor marked R on the S... A-0 and S B-0 The reset signal portions can be shorted together (e.g., by simultaneously activating the corresponding transistors in the sample-and-hold circuit system 2220), and S A-0 and S B-0 The sum of the reset signal portions can be read from the sample and hold circuit system 2220 to the column readout circuit system. Continuing this example, the S values ​​stored in the sample capacitors labeled A0 and B0 in the sample and hold circuit system 2220 are respectively stored on the sample capacitor labeled S. A-0 and S B-0 The signal portions can be shorted together (e.g., by simultaneously activating the corresponding transistors in the sample-and-hold circuit system 2220), and S A-0 and S B-0 The sum of the signals obtained from the sample and hold circuit system 2220 can be read from the column readout circuit system. Thereafter, the column circuit system can read the signals from S... A-0 and S B-0 The sum of the signal components minus S A-0 and S B-0 The sum of the reset signal portions is used to calculate signal S. A-0 With S B-0 The sum of .

[0213] At box 2384, method 2380 calculates signal S. A-1 With signal S B-1 The sum continues. For example, stored separately in CONCLUSION In the sampling and holding circuit system 2220, the sampling capacitors marked A1 and B1 are aligned with the sampling capacitor marked R on the S... A-1 and S B-1 The reset signal portions can be shorted together (e.g., by simultaneously activating the corresponding transistors in the sample-and-hold circuit system 2220), and SA-1 and the resulting sum of the signal portions of S B-1 and S A-1 may be shorted together (e.g., by simultaneously activating corresponding transistors of the sample-and-hold circuitry 2220), and the resulting sum of the signal portions of S B-1 and S A-1 may be read out from the sample-and-hold circuitry 2220 to the column readout circuitry. Thereafter, the column circuitry can calculate the signal S B-1 by subtracting the sum of the reset signal portions of S A-1 and S B-1 from the sum of the signal portions of S A-1 and S B-1 . A-1 and S B-1 .

[0214] In some embodiments, the column circuitry can additionally determine a signal light component captured by the pixel 2200 during a frame that deducts FPN (dark current FPN, ambient PLS, and pulsed signal PLS), and multiply by a sum of known camera gain factors / constants of the pixel 2200. For example, the column circuitry can determine the signal light component by subtracting (i) the sum of the signals S A-0 and S B-0 from (ii) the sum of the signals S A-1 and the signal S B-1 . Continuing this example, the signal light component can be represented by (signal S A-0 + signal S B-0 ) - (signal S A-1 + signal S B-1 ). The above process can be repeated for subsequent frames.

[0215] Although the steps of the method 2380 are discussed and illustrated in a particular order, the method 2380 is not limited thereto. In other embodiments, the method 2380 can be performed in a different order. In these and other embodiments, any of the steps of the method 2380 can be performed before, during, and / or after any of the other steps of the method 2380. Moreover, the method 2380 can be altered and still remain within the scope of these and other embodiments of the technology. For example, in some embodiments, one or more steps of the method 2380 can be omitted and / or repeated.

[0216] C. ​

[0217] The foregoing detailed description of embodiments of the technology has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology to the precise form disclosed. While the technology has been described with reference to particular embodiments and examples, a person of ordinary skill in the relevant art will appreciate that various equivalent modifications can be made to the technology without departing from the scope of the technology. For example, while steps are presented in a given order, alternative embodiments can perform steps in a different order. Additionally, various embodiments described herein can also be combined to provide other embodiments.

[0218] From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but well-known structures and functions have not been described in detail so as to not obscure the description of the embodiments of the technology. Any material incorporated by reference in the present document is to be taken as being incorporated in its entirety for all purposes as if fully set forth herein. To the extent that any material incorporated by reference conflicts with the present disclosure, the present disclosure controls. Where a singular or plural term is used herein, it is intended to include the plural or singular, respectively. Additionally, the use of “or” means “and / or” unless strictly used in a negative sense. Further, the use of “based on” means “based, at least in part, on,” unless otherwise noted. Moreover, the term “based on” is not exclusive as to other items that can be based on. For example, an exemplary step that is described as “based on condition A” can be based on both condition A and condition B, unless otherwise indicated. In other words, the phrase “based on” should be interpreted as “based, at least in part, on,” as the same as the phrase “based at least in part on.” Also, the terms “connected” and “coupled” are used herein interchangeably and mean both directly and indirectly connected or coupled. For example, in context, where element A is “connected” or “coupled” to element B, it can mean that A is either directly connected or directly coupled to B or that A is indirectly connected or indirectly coupled to B, as context permits.

[0219] It will be appreciated from the foregoing that various modifications can be made without departing from this disclosure or the technology. For example, it will be appreciated by those skilled in the art that various components of the technology can be further subdivided into subcomponents, or various components and functions of the technology can be combined and integrated. In addition, certain aspects of the technology described in the context of a particular embodiment can also be combined or eliminated in other embodiments. Moreover, while advantages associated with some embodiments of the technology have been described in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass a wide variety of embodiments.

Claims

1. A method for operating two-tap pixels to reduce fixed-pattern noise, the method comprising: During the first sub-exposure cycle of the frame The first tap of the two-tap pixel is operated to capture a first signal of a first charge corresponding to a first floating diffuser portion of the first tap, wherein operating the first tap includes activating a first transfer transistor of the first tap to transfer the first charge to the first floating diffuser portion, and wherein the first charge is generated by a photodetector of the two-tap pixel in response to first light incident on the photodetector. The second tap of the two tapped pixels is operated to capture the first parasitic signal of the fixed pattern noise FPN at the second floating diffuser corresponding to the second tap; and During the second sub-exposure cycle of the frame Operating the second tap to capture a second signal corresponding to a second charge at the second floating diffuser, wherein operating the second tap includes activating a second transfer transistor of the second tap to transfer the second charge to the second floating diffuser, and wherein the second charge is generated by the photodetector in response to second light incident on the photodetector. The first tap is operated to capture the second parasitic signal corresponding to the FPN at the first floating diffuser.

2. The method according to claim 1, wherein: The first light corresponds to one or more first light pulses incident on the photoelectric sensor; and The second light corresponds to one or more second light pulses incident on the photoelectric sensor.

3. The method according to claim 1, wherein: Operating the first tap of the two tap pixels during the first sub-exposure cycle to capture the first signal includes a first timing activation of the first transfer transistor corresponding to the time when the first light is incident on the photoelectric sensor; and Operating the second tap of the two tap pixels during the first sub-exposure cycle to capture the first parasitic signal includes activating the second transfer transistor in a second timing sequence different from the first timing sequence.

4. The method according to claim 3, wherein: During the second sub-exposure cycle, the second tap of the two tapped pixels is operated to capture the second signal, which includes a third timing activation of the second transfer transistor corresponding to the time when the second light is incident on the photosensitive sensor; and Operating the first tap of the two tap pixels during the second sub-exposure period to capture the second parasitic signal includes activating the first transfer transistor in a fourth timing sequence different from the third timing sequence.

5. The method of claim 1, further comprising using a correlated dual-sampling CDS to capture the first signal, the first parasitic signal, the second signal, the second parasitic signal, or any combination thereof.

6. The method according to claim 5, wherein: The method includes using a CDS to capture the first signal and the first parasitic signal; and The capture of the first signal and the first parasitic signal using CDS includes: The first and second floating diffusion sections are reset in the first timing sequence. Using the second timing sequence following the first timing sequence, the reference voltage of the first signal is sampled using the first tap, and the reference voltage of the first parasitic signal is sampled using the second tap. The first transfer transistor of the first tap is activated in the third timing sequence, and The signal voltage of the first signal is sampled using the first tap in the fourth timing sequence following the third timing sequence, and the signal voltage of the first parasitic signal is sampled using the second tap.

7. The method according to claim 6, wherein: The method includes using a CDS to capture the second signal and the second parasitic signal; and The capture of the second signal and the second parasitic signal using CDS includes: The first and second floating diffusion sections are reset in the fifth timing sequence. The reference voltage of the second signal is sampled using the second tap in a sixth timing sequence that is after the fifth timing sequence and different from the fourth timing sequence, and the reference voltage of the second parasitic signal is sampled using the first tap. The second transfer transistor of the second tap is activated in the seventh timing sequence, and The signal voltage of the second signal is sampled using the second tap in the eighth timing sequence following the seventh timing sequence, and the signal voltage of the second parasitic signal is sampled using the first tap.

8. The method according to claim 6, wherein: The method includes using a CDS to capture the second signal and the second parasitic signal; and The capture of the second signal and the second parasitic signal using CDS includes: The reference voltage of the second signal is sampled using the second tap in the fourth timing sequence, and the reference voltage of the second parasitic signal is sampled using the first tap. The second transfer transistor of the second tap is activated in the fifth timing sequence, and The signal voltage of the second signal is sampled using the second tap in the sixth timing sequence following the fifth timing sequence, and the signal voltage of the second parasitic signal is sampled using the first tap.

9. The method of claim 6, further comprising reading the signal voltage of the first signal and the signal voltage of the first parasitic signal from the two tap pixels during the second sub-exposure cycle.

10. The method of claim 1, further comprising using quad-sampling to capture the first signal, the first parasitic signal, the second signal, the second parasitic signal, or any combination thereof.

11. The method of claim 10, wherein: The method includes capturing the first signal and the first parasitic signal using quad-sampling; and The first signal and the first parasitic signal captured using quad-sampling include: The first reset noise voltage of the first signal is sampled using the first tap and the second tap is used to sample the first reset noise voltage of the first parasitic signal during the reset of the first and second floating diffusion sections, in a first timing sequence. The reference voltage of the first signal is sampled using the first tap in a second timing sequence, and the reference voltage of the first parasitic signal is sampled using the second tap. The first transfer transistor of the first tap is activated in the third timing sequence. In the fifth timing sequence following the fourth timing sequence, and while the first transfer transistor is not activated, the first tap is used to sample the signal voltage of the first signal, and the second tap is used to sample the signal voltage of the first parasitic signal. In the fifth timing sequence, when resetting the first and second floating diffusion sections, the first tap is used to sample the second reset noise voltage of the first signal, and the second tap is used to sample the second reset noise voltage of the first parasitic signal.

12. The method according to claim 11, wherein: The method includes using quad-sampling to capture the second signal and the second parasitic signal; and The second signal and the second parasitic signal were captured using quad-sampling, which included: Using a sixth timing sequence different from the fifth timing sequence, and sampling the first reset noise voltage of the second signal using the second tap and sampling the first reset noise voltage of the second parasitic signal using the first tap when resetting the first and second floating diffusion sections. The reference voltage of the second signal is sampled using the second tap in the seventh timing sequence, and the reference voltage of the second parasitic signal is sampled using the first tap. The second transfer transistor of the second tap is activated in the eighth timing sequence. Using the ninth timing sequence following the eighth timing sequence, and while the second transfer transistor is not activated, the second tap is used to sample the signal voltage of the second signal, and the first tap is used to sample the signal voltage of the second parasitic signal. The second tap is used to sample the second reset noise voltage of the second signal when resetting the first and second floating diffusion sections in the tenth timing sequence, and the first tap is used to sample the second reset noise voltage of the second parasitic signal.

13. The method according to claim 11, wherein: The method includes using quad-sampling to capture the second signal and the second parasitic signal; The second signal and the second parasitic signal were captured using quad-sampling, which included: The first reset noise voltage of the second signal is sampled using the second tap during the fifth timing sequence and when resetting the first and second floating diffusion sections, and the first reset noise voltage of the second parasitic signal is sampled using the first tap. The reference voltage of the second signal is sampled using the second tap in the sixth timing sequence, and the reference voltage of the second parasitic signal is sampled using the first tap. The second transfer transistor of the second tap is activated in the seventh timing sequence. In the eighth timing sequence following the seventh timing sequence, and when the second transfer transistor is not activated, the second tap is used to sample the signal voltage of the second signal, and the first tap is used to sample the signal voltage of the second parasitic signal. The second tap is used to sample the second reset noise voltage of the second signal when resetting the first and second floating diffusion sections in the ninth timing sequence, and the first tap is used to sample the second reset noise voltage of the second parasitic signal.

14. The method of claim 10, wherein: The method includes capturing the first signal and the first parasitic signal using quad-sampling; and The first signal and the first parasitic signal captured using quad-sampling include: The first reset noise voltage of the first signal is sampled using the first tap and the second tap is used to sample the first reset noise voltage of the first parasitic signal during the reset of the first and second floating diffusion sections, in a first timing sequence. The reference voltage of the first signal is sampled using the first tap and the reference voltage of the first parasitic signal is sampled using the second tap when the first transfer transistor is activated, in a second timing sequence. When the first transfer transistor is activated, the signal voltage of the first signal is sampled using the first tap in a third timing sequence, and the signal voltage of the first parasitic signal is sampled using the second tap. In the fourth timing sequence, when resetting the first and second floating diffusion sections, the first tap is used to sample the second reset noise voltage of the first signal, and the second tap is used to sample the second reset noise voltage of the first parasitic signal.

15. The method of claim 14, wherein: The method includes using quad-sampling to capture the second signal and the second parasitic signal; and The second signal and the second parasitic signal were captured using quad-sampling, which included: Using a fifth timing sequence different from the fourth timing sequence, and sampling the first reset noise voltage of the second signal using the second tap and sampling the first reset noise voltage of the second parasitic signal using the first tap when resetting the first and second floating diffusion sections. The reference voltage of the second signal is sampled using the second tap in the sixth timing sequence, when the second transfer transistor is activated, and the reference voltage of the second parasitic signal is sampled using the first tap. When the second transfer transistor is activated, the signal voltage of the second signal is sampled using the second tap in a seventh timing sequence, and the signal voltage of the second parasitic signal is sampled using the first tap. The second tap is used to sample the second reset noise voltage of the second signal when resetting the first and second floating diffusion sections in the eighth timing sequence, and the first tap is used to sample the second reset noise voltage of the second parasitic signal.

16. The method of claim 14, wherein: The method includes using quad-sampling to capture the second signal and the second parasitic signal; The second signal and the second parasitic signal were captured using quad-sampling, which included: In the fourth timing sequence, when resetting the first and second floating diffusion sections, the second tap is used to sample the first reset noise voltage of the second signal, and the first tap is used to sample the first reset noise voltage of the second parasitic signal. The reference voltage of the second signal is sampled using the second tap in the fifth timing sequence, when the second transfer transistor is activated, and the reference voltage of the second parasitic signal is sampled using the first tap. When the second transfer transistor is activated, the signal voltage of the second signal is sampled using the second tap in a sixth timing sequence, and the signal voltage of the second parasitic signal is sampled using the first tap. The second tap is used to sample the second reset noise voltage of the second signal when resetting the first and second floating diffusion sections in the seventh timing sequence, and the first tap is used to sample the second reset noise voltage of the second parasitic signal.

17. A method of operating an image sensor to reduce fixed-pattern noise, the image sensor comprising pixels having: (a) a photoelectric sensor; (b) a first tap comprising a first transfer transistor coupling a first charge storage region to the photoelectric sensor; and (c) a second tap: which includes a second transfer transistor coupling a second charge storage region to the photoelectric sensor, the method comprising: During the first sub-exposure cycle of the frame The first tap of the pixel is used to capture a first signal, wherein capturing the first signal includes activating the first transfer transistor such that (i) the first transfer transistor is activated in a first timing sequence corresponding to the time when the first light is emitted by the illuminator or the time when the second light is incident on the photosensor and (ii) a first charge corresponding to the first light or the second light is transferred from the photosensor to the first charge storage region via the first transfer transistor. The first parasitic signal is captured using the second tap of the pixel, the first parasitic signal corresponding to the fixed pattern noise FPN at the second charge storage region; and During the second sub-exposure cycle of the frame The second tap of the pixel is used to capture a second signal, wherein capturing the second signal includes activating the second transfer transistor such that (i) the second transfer transistor is activated at a second timing corresponding to the time when the third light is emitted by the illuminator or the time when the fourth light is incident on the photosensor and (ii) a second charge corresponding to the third light or the fourth light is transferred from the photosensor to the second charge storage region via the second transfer transistor, and The first tap of the pixel is used to capture a second parasitic signal, the second parasitic signal corresponding to the FPN at the first charge storage region.

18. The method of claim 17, further comprising: Determine the first difference between the first signal and the second parasitic signal; Determine the second difference between the second signal and the first parasitic signal; and Sum the first difference and the second difference.

19. The method of claim 17, wherein capturing the first parasitic signal comprises activating the second transfer transistor in a third timing sequence, the third timing sequence being (i) different from the first and second timing sequences and (ii) corresponding to the time when the first light is not emitted by the illuminator or the time when the second light is not incident on the photosensor.

20. The method of claim 19, wherein capturing the second parasitic signal comprises activating the first transfer transistor in a fourth timing sequence, the fourth timing sequence being (i) different from the first and second timing sequences and (ii) corresponding to the time when the third light is not emitted by the illuminator or the time when the fourth light is not incident on the photosensor.

21. The method of claim 17, wherein capturing the first signal, the first parasitic signal, the second signal, the second parasitic signal, or any combination thereof comprises capturing the first signal, the first parasitic signal, the second signal, the second parasitic signal, or any combination thereof using a correlated dual-sampling CDS.

22. The method of claim 21, wherein: The first tap of the pixel further includes a first reset transistor that selectively couples the first charge storage region to a known reference voltage; The second tap of the pixel further includes a second reset transistor that selectively couples the second charge storage region to the known reference voltage; Capturing the first signal and the first parasitic signal includes using a CDS to capture the first signal and the first parasitic signal respectively; Capturing the first signal using CDS includes: The first reset transistor is activated immediately. The first reset transistor is deactivated at the second time. The reference voltage of the first signal is sampled at the third time. The first transfer transistor is activated at the fourth time. The first transfer transistor is deactivated at the fifth time, and The signal voltage of the first signal is sampled at the sixth time; and Capturing the first parasitic signal using CDS includes: The second reset transistor is activated at the first time. The second reset transistor is deactivated at the second time. The reference voltage of the first parasitic signal is sampled at the third time, and The signal voltage of the first parasitic signal is sampled at the sixth time.

23. The method according to claim 22, wherein: The pixel further includes an overflow gate coupled to the photoelectric sensor; Capturing the first signal using CDS further includes sampling the reference voltage of the first signal and the signal voltage of the first signal when the overflow gate is activated; and Capturing the first parasitic signal using CDS further includes sampling the reference voltage of the first parasitic signal and the signal voltage of the first parasitic signal when the overflow gate is activated.

24. The method of claim 22, wherein: Capturing the second signal and the second parasitic signal includes using a CDS to capture the second signal and the second parasitic signal respectively; The second signal captured using CDS includes: The second reset transistor is activated at the seventh time. The second reset transistor is deactivated at the eighth time. The reference voltage of the second signal is sampled at a ninth time, which is after the eighth time and different from the sixth time. The second transfer transistor is activated at the tenth time. The second transfer transistor is deactivated at the eleventh time, and The signal voltage of the second signal is sampled at the twelfth time; and The second parasitic signal captured using CDS includes: The first reset transistor is activated at the seventh time. The first reset transistor is deactivated at the eighth time. The reference voltage of the second parasitic signal is sampled at the ninth time, and The signal voltage of the second parasitic signal is sampled at the twelfth time.

25. The method of claim 24, wherein: The pixel further includes an overflow gate coupled to the photoelectric sensor; The capture of the second signal using CDS further includes sampling the reference voltage of the second signal and the signal voltage of the second signal when the overflow gate is activated; and The capture of the second parasitic signal using CDS further includes sampling the reference voltage of the second parasitic signal and the signal voltage of the second parasitic signal when the overflow gate is activated.

26. The method according to claim 22, wherein: Capturing the second signal and the second parasitic signal includes using a CDS to capture the second signal and the second parasitic signal respectively; The second signal captured using CDS includes: The reference voltage of the second signal is sampled at the sixth time. The second transfer transistor is activated at the seventh time. The second transfer transistor is deactivated at the eighth time, and The signal voltage of the second signal is sampled at the ninth time; and The second parasitic signal captured using CDS includes: The reference voltage of the second parasitic signal is sampled at the sixth time, and The signal voltage of the second parasitic signal is sampled at the ninth time.

27. The method of claim 22, further comprising reading from the pixel the signal voltage of the first signal and the signal voltage of the first parasitic signal during the second sub-exposure period.

28. The method of claim 17, wherein capturing the first signal, the first parasitic signal, the second signal, the second parasitic signal, or any combination thereof comprises capturing the first signal, the first parasitic signal, the second signal, the second parasitic signal, or any combination thereof using quad-sampling.

29. The method according to claim 28, wherein: The first tap of the pixel further includes a first reset transistor that selectively couples the first charge storage region to a known reference voltage; The second tap of the pixel further includes a second reset transistor that selectively couples the second charge storage region to the known reference voltage; Capturing the first signal and the first parasitic signal involves using four samples to capture the first signal and the first parasitic signal respectively; The first signal captured using quad-sampling includes: The first reset transistor is activated immediately. The first reset noise voltage of the first signal is sampled at a second time and when the first reset transistor is activated. The first reset transistor is deactivated at the third time. The reference voltage of the first signal is sampled at the fourth time. The first transfer transistor is activated at the fifth time. The first transfer transistor is deactivated at the sixth time. The signal voltage of the first signal is sampled at the seventh time. The first reset transistor is activated at the eighth time, and The second reset noise voltage of the first signal is sampled at the ninth time and when the first reset transistor is activated; and The first parasitic signal captured using quad-sampling includes: The second reset transistor is activated at the first time. The first reset noise voltage of the first parasitic signal is sampled at the second time and when the second reset transistor is activated. The second reset transistor is deactivated at the third time. The reference voltage of the first parasitic signal is sampled at the fourth time. The signal voltage of the first parasitic signal is sampled at the seventh time. The second reset transistor is activated at the eighth time, and The second reset noise voltage of the first parasitic signal is sampled at the ninth time and when the second reset transistor is activated.

30. The method according to claim 29, wherein: The pixel further includes an overflow gate coupled to the photoelectric sensor; The use of quad-sampling to capture the first signal includes sampling the first reset noise voltage of the first signal, the reference voltage of the first signal, the signal voltage of the first signal, the second reset noise voltage of the first signal, or any combination thereof, when the overflow gate is activated; and The use of quad-sampling to capture the first parasitic signal involves sampling the first reset noise voltage of the first parasitic signal, the reference voltage of the first parasitic signal, the signal voltage of the first parasitic signal, the second reset noise voltage of the first parasitic signal, or any combination thereof, when the overflow gate is activated.

31. The method according to claim 29, wherein: Capturing the second signal and the second parasitic signal involves using four samples to capture the second signal and the second parasitic signal respectively; The second signal, captured using four samples, includes: The first reset noise voltage of the second signal is sampled at a tenth time, different from the ninth time, and when the second reset transistor is activated. The second reset transistor is deactivated at the eleventh time. The reference voltage of the second signal is sampled at the twelfth time. The second transfer transistor is activated at the thirteenth time. The second transfer transistor is deactivated at the fourteenth time. The signal voltage of the second signal is sampled at the fifteenth time point. The second reset transistor is activated at the sixteenth time. The second reset noise voltage of the second signal is sampled at the seventeenth time and when the second reset transistor is activated; and The second parasitic signal captured using quad-sampling includes: At the tenth time and when the first reset transistor is activated, the first reset noise voltage of the second parasitic signal is sampled. The first reset transistor is deactivated at the eleventh time. The reference voltage of the second parasitic signal is sampled at the twelfth time. The signal voltage of the second parasitic signal is sampled at the fifteenth time. The first reset transistor is activated at the sixteenth time, and At the seventeenth time and when the first reset transistor is activated, the second reset noise voltage of the second parasitic signal is sampled.

32. The method according to claim 31, wherein: The pixel further includes an overflow gate coupled to the photoelectric sensor; The second signal is captured using quad-sampling, which involves sampling the first reset noise voltage of the second signal, the reference voltage of the second signal, the signal voltage of the second signal, the second reset noise voltage of the second signal, or any combination thereof, when the overflow gate is activated; and The use of quad-sampling to capture the second parasitic signal involves sampling the first reset noise voltage of the second parasitic signal, the reference voltage of the second parasitic signal, the signal voltage of the second parasitic signal, the second reset noise voltage of the second parasitic signal, or any combination thereof, when the overflow gate is activated.

33. The method according to claim 29, wherein: Capturing the second signal and the second parasitic signal involves using four samples to capture the second signal and the second parasitic signal respectively; The second signal, captured using four samples, includes: The first reset noise voltage of the second signal is sampled at the ninth time. The second reset transistor is deactivated at the tenth time. The reference voltage of the second signal is sampled at the eleventh time. The second transfer transistor is activated at the twelfth time. The second transfer transistor is deactivated at the thirteenth time. The signal voltage of the second signal is sampled at the fourteenth time. The second reset transistor is activated at the fifteenth time. The second reset noise voltage of the second signal is sampled at the sixteenth time and when the second reset transistor is activated; and The second parasitic signal captured using quad-sampling includes: The first reset noise voltage of the second parasitic signal is sampled at the ninth time. The first reset transistor is deactivated at the tenth time. The reference voltage of the second parasitic signal is sampled at the eleventh time. The signal voltage of the second parasitic signal is sampled at the fourteenth time. The first reset transistor is activated at the fifteenth time, and The second reset noise voltage of the second parasitic signal is sampled at the seventeenth time and when the first reset transistor is activated.

34. The method according to claim 28, wherein: The first tap of the pixel further includes a first reset transistor that selectively couples the first charge storage region to a known reference voltage; The second tap of the pixel further includes a second reset transistor that selectively couples the second charge storage region to the known reference voltage; Capturing the first signal and the first parasitic signal involves using four samples to capture the first signal and the first parasitic signal respectively; The first signal captured using quad-sampling includes: The first reset transistor is activated immediately. The first transfer transistor is activated at the second time. The first reset noise voltage of the first signal is sampled at a third time, when the first reset transistor and the first transfer transistor are activated. The first reset transistor is deactivated at the fourth time. The reference voltage of the first signal is sampled at the fifth time and when the first transfer transistor is activated. The signal voltage of the first signal is sampled at the sixth time and when the first transfer transistor is activated. The first reset transistor is activated at the seventh time, and The second reset noise voltage of the first signal is sampled at the eighth time and when the first reset transistor and the first transfer transistor are activated; and The first parasitic signal captured using quad-sampling includes: The second reset transistor is activated at the first time. The first reset noise voltage of the first parasitic signal is sampled at the third time and when the second reset transistor is activated. The second reset transistor is deactivated at the fourth time. The reference voltage of the first parasitic signal is sampled at the fifth time point. The signal voltage of the first parasitic signal is sampled at the sixth time. The second reset transistor is activated at the seventh time, and The second reset noise voltage of the first parasitic signal is sampled at the eighth time and when the second reset transistor is activated.

35. The method according to claim 34, wherein: The pixel further includes an overflow gate coupled to the photoelectric sensor; The four-sample capture of the first signal includes sampling the first reset noise voltage of the first signal, the reference voltage of the first signal, the signal voltage of the first signal, the second reset noise voltage of the first signal, or any combination thereof, when the overflow gate is not activated; and The first parasitic signal is captured by four-sampling, which involves sampling the first reset noise voltage of the first parasitic signal, the reference voltage of the first parasitic signal, the signal voltage of the first parasitic signal, the second reset noise voltage of the first parasitic signal, or any combination thereof, when the overflow gate is not activated.

36. The method of claim 34, wherein: Capturing the second signal and the second parasitic signal involves using four samples to capture the second signal and the second parasitic signal respectively; The second signal, captured using four samples, includes: The second transfer transistor is activated at the ninth time. The first reset noise voltage of the second signal is sampled at the tenth time and when the second reset transistor and the second transfer transistor are activated. The second reset transistor is deactivated at the eleventh time. The reference voltage of the second signal is sampled at the twelfth time and when the second transfer transistor is activated. The signal voltage of the second signal is sampled at the thirteenth time and when the second transfer transistor is activated. The second reset transistor is activated at the fourteenth time, and The second reset noise voltage of the second signal is sampled at the fifteenth time and when the second reset transistor and the second transfer transistor are activated; and The second parasitic signal captured using quad-sampling includes: The first reset transistor is activated at the ninth time. At the tenth time and when the first reset transistor is activated, the first reset noise voltage of the second parasitic signal is sampled. The first reset transistor is deactivated at the eleventh time. The reference voltage of the second parasitic signal is sampled at the twelfth time. The signal voltage of the second parasitic signal is sampled at the thirteenth time. The first reset transistor is activated at the fourteenth time, and At the fifteenth time and when the first reset transistor is activated, the second reset noise voltage of the second parasitic signal is sampled.

37. The method of claim 36, wherein: The pixel further includes an overflow gate coupled to the photoelectric sensor; The second signal is captured using quad-sampling, which involves sampling the first reset noise voltage of the second signal, the reference voltage of the second signal, the signal voltage of the second signal, the second reset noise voltage of the second signal, or any combination thereof, when the overflow gate is not activated; and The second parasitic signal is captured by using quad sampling, which involves sampling the first reset noise voltage of the second parasitic signal, the reference voltage of the second parasitic signal, the signal voltage of the second parasitic signal, the second reset noise voltage of the second parasitic signal, or any combination thereof, when the overflow gate is not activated.

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