Semiconductor memory device manufacturing method
By using oxide and nitride spacers to define the character line metal layer in semiconductor memory devices, the problem of difficult signal routing is solved, enabling precise character line patterning and improving manufacturing efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2022-11-25
- Publication Date
- 2026-05-26
AI Technical Summary
As the complexity and number of integrated circuit components increase, efficient signal routing on devices becomes difficult, and existing technologies struggle to effectively connect and define circuit elements in semiconductor memory devices.
The character line metal layer is defined by oxide and nitride spacers surrounding a polysilicon pillar. The nitride spacers are formed using an atomic layer deposition process to precisely control the layer thickness, and the character line metal layer is precisely patterned using an enhanced self-aligned character line process.
It enables precise control of word line width, improves the manufacturing efficiency and quality of semiconductor memory devices, and enhances the reliability of signal connections.
Smart Images
Figure CN117641884B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing a semiconductor memory device. Background Technology
[0002] Integrated circuit (IC) devices (also known as semiconductor chips) can contain millions of transistors and other circuit elements fabricated on a single silicon crystal substrate (chip). For an IC device to function, a complex network of signal paths is typically routed to connect the circuit elements distributed across the device's surface. As the complexity and number of circuit elements increase, the efficient routing of these signals across the device becomes increasingly difficult. Summary of the Invention
[0003] This invention proposes an innovative method for manufacturing semiconductor memory devices, solving the problems of prior art.
[0004] In some embodiments of the present invention, a method for manufacturing a semiconductor memory device includes: sequentially forming a lower oxide layer, a word line metal layer, and an upper oxide layer over at least a portion of a memory cell; forming at least one via penetrating the upper oxide layer, the word line metal layer, and the lower oxide layer to expose the portion of the memory cell; forming at least one sacrificial pillar within the at least one via; removing the upper oxide layer to expose the top of the at least one sacrificial pillar; sequentially forming a first oxide sidewall, a nitride sidewall, and a second oxide sidewall on the sidewall of the top of the at least one sacrificial pillar; removing the nitride sidewall to form a void; and etching the word line metal layer through the void to form a plurality of separate word lines.
[0005] In some embodiments of the present invention, a method for manufacturing a semiconductor memory device includes: sequentially forming a lower oxide layer, a word line metal layer, and an upper oxide layer on the lower portion of a plurality of memory cells; forming a plurality of vias penetrating the upper oxide layer, the word line metal layer, and the lower oxide layer to expose the lower portion of the plurality of memory cells respectively; forming a plurality of sacrificial pillars in the plurality of vias respectively; removing the upper oxide layer to expose the tops of the plurality of sacrificial pillars; sequentially forming a plurality of first oxide sidewalls and a plurality of nitride sidewalls on the sidewalls of the tops of the plurality of sacrificial pillars; forming a plurality of second oxide sidewalls to fill a plurality of first gaps between adjacent pairs of the plurality of nitride sidewalls; removing the plurality of nitride sidewalls to form a plurality of second gaps; and etching the word line metal layer through the plurality of second gaps to form a plurality of separate word lines.
[0006] In some embodiments of the present invention, a nitride sidewall is disposed between a first oxide sidewall and a second oxide sidewall.
[0007] In some embodiments of the present invention, the first oxide sidewall is disposed between the nitride sidewall and the sidewall at the top of the sacrificial column.
[0008] In some embodiments of the present invention, the nitride sidewalls are formed using an atomic layer deposition process.
[0009] In some embodiments of the present invention, the character line metal layer comprises tungsten.
[0010] In some embodiments of the present invention, the sacrificial pillar comprises polycrystalline silicon.
[0011] In some embodiments of the invention, the method further includes removing a portion of the sacrificial pillar to expose a portion of the memory cell, and forming another portion of the memory cell to connect to that portion.
[0012] In some embodiments of the invention, the method further includes removing the sacrificial pillar to expose the lower portion of the memory cell and forming the upper portion of the memory cell to connect the lower portion of the memory cell.
[0013] In some embodiments of the present invention, the memory cell includes an indium gallium zinc oxide layer.
[0014] In some embodiments of the present invention, the memory cell includes an indium gallium zinc oxide layer disposed between two indium tin oxide layers.
[0015] In some embodiments of the present invention, the character line metal layer is formed to have a thickness in the range of 40 nanometers to 50 nanometers.
[0016] In some embodiments of the present invention, the character line metal layer is formed to have a thickness of 46 nanometers.
[0017] In some embodiments of the invention, each of the plurality of nitride sidewalls is disposed between an adjacent first oxide sidewall and an adjacent second oxide sidewall.
[0018] In some embodiments of the invention, each of the plurality of first oxide sidewalls is disposed between the adjacent nitride sidewall and the adjacent top sidewall of the sacrificial column.
[0019] In summary, the semiconductor memory device manufacturing method disclosed in this case uses oxide and nitride spacers surrounding polysilicon pillars to define the word line metal layer. Nitride spacers can be formed using atomic layer deposition processes to precisely control the layer thickness. Enhanced self-aligned word line processes utilize spacers of different materials to precisely pattern the word line metal layer to form multiple word lines with balanced widths.
[0020] The above description will be given in detail below with reference to the embodiments, and a further explanation of the technical solution of the present invention will be provided. Attached Figure Description
[0021] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:
[0022] Figures 1 to 19 A partial cross-sectional view illustrating the manufacturing steps of a semiconductor memory device according to some embodiments of the present invention; and
[0023] Figure 20 To illustrate some embodiments of the invention and Figure 19 The associated top view. Detailed Implementation
[0024] To provide a more detailed and complete description of the invention, reference can be made to the accompanying drawings and the various embodiments described below, in which the same numbers represent the same or similar elements. Furthermore, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention.
[0025] Please refer to Figure 1 This diagram illustrates a partial cross-sectional view of a first manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A lower oxide layer 112 is formed on the lower portion of the memory cell and on the top surface of the nitride layer 104. In some embodiments of the present invention, the lower oxide layer 112 may be formed to have a thickness of approximately 30 nanometers. In some embodiments of the present invention, the lower oxide layer 112 may be a silicon oxide layer. In some embodiments of the present invention, the lower oxide layer 112 may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, and hafnium oxide. Other possible oxides include barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, and lead scandium tantalum oxide. In some embodiments of the present invention, the lower oxide layer 112 may be deposited by any suitable method, such as CVD or plasma-enhanced CVD (PECVD).
[0026] A nitride layer 104 is formed on and in contact with the top surface of the oxide layer 102. In some embodiments of the present invention, the nitride layer 104 may be a silicon nitride layer formed in contact with the top surface of the oxide layer 102. In some embodiments of the present invention, the nitride layer 104 may be deposited by any suitable method, such as CVD or plasma-enhanced CVD (PECVD).
[0027] An etching process can be performed in the oxide layer 102 and the nitride layer 104 to form a plurality of vias. A lower portion of a memory cell is formed within each via. The lower portion of the memory cell may include a polysilicon layer 106 and a bottom indium tin oxide layer 108 in contact with the top surface of the polysilicon layer 106. Dielectric sidewalls 110 may be formed to surround the sidewalls of the lower portion of each memory cell. In some embodiments of the invention, the dielectric sidewalls 110 may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, and lead scandium tantalum oxide. In some embodiments of the invention, the bottom indium tin oxide layer 108 may be deposited by any suitable method, such as PVD or plasma-enhanced PVD.
[0028] Please refer to Figure 2 This diagram illustrates a partial cross-sectional view of a second manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A lower oxide layer 112 is formed on the lower portion of the memory cell and on the top surface of the nitride layer 104. In some embodiments of the present invention, the lower oxide layer 112 may be formed to have a thickness of approximately 30 nanometers. In some embodiments of the present invention, the lower oxide layer 112 may be a silicon oxide layer. In some embodiments of the present invention, the lower oxide layer 112 may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, hafnium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, and lead scandium tantalum oxide. In some embodiments of the present invention, the lower oxide layer 112 may be deposited by any suitable method, such as CVD or plasma-enhanced CVD (PECVD).
[0029] A patterned character line metal layer 114 is formed above the lower oxide layer 30. In some embodiments of the invention, the metal layer 114 may be formed of tungsten (W) and have a thickness ranging from about 40 nanometers to about 50 nanometers. In some embodiments of the invention, the metal layer 114 may be formed of tungsten (W) and have a thickness of about 46 nanometers. In some embodiments of the invention, the metal layer 114 may be formed using metals and / or metal alloys, such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), ruthenium (Ru), platinum (Pt), and alloys thereof.
[0030] An upper oxide layer 116 is then formed over the metal layer 114. In some embodiments of the invention, the lower oxide layer 112 may be formed to have a thickness of about 60 nanometers. In some embodiments of the invention, the upper oxide layer 116 may be a silicon oxide layer. In some embodiments of the invention, the upper oxide layer 116 may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, hafnium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, and lead scandium tantalum oxide. In some embodiments of the invention, the upper oxide layer 116 may be deposited by any suitable method, such as CVD or plasma-enhanced CVD (PECVD). The metal layer 114 is sandwiched between the lower oxide layer 112 and the upper oxide layer 116 to form a stack.
[0031] Please refer to Figure 3 The diagram illustrates a partial cross-sectional view of a third manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A trench etching process is performed to form vias 118 in the stack of an upper oxide layer 116, a metal layer 114, and a lower oxide layer 112 to expose the top of the lower portion of the memory cell, namely the bottom indium tin oxide layer 108.
[0032] Please refer to Figure 4 The diagram illustrates a partial cross-sectional view of the fourth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A sacrificial polysilicon layer 120 is deposited on the upper oxide layer 116 and filled into the via 118.
[0033] Please refer to Figure 5 The diagram illustrates a partial cross-sectional view of the fifth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A planarization process, such as chemical mechanical polishing, may be performed to remove excess polysilicon material and to form polysilicon pillars 120a in vias 118. The bottom of each polysilicon pillar 120a contacts the top of the lower portion of the memory cell, i.e., the bottom indium tin oxide layer 108.
[0034] Please refer to Figure 6 The diagram illustrates a partial cross-sectional view of the sixth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. An etching process is performed to remove the upper oxide layer 116 and expose the top surface of the metal layer 114 and the top 120b of the polysilicon pillar 120a.
[0035] Please refer to Figure 7This diagram illustrates a partial cross-sectional view of the seventh manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A spacer oxide layer 122 is deposited to cover all exposed surfaces of the metal layer 114 and the top 120b of the polysilicon pillar 120a. In some embodiments of the present invention, the spacer oxide layer 122 may be formed to have a thickness of about 5 nanometers to about 10 nanometers. In some embodiments of the present invention, the spacer oxide layer 122 may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD).
[0036] Please refer to Figure 8 The diagram illustrates a partial cross-sectional view of the eighth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. An etching process is performed to remove a portion of the spacer oxide layer 122 above the metal layer 114 and above the top surface of the top 120b of the polysilicon pillar 120a, such that oxide sidewalls 122a remain on the sidewalls of the top 120b of the polysilicon pillar 120a.
[0037] Please refer to Figure 9 This diagram illustrates a partial cross-sectional view of the ninth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A spacer nitride layer 124 is deposited to cover all exposed surfaces of the oxide sidewalls 122a, the metal layer 114, and the top 120b of the polysilicon pillar 120a. In some embodiments of the present invention, the spacer nitride layer 124 may be formed using an atomic layer deposition process to precisely control the layer thickness. In some embodiments of the present invention, the spacer nitride layer 124 may comprise silicon nitride.
[0038] Please refer to Figure 10 This diagram illustrates a partial cross-sectional view of the tenth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. An etching process is performed to remove a portion of the spacer nitride layer 124 on the top surface of the metal layer 114 and the top 120b of the polysilicon pillar 120a, such that nitride sidewalls 124a remain on the oxide sidewalls 122a and the sidewalls of the top 120b of the polysilicon pillar 120a. Each oxide sidewall 122a is located between its adjacent nitride sidewall 124a and its adjacent top 120b of the polysilicon pillar 120a.
[0039] Please refer to Figure 11This diagram illustrates a partial cross-sectional view of the eleventh fabrication step of a semiconductor memory device according to some embodiments of the present invention. An oxide layer 126 is deposited in the void between two adjacent nitride sidewalls 124a. The oxide layer 126 may be referred to as another oxide sidewall. Each nitride sidewall 124a is sandwiched between an adjacent oxide layer 126 and an oxide sidewall. A planarization process, such as chemical mechanical polishing, may be performed to remove excess oxide material. In some embodiments of the invention, the oxide layer 126 and the oxide sidewalls 122a may be made of the same or substantially the same oxide material. In some embodiments of the invention, the oxide layer 126 may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD).
[0040] Please refer to Figure 12 The diagram illustrates a partial cross-sectional view of the twelfth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A carbon layer 128 is deposited on the polished top surface of a polysilicon pillar 120a, a nitride sidewall 124a, an oxide layer 126, and an oxide sidewall 122a.
[0041] Please refer to Figure 13 The diagram illustrates a partial cross-sectional view of the thirteenth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A photoresist layer 130 is deposited on a carbon layer 128 and patterned by a photolithography process to form an opening 130a. An etching process is performed using the patterned photoresist layer 130 as a shield to pattern the carbon layer 128. Each opening 130a is aligned with a corresponding underlying nitride sidewall 124a and is used to expose the corresponding nitride sidewall 124a.
[0042] Please refer to Figure 14 This diagram illustrates a partial cross-sectional view of the fourteenth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A patterned carbon layer 128 is used as a shield to perform a further etching process to remove nitride sidewalls 124a. After removing the nitride sidewalls 124a, the remaining photoresist layer 130 and carbon layer 128 are also removed. A void 132 is formed between adjacent oxide layers 126 and oxide sidewalls 122a.
[0043] Please refer to Figure 15 This diagram illustrates a partial cross-sectional view of the fifteenth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. An etching process is performed using the remaining oxide layer 126 and the remaining oxide sidewalls 122a as a shield to pattern the metal layer 114, i.e., to form gaps 132 to define separate character lines 114a.
[0044] Please refer to Figure 16This diagram illustrates a partial cross-sectional view of the sixteenth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. An oxide layer 134 is deposited on the remaining oxide layer 126 and the remaining oxide sidewalls 122a, and fills the voids 132 between word lines 114a (see also...). Figure 15 In some embodiments of this disclosure, oxide layer 134, oxide layer 126, and oxide sidewall 122a may be made of the same or substantially the same oxide material, such that... Figures 16-19 Interfaces of all oxide material layers (e.g., 134, 126, 122a) are not shown. In some embodiments of the invention, oxide layer 134 can be deposited by any suitable method, such as CVD or plasma-enhanced CVD (PECVD).
[0045] Please refer to Figure 17 The diagram illustrates a partial cross-sectional view of the seventeenth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. A planarization process, such as chemical mechanical polishing, may be performed to remove excess oxide material from the oxide layer 134 until the top 120b of the polysilicon pillar 120a is exposed.
[0046] Please refer to Figure 18 The diagram illustrates a partial cross-sectional view of the eighteenth manufacturing step of a semiconductor memory device according to some embodiments of the present invention. An etching process is performed to remove the polysilicon pillar 120a without removing the oxide material surrounding the polysilicon pillar 120a to form openings 136. The top of the lower portion of the memory cell (i.e., the bottom indium tin oxide layer 108) is exposed at the bottom of each opening 136.
[0047] Please refer to Figures 19-20 , Figure 20 Illustrations of some embodiments according to this disclosure and Figure 19 The associated partial top view, and Figure 19 The diagram shows the route along Figure 20A partial cross-sectional view taken by lines 19-19. The upper portion of each memory cell 140 is formed in each opening 136. The upper portion of each memory cell 140 includes an indium gallium zinc oxide (IGZO) layer 141, a top indium tin oxide (ITO) layer 144, and a landing pad 146. The ITO layer 141 is sandwiched between a bottom ITO layer 108 and a top ITO layer 144. A gate oxide layer 142 is formed as a sidewall surrounding the ITO layer 141 and serves to separate the ITO layer 141 from the corresponding word line 114a. In some embodiments of this disclosure, the top ITO layer 144 may be deposited by any suitable method, such as PVD or plasma-enhanced PVD. In some embodiments of the invention, the gate oxide layer 142 may be a silicon oxide layer. In some embodiments of the present invention, the gate oxide layer 142 may include at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, hafnium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, and lead scandium tantalum oxide. In some embodiments of this disclosure, the landing pad 146 may be formed using metals and / or metal alloys, such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), ruthenium (Ru), tungsten (W), platinum (Pt), and alloys thereof. In some embodiments of this disclosure, the bonding landing pad 146 may be deposited by any suitable method, such as PVD or plasma-enhanced PVD.
[0048] In summary, the semiconductor memory device manufacturing method disclosed in this case uses oxide spacers and nitride spacers surrounding polysilicon pillars to define word line metal layers. Nitride spacers can be formed using atomic layer deposition processes to precisely control layer thickness. Enhanced self-aligned word line processes utilize spacers of different materials to precisely pattern the word line metal layers to form multiple word lines with balanced widths.
[0049] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0050] [Symbol Explanation]
[0051] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the appended symbols are explained as follows:
[0052] 102: Oxide layer
[0053] 104: Nitride layer
[0054] 106: Polycrystalline silicon layer
[0055] 108: Bottom Indium Tin Oxide Layer
[0056] 110: Dielectric sidewall
[0057] 112: Lower oxide layer
[0058] 114: Metal layer
[0059] 114a: Character Line
[0060] 116: Upper oxide layer
[0061] 118: Through hole
[0062] 120: Sacrificial polysilicon layer
[0063] 120a: Polycrystalline silicon pillar
[0064] 120b: Top
[0065] 122: Spacer oxide layer
[0066] 122a: Oxide sidewall
[0067] 124: Spacer nitride layer
[0068] 124a: Nitride sidewall
[0069] 126: Oxide layer
[0070] 128: Carbon layer
[0071] 130: Photoresist layer
[0072] 130a: Opening
[0073] 132: Gap
[0074] 134: Oxide layer
[0075] 136: Opening
[0076] 140: Memory Unit
[0077] 141: Indium gallium zinc oxide layer
[0078] 142: Gate oxide layer
[0079] 144: Top Indium Tin Oxide Layer
[0080] 146: Landing pad.
Claims
1. A method of manufacturing a semiconductor memory device, characterized by, Include: A lower oxide layer, a word line metal layer, and an upper oxide layer are sequentially formed on at least a portion of a memory cell; At least one via is formed through the upper oxide layer, the word line metal layer and the lower oxide layer to expose that portion of the memory cell; At least one sacrificial column is formed within the at least one through hole; Remove the upper oxide layer to expose the top of at least one sacrificial column; A first oxide sidewall, a nitride sidewall, and a second oxide sidewall are sequentially formed on the sidewall of the top of the at least one sacrificial column; Remove the nitride sidewalls to create voids; and The character line metal layer is etched through the gap to form multiple separate character lines.
2. The method of claim 1, wherein the nitride sidewall is disposed between the first oxide sidewall and the second oxide sidewall.
3. The method of claim 1, wherein the first oxide sidewall is disposed between the nitride sidewall and the sidewall of the top of the at least one sacrificial column.
4. The method according to claim 1, wherein the nitride sidewall is formed using an atomic layer deposition process.
5. The method of claim 1, wherein the character line metal layer comprises tungsten.
6. The method of claim 1, wherein the at least one sacrificial pillar comprises polycrystalline silicon.
7. The method according to claim 1, wherein, Also includes: Remove at least one sacrificial pillar to expose that portion of the memory cell; and This forms another part of the memory cell to connect to that part of the memory cell.
8. The method of claim 7, wherein the memory cell comprises an indium gallium zinc oxide layer.
9. The method of claim 7, wherein the memory cell comprises an indium gallium zinc oxide layer disposed between two indium tin oxide layers.
10. The method of claim 1, wherein the character line metal layer is formed to have a thickness in the range of 40 nanometers to 50 nanometers.
11. A method for manufacturing a semiconductor memory device, characterized in that, Include: A lower oxide layer, a word line metal layer, and an upper oxide layer are sequentially formed on the lower part of multiple memory cells; Multiple vias are formed to penetrate the upper oxide layer, the character line metal layer, and the lower oxide layer, so as to expose the lower part of the multiple memory cells respectively; Multiple sacrificial pillars are formed within the multiple through holes respectively; Remove the upper oxide layer to expose the tops of the multiple sacrificial pillars; Multiple first oxide sidewalls and multiple nitride sidewalls are sequentially formed on the sidewalls at the top of the multiple sacrificial pillars; Multiple second oxide sidewalls are formed to fill multiple first voids between adjacent nitride sidewalls; Remove the multiple nitride sidewalls to form multiple second voids; as well as The character line metal layer is etched through the multiple second gaps to form multiple separate character lines.
12. The method of claim 11, wherein each of the plurality of nitride sidewalls is disposed between an adjacent first oxide sidewall and an adjacent second oxide sidewall.
13. The method of claim 11, wherein each of the plurality of first oxide sidewalls is disposed between an adjacent nitride sidewall and an adjacent sidewall of the top of the sacrificial column.
14. The method of claim 11, wherein the plurality of nitride sidewalls are formed using an atomic layer deposition process.
15. The method of claim 11, wherein the character line metal layer comprises tungsten.
16. The method of claim 11, wherein the plurality of sacrificial pillars comprise polycrystalline silicon.
17. The method according to claim 11, wherein, Also includes: Remove the plurality of sacrificial pillars to expose the lower portion of the plurality of memory cells; and The upper part of the plurality of memory cells is formed to connect the lower part of the plurality of memory cells.
18. The method of claim 11, wherein each of the plurality of memory cells comprises an indium gallium zinc oxide layer.
19. The method of claim 11, wherein each of the plurality of memory cells includes an indium gallium zinc oxide layer disposed between two indium tin oxide layers.
20. The method of claim 11, wherein the character line metal layer is formed to have a thickness of 46 nanometers.