Coordinate Image Cache System

Abstract

The present invention relates to the field of industrial automation technology, and in particular to a coordinate image cache system for an extreme ultraviolet camera, comprising an FPGA module, an image uplink / image downlink interface circuit and an SRAM memory, wherein the image uplink interface circuit is used to read out the minimum unit uplink data of the coordinate image by line, a cycle counter is used for counting, an image receiving FIFO is used for caching the coordinate position of the minimum unit uplink data by line, an SRAM control right switch is used for switching control rights, an image cache state machine is used for uplinking the minimum unit uplink data by line, an SRAM memory is used for storing the minimum unit uplink data of the coordinate image by line, an image downlink state machine is used for downlinking the minimum unit downlink data by line, an image downlink FIFO is used for caching the minimum unit downlink data by line, and an image downlink interface circuit is used for outputting the minimum unit downlink data by line. The present invention can simultaneously write and read the image data of the coordinate image.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial automation, and in particular to a coordinate image cache system. Background Art

[0002] The image captured by the extreme ultraviolet camera is a coordinate image. The initial image can be imagined as a whiteboard with a coordinate image of row resolution × column resolution. The initial value of each pixel is 0. When the image data is received, the cache data corresponding to the coordinate of the image data is read out and added by one, and then the image data is written back. When the exposure time of the extreme ultraviolet camera is reached, the entire coordinate image is read out from the cache and a coordinate image is written down. At present, the cache of the coordinate image requires two independent SRAM memories or only one SRAM memory is expanded on the FPGA module. The expansion of the two SRAM memories is to perform ping-pong writing on the two SRAM memories, that is, write the image data to one of the SRAM memories and read the image data from the other SRAM memory. When an SRAM memory is expanded on the FPGA module, the writing and reading of the image data cannot be performed at the same time, which is not conducive to the integration of the circuit. Summary of the invention

[0003] In order to solve the disadvantage in the prior art that multiple chips are required to simultaneously write and read image data of a coordinate image, which is not conducive to circuit integration, the present invention provides a coordinate image cache system for an extreme ultraviolet camera. Only one SRAM memory is expanded in an FPGA module to realize simultaneous writing and reading of image data of the coordinate image, which is conducive to circuit integration and reduces circuit size and power consumption.

[0004] The coordinate image caching system for an extreme ultraviolet camera proposed in the present invention comprises an FPGA module, and an image uplink interface circuit, an image downlink interface circuit and an SRAM memory extended on the FPGA module. The FPGA module comprises a controller, an image receiving FIFO, an image downlink FIFO, a cycle counter, a clock counter, an SRAM control right switch, an image caching state machine and an image downlink state machine, wherein:

[0005] The controller is used to control the image receiving FIFO, the image downlink FIFO, the cycle counter, the clock counter, the SRAM control right switch, the image buffer state machine, the image downlink state machine, the image uplink interface circuit, the image downlink interface circuit and the SRAM memory;

[0006] The clock counter is used to perform counting operations according to the reset initialization instruction issued by the controller, and restart counting when the count value of the clock counter is the same as the exposure time of the coordinate image. The cycle counter is used to perform counting operations according to the reset initialization instruction issued by the controller, and restart counting after reaching the maximum count value. The image uplink interface circuit is used to input the minimum unit uplink data of the coordinate image to the image receiving FIFO row by row. The image receiving FIFO is used to cache the coordinate position of the minimum unit uplink data row by row. The SRAM control right switcher is used to switch the control right of the image cache state machine or the image downlink state machine according to the counting range of the cycle counter. The image cache state machine is used to read out the coordinate position of the minimum unit uplink data bit by bit in the corresponding position of the uplink area of ​​the SRAM memory. The uplink area of ​​the SRAM memory is used to write the minimum unit uplink data bit by bit until the coordinate image is completely written into the uplink area of ​​the SRAM memory.

[0007] The image downlink state machine is used to store the minimum unit downlink data of the coordinate image in the downlink area of ​​the downlink SRAM memory row by row, the image downlink FIFO is used to cache the minimum unit downlink data stored in the downlink area of ​​the SRAM memory row by row, and the image downlink interface circuit is used to output the minimum unit downlink data cached by the image downlink FIFO row by row.

[0008] Preferably, the uplink data rate of the minimum unit uplink data of the coordinate image is determined according to the maximum data rate of the SRAM memory for image uplink; and the downlink data rate of the minimum unit downlink data of the coordinate image is determined according to the maximum data rate of the SRAM memory for image downlink.

[0009] Preferably, assuming that the clock cycle of the FPGA is T, the maximum count value of the cycle counter is X max :

[0010] X max =X1+X2(1);

[0011] Among them, X1>X in , X in =T in / T,X in The number of clocks required to perform an uplink processing of the minimum unit of uplink data, T in The time required to perform the uplink processing of the minimum unit of uplink data, X2>X out , X out =T out / T,X out The number of clocks required to perform a downlink processing of the minimum unit of downlink data, T out It is the time required to perform downlink processing of the minimum unit of downlink data.

[0012] Preferably, when the counting range of the cycle counter is 0 to (X1-1), the SRAM control right switcher switches the control right to the image cache state machine;

[0013] When the counting range of the cycle counter is X1~X max , the SRAM control switch switches the control to the image downlink state machine.

[0014] Preferably, the uplink bandwidth V of the coordinate image inmax :

[0015] V inmax =V max ×X1 / X max (2);

[0016] Among them, V inmax >2V in , V in The maximum data rate required to perform uplink processing of the minimum unit of uplink data, V max The maximum uplink / downlink data rate of the SRAM memory;

[0017] Coordinate image downlink bandwidth V outmax :

[0018] V outmax =V max ×X2 / X max (3);

[0019] Among them, V outmax >2V out , V out The maximum data rate required to perform downlink processing of the minimum unit of downlink data.

[0020] Preferably, if the upper and lower half area set flags issued by the controller are "0", the upper storage area of ​​the SRAM memory is the upstream area, and the lower storage area of ​​the SRAM memory is the downstream area; if the upper and lower half area set flags issued by the controller are "1", the lower storage area of ​​the SRAM memory is the upstream area, and the upper storage area of ​​the SRAM memory is the downstream area.

[0021] The coordinate image caching method for an extreme ultraviolet camera proposed in the present invention is implemented using a coordinate image caching system and specifically includes the following steps:

[0022] S1: Build a coordinate image cache system;

[0023] S2: The coordinate image cache system is powered on, and the SRAM memory is cleared according to the set initialization instruction issued by the controller;

[0024] S3: The cycle counter and clock counter start counting after receiving the set initialization instruction, and the controller sends the upper and lower half zone set flag "0";

[0025] S4: the image uplink interface circuit inputs the minimum unit uplink data of the coordinate image to the image receiving FIFO line by line, and the controller determines whether the buffer area of ​​the image receiving FIFO is full, if not, executes step S5, if full, executes step S6;

[0026] S5: When the counting time of the clock counter is equal to the exposure time of the extreme ultraviolet camera, query the controller to see whether it has issued an "exposure time has expired" instruction. If so, flip the upper and lower half-area setting flags to make the clock counter restart counting and then execute step S4; otherwise, directly execute step S4;

[0027] S6: The controller sends a write instruction to the image buffer state machine, and the image buffer state machine controls the image receiving FIFO to write the minimum unit uplink data into the uplink area of ​​the SRAM memory in sequence bit by bit;

[0028] S7: after a row of minimum unit upstream data is written into the upstream area of ​​the SRAM memory, step S5 is executed until all coordinate images are written into the upstream area of ​​the SRAM memory;

[0029] S8: The controller queries whether the coordinate image is fully written in the upstream area of ​​the SRAM memory, and if so, executes step S9, otherwise, executes step S4;

[0030] S9: Check whether the controller issues a "data cacheable" instruction, if so, execute step S10, otherwise enter a waiting state;

[0031] S10: The controller inputs a downlink instruction to the image downlink state machine, and the image downlink state machine controls the image downlink FIFO to cache the minimum unit downlink data of the coordinate image stored in the downlink area of ​​the SRAM memory in rows;

[0032] S11: After reading out a row of minimum unit downstream data from the downstream area of ​​the SRAM memory, repeat step S9 until all coordinate images stored in the downstream area of ​​the SRAM memory are read out, then clear the downstream area of ​​the SRAM memory and return to step S8.

[0033] Preferably, step S6 specifically includes the following steps:

[0034] S61: When the SRAM control right switcher switches the control right to the image cache state machine and the count value of the cycle counter is 0, the image receiving FIFO reads the coordinate position of a pixel point, and the controller determines whether the coordinate position of the pixel point is in the upstream area of ​​the SRAM memory. If so, step S62 is executed, otherwise, step S63 is executed;

[0035] S62: Map the corresponding position of the coordinate position of the pixel point in the upstream area of ​​the SRAM memory, read the pixel point at the corresponding position and add 1, and write the coordinate position of the pixel point read by the image receiving FIFO into the corresponding position;

[0036] S63: adding 1 to the count value of the controller's write image data counter, and repeating step S61 until the count value of the write image data counter is equal to the pixel value of the coordinate image.

[0037] Preferably, step S10 specifically includes the following steps:

[0038] S101: The controller calculates the address to be downloaded in the downstream area of ​​the SRAM memory;

[0039] S102: When the SRAM control right switcher switches the control right to the image downlink state machine and the count value of the cycle counter is X1, the image downlink FIFO caches the minimum unit downlink data corresponding to the downlink address according to the calculation result of step S101;

[0040] S103: the count value of the image pixel counter of the controller is increased by 1, and it is determined whether the count value of the image pixel counter is equal to the pixel value of the minimum unit downlink data. If so, step S104 is executed, otherwise, step S102 is executed;

[0041] S104: the count value of the image row counter of the controller is increased by 1, and it is determined whether the count value of the image row counter is the same as the total number of rows in the downstream area of ​​the SRAM memory. If so, step S105 is executed, otherwise, step S101 is executed;

[0042] S105: Clear the downstream area of ​​the SRAM memory and execute step S8.

[0043] Preferably, step S105 specifically includes the following steps:

[0044] S1051: The controller issues a clear instruction and calculates the address to be cleared in the downstream area of ​​the SRAM memory;

[0045] S1052: When the SRAM control right switcher switches the control right to the image downlink state machine and the count value of the cycle counter is X1, the controller clears the pixel points at the address to be cleared;

[0046] S1053: The count value of the reset counter of the controller is increased by 1, and it is determined whether the count value of the reset counter is the same as the total number of rows in the downstream area of ​​the SRAM memory. If so, step S8 is executed, otherwise step S1051 is executed.

[0047] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0048] The present invention can realize simultaneous writing and reading of image data of a coordinate image by only expanding one SRAM memory on the FPGA module, which effectively reduces the number of chips used and the number of FPGA expansion IOs compared to the prior art, effectively saves the hardware resources of the circuit, is conducive to the integration of the circuit, and reduces the power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a schematic structural diagram of a coordinate image caching system for an extreme ultraviolet camera provided according to an embodiment of the present invention;

[0050] Figure 2 is a schematic diagram of the structure of timeline polling provided according to an embodiment of the present invention;

[0051] Figure 3 is a schematic diagram of the working process of a cycle counter provided according to an embodiment of the present invention;

[0052] Figure 4 is a schematic diagram of control right management of an SRAM control right switch provided by an embodiment of the present invention;

[0053] Figure 5 It is a flow chart of a coordinate image caching method for an extreme ultraviolet camera provided according to an embodiment of the present invention.

[0054] Figure numerals: FPGA module 1, image uplink interface circuit 2, image downlink interface circuit 3, SRAM memory 4, cycle counter 11, SRAM control authority switch 12, image receiving FIFO 13, image downlink FIFO 14, image cache state machine 15, image downlink state machine 16, clock counter 17 and controller 18. DETAILED DESCRIPTION

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same modules are represented by the same reference numerals. In the case of the same reference numerals, their names and functions are also the same. Therefore, the detailed description thereof will not be repeated.

[0056] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0057] Figure 1 The structure of a coordinate image caching system provided according to an embodiment of the present invention is shown.

[0058] like Figure 1As shown, the coordinate image caching system for an extreme ultraviolet camera proposed in an embodiment of the present invention includes an FPGA module 1, and an image uplink interface circuit 2, an image downlink interface circuit 3 and an SRAM memory 4 extended on the FPGA module 1. The FPGA module 1 includes a controller 18, an image receiving FIFO 13, an image downlink FIFO 14, a cycle counter 11, a clock counter 17, an SRAM control right switch 12, an image cache state machine 15 and an image downlink state machine 16, wherein:

[0059] The controller 18 is used to control the image receiving FIFO 13, the image downlink FIFO 14, the cycle counter 11, the clock counter 17, the SRAM control right switch 12, the image buffer state machine 15, the image downlink state machine 16, the image uplink interface circuit 2, the image downlink interface circuit 3 and the SRAM memory 4;

[0060] The clock counter 17 is used to perform a counting operation according to a set initialization instruction issued by the controller 18, and restart counting when the count value of the clock counter is the same as the exposure time of the coordinate image. The cycle counter 11 is used to perform a counting operation according to the set initialization instruction issued by the controller 18, and restart counting after reaching the maximum count value. The image uplink interface circuit 2 is used to input the minimum unit uplink data of the coordinate image to the image receiving FIFO 13 by line. The image receiving FIFO 13 is used to cache the coordinate position of the minimum unit uplink data by line. The SRAM control right switch 12 is used to switch the control right of the image cache state machine 15 or the image downlink state machine 16 according to the counting range of the cycle counter 11. The image cache state machine 15 is used to read out the coordinate position of the minimum unit uplink data in the corresponding position of the uplink area of ​​the SRAM memory 4 bit by bit. The uplink area of ​​the SRAM memory 4 is used to write the minimum unit uplink data cached by the image receiving FIFO 13 bit by bit until the coordinate image is completely written into the uplink area of ​​the SRAM memory 4.

[0061] The image downlink state machine 16 is used to store the minimum unit downlink data of the coordinate image in the downlink area of ​​the downlink SRAM memory 4 row by row, the image downlink FIFO 14 is used to cache the minimum unit downlink data stored in the downlink area of ​​the SRAM memory 4 row by row, and the image downlink interface circuit 3 is used to output the minimum unit downlink data cached by the image downlink FIFO 14 row by row.

[0062] The uplink data rate of the minimum unit uplink data of the coordinate image is determined according to the maximum data rate of the image uplink of the SRAM memory 4; the downlink data rate of the minimum unit downlink data of the coordinate image is determined according to the maximum data rate of the image downlink of the SRAM memory 4.

[0063] If the upper and lower half area set flags issued by the controller 18 are "0", the upper half storage area of ​​the SRAM memory 4 is the upstream area, and the lower half storage area of ​​the SRAM memory 4 is the downstream area; if the upper and lower half area set flags issued by the controller 18 are "1", the lower half storage area of ​​the SRAM memory 4 is the upstream area, and the upper half storage area of ​​the SRAM memory 4 is the downstream area.

[0064] Figure 2 The structure of timeline polling provided according to an embodiment of the present invention is shown.

[0065] like Figure 2 As shown, when the clock count is in the low level interval, data can only be written in the upstream area of ​​the SRAM memory 4, and when the clock count is in the high level interval, data can only be read from the downstream area of ​​the SRAM memory 4 to complete the downstream of the minimum unit downstream data.

[0066] Figure 3 The flowchart of the cycle counter provided according to the embodiment of the present invention is shown.

[0067] like Figure 3 As shown, when the cycle counter 11 counts from zero to X max , it is necessary to clear the cycle counter 11 and then start accumulating again.

[0068] Figure 4 The control right management of the SRAM control right switch 12 provided according to an embodiment of the present invention is shown.

[0069] like Figure 4 As shown, when the counting range of the cycle counter 11 is 0 to (X1-1), the SRAM control right switch 12 switches the control right to the image cache state machine 15;

[0070] When the counting range of the cycle counter 11 is X1~X max , the SRAM control right switch 12 switches the control right to the image downlink state machine 16.

[0071] Assume that the clock cycle of FPGA is T, then the maximum value of cycle counter 11 is X max :

[0072] X max =X1+X2(1);

[0073] Among them, X1>X in , X in =T in / T,X in The number of clocks required to perform an uplink processing of the minimum unit of uplink data, T inThe time required to perform the uplink processing of the minimum unit of uplink data, X2>X out , X out =T out / T,X out The number of clocks required to perform a downlink processing of the minimum unit of downlink data, T out It is the time required to perform downlink processing of the minimum unit of downlink data.

[0074] Uplink bandwidth V of coordinate image inmax :

[0075] V inmax =V max ×X1 / X max (2);

[0076] Among them, V inmax >2V in , V in The maximum data rate required to perform uplink processing of the minimum unit of uplink data, V max is the maximum uplink / downlink data rate of the SRAM memory 4;

[0077] Coordinate image downlink bandwidth V outmax :

[0078] V outmax =V max ×X2 / X max (3);

[0079] Among them, V outmax >2V out , V out The maximum data rate required to perform downlink processing of the minimum unit of downlink data.

[0080] During the counting process of the cycle counter 11 , if the image buffer state machine 15 or the image buffer state machine 15 does not receive the minimum unit uplink data or the minimum unit downlink data correspondingly, no operation is selected.

[0081] The cycle counter 11 varies within the range of 0 to the maximum value according to the program design. When the program runs abnormally or runs away, the cycle counter 11 will show other values ​​outside the counting range. At this time, all CS, AOE, and AWE signals of the SRAM memory 4 need to be pulled high to protect the coordinate image cache system.

[0082] Figure 5 The flowchart of the coordinate image caching method for an extreme ultraviolet camera provided according to an embodiment of the present invention is shown.

[0083] like Figure 5As shown, the coordinate image caching method for an extreme ultraviolet camera proposed in an embodiment of the present invention is implemented using a coordinate image caching system, and specifically includes the following steps:

[0084] S1: Build a coordinate image cache system.

[0085] S2: The coordinate image cache system is powered on, and the SRAM memory 4 performs a clearing operation according to the reset initialization instruction issued by the controller 18 .

[0086] S3: The cycle counter 11 and the clock counter 17 start counting after receiving the set initialization instruction, and the controller 18 issues the upper and lower half area set flag "0".

[0087] S4: The image uplink interface circuit 2 inputs the minimum unit uplink data of the coordinate image to the image receiving FIFO 13 row by row, and the controller 18 determines whether the buffer area of ​​the image receiving FIFO 13 is full. If not, step S5 is executed; if full, step S6 is executed.

[0088] S5: When the counting time of the clock counter 17 is equal to the exposure time of the extreme ultraviolet camera, query the controller 18 to see if it issues an instruction of "exposure time has expired". If so, flip the upper and lower half-area setting flags to make the clock counter restart counting and then execute step S4. Otherwise, directly execute step S4.

[0089] S6: the controller 18 sends a write instruction to the image buffer state machine 15, and the image buffer state machine 15 controls the image receiving FIFO 13 to write the minimum unit uplink data into the uplink area of ​​the SRAM memory 4 bit by bit.

[0090] Step S6 specifically includes the following steps:

[0091] S61: When the SRAM control right switch 12 switches the control right to the image cache state machine 15 and the count value of the cycle counter 11 is 0, the image receiving FIFO 13 reads out the coordinate position of a pixel point, and the controller 18 determines whether the coordinate position of the pixel point is in the upstream area of ​​the SRAM memory 4. If so, execute step S62, otherwise execute step S63.

[0092] S62: Map the corresponding position of the coordinate position of the pixel point in the upstream area of ​​the SRAM memory 4, read the pixel point at the corresponding position and add 1, and write the coordinate position of the pixel point read out by the image receiving FIFO 13 into the corresponding position.

[0093] S63: Add 1 to the count value of the write image data counter of the controller 18, and repeat step S61 until the count value of the write image data counter is equal to the pixel value of the coordinate image.

[0094] S7: After a row of minimum unit upstream data is written into the upstream area of ​​the SRAM memory 4, step S5 is executed until the coordinate image is completely written into the upstream area of ​​the SRAM memory 4.

[0095] S8: The controller 18 queries the upper area of ​​the SRAM memory 4 to see whether the coordinate image is completely written. If so, the controller 18 executes step S9, otherwise, the controller 18 executes step S4.

[0096] S9: Check whether the controller 18 has issued a "data can be cached" instruction. If so, execute step S10, otherwise enter the waiting state.

[0097] S10: the controller 18 inputs a downlink instruction to the image downlink state machine 16, and the image downlink state machine 16 controls the image downlink FIFO 14 to cache the minimum unit downlink data of the coordinate image stored in the downlink area of ​​the SRAM memory 4 in rows.

[0098] Step S10 specifically includes the following steps:

[0099] S101 : The controller 18 calculates the address to be downloaded in the downstream area of ​​the SRAM memory 4 .

[0100] S102: When the SRAM control right switch 12 switches the control right to the image downlink state machine 16 and the count value of the cycle counter 11 is X1, the image downlink FIFO 14 buffers the minimum unit downlink data corresponding to the downlink address according to the calculation result of step S101.

[0101] S103: the count value of the image pixel counter of the controller 18 is increased by 1, and it is determined whether the count value of the image pixel counter is equal to the pixel value of the minimum unit downlink data. If so, step S104 is executed, otherwise, step S102 is executed.

[0102] S104: the count value of the image row counter of the controller 18 is increased by 1, and it is determined whether the count value of the image row counter is the same as the total number of rows in the downstream area of ​​the SRAM memory 4. If so, step S105 is executed, otherwise step S101 is executed.

[0103] S105: Clear the downstream area of ​​the SRAM memory 4 and execute step S8.

[0104] Step S105 specifically includes the following steps:

[0105] S1051: The controller 18 issues a clear instruction and calculates the address to be cleared in the downstream area of ​​the SRAM memory 4.

[0106] S1052: When the SRAM control right switch 12 switches the control right to the image downlink state machine 16, and the count value of the cycle counter 11 is X1, the controller 18 clears the pixel points at the address to be cleared.

[0107] S1053: The count value of the reset counter of the controller 18 is increased by 1, and it is determined whether the count value of the reset counter is the same as the total number of rows in the downstream area of ​​the SRAM memory 4. If so, step S8 is executed, otherwise step S1051 is executed.

[0108] S11: After reading out a row of minimum unit downstream data from the downstream area of ​​the SRAM memory 4, repeat step S9 until all coordinate images stored in the downstream area of ​​the SRAM memory 4 are read out, then clear the downstream area of ​​the SRAM memory 4 and return to step S8.

[0109] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the disclosure of the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0110] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A coordinate image caching system for an extreme ultraviolet camera, characterized in that: The invention comprises an FPGA module, and an image uplink interface circuit, an image downlink interface circuit and an SRAM memory extended on the FPGA module. The FPGA module comprises a controller, an image receiving FIFO, an image downlink FIFO, a cycle counter, a clock counter, an SRAM control right switch, an image buffer state machine and an image downlink state machine, wherein: The controller is used to control the image receiving FIFO, the image downlink FIFO, the cycle counter, the clock counter, the SRAM control right switch, the image buffer state machine, the image downlink state machine, the image uplink interface circuit, the image downlink interface circuit and the SRAM memory; The clock counter is used to perform a counting operation according to a set initialization instruction issued by the controller, and restart counting when the count value of the clock counter is the same as the exposure time of the coordinate image. The cycle counter is used to perform a counting operation according to the set initialization instruction issued by the controller, and restart counting after reaching a maximum count value. The image uplink interface circuit is used to input the minimum unit uplink data of the coordinate image to the image receiving FIFO by line, and the image receiving FIFO is used to cache the coordinate position of the minimum unit uplink data by line. The SRAM control right switch is used to switch the control right of the image buffer state machine or the image downlink state machine according to the counting range of the cycle counter. The image buffer state machine is used to read out the coordinate position of the minimum unit uplink data in the corresponding position of the uplink area of ​​the SRAM memory bit by bit, and the uplink area of ​​the SRAM memory is used to write the minimum unit uplink data bit by bit until the coordinate image is completely written into the uplink area of ​​the SRAM memory; The image downlink state machine is used to downlink the minimum unit downlink data of the coordinate image stored in the downlink area of ​​the SRAM memory by line, the image downlink FIFO is used to cache the minimum unit downlink data stored in the downlink area of ​​the SRAM memory by line, and the image downlink interface circuit is used to output the minimum unit downlink data cached by the image downlink FIFO by line; If the upper and lower half area set flags issued by the controller are "0", the upper storage area of ​​the SRAM memory is the upstream area, and the lower storage area of ​​the SRAM memory is the downstream area; if the upper and lower half area set flags issued by the controller are "1", the lower storage area of ​​the SRAM memory is the upstream area, and the upper storage area of ​​the SRAM memory is the downstream area.

2. The coordinate image caching system for an extreme ultraviolet camera according to claim 1, characterized in that: Determine the uplink data rate of the minimum unit uplink data of the coordinate image according to the maximum data rate of the image uplink of the SRAM memory; The downlink data rate of the minimum unit downlink data of the coordinate image is determined according to the maximum data rate of the SRAM memory for image downlink.

3. The coordinate image buffer system for an extreme ultraviolet camera according to claim 2, characterized in that: The clock cycle of the FPGA is T, then the maximum value of the cycle counter is X max : X max =X1+X2(1); Among them, X1>X in , X in =T in / T,X in The number of clocks required to perform an uplink processing of the minimum unit of uplink data, T in The time required to perform the uplink processing of the minimum unit of uplink data, X2>X out , X out =T out / T,X out The number of clocks required to perform a downlink processing of the minimum unit of downlink data, T out It is the time required to perform downlink processing of the minimum unit of downlink data.

4. The coordinate image caching system for an extreme ultraviolet camera according to claim 3, characterized in that: When the counting range of the cycle counter is 0~(X1-1), the SRAM control right switch switches the control right to the image cache state machine; When the counting range of the cycle counter is X1~X max , the SRAM control right switch switches the control right to the image downlink state machine.

5. The coordinate image caching system for an extreme ultraviolet camera according to claim 4, characterized in that: The uplink bandwidth V of the coordinate image inmax : V inmax =V max ×X1 / X max (2); Among them, V inmax >2V in , V in The maximum data rate required to perform uplink processing of the minimum unit of uplink data, V max is the maximum uplink / downlink data rate of the SRAM memory; The downlink bandwidth V of the coordinate image outmax : V outmax =V max ×X2 / X max (3); Among them, V outmax >2V out , V out The maximum data rate required to perform downlink processing of the minimum unit of downlink data.

6. The coordinate image caching system for an extreme ultraviolet camera according to claim 5, characterized in that: If the upper and lower half area setting flags issued by the controller are "0", the upper half storage area of ​​the SRAM memory is the upstream area, and the lower half storage area of ​​the SRAM memory is the downstream area; if the upper and lower half area setting flags issued by the controller are "1", the lower half storage area of ​​the SRAM memory is the upstream area, and the upper half storage area of ​​the SRAM memory is the downstream area.

7. A coordinate image caching method for an extreme ultraviolet camera, implemented using the coordinate image caching system of claim 6, characterized in that: The specific steps include: S1: Building the coordinate image caching system as claimed in claim 6; S2: Powering on the coordinate image cache system, and performing a clearing operation on the SRAM memory according to the reset initialization instruction issued by the controller; S3: the cycle counter and the clock counter start counting after querying the setting initialization instruction, and the controller issues the upper and lower half area setting flag "0"; S4: the image uplink interface circuit inputs the minimum unit uplink data of the coordinate image to the image receiving FIFO line by line, and the controller determines whether the buffer area of ​​the image receiving FIFO is full, and if not, executes step S5; if full, executes step S6; S5: When the counting time of the clock counter is equal to the exposure time of the extreme ultraviolet camera, query whether the controller issues an "exposure time has expired" instruction; if so, flip the upper and lower half-area setting flags to make the clock counter restart counting and then execute step S4; otherwise, directly execute step S4; S6: the controller sends a write instruction to the image buffer state machine, and the image buffer state machine controls the image receiving FIFO to write the minimum unit uplink data into the uplink area of ​​the SRAM memory bit by bit in sequence; S7: after a row of the minimum unit upstream data is written into the upstream area of ​​the SRAM memory, the step S5 is executed until all the coordinate images are written into the upstream area of ​​the SRAM memory; S8: the controller inquires whether the coordinate image is completely written into the upstream area of ​​the SRAM memory, and if so, executes step S9, otherwise, executes step S4; S9: Check whether the controller issues a "data cacheable" instruction, if so, execute step S10, otherwise enter a waiting state; S10: the controller inputs a downlink instruction to the image downlink state machine, and the image downlink state machine controls the image downlink FIFO to cache the minimum unit downlink data of the coordinate image stored in the downlink area of ​​the SRAM memory in rows; S11: After reading out a row of the minimum unit downstream data from the downstream area of ​​the SRAM memory, repeat step S9 until all the coordinate images stored in the downstream area of ​​the SRAM memory are read out, clear the downstream area of ​​the SRAM memory and return to step S8.

8. The coordinate image caching method for an extreme ultraviolet camera according to claim 7, characterized in that: The step S6 specifically includes the following steps: S61: When the SRAM control right switcher switches the control right to the image cache state machine and the count value of the cycle counter is 0, the image receiving FIFO reads out the coordinate position of a pixel point, and the controller determines whether the coordinate position of the pixel point is in the upstream area of ​​the SRAM memory, and if so, executes step S62, otherwise executes step S63; S62: mapping the corresponding position of the coordinate position of the pixel point in the upstream area of ​​the SRAM memory, adding 1 after reading the pixel point at the corresponding position, and writing the coordinate position of the pixel point read by the image receiving FIFO into the corresponding position; S63: adding 1 to the count value of the image data writing counter of the controller, and repeating step S61 until the count value of the image data writing counter is equal to the pixel value of the coordinate image.

9. The coordinate image caching method for an extreme ultraviolet camera according to claim 7, characterized in that: The step S10 specifically includes the following steps: S101: The controller calculates a waiting downlink address of a downlink area of ​​the SRAM memory; S102: When the SRAM control right switcher switches the control right to the image downlink state machine and the count value of the cycle counter is X1, the image downlink FIFO caches the minimum unit downlink data corresponding to the to-be-downlinked address bit by bit according to the calculation result of step S101; S103: adding 1 to the count value of the image pixel counter of the controller, and determining whether the count value of the image pixel counter is equal to the pixel value of the minimum unit downlink data, if so, executing step S104, otherwise executing step S102; S104: adding 1 to the count value of the image row counter of the controller, and determining whether the count value of the image row counter is the same as the total number of rows in the downstream area of ​​the SRAM memory, if so, executing step S105, otherwise executing step S101; S105: clear the downstream area of ​​the SRAM memory and execute step S8.

10. The coordinate image caching method for an extreme ultraviolet camera according to claim 9, characterized in that: The step S105 specifically includes the following steps: S1051: the controller issues a clear instruction and calculates the address to be cleared in the downstream area of ​​the SRAM memory; S1052: When the SRAM control right switcher switches the control right to the image downlink state machine and the count value of the cycle counter is X1, the controller clears the pixel points at the address to be cleared; S1053: the count value of the reset counter of the controller is increased by 1, and it is determined whether the count value of the reset counter is the same as the total number of rows in the downstream area of ​​the SRAM memory. If so, the step S8 is executed, otherwise the step S1051 is executed.

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