Chip operating voltage adjustment device and adjustment method

Abstract

The application discloses a chip working voltage adjusting device and adjusting method, relates to the technical field of integrated circuits, and is used for adjusting the working voltage of a chip based on the parameters of a critical path, so as to reduce the power consumption of the chip. The device comprises a ring oscillator circuit, a coding circuit, a voltage adjusting unit and a chip power supply unit. The ring oscillator circuit is used for outputting a plurality of pulse signals according to an enabling signal output by the voltage adjusting unit and in combination with the threshold voltage of the critical path of the chip corresponding to the ring oscillator circuit. The coding circuit is used for generating a corresponding target coding signal based on the plurality of pulse signals. The voltage adjusting unit is used for generating a voltage adjusting signal based on the target coding signal in combination with a preset condition. The chip power supply unit is used for adjusting the working voltage of the chip according to the voltage adjusting signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a device and method for adjusting the operating voltage of a chip. Background Technology

[0002] With the development of the integrated circuit industry, chips are becoming increasingly integrated and larger in scale, making it imperative to reduce chip power consumption. Chip power consumption is related to its operating voltage; the higher the operating voltage, the greater the power consumption.

[0003] The maximum operating voltage of a chip is determined by the critical path, that is, by the circuit that requires the maximum voltage to operate. When the chip operates at a fixed voltage, if the minimum operating voltage required by the chip is lower than the set fixed voltage, it will result in wasted power consumption.

[0004] Therefore, how to adjust the chip's operating voltage based on the parameters of the critical path in order to reduce chip power consumption has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a chip operating voltage adjustment device and method for adjusting the chip operating voltage based on critical path parameters, thereby reducing the chip power consumption.

[0006] In a first aspect, the present invention provides a chip operating voltage adjustment device for adjusting the operating voltage of the chip, the device comprising: an oscillating ring circuit, an encoding circuit, a voltage adjustment unit, and a chip power supply unit.

[0007] The enable terminal of the voltage adjustment unit is electrically connected to the input terminal of the oscillating ring circuit, the output terminal of the encoding circuit is electrically connected to the input terminal of the voltage adjustment unit, and the output terminal of the voltage adjustment unit is electrically connected to the input terminal of the chip power supply unit.

[0008] The oscillating loop circuit is used to output multiple pulse signals based on the enable signal output by the voltage adjustment unit and the threshold voltage of the critical path of the chip corresponding to the oscillating loop circuit.

[0009] The encoding circuit is used to generate a corresponding target encoded signal based on multiple pulse signals.

[0010] The voltage adjustment unit is used to generate a voltage adjustment signal based on the target encoded signal and preset conditions.

[0011] The chip power supply unit is used to adjust the chip's operating voltage according to the voltage adjustment signal.

[0012] Compared with existing technologies, the chip operating voltage adjustment device provided by this invention, in which the voltage adjustment unit outputs an enable signal to the enable terminal of the oscillating ring circuit, not only can it drive the oscillating ring circuit to output multiple pulse signals related to the threshold voltage of the chip's critical path, but it can also avoid unnecessary switching of the oscillating ring circuit. It can control the oscillating ring circuit to generate pulse signals only when needed, thus saving dynamic power consumption. Each pulse signal is transmitted to the corresponding input terminal of the encoding circuit. The encoding circuit detects and encodes multiple pulse signals, and outputs the corresponding target encoded signal. Since the target encoded signal is determined based on the pulse signals related to the threshold voltage of the critical path, the target encoded signal output by the encoding circuit can reflect the performance of the chip's critical path. The voltage adjustment unit can determine the corresponding chip operating voltage value of the critical path based on the received target encoded signal and preset conditions. When the chip operating voltage value corresponding to the target encoded signal is less than the benchmark value determined by the test, it indicates that the current chip operating voltage is too low. The voltage adjustment signal generated by the voltage adjustment unit can control the chip power supply unit to issue an instruction to gradually increase the chip operating voltage. When the chip operating voltage value corresponding to the target encoded signal is greater than the benchmark value determined by the test, it indicates that the current chip operating voltage is too high. The voltage adjustment signal generated by the voltage adjustment unit can control the chip power supply unit to issue an instruction to gradually decrease the chip operating voltage. This allows the current operating voltage of the chip to change with the minimum operating voltage required by the chip, thereby realizing dynamic adjustment of the current operating voltage of the chip and further reducing chip power consumption.

[0013] In a second aspect, the present invention also provides a method for adjusting the operating voltage of a chip, used in the chip operating voltage adjustment device provided in the first aspect, the method comprising:

[0014] The oscillating loop circuit outputs multiple pulse signals based on the enable signal output by the voltage adjustment unit and the threshold voltage of the critical path of the chip corresponding to the oscillating loop circuit.

[0015] The encoding circuit generates the corresponding target encoded signal based on multiple pulse signals.

[0016] The voltage adjustment unit generates a voltage adjustment signal based on the target encoded signal and preset conditions.

[0017] The chip power supply unit adjusts the chip's operating voltage according to the voltage adjustment signal.

[0018] Compared with the prior art, the beneficial effects of the chip operating voltage adjustment method provided by the present invention are the same as those of the chip operating voltage adjustment device described in the above technical solutions, and will not be repeated here. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the working voltage adjustment device of the chip in an embodiment of the present invention; Figure 2 This is a circuit diagram of the oscillating ring circuit in an embodiment of the present invention; Figure 3 This is a circuit diagram of the first detection submodule in an embodiment of the present invention; Figure 4 This is a circuit diagram of the second detection submodule in an embodiment of the present invention.

[0020] Figure label: 1-Oscillating ring circuit, 2-Encoding circuit, 3-Voltage adjustment unit, 4-Chip power supply unit, 11-Delay module, 12-Enable signal input module, 21-Counting module, 22-Detection module, 23-Encoding output module, 221-First detection submodule, 222-Second detection submodule, 2211-Pulse signal detection unit, 2221 - Binary search detection unit; 211 - Multiplexer; 212-Counter. Detailed Implementation

[0021] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0022] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0023] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0024] like Figure 1 As shown, this embodiment of the invention provides a chip operating voltage adjustment device for adjusting the operating voltage of a chip. The device includes: an oscillating ring circuit 1, an encoding circuit 2, a voltage adjustment unit 3, and a chip power supply unit 4. The enable terminal of the voltage adjustment unit 3 is electrically connected to the input terminal of the oscillating ring circuit 1, the output terminal of the encoding circuit 2 is electrically connected to the input terminal of the voltage adjustment unit 3, and the output terminal of the voltage adjustment unit 3 is electrically connected to the input terminal of the chip power supply unit 4. The oscillating ring circuit 1 outputs multiple pulse signals based on the enable signal output by the voltage adjustment unit 3 and the threshold voltage of the critical path of the chip corresponding to the oscillating ring circuit 1. The encoding circuit 2 generates a corresponding target encoded signal based on the multiple pulse signals. The voltage adjustment unit 3 generates a voltage adjustment signal based on the target encoded signal and preset conditions. The chip power supply unit 4 adjusts the operating voltage of the chip according to the voltage adjustment signal.

[0025] Understandably, the aforementioned preset condition can actually be the correspondence between the target encoded signal and the chip operating voltage value, Y = aX + b, where X represents the target encoded signal, Y represents the current chip operating voltage value, and a and b represent weight values, determined by fitting the temperature-minimum voltage curve obtained from the Automatic Test Equipment (ATE). Therefore, after determining the target encoded signal X and the weight values ​​a and b, the corresponding current chip operating voltage value Y can be determined. Y is compared with the reference value obtained from the ATE test. When Y is less than the reference value, it indicates that the current chip operating voltage is too low. The voltage adjustment signal generated by the voltage adjustment unit 3 can control the chip power supply unit 4 to issue commands to gradually increase the chip operating voltage. When Y is greater than the reference value, it indicates that the current chip operating voltage is too high. The voltage adjustment signal generated by the voltage adjustment unit 3 can control the chip power supply unit 4 to issue commands to gradually decrease the chip operating voltage, thereby achieving adjustment of the chip operating voltage.

[0026] The aforementioned oscillating loop circuit 1 can be composed of the threshold voltage VT type used in the critical path, so that the pulse signal output by the oscillating loop circuit 1 can be a pulse signal that reflects the threshold voltage VT type used.

[0027] The specific structure of the operating voltage adjustment device for the chip described above shows that: the voltage adjustment unit 3 outputs an enable signal to the enable terminal of the oscillating ring circuit 1. This not only drives the oscillating ring circuit 1 to output multiple pulse signals related to the threshold voltage of the chip's critical path, but also prevents unnecessary switching of the oscillating ring circuit 1. It controls the oscillating ring circuit 1 to generate pulse signals only when needed, thus saving dynamic power consumption. Each pulse signal is transmitted to the corresponding input terminal of the encoding circuit 2. The encoding circuit 2 detects and encodes the multiple pulse signals, then outputs the corresponding target encoded signal. Since the target encoded signal is determined based on the pulse signals related to the threshold voltage of the critical path, the target encoded signal output by the encoding circuit 2 can reflect the performance of the chip's critical path. The voltage adjustment unit 3 can determine the corresponding chip operating voltage value of the critical path based on the received target encoding signal and preset conditions. When the chip operating voltage value corresponding to the target encoding signal is less than the benchmark value determined by the test, it indicates that the current chip operating voltage is too low. The voltage adjustment signal generated by the voltage adjustment unit 3 can control the chip power supply unit 4 to issue an instruction to increase the chip operating voltage step by step. When the chip operating voltage value corresponding to the target encoding signal is greater than the benchmark value determined by the test, it indicates that the current chip operating voltage is too high. The voltage adjustment signal generated by the voltage adjustment unit 3 can control the chip power supply unit 4 to issue an instruction to decrease the chip operating voltage step by step. This allows the current operating voltage of the chip to change with the minimum operating voltage required by the chip, thereby realizing dynamic adjustment of the current operating voltage of the chip and further reducing chip power consumption.

[0028] In one possible implementation, such as Figure 2 As shown, the oscillating ring circuit 1 includes multiple delay modules 11 connected end to end, and the output terminal of each delay module 11 is electrically connected to the corresponding input terminal of the encoding circuit 2.

[0029] Furthermore, the oscillating ring circuit 1 also includes an enable signal input module 12, which is connected between the first delay module 11 and the last delay module 11. The first input terminal of the enable signal input module 12 is electrically connected to the output terminal of the last delay module 11, the second input terminal of the enable signal input module 12 is electrically connected to the enable terminal of the voltage adjustment unit 3, and the output terminal of the enable signal input module 12 is electrically connected to the input terminal of the first delay module 11.

[0030] With the above technical solution, the enable signal input module 12 can output a corresponding drive signal to the delay module 11 based on the enable signal output by the voltage adjustment unit 3, so as to drive the delay module 11 to output the corresponding pulse signal. When the enable signal input module 12 does not receive the enable signal, the enable signal input module 12 cannot output the drive signal, and the delay module 11 will not generate the corresponding pulse signal. Based on this, the oscillation ring circuit 1 can control the duration of pulse signal generation under the control of the voltage adjustment unit 3, and can also generate pulse signal only when needed, thereby saving the dynamic power consumption of the circuit to a certain extent.

[0031] It should be understood that the delay of delay module 11 will be different when the chip is operating at different voltages. The higher the voltage, the smaller the delay, and vice versa. Each delay module 11 has a delay Ti. Each delay module 11 has an inversion function. After 5Ti time, the output values ​​of two adjacent delay modules 11 are different before 5Ti time. After 5Ti time, the output values ​​of two adjacent delay modules 11 are the same. Therefore, the output of each delay module 11 will show 0, 1, 0, 1, 0, 0, 1, 0, 1, 0…0. That is, the output values ​​of the fifth and sixth delay modules are the same. When the voltage increases, after 5Ti time, the output of each delay module 11 will show 0, 1, 0, 1, 1, 0, 1, 0, 1, 0…0. That is, the output values ​​of the fourth and fifth delay modules are the same. Therefore, in this application, the change of the chip's current operating voltage can be reflected by whether the output values ​​of two adjacent delay modules 11 are the same. The number of delay modules 11 can be any number, such as 4, 8, 16 or 20, depending on the precision requirements of the specific circuit. The higher the precision requirements of the circuit, the more delay modules 11 are set, but correspondingly, the power consumption of the circuit is also greater. The specific number can be set according to the actual situation, and the embodiments of the present invention do not make specific limitations in this regard.

[0032] For example, such as Figure 2 As shown, the enable signal input module 12 includes an AND gate, and the delay module 11 includes a NOT gate, wherein multiple NOT gates are electrically connected sequentially. The first input terminal of the AND gate is electrically connected to the output terminal of the last NOT gate, the second input terminal of the AND gate is electrically connected to the enable terminal of the voltage adjustment unit 3, and the output terminal of the AND gate is electrically connected to the input terminal of the first NOT gate. The output terminal of each NOT gate is also electrically connected to the corresponding input terminal of the encoding circuit 2.

[0033] It is understandable that AND gates and NOT gates are both basic logic circuits in digital circuits. An AND gate has at least two inputs and one output. The output is high (logic "1") only when all inputs are high (logic "1"); otherwise, it is low (logic "0"). A NOT gate has one input and one output. When the input is high (logic "1"), the output is low (logic "0"); conversely, when the input is low (logic "0"), the output is high (logic "1").

[0034] Specifically, such as Figure 2 As shown, after receiving the enable signal, the AND gate outputs the corresponding drive signal to the first NOT gate. After receiving the drive signal, the first NOT gate inverts the drive signal and outputs the opposite pulse signal. The second NOT gate inverts the output signal of the first NOT gate again, and so on. Since each NOT gate has a delay Ti, the pulse signals output by multiple NOT gates may have two adjacent pulse signals that are the same.

[0035] In some embodiments, the encoding circuit 2 includes a counting module 21, a detection module 22, and an encoding output module 23, wherein: multiple output terminals of the oscillating ring circuit 1 are electrically connected to multiple input terminals of the counting module 21 and multiple input terminals of the detection module 22, respectively; and the output terminals of both the counting module 21 and the detection module 22 are electrically connected to the input terminals of the encoding output module 23. The oscillating ring circuit 1 is used to output multiple pulse signals to the counting module 21 and the detection module 22, respectively. The counting module 21 is used to output a first encoded signal based on the sum of the number of rising and falling edges of any pulse signal. The detection module 22 is used to output a second encoded signal based on every two adjacent identical pulse signals. The encoding output module 23 is used to generate a corresponding target encoded signal based on the first encoded signal and the second encoded signal.

[0036] Based on this, the counting module 21 can count the number of pulse signals within a fixed time period and output the corresponding first encoded signal. The detection module 22 can detect every two adjacent pulse signals to determine whether they are the same, thereby reflecting the change in the chip's current operating voltage. The encoding output module 23 can generate a corresponding target encoded signal based on the first and second encoded signals, thereby using the target encoded signal to provide feedback on the performance of the current critical path.

[0037] In some embodiments, the detection module 22 includes a first detection submodule 221 and a second detection submodule 222 electrically connected in sequence, wherein: the input terminal of the first detection submodule 221 is electrically connected to the output terminals of a plurality of delay modules 11 respectively, and the output terminal of the second detection submodule 222 is electrically connected to the input terminal of the encoding output module 23. The first detection submodule 221 is used to output a corresponding detection signal based on every two adjacent identical pulse signals. The second detection submodule 222 is used to output a second encoded signal based on the detection signal.

[0038] With the above technical solution, the first detection submodule 221 can encode multiple pulse signals, encoding only the corresponding detection signal at consecutive 0s or consecutive 1s. The second detection submodule 222 can detect the detection signal output by the first detection submodule 221 and output a corresponding second encoded signal to indicate which bit the pulse signal at the consecutive 0s or consecutive 1s is located in. For example, when the oscillating ring circuit 1 has 16 stages, it can output a 16-bit signal. The detection module 22 can detect the 16-bit signal and output a 4-bit second encoded signal to indicate which bit the pulse signal at the consecutive 0s or consecutive 1s is located in.

[0039] For example, the first detection submodule 221 includes a plurality of pulse signal detection units 2211, the number of which is equal to the number of delay modules 11. The output terminals of every two adjacent delay modules 11 are electrically connected to the input terminals of the corresponding pulse signal detection units 2211. The pulse signal detection units 2211 are used to output a corresponding detection signal when every two adjacent pulse signals are detected to be the same.

[0040] In this application, the number of pulse signal detection units 2211 is the same as the number of delay modules 11. Each pulse detection unit can detect every two adjacent pulse signals. A pulse detection unit may include two AND gates, one OR gate, and two NOT gates. It should be understood that an OR gate is also a basic logic circuit in digital circuits. An OR gate has at least two inputs and one output. The output of the circuit is low (logic "0") only when all inputs are low (logic "0"); otherwise, the output is high (logic "1").

[0041] Specifically, taking the output signals of the first delay module and the second delay module as examples, the signal output by the first delay module is regarded as the first pulse signal, and the signal output by the second delay module is regarded as the second pulse signal. The two input terminals of AND gate a1 are used to obtain the first pulse signal and the second pulse signal, respectively. The two input terminals of OR gate or1 are also used to obtain the first pulse signal and the second pulse signal, respectively. The output signal of AND gate a1 is transmitted to NOT gate n1 for inversion and then transmitted to AND gate a2. The output signal of OR gate or1 is directly transmitted to AND gate a2, and the output signal of AND gate a2 is transmitted to NOT gate n2. When the first pulse signal and the second pulse signal are the same, the pulse signal detection unit 2211 outputs logic "1". When the first pulse signal and the second pulse signal are different, the pulse signal detection unit 2211 outputs logic "0".

[0042] For example, the second detection submodule 222 includes a plurality of binary detection units 2221. The input terminals of the plurality of binary detection units 2221 are electrically connected to the output terminals of the corresponding pulse signal detection units 2211, respectively, for encoding the detection signals and outputting the corresponding second encoded signals.

[0043] Specifically, the binary detection unit 2221 can be as follows: Figure 4 As shown, it includes two OR gates, two 2-to-1 data selectors, and one NOT gate. Taking four adjacent pulse signal detection units 2211 as an example, the output signal of the first pulse signal detection unit is regarded as the first detection signal, the output signal of the second pulse signal detection unit is regarded as the second detection signal, the output signal of the third pulse signal detection unit is regarded as the third detection signal, and the output signal of the fourth pulse signal detection unit is regarded as the fourth detection signal.

[0044] The two inputs of OR gate OR2 are used to acquire the first detection signal and the second detection signal, respectively. The output signal of OR gate OR2 is inverted by NOT gate N3 and outputs the first sub-encoded signal. The third detection signal is transmitted to the first input of 2-to-1 data selector mux1, and the first detection signal is also transmitted to the second input of 2-to-1 data selector mux1. The fourth detection signal is transmitted to the first input of 2-to-1 data selector mux2, and the second detection signal is also transmitted to the second input of 2-to-1 data selector mux2. The selection signals of the two 2-to-1 data selectors are the first sub-encoded signals. The output signals of the two 2-to-1 data selectors are transmitted to the two inputs of OR gate OR3, and OR gate OR3 outputs the second sub-encoded signal. Thus, the binary detection unit 2221 can encode the first detection signal, the second detection signal, the third detection signal, and the fourth detection signal into the first sub-encoded signal and the second sub-encoded signal. The output signal of the multiple binary detection units 2221 is the second encoded signal.

[0045] It should be understood that the above is for ease of explanation only, therefore... Figure 4 Only one binary search detection unit 2221 is shown as an example. Taking a 4-bit signal as an example, it is ultimately encoded into a 2-bit signal through binary search; and so on, it can be used to detect signals in other ways. Figure 4 The circuit is expanded into a 16-bit signal input and finally encoded into a 4-bit signal. This embodiment of the invention does not impose specific limitations on this.

[0046] In some embodiments, such as Figure 1 As shown, the counting module 21 includes a multiplexer 211 and a counter 212. The input terminals of the multiplexer 211 are electrically connected to the output terminals of multiple delay modules 11, respectively, to receive multiple pulse signals. The output terminal of the multiplexer 211 is electrically connected to the input terminal of the counter 212, and the counter 212 is electrically connected to the input terminal of the encoding output module 23. The multiplexer 211 transmits the target pulse signal to the counter 212, and the counter 212 outputs a first encoded signal based on the sum of the number of rising and falling edges of the target pulse signal. The target pulse signal is any one of the multiple pulse signals.

[0047] For example, such as Figure 1 As shown, the multiplexer can be determined according to the number of delay modules 11 in the oscillating ring circuit 1. For example, when the oscillating ring circuit 1 includes 16 delay modules 11, the multiplexer 211 is a 16-channel data selector; when the oscillating ring circuit 1 includes 8 delay modules 11, the multiplexer 211 is an 8-channel data selector, and so on. This embodiment of the invention does not make specific limitations in this regard.

[0048] Understandably, the multiplexer also includes a selection terminal for selecting one of the multiple input signals to be transmitted to the output terminal. Therefore, the multiplexer can select one pulse signal from multiple pulse signals to be transmitted to the counter 212, and the selected pulse signal is the target pulse signal. To count the number of pulse signals within a fixed time width, the counter 212 can be an edge-triggered counter 212. However, to improve counting accuracy, it is necessary to calculate the pulses that are less than one pulse width at the end of the fixed time width. Therefore, the counter 212 in this application can be a dual-edge triggered counter 212, meaning that the counter 212 can be triggered on both the rising and falling edges of the signal. The final count is the sum of the number of rising and falling edges of the target pulse signal. In this application, the output of the counter 212 can be determined based on the length of the enable signal. For example, in this application, when the length of the enable signal is selected to be approximately 20 ns (nanoseconds), the bit width of the counter 212 can be selected as 6 bits.

[0049] As can be seen from the above, the counter 212 can characterize chips with large performance differences by calculating the sum of the number of rising and falling edges of the target pulse signal and output the first encoded signal. The detection module 22 can characterize chips with small performance differences by detecting whether every two adjacent pulse signals are the same and output the second encoded signal. The final encoding module determines the final target encoded signal based on the first and second encoded signals. Since the target encoded signal is determined based on the pulse signal related to the threshold voltage of the critical path, the target encoded signal output by the encoding circuit 2 can more comprehensively reflect the performance of the chip's critical path.

[0050] This invention also provides a method for adjusting the operating voltage of a chip, which is used in the chip operating voltage adjustment device provided in the first aspect. The method for adjusting the operating voltage of a chip includes...

[0051] The oscillating loop circuit outputs multiple pulse signals based on the enable signal output by the voltage adjustment unit and the threshold voltage of the critical path of the chip corresponding to the oscillating loop circuit.

[0052] The encoding circuit generates the corresponding target encoded signal based on multiple pulse signals.

[0053] The voltage adjustment unit generates a voltage adjustment signal based on the target encoded signal and preset conditions.

[0054] The chip power supply unit adjusts the chip's operating voltage according to the voltage adjustment signal.

[0055] Compared with the prior art, the beneficial effects of the chip operating voltage adjustment method provided in the embodiments of the present invention are the same as the beneficial effects of the chip operating voltage adjustment device described in the above embodiments, and will not be repeated here.

[0056] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A chip operating voltage adjustment device, characterized in that, The device for adjusting the operating voltage of the chip includes: an oscillating ring circuit, an encoding circuit, a voltage adjustment unit, and a chip power supply unit; The enable terminal of the voltage adjustment unit is electrically connected to the input terminal of the oscillating ring circuit, the output terminal of the encoding circuit is electrically connected to the input terminal of the voltage adjustment unit, and the output terminal of the voltage adjustment unit is electrically connected to the input terminal of the chip power supply unit. The oscillating ring circuit is used to output multiple pulse signals based on the enable signal output by the voltage adjustment unit and the threshold voltage of the critical path of the chip corresponding to the oscillating ring circuit. The encoding circuit is used to generate a corresponding target encoded signal based on multiple pulse signals; The voltage adjustment unit is used to generate a voltage adjustment signal based on the target encoded signal and preset conditions; The chip power supply unit is used to adjust the operating voltage of the chip according to the voltage adjustment signal; The oscillating ring circuit includes multiple delay modules connected end to end, and the output terminal of each delay module is electrically connected to the corresponding input terminal of the encoding circuit. The encoding circuit includes a counting module, a detection module, and an encoding output module, wherein: The multiple output terminals of the oscillating ring circuit are electrically connected to the multiple input terminals of the counting module and the multiple input terminals of the detection module, respectively. The output terminals of the counting module and the detection module are both electrically connected to the input terminal of the encoding output module. The oscillating ring circuit is used to output multiple pulse signals to the counting module and the detection module respectively; The counting module is used to output a first encoded signal based on the sum of the number of rising and falling edges of any one of the pulse signals; The detection module is used to output a second encoded signal based on every two adjacent identical pulse signals; The encoding output module is used to generate a corresponding target encoding signal based on the first encoding signal and the second encoding signal.

2. The chip operating voltage adjustment device according to claim 1, characterized in that, The detection module includes a first detection submodule and a second detection submodule that are electrically connected in sequence, wherein: The input terminal of the first detection submodule is electrically connected to the output terminals of the plurality of delay modules respectively, and the output terminal of the second detection submodule is electrically connected to the input terminal of the encoding output module; The first detection submodule is used to output a corresponding detection signal based on every two adjacent identical pulse signals; The second detection submodule is used to output the second encoded signal based on the detection signal.

3. The chip operating voltage adjustment device according to claim 2, characterized in that, The first detection submodule includes multiple pulse signal detection units, the number of which is equal to the number of delay modules; The output terminals of each pair of adjacent delay modules are electrically connected to the input terminal of the corresponding pulse signal detection unit. The pulse signal detection unit is used to output a corresponding detection signal when each pair of adjacent pulse signals is the same.

4. The chip operating voltage adjustment device according to claim 2, characterized in that, The second detection submodule includes multiple binary detection units; the input terminals of the multiple binary detection units are electrically connected to the output terminals of the corresponding pulse signal detection units, respectively, for encoding the multiple detection signals and outputting the corresponding second encoded signal.

5. The chip operating voltage adjustment device according to claim 1, characterized in that, The counting module includes a multiplexer and a counter, wherein: The input terminal of the multiplexer is electrically connected to the output terminals of the multiple delay modules one by one, for receiving multiple pulse signals. The output terminal of the multiplexer is electrically connected to the input terminal of the counter, and the counter is electrically connected to the input terminal of the encoding output module. The multiplexer is used to transmit the target pulse signal to the counter, and the counter is used to output the first encoded signal based on the sum of the number of rising edges and falling edges of the target pulse signal; wherein the target pulse signal is any one of the plurality of pulse signals.

6. The chip operating voltage adjustment device according to claim 1, characterized in that, The oscillating loop circuit further includes an enable signal input module, which is connected between the first delay module and the last delay module. The first input terminal of the enable signal input module is electrically connected to the output terminal of the last delay module, the second input terminal of the enable signal input module is electrically connected to the enable terminal of the voltage adjustment unit, and the output terminal of the enable signal input module is electrically connected to the input terminal of the first delay module.

7. The chip operating voltage adjustment device according to claim 6, characterized in that, The enable signal input module includes an AND gate, and the delay module includes a NOT gate, wherein: a plurality of the NOT gates are electrically connected end to end in sequence; The first input terminal of the AND gate is electrically connected to the output terminal of the last NOT gate, the second input terminal of the AND gate is electrically connected to the enable terminal of the voltage adjustment unit, and the output terminal of the AND gate is electrically connected to the input terminal of the first NOT gate. The output of each NOT gate is also electrically connected to the corresponding input of the encoding circuit.

8. A method for adjusting the operating voltage of a chip, characterized in that, The operating voltage adjustment device for the chip according to any one of claims 1-7, wherein the operating voltage adjustment method for the chip comprises: The oscillating loop circuit outputs multiple pulse signals based on the enable signal output by the voltage adjustment unit and the threshold voltage of the critical path of the chip corresponding to the oscillating loop circuit. The encoding circuit generates a corresponding target encoded signal based on multiple pulse signals; The voltage adjustment unit generates a voltage adjustment signal based on the target encoded signal and preset conditions; The chip power supply unit adjusts the chip's operating voltage according to the voltage adjustment signal.

Images