Spaceborne solid-state memory supporting on-orbit program reconfiguration

Abstract

The application discloses a kind of support in-orbit program reconfiguration's satellite-borne solid-state memory, belong to electronic information field.Satellite-borne solid-state memory includes control core, data storage array, cache unit, refresh loading circuit, interface unit, program storage unit, control core realizes the control of storage array, parse host computer instruction, bad block management, wear leveling and address management, cache unit effectively prevents single event upset error.Storage array avoids the timing violation of FPGA that can appear under high main frequency and other difficult problems.Load refresh circuit uses refresh loading circuit to refresh FPGA internal program regularly, reduces the influence of single event upset.Interface unit realizes the control management of host computer to satellite-borne solid-state memory.Program storage unit selects storage carrier according to function, storage capacity size, read-write bandwidth requirement.The whole hardware design is with FPGA soft core to realize the control management function of satellite-borne solid-state memory, and special CPU hardware does not have to be designed.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of electronic information technology, and relates to a spaceborne solid-state memory supporting in-orbit program reconstruction. BACKGROUND

[0002] FPGA devices are widely used in the field of spaceflight because of rich programmable resources, high-grade anti-radiation and the like, and can replace special storage controllers in the field of spaceborne solid-state storage.

[0003] At present, CPU+FPGA architecture is mostly used in the field of spaceborne solid-state memory products and design, and the CPU usually adopts processors such as 8051, SPARC V8 and ARM. These processors are extremely expensive due to the adoption of anti-radiation design, which is contrary to the increasingly fierce market competition. The soft core in the FPGA is built by the general resources in the FPGA, and has better flexibility and portability than the hard core. The adoption of the soft core to replace the CPU outside the FPGA can effectively reduce the cost of components. In order to ensure the redundancy and disaster recovery of the spaceborne solid-state memory in orbit, program reconstruction is usually designed. Taking Xilinx series FPGA as an example, the configuration bit stream size is from 4MB to 35MB, and the size of the soft core program based on the FPGA is about hundreds of KB. In actual application, the updating frequency of the FPGA configuration bit stream is much lower than that of the soft core program. The soft core program and the FPGA configuration bit stream are the same file in the prior art, and the whole file needs to be replaced during updating. Under the current status of the highest Mbps level of the space-ground channel, the program updating efficiency is low. SUMMARY

[0004] The application aims to solve the problem of low program updating efficiency in the prior art that the soft core program and the FPGA configuration bit stream are the same file, and the whole file needs to be replaced during updating, and under the current status of the highest Mbps level of the space-ground channel, and provides a spaceborne solid-state memory supporting in-orbit program reconstruction.

[0005] To achieve the above-mentioned purpose, the application adopts the following technical solutions:

[0006] The application provides a spaceborne solid-state memory supporting in-orbit program reconstruction, which comprises a control core, a data storage array, a cache unit, a refreshing and loading circuit, a program storage unit and an interface unit. The control core comprises a soft core and a logic unit. The control core, the interface unit and the refreshing and loading circuit all interact with an upper computer.

[0007] The soft core interacts with the logic unit for on-board solid-state memory erasing, recording, playback timing starting and combining; the cache unit interacts with the logic unit for realizing recording, playback data caching, sorting and combining; the data storage array interacts with the control core for realizing state detection, fault management, redundancy strategy management execution and timing control of the storage array; the refresh loading circuit interacts with the control core for controlling core program loading refresh; the interface unit interacts with the control core for realizing on-board solid-state memory data interaction; the program storage unit interacts with the control core for loading command word detection, program partition loading and parameter storage.

[0008] Preferably, the logic unit comprises recording process cache management, playback process cache management, data scheduling control and array controller.

[0009] During the recording process, data enters the logic unit in the control core from the interface unit, the data scheduling control calls the recording process cache management to store the data into the cache unit, after the completion of the caching, the recording process cache management performs data sorting and combining to store into the storage array unit through the array controller;

[0010] The playback process is opposite to the recording process, the array controller takes out the stored data from the data storage array, the data scheduling control puts the data into the cache unit through the playback process cache management, and then sends the data to the upper computer through the interface unit after the data sorting.

[0011] Preferably, the refresh loading circuit is connected with a NOR FLASH.

[0012] Preferably, the soft core interacts with the logic unit through an AXI bus; the control core interacts with the upper computer through a CAN bus; and the refresh loading circuit interacts with the upper computer through an RS422.

[0013] Preferably, the steps of on-orbit program reconstruction in the soft core are as follows: power-on solidification, soft core loading detection, soft core program reconstruction and FPGA program reconstruction.

[0014] Preferably, the power-on solidification step is as follows:

[0015] 1) The upper computer sends a program loading instruction to the loading refresh circuit, loads the FPGA.bit to the loading refresh circuit, and guides the program to be loaded into the soft core to run;

[0016] 2) The soft core checks the command word in the program storage unit, and enters the waiting reconstruction process;

[0017] 3) The upper computer sends a reconstruction instruction to the soft core, and updates the application program to the program storage unit;

[0018] 4), after the update is completed, the host computer sends a pre-run instruction to the boot program of the soft core, the boot program guides the loading of the application program into the cache unit and executes, the soft core feeds back to the host computer that it enters the pre-run state, and the host computer sends a reconfiguration exit instruction to the soft core;

[0019] 5), after the application program of the soft core receives the reconfiguration exit instruction, the command word is backfilled into the program storage unit;

[0020] 6), the host computer sends a loading instruction to the loading refresh circuit to restart the system, and the application program starts normal operation.

[0021] Preferably, the soft core loading detection step is as follows:

[0022] 1), the boot program is normally loaded and runs, and whether normal loading is achieved is judged through the loading completion pin of the loading refresh circuit;

[0023] 2), after the command word in the program storage unit is detected to exist, the application program is directly loaded from the program storage unit into the cache unit for execution.

[0024] Preferably, the soft core program reconfiguration step is as follows:

[0025] 1) the host computer sends a reconfiguration entry query application program system state; when the system state is idle, the host computer sends a reconfiguration start instruction, erases the command word in the program storage unit, and then normally returns a response, at this time, the system needs to be powered on again;

[0026] 2) the system is powered on to load and run the boot program, checks that the command word does not exist, and enters the reconfiguration flow;

[0027] 3), the host computer sends a reconfiguration instruction to update a new application program into the program storage unit;

[0028] 4), after the update is completed, the host computer sends a pre-run instruction to the boot program, and the boot program guides the loading of the application program into the cache unit and executes;

[0029] 5), the host computer sends a reconfiguration entry instruction and a reconfiguration exit instruction;

[0030] 6), after the application program receives the reconfiguration exit instruction, it indicates that the reconfiguration mode is exited, and the command word is backfilled into the program storage unit;

[0031] 7), the host computer sends a loading instruction to the loading refresh circuit to restart the system, the application program starts normal operation, and the reconfiguration process is completed.

[0032] Preferably, the program reconfiguration step is as follows:

[0033] 1) The host computer controls the NorFlash erasing instruction sent by the loading refresh device through the UART bus, performs the erasing operation on the FPGA.bit, and reads back the state variable to determine whether the erasing is completed;

[0034] 2) The host computer sends the reconfiguration program data to the loading refresh circuit through the UART bus, and performs the NorFlash programming operation;

[0035] 3) After the programming is completed, the host computer sends the program check instruction to the loading refresh circuit to perform the program check, and after the NorFlash program check is performed, the loading refresh circuit feeds back the check result to the host computer, and the host computer controls the power-off;

[0036] 4) The host computer sends the loading instruction to the loading refresh circuit to restart the system, and the reconfiguration is completed.

[0037] Preferably, the cache unit is composed of five DDRs.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] The application provides a satellite-borne solid-state memory supporting on-orbit program reconstruction, which can partially or totally reconstruct a soft-core program, and has important significance for reducing the production and development cost of the satellite-borne solid-state memory and improving the reliability. Specifically, the control core is a key unit of the satellite-borne solid-state memory, and is composed of a soft core and a logic unit to realize the control of a storage array, the analysis of a host computer instruction, bad block management, wear leveling, and address management. The cache unit can effectively prevent single event upset errors. The cache unit has two functions, one is to design a data cache unit to ensure that data is not lost during data recording based on the feature that the data storage array cannot be directly written and must be erased before writing programming operation is performed; and the other is to serve as a memory of the soft core, and an application program of the soft core runs in the memory. The data storage array ensures that the NAND FLASH works at a low frequency, thereby meeting the bandwidth requirement of the host computer for the satellite-borne solid-state memory and avoiding the timing violation problem of the FPGA at a high frequency. The NAND FLASH in the data storage array is operated in parallel, and the control core generates an instruction sequence of all the NAND FLASH of the storage array at the same time. The loading and refreshing circuit is used to refresh the internal program of the FPGA at a fixed time to reduce the influence of the single event upset. The interface unit is a communication management unit of the satellite-borne solid-state memory and the host computer. The program storage unit selects a storage carrier according to the function, the storage capacity, and the read-write bandwidth requirement, and the program storage unit is selected as a program storage area in the application. Compared with the prior art, the hardware design mainly focuses on the realization of the control and management functions of the satellite-borne solid-state memory by the FPGA soft core, and a special CPU hardware does not need to be designed. The soft core completely replaces the CPU in the function, and mainly realizes the functions of instruction analysis, bad block management, and address management. Since the use of the CPU device is reduced, the satellite-borne solid-state memory designed in the application has advantages in updating efficiency and weight compared with the prior art.

[0040] Further, the cache unit is realized by DDR, 5 pieces of DDR realize 64+8 EDAC design, and can effectively prevent single event upset errors. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0042] Figure 1 The figure is a hardware architecture diagram of the satellite-borne memory of the application.

[0043] Figure 2 A soft core system diagram of the present application.

[0044] Figure 3 A first power-on flowchart of the present application.

[0045] Figure 4 A soft core disaster mitigation detection flowchart of the present application.

[0046] Figure 5 A soft core program reconfiguration flowchart of the present application.

[0047] Figure 6 An FPGA program reconfiguration flowchart of the present application. DETAILED DESCRIPTION

[0048] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0050] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0051] In the description of the embodiments of the present application, it should be noted that if the terms "upper", "lower", "horizontal", "inner" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the present application. In addition, the terms "first", "second" and the like are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0052] In addition, if the term "horizontal" is used, it is not meant to require absolutely horizontal surfaces, but rather can be slightly inclined. As such, the term "horizontal" is used to merely mean more horizontal than "vertical" as the term is used in this description.

[0053] In the description of the embodiments of the present application, it should also be noted that unless specifically defined and limited otherwise, if the terms "set", "install", "connect", "connect" appear, they should be understood in a broad sense, for example, they can be fixedly connected, or can be detachably connected, or integrally connected; can be mechanically connected, or can be electrically connected; can be directly connected, or indirectly connected through an intermediate medium, or can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0054] The present application will be described in further detail below with reference to the accompanying drawings:

[0055] The present application proposes a spaceborne solid-state memory supporting on-orbit program reconstruction, which is a key spaceborne device, and mainly functions to complete recording and playback of on-orbit data. The spaceborne solid-state memory designed in the present application is composed of six modules of control core, data storage array, cache unit, refresh loading circuit, interface unit and program storage unit, as shown in Figure 1 The control core needs to select an FPGA with soft core function instead of a separate CPU processor for cost reduction, and the functions of each module are as follows:

[0056] Control core: The control core is a key unit of the spaceborne solid-state memory of the present application, and realizes control of the storage array, analysis of the host computer instructions, bad block management, wear leveling and address management. In the present application, the control core is an SRAM type FPGA with a Microblaze soft core. The control core is composed of a soft core and a logic unit. The soft core is used as a processor to interact with the FPGA logic part through an AXI bus to control the array controller to realize file management, NAND FLASH bad block management, wear leveling management and other functions. Considering the radiation requirements of space application, the Microblaze soft core in the present application is designed in three modes. The logic unit includes record process cache management, playback process cache management, data scheduling control and array controller. In the recording process, data enters the logic unit in the control core from the interface unit, the data scheduling control stores the data into the cache unit by calling the record process cache management, and after the cache is completed, the record process cache management sorts and combines the data to store into the storage array unit through the array controller. The playback process is opposite to the recording process. The array controller takes out the stored data from the data storage array, and the data scheduling control puts the data into the cache unit through the playback process cache management, and then sends the data to the host computer through the interface unit after sorting the data.

[0057] Cache Unit: The cache unit in this invention adopts a radiation-resistant design and is implemented using DDR memory. Five DDR chips implement a 64+8 EDAC design, which can effectively prevent single-event faults. The cache unit has two functions: first, based on the characteristic that the storage medium NAND FLASH cannot be directly written to and must first undergo an erase operation before a write programming operation can be performed, the data cache unit is designed to ensure that data is not lost during data recording; second, it serves as the memory of the soft-core processor, in which the soft-core application runs.

[0058] Data storage array: Spaceborne storage systems have gone through three development stages: SRAM, SDRAM, and NAND FLASH. Ultimately, NAND FLASH became the primary storage medium in spaceborne storage systems due to its high storage density, low cost, and non-volatility. Unlike commercial SSDs which use high clock speeds and low bit widths, this invention features a high bit width storage array. This ensures that the NAND FLASH operates at a relatively low clock speed, meeting the bandwidth requirements of the host computer for the spaceborne solid-state storage, thus avoiding timing violations and other problems that may occur with FPGAs at high clock speeds. All NAND FLASH operations in the storage array are performed in parallel, with the control core generating a sequence of instructions for all NAND FLASH chips simultaneously.

[0059] Loading and refreshing circuit: To address the issue of poor single-event upset (SEI) resistance in SRAM-based FPGAs, a loading and refreshing circuit is used to periodically refresh the internal program of the FPGA, reducing the impact of SEI. The FPGA loading and refreshing circuit uses SelectMAP mode for loading.

[0060] Interface Unit: The interface unit includes a control interface and a data interface, serving as the communication management unit between the onboard solid-state memory and the host computer. The data interface, which can use interfaces such as 2711, LVDS, and GTH, is primarily responsible for data transmission. The control interface is mainly responsible for receiving and transmitting instructions from the host computer to enable control and management of the onboard solid-state memory. The control interface primarily uses low-speed interfaces such as 1553B, CAN, and UART buses.

[0061] Program storage unit: In this invention, the program storage unit is selected as the storage medium based on its function, storage capacity, and read / write bandwidth requirements. In this invention, the program storage unit is selected as the program storage area.

[0062] Compared with existing technologies, the entire hardware design focuses on implementing the control and management functions of the spaceborne solid-state memory using FPGA soft cores. There is no need to design dedicated CPU hardware. The soft core completely replaces the CPU in terms of functionality, mainly implementing functions such as instruction parsing, bad block management, and address management. Due to the reduction of the use of CPU devices, the spaceborne solid-state memory designed in this invention has advantages over current technologies in terms of cost, weight, and size.

[0063] To improve the flexibility and reliability of on-orbit use of spaceborne solid-state storage (SSD), and to provide a platform for software-defined storage, a strategy supporting partial program refactoring was designed. The external host computer and loading / refreshing circuitry of the spaceborne SSD interact via CAN bus and UART. Nor FLASH and program storage units are used as the program storage area, and DDR is selected as the application program. (See schematic diagram). Figure 1 Two program storage areas are designed: the bootloader and FPGA bitstream are merged into a configuration program and stored in Nor FLASH, while the application program is stored in MRAM memory.

[0064] like Figure 2 As shown, the FPGA configuration bitstream that needs to be updated is defined as FPGA.bit in this invention. The on-orbit program reconfiguration in the soft core includes four parts: initial power-on solidification, soft core loading detection, soft core program reconfiguration, and FPGA program reconfiguration.

[0065] Part 1: Initial power-on curing, such as Figure 3 As shown;

[0066] Upon initial power-up, the configuration program, which combines the FPGA.bit and the bootloader, is first burned into the Nor Flash of the bitstream storage area by the host computer through a loading refresh circuit, thus completing the preparation for program reconstruction.

[0067] Process steps:

[0068] 1) When the system is powered on, the host computer sends a program loading command to the loading and refresh circuit, loading FPGA.bit into the loading and refresh circuit and guiding the program to be loaded into the soft core for execution;

[0069] 2) If no command word is found in the program storage unit, proceed to the waiting refactoring process;

[0070] 3) The host computer sends a reconstruction command to update the application program in the program storage unit;

[0071] 4) After the update is completed, the host computer sends a pre-run instruction to the bootloader. The bootloader loads the application into the cache unit and executes it. At this time, the host computer is required to send a refactoring entry instruction and a refactoring exit instruction to ensure that the application supports the refactoring function during operation.

[0072] 5) After receiving the refactoring exit instruction, the application indicates that it has exited the refactoring mode and fills the command word back into the program storage unit;

[0073] 6) The system restarts, and the application begins to run normally.

[0074] Part Two: Soft Core Loading Detection, such as Figure 4 As shown;

[0075] Upon initial power-up, after the injection process is complete, the system checks whether the soft core has loaded correctly. The conditions for normal soft core loading are: the bootloader has been loaded into Norflash, and the application program has been loaded into the program storage unit.

[0076] Process steps:

[0077] 1) When the system is powered on, the boot program loads and runs normally. The loading completion pin of the loading refresh circuit is used to determine whether the loading is normal.

[0078] 2) If the command word is detected in the program storage unit, the application is directly loaded from the program storage unit into the cache unit for execution.

[0079] Part Three: Soft-core program refactoring, such as Figure 5 As shown;

[0080] For a soft-core program to be refactored, it must be ensured that the soft-core program is running normally. The program refactoring process is executed while the soft-core program is running normally.

[0081] Process steps:

[0082] 1) First, the host computer sends a reconfiguration request to query the application system status;

[0083] 2) If the system status is returned as idle, the host computer will send a reconstruction start command, erase the command word in the program storage unit, and then return a normal response.

[0084] 3) At this point, the system needs to be powered on again. The host computer sends a loading command to the loading and refreshing circuit to restart the system.

[0085] 4) Upon system power-up, the bootloader is loaded and runs. If the command word is missing, the refactoring process begins.

[0086] 5) The host computer sends a reconstruction command to update the new application to the program storage unit;

[0087] 6) After the update is complete, the host computer sends a pre-run instruction to the bootloader, which then loads the application into the cache unit and executes it;

[0088] 7) At this point, the host computer is required to send reconstruction entry and reconstruction exit commands to ensure that the application supports reconstruction functionality during operation.

[0089] 8) After receiving the refactoring exit instruction, the application indicates that it is exiting the refactoring mode and fills the command word back into the program cache unit;

[0090] 9) The host computer sends a loading command to the loading and refreshing circuit to restart the system, and the application starts to run normally, thus completing the reconstruction process.

[0091] Part Four: Program Refactoring, such as Figure 6 As shown;

[0092] 1) Upon power-on, the host computer sends a loading command to the loading and refresh circuit;

[0093] 2) The host computer controls the loading and refreshing circuit to send the NorFlash erase command through the UART bus to perform the erase operation on FPGA.bit, and reads back the status variable to determine whether the erase is complete;

[0094] 3) The host computer sends the reconfiguration program data to the loading and refresh circuit via the UART bus to perform NorFlash programming operations;

[0095] 4) After programming is completed, the program is verified, and the host computer controls the power-off.

[0096] 5) The host computer sends a loading command to the loading and refreshing circuit, the system restarts, and the reconstruction is complete.

[0097] Compared with current technologies, the program refactoring strategy can perform partial refactoring or full refactoring of soft core and FPGA programs, accurately locate the refactoring content, and effectively improve refactoring efficiency, especially when only the soft core program needs to be updated. The lightweight design of the refactoring program avoids the waste of on-orbit satellite-to-ground link communication.

[0098] The control core uses JFM7VX690T36 to handle high-speed data interfaces for input and output and cache management; it manages the internal data channels, packages data, addresses, instructions and other information into specific data packets according to the memory's specified format, realizes write, read and erase operations on the FLASH array, and reflects the array's working status to the processor; it also manages the internal recording, playback and simultaneous recording and playback task scheduling.

[0099] The data storage array uses the SLC-type NAND FLASH substrate SM29F512G08SRM. The product contains 17 NAND FLASH chips, 16 of which are active chips, and 1 is used to store RS (Reverse Error Correction) codes. RS error correction and detection are performed on the data stored in the first 16 FLASH chips. These 16 chips form a 9.6Tb storage space. A single SM29F512G08SRM has an installed storage capacity of 848Gb. Considering error correction and detection coding efficiency (168 / 182), the effective storage capacity is 782Gb. Considering the initial bad blocks (1884 / 2012), the effective storage capacity is 732Gb. The total capacity of the storage array is approximately 11.43Tb, with an active capacity of 9.6Tb and a backup capacity of 1.83Tb. The ratio of active capacity to backup capacity is approximately 5.2:1, with the backup capacity used for on-orbit bad block replacement.

[0100] The loading and refresh circuit adopts JFMRS01RH and uses timed refresh technology to poll and refresh the SRAM-type main control FPGA, thereby mitigating the impact of SEU on the FPGA and improving the adaptability to the space environment.

[0101] The data buffer unit uses IS46TR16256BL-107MBLA3, which adopts 4+1 EDAC verification method, parallel bit width of 64bit, and clock rate maximum support of 933MHz. The designed clock rate is 533MHz. When used at 80% derating, the interface rate can reach 27.2Gbps.

[0102] The interface unit adopts CAN bus and UART bus, and the 422 bus interface circuit uses JSR26CLV31AF and JSR26CLV32F integrated circuit chips from Institute 58.

[0103] The host computer uses LCSoC3233, which integrates UART; the NOR Flash uses N25Q512A11G1240E; and the MRAM uses LSMR64M08VS4E1.

[0104] This invention proposes a spaceborne solid-state memory (SSD) that supports on-orbit program reconfiguration. The program reconfiguration technology in this invention can update the soft-core program and FPGA configuration bitstream separately, enabling partial or complete reconfiguration of the spaceborne SSD program. This improves the accuracy and efficiency of program reconfiguration, providing a foundation for on-orbit fault handling and functional reconfiguration of spaceborne SSDs, and also providing technical support for software-defined spaceborne SSDs. Ground testing and on-orbit flight verification have shown that the effects are mainly reflected in three aspects: First, the spaceborne SSD reduces costs by 50,000-100,000 RMB due to the reduction in the use of CPU devices, resulting in a significant cost advantage compared to similar products; second, the program reconfiguration design ensures the reliability and flexibility of on-orbit use; and third, it supports partial and complete program reconfiguration, improving the accuracy and efficiency of program reconfiguration and reducing the waste of space-to-ground communication bandwidth.

[0105] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A spaceborne solid-state memory supporting on-orbit program reconfiguration, characterized in that, It includes a control core, a data storage array, a cache unit, a refresh and loading circuit, a program storage unit, and an interface unit; the control core includes a soft core and a logic unit; the control core, the interface unit, and the refresh and loading circuit all interact with the host computer; The soft core interacts with the logic unit to erase, record, and replay the timing sequence of the onboard solid-state memory, and to combine them; the cache unit interacts with the logic unit to implement recording, replaying data caching, sorting, and combining; the data storage array interacts with the control core to implement status detection, fault management, redundancy strategy management, and timing control of the storage array; the refresh loading circuit interacts with the control core to control the core program loading and refreshing. The interface units all interact with the control core to realize data interaction with the onboard solid-state memory; the program storage unit interacts with the control core to load command word detection, program partition loading, and parameter storage; the refresh loading circuit is connected to NOR FLASH. The bootloader and FPGA bitstream are merged into a configuration program and stored in Nor FLASH. The application program is stored in MRAM memory, and the program storage unit is MRAM memory. The steps for on-orbit program refactoring in the soft core are as follows: power-on solidification, soft core loading detection, soft core program refactoring, and FPGA program refactoring. The soft-core program refactoring steps are as follows: 1) The host computer sends a refactoring entry command to query the application system status; when the system status is idle, the host computer sends a refactoring start command, erases the command word in the program storage unit, and returns a normal response. At this time, the system needs to be powered on again; 2) The system powers on and loads the bootloader to run, checks that the command word does not exist, and enters the refactoring process; 3) The host computer sends a refactoring command to update the new application to the program storage unit; 4) After the update is completed, the host computer sends a pre-run command to the bootloader, which loads the application into the cache unit and executes it; 5) The host computer sends a refactoring entry command and a refactoring exit command; 6) After receiving the refactoring exit command, the application indicates that it has exited the refactoring mode and fills the command word back into the program storage unit; 7) The host computer sends a loading command to the loading refresh circuit to restart the system, and the application starts to run normally, completing the refactoring process; The FPGA program refactoring steps are as follows: 1) The host computer controls the load refresher to send a NorFlash erase command via the UART bus to perform an erase operation on the FPGA.bit and reads back the status variables to determine whether the erase is complete; 2) The host computer sends the refactoring program data to the load refresh circuit via the UART bus to perform the NorFlash programming operation; 3) After programming is completed, the host computer sends a program verification command to the load refresh circuit to perform program verification. After performing the NorFlash program verification, the load refresh circuit feeds back the verification result to the host computer, and the host computer controls the power-down; 4) The host computer sends a load command to the load refresh circuit to restart the system, and the refactoring is complete.

2. The spaceborne solid-state memory supporting on-orbit program reconfiguration according to claim 1, characterized in that, The logical unit includes recording process cache management, playback process cache management, data scheduling control, and array controller; During the recording process, data enters the logic unit in the control core from the interface unit. The data scheduling control calls the recording process cache management to store the data into the cache unit. After caching is completed, the recording process cache management sorts and combines the data and stores it into the storage array unit through the array controller. The playback process is the opposite. The array controller retrieves the stored data from the data storage array. The data scheduling control puts the data into the cache unit through the playback process cache management. After data sorting, the data is sent to the host computer through the interface unit.

3. The spaceborne solid-state memory supporting on-orbit program reconfiguration according to claim 1, characterized in that, The soft core interacts with the logic unit via the AXI bus; the control core interacts with the host computer via the CAN bus; and the refresh loading circuit interacts with the host computer via RS422.

4. The spaceborne solid-state memory supporting on-orbit program reconfiguration according to claim 1, characterized in that, The power-on curing steps are as follows: 1) The host computer sends a program loading command to the loading and refresh circuit, loads FPGA.bit into the loading and refresh circuit, and guides the program to be loaded into the soft core for execution; 2) The soft core checks the command words in the program storage unit and enters the waiting reconstruction process; 3) The host computer sends a refactoring command to the soft core to update the application program in the program storage unit; 4) After the update is completed, the host computer sends a pre-run instruction to the soft core's bootloader. The bootloader loads the application into the cache unit and executes it. The soft core reports to the host computer that it has entered the pre-run state. The host computer then sends a refactoring and exit instruction to the soft core. 5) After receiving the refactoring exit instruction, the soft-core application fills the command word back into the program storage unit; 6) The host computer sends a loading command to the loading and refreshing circuit, the system restarts, and the application starts to run normally.

5. The spaceborne solid-state memory supporting on-orbit program reconfiguration according to claim 1, characterized in that, The soft core loading detection steps are as follows: 1) The boot program loads and runs normally. The loading completion pin of the loading refresh circuit is used to determine whether the loading is normal. 2) If the command word is detected in the program storage unit, the application is directly loaded from the program storage unit into the cache unit for execution.

6. The spaceborne solid-state memory supporting on-orbit program reconfiguration according to claim 1, characterized in that, The cache unit consists of five DDRs.

Images