Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a first material layer on the substrate; performing ion implantation on the first material layer to form ion doped regions in the first material layer, a size of the ion doped regions in a first direction is a first size, the first direction is parallel to a surface of the substrate, a size of the ion doped regions in a direction perpendicular to the first direction is a second size, the first size is greater than or equal to the second size; forming a plurality of first mask structures on the first material layer, each first mask structure is located on at least part of a surface of each ion doped region; etching the first material layer to form a plurality of second core structures by taking the first mask structures as masks, each second core structure includes an ion doped region and a sacrifice structure adjacent to the ion doped region; forming a second side wall structure on a sidewall of each second core structure; and removing the sacrifice structure. The method for forming the semiconductor structure improves flexibility of a structure pattern, and improves a process window and compatibility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor structure. Background Technology

[0002] With the development of semiconductor technology, the size of semiconductor devices continues to shrink. In particular, the requirements for the size of metal lines in the back-end fabrication process of integrated circuits have also increased accordingly. Therefore, improving the process to ensure high-quality, small-size metal lines is a topic of extensive research.

[0003] In existing semiconductor fabrication processes below 7nm, self-aligned quadruple patterning (SAQP) is an important method for fabricating small-size metal lines. The SAQP process includes: first, forming a first mandrel pattern; second, depositing a first sidewall pattern on the sidewalls of the first mandrel pattern and removing the first mandrel pattern; third, transferring the first sidewall pattern and using it to form a second mandrel pattern; and fourth, depositing a second sidewall pattern on the sidewalls of the second mandrel pattern and removing the second mandrel pattern. This results in a final pattern pitch that is only one-quarter of the initial pattern pitch, significantly reducing the pattern size.

[0004] However, in existing processes, the pattern of metal lines formed by self-aligned quadruple patterning is determined by the structure of the first mandrel pattern and the second mandrel pattern. It is usually a continuous and equal-length linear structure, and the choice of patterns is very limited. It is difficult to form head-to-head discontinuous metal line structures of various sizes that can be achieved by traditional photolithography processes. Therefore, the flexibility of integrated circuit design is poor. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, which improves the patterning flexibility of the semiconductor structure and enhances the process window and compatibility.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first material layer on the substrate; performing ion implantation on the first material layer to form a plurality of ion-doped regions located within the first material layer, wherein the size of the ion-doped region parallel to a first direction is a first size, and the size of the ion-doped region in a second direction perpendicular to the first direction is a second size, the first size is greater than or equal to the second size, and both the first direction and the second direction are parallel to the substrate surface; forming a plurality of first mask structures on the first material layer, each first mask structure being located at least on a portion of the surface of each ion-doped region; using the first mask structures as masks, etching the first material layer to form a plurality of second mandrel structures, each second mandrel structure including an ion-doped region and a sacrificial structure adjacent to the ion-doped region; forming a second sidewall structure on the sidewall of each second mandrel structure; and removing the sacrificial structure.

[0007] Optionally, the projection pattern of each first mask structure on the surface of the first material layer is a first pattern, and each ion-doped region intersects with only one first pattern.

[0008] Optionally, the first size of each ion-doped region may be the same or different.

[0009] Optionally, the dimension of each first mask structure in the second direction perpendicular to the first direction is a third dimension, and the second dimension is greater than or equal to the third dimension.

[0010] Optionally, the first size is greater than 200 nanometers.

[0011] Optionally, the dopant ions in the ion-doped region include one of boron ions, carbon ions, or germanium ions.

[0012] Optionally, before ion implantation of the first material layer, the method further includes: forming an initial mask layer on the first material layer, the initial mask layer having a mask opening that exposes a portion of the surface of the first material layer.

[0013] Optionally, the process for removing the sacrificial structure includes wet etching.

[0014] Optionally, the etching solution used in the wet etching process may include an alkaline solution.

[0015] Optionally, the process of etching the first material layer using the first mask structure as a mask is a dry etching process.

[0016] Optionally, the method of forming the first mask structure includes: forming a first mandrel structure on a first material layer after forming an ion-doped region; depositing a first mask material layer on the sidewalls and top surface of the first mandrel structure; etching back the first mask material layer on the top surface of the first mandrel structure to form a first mask structure on the sidewall surface of the first mandrel structure; and removing the first mandrel structure.

[0017] Optionally, the method of forming the first mask structure includes: forming an initial material layer on the first material layer after forming the ion-doped region; and patterning the initial material layer to form the first mask structure.

[0018] Optionally, the substrate includes a base and an interlayer dielectric layer located on the base.

[0019] Optionally, after removing the sacrificial structure, the method further includes: using the second sidewall structure and the ion-doped region as a mask, etching the interlayer dielectric layer to form a plurality of isolation structures on the substrate and isolation gaps between the isolation structures.

[0020] Optionally, the method for forming the semiconductor structure further includes forming an electrical interconnect structure within each isolation gap.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] In the semiconductor structure formation method provided by the present invention, before forming the first mask structure, a plurality of ion-doped regions are first formed in the first material layer, and each subsequently formed first mask structure is located at least on a portion of the surface of each ion-doped region. Therefore, after etching the first material layer using the first mask structure as a mask to form a plurality of second core structures, the materials of the ion-doped regions included in the second core structures are different from those of the surrounding sacrificial structures. The ion-doped regions can be retained by selectively removing the sacrificial structures. On the one hand, the pattern formed by the ion-doped regions and the second sidewall structures determines the pattern of the subsequently formed metal lines, breaking through the continuous structure formed by the traditional four-fold self-aligned process and increasing the flexibility of the pattern. On the other hand, for the formation of wider patterns, compared with the patterning process performed by the traditional photolithography process, patterning by ion doping can reduce the impact of the patterning of wider patterns on adjacent structures, making the process window larger and the process less difficult.

[0023] Furthermore, the dimension of the ion-doped region perpendicular to the first direction is the second dimension, and the dimension of the first mask structure perpendicular to the first direction is the third dimension, with the second dimension being greater than or equal to the third dimension. During the subsequent formation of the second mandrel structure, the second dimension of the ion-doped region can be thinned by etching the first material layer until the third dimension is reached. Therefore, the second dimension of the ion-doped region formed by ion implantation of the first material layer can be greater than or equal to the third dimension. Compared to the patterning process performed by traditional photolithography, the formation process of the ion-doped region has a larger process window and lower requirements for the photolithography process during the initial mask layer formation, thus reducing process difficulty and cost. Attached Figure Description

[0024] Figures 1 to 12 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention;

[0025] Figures 13 to 16 This is a schematic diagram of the formation process of a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, in existing semiconductor fabrication processes below 7nm, self-aligned quadruple patterning (SAQP) is an important method for fabricating small-size metal lines. The SAQP process includes: first, forming a first mandrel pattern; second, depositing a first sidewall pattern on the sidewalls of the first mandrel pattern and removing the first mandrel pattern; third, transferring the first sidewall pattern and using it to form a second mandrel pattern; and fourth, depositing a second sidewall pattern on the sidewalls of the second mandrel pattern and removing the second mandrel pattern.

[0027] However, in existing processes, the pattern of metal lines formed by self-aligned quadruple patterning is determined by the structure of the first mandrel pattern and the second mandrel pattern. It is usually a continuous and equal-length linear structure, and the choice of patterns is very limited. It is difficult to form head-to-head discontinuous metal line structures of various sizes that can be achieved by traditional photolithography processes. Therefore, the flexibility of integrated circuit design is poor.

[0028] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. Before forming a first mask structure, a plurality of ion-doped regions are first formed within a first material layer. Each subsequently formed first mask structure is located at least on a portion of the surface of each ion-doped region. Therefore, after using the first mask structure as a mask to etch the first material layer and form a plurality of second core structures, the materials of the ion-doped regions and the surrounding sacrificial structures in the second core structures are different. This allows for selective removal of the sacrificial structures while retaining the ion-doped regions. On one hand, the pattern formed by the ion-doped regions and the second sidewall structures determines the pattern of the subsequently formed metal lines, breaking through the continuous structure formed by the traditional four-fold self-aligned process and increasing the flexibility of the pattern. On the other hand, compared to the patterning process performed by traditional photolithography, patterning through ion doping can reduce the impact of wide-size patterning on adjacent structures, resulting in a larger process window and lower process difficulty.

[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 1 to 12 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0031] Please refer to Figure 1 Substrate 100 is provided.

[0032] In this embodiment, the substrate 100 includes a substrate 101 and an interlayer dielectric layer 102 located on the substrate 101.

[0033] In this embodiment, the interlayer dielectric layer 102 provides raw materials for the isolation structure between the subsequently formed electrical interconnect structures.

[0034] In this embodiment, the material of the substrate 101 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. Specifically, in this embodiment, the material of the substrate 101 is silicon.

[0035] Please refer to Figure 2 and Figure 3 , Figure 2 for Figure 3 A cross-sectional view along the AA' direction. Figure 3 for Figure 2 Top view along the P direction; a first material layer 103 is formed on the substrate 100.

[0036] In this embodiment, the first material layer 103 provides raw materials for the subsequently formed second mandrel structure.

[0037] In this embodiment, the material of the first material layer 103 includes silicon.

[0038] Please refer to Figure 4 , Figure 4 and Figure 3 The view direction is consistent; an initial mask layer 111 is formed on the first material layer 103, and the initial mask layer 111 has a mask opening 112, which exposes part of the surface of the first material layer 103.

[0039] In this embodiment, the initial mask layer 111 acts as a mask during the subsequent ion implantation process.

[0040] In this embodiment, each mask opening 112 defines the pattern of the electrical interconnect structure subsequently formed on the substrate 101, as well as the pattern of the isolation structure located between the electrical interconnect structures.

[0041] Please combine Figures 2 to 4 refer to Figure 5Using the initial mask layer 111 as a mask, ion implantation is performed on the first material layer 103 to form a plurality of ion-doped regions 120 located within the first material layer 103. The dimension of the ion-doped region 120 parallel to the first direction is defined as a first dimension X, and the dimension of the ion-doped region 120 in a second direction perpendicular to the first direction is defined as a second dimension Y. The first dimension X is greater than or equal to the second dimension Y. Both the first and second directions are parallel to the surface of the substrate 100.

[0042] In this embodiment, the first size X of each ion-doped region 120 is different.

[0043] In other embodiments, the first size of each ion-doped region may be the same.

[0044] In this embodiment, during the formation of the initial mask layer 111, in order to avoid the generation of structural defects, the size of the mask opening 112 needs to be larger than the limit size of the photolithography process. Specifically, the size of the mask opening 112 parallel to the first direction needs to be greater than 200 nanometers, so as to form a clear and complete mask opening 112.

[0045] Therefore, in this embodiment, the first size X of each ion-doped region 120 is greater than 200 nanometers.

[0046] In this embodiment, the purpose of ion implantation on the first material layer 103 to form a plurality of ion-doped regions 120 within the first material layer 103 is to differentiate the materials in different regions of the first material layer 103, so that after the first material layer 103 is subsequently etched to form the second mandrel structure, some regions of the second mandrel structure can be selectively removed, thereby enabling more flexible definition of the pattern of the subsequently formed electrical interconnect structure.

[0047] In this embodiment, the dopant ions in the ion-doped region 120 include one of boron ions, carbon ions, or germanium ions.

[0048] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 Top view along the Q direction, Figure 7 for Figure 6 A cross-sectional view along the BB' direction shows that after removing the initial mask layer 111, a plurality of first mask structures 130 are formed on the first material layer 103, and each first mask structure 130 is located at least on a portion of the surface of each ion-doped region 120.

[0049] In this embodiment, the function of each first mask structure 130 being located at least on a portion of the surface of each ion-doped region 120 is that, in subsequent processes, after etching the first material layer 103 using the first mask structure 130 as a mask to form several second mandrel structures, the second mandrel structures include two different materials, thereby allowing for more flexible patterns to be formed by selectively removing a portion of them.

[0050] Please continue to refer to this. Figure 6 In this embodiment, in the second direction perpendicular to the first direction, the size of each first mask structure 130 is a third dimension L, which is equal to the second dimension Y of the ion-doped region 120. Therefore, in this embodiment, the first mask structure 130 can completely cover the ion-doped region 120, thereby reducing structural defects and improving the process window for subsequent etching of the first material layer 103.

[0051] In this embodiment, the method for forming the first mask structure 130 includes: after forming the ion-doped region 120, forming a first mandrel structure (not shown) on the first material layer 103; depositing a first mask material layer (not shown) on the sidewalls and top surface of the first mandrel structure; etching back the first mask material layer on the top surface of the first mandrel structure to form the first mask structure 130 on the sidewall surface of the first mandrel structure; and removing the first mandrel structure.

[0052] In this embodiment, the first mask structure 130 is formed on the sidewall surface of the first mandrel structure via self-alignment. The first mask structure 130 serves as the first sidewall structure, and the pattern of the first mask structure 130 is further transferred downwards through subsequent etching processes. Compared with traditional photolithography processes, the sidewall structure formed by self-alignment can meet the requirements of small-sized device structures, breaking through the size limits of traditional processes.

[0053] In another embodiment, the method of forming the first mask structure includes: forming an initial material layer on a first material layer after forming an ion-doped region; and patterning the initial material layer to form the first mask structure.

[0054] In the above embodiments, the first mask structure is formed by directly patterning the initial material layer, which is relatively simple and has a low cost.

[0055] Please refer to Figure 8 Using the first mask structure 130 as a mask, the first material layer 103 is etched to form a plurality of second core structures 141, each second core structure 141 including an ion-doped region 120 and a sacrificial structure 140 adjacent to the ion-doped region 120.

[0056] In this embodiment, since the materials of the ion-doped region 120 and the sacrificial structure 140 are different, the sacrificial structure 140 can be removed while retaining the ion-doped region 120 by selecting a suitable etching solution, thereby allowing for more flexible adjustment of the pattern of the second mandrel structure 141.

[0057] In this embodiment, the process of etching the first material layer 103 using the first mask structure 130 as a mask is a dry etching process.

[0058] In this embodiment, since the third dimension L of the ion-doped region 120 is equal to the second dimension Y of the ion-doped region 120, the etched material is more uniform during the etching of the first material layer 103, thereby improving the etching process window and reducing defects in the formed second mandrel structure 141.

[0059] In this embodiment, each second mandrel structure 141 includes only one ion-doped region 120.

[0060] In other embodiments, the number of ion-doped regions included in each second mandrel structure may be greater than 1, and the ion-doped regions are spaced apart by sacrificial structures, thereby further increasing the flexibility of the pattern.

[0061] After the second mandrel structure is formed, the first mask structure 130 is removed.

[0062] Please refer to Figure 9 A second sidewall structure 150 is formed on the sidewall of each second spindle structure 141.

[0063] In this embodiment, the self-aligned quadruple patterning process is completed through the pattern formation and transfer of the first mask structure 130, the second mandrel structure 141 and the second sidewall structure 150, so that the final pattern pitch is only one-quarter of the initial pattern pitch, which greatly reduces the pattern size.

[0064] In this embodiment, the method for forming the second sidewall structure 150 includes: depositing a second sidewall material layer (not shown) on the sidewall and top surface of the second mandrel structure 141; and etching back the second sidewall material layer on the top surface of the second mandrel structure 141 to form the second sidewall structure 150 located on the sidewall surface of the second mandrel structure 141.

[0065] In this embodiment, the material of the second sidewall structure 150 is the same as that of the first mask structure 130, and the material of the second sidewall structure 150 is different from that of the first material layer 103.

[0066] Please refer to Figure 10 Remove the sacrificial structure 140.

[0067] In this embodiment, by removing the sacrificial structure 140 and retaining the ion-doped region 120, the pattern formed by the ion-doped region 120 and the second sidewall structure 150 determines the pattern of the subsequently formed electrical interconnect structure and isolation structure. This structure breaks through the continuous linear structure formed by the traditional four-fold self-aligned process and increases the flexibility of the pattern.

[0068] In this embodiment, the process for removing the sacrificial structure 140 includes a wet etching process. Specifically, the etching solution used in the wet etching process includes an alkaline solution, which allows the sacrificial structure 140 to be removed without affecting the ion-doped region 120 and the second sidewall structure 150.

[0069] Please refer to Figure 11 Using the second sidewall structure 150 and the ion-doped region 120 as a mask, the interlayer dielectric layer 102 is etched to form a plurality of isolation structures 160 on the substrate 101 and isolation gaps (not shown) between each isolation structure 160.

[0070] In this embodiment, the isolation gap provides space for the subsequent electrical interconnect structure.

[0071] In this embodiment, the etching process for the interlayer dielectric layer 102 includes a dry etching process.

[0072] Please refer to Figure 12 Electrical interconnection structure 162 is formed within each isolation gap.

[0073] In this embodiment, the material of the electrical interconnect structure 162 includes metal.

[0074] In the formation of the semiconductor structure in this embodiment, the sacrificial structure 140 is selectively removed while the ion-doped region 120 is retained. Therefore, on the one hand, the pattern formed by the ion-doped region 120 and the second sidewall structure 150 determines the pattern of the formed isolation structure 160 and electrical interconnect structure 162, breaking through the continuous linear structure formed by the traditional four-fold self-alignment process and forming head-to-head structures of various sizes. The intermittent electrical interconnect structure 162 at the head of the ion-doped region 120 becomes the intermittent isolation structure between the two ends of the intermittent electrical interconnect structure 162 (as shown in region C), thereby increasing the flexibility of the pattern. On the other hand, due to the limitations of the photolithography process in forming the initial mask layer 111, the size of each ion-doped region 120 needs to be larger than the photolithography limit size. Therefore, the size of the intermittent isolation structure between the electrical interconnect structures 162 is wider. Compared with the patterning process performed by the traditional photolithography process, the patterning by ion doping in this embodiment can reduce the impact of the patterning of wide-sized patterns on adjacent structures, thereby providing a better and more flexible method for forming head-to-head intermittent electrical interconnect structures. The process window is larger, and the resulting electrical interconnect structure 162 has better structural uniformity and fewer defects.

[0075] Figures 13 to 16 This is a schematic diagram of the formation process of a semiconductor structure according to another embodiment of the present invention.

[0076] Please Figures 1 to 5 Based on reference Figure 13 The method for forming a semiconductor structure includes: providing a substrate (not shown), the substrate including: a base and an interlayer dielectric layer located on the base; forming a first material layer 203 on the substrate; performing ion implantation on the first material layer 203 to form a plurality of ion-doped regions 220 located within the first material layer 203; and forming a plurality of first mask structures 230 on the first material layer 203.

[0077] In this embodiment, the structure and material of the substrate and the first material layer 203 are similar to those of the substrate and the first material layer 203. Figures 1 to 5 The substrate 100 and the first material layer 103 have the same structure and material.

[0078] In this embodiment, the method for forming the ion-doped region 220 is the same as... Figure 5 The method for forming the ion-doped region 120 is the same, and will not be described in detail here.

[0079] In this embodiment, the dimension of the ion-doped region 220 parallel to the first direction is the first dimension, the first direction is parallel to the substrate surface, the dimension of the ion-doped region 220 perpendicular to the first direction is the second dimension H1, and the dimension of each first mask structure 230 perpendicular to the first direction is the third dimension H2. The second dimension H1 is greater than the third dimension H2.

[0080] In this embodiment, since the mandrel pattern that needs to be retained is defined by ion implantation, and the area in the ion-doped region 220 that extends beyond the coverage of the first mask structure 230 can be removed by a subsequent dry etching process, the second size H1 of the ion-doped region 220 does not need to be limited to the small size of the third size H2 of the first mask structure 230. This makes the formation process window of the ion-doped region 220 larger and the formation difficulty of the ion-doped region 220 lower.

[0081] In this embodiment, the projected pattern of each first mask structure 230 on the surface of the first material layer 203 is a first pattern, and each ion-doped region 220 intersects with only one first pattern. The boundary of the ion-doped region 220 reaches as far as but does not touch the boundary of the adjacent first mask structure 230, thereby ensuring that the first material layer 203 at the bottom of other adjacent first mask structures 230 is not affected by ion implantation, thus avoiding unnecessary residues in subsequent processes when removing the un-ion-implanted first material layer 203.

[0082] Please refer to Figure 14 Using the first mask structure 230 as a mask, the first material layer 203 is etched to form a plurality of second core structures 241, each second core structure 241 including an ion-doped region 220 and a sacrificial structure 240 adjacent to the ion-doped region 220.

[0083] In this embodiment, the process of etching the first material layer 203 using the first mask structure 230 as a mask is a dry etching process.

[0084] In this embodiment, since the formation of the ion-doped region 220 does not affect the dry etching process, by etching the first material layer 203, the area of ​​the ion-doped region 220 that exceeds the coverage of the first mask structure 230 can be removed, thereby thinning the second dimension H1 of the ion-doped region 220 until the third dimension H2 is reached, thus enabling the formed second mandrel structure 241 to... Figure 8 The second mandrel structure 141 shown has the same dimensions and structure.

[0085] In this embodiment, compared with the patterning process performed by traditional photolithography, the process window for forming the ion-doped region 220 is larger, and the photolithography requirements for the mask layer used in the formation of the ion-doped region 220 are lower. This reduces the process difficulty and cost without affecting the self-alignment process.

[0086] Please refer to Figure 15 A second sidewall structure 250 is formed on the sidewall of each second spindle structure 241; the sacrificial structure 240 is removed.

[0087] In this embodiment, the method for forming the second sidewall structure 250 and the method for removing the sacrificial structure 240 are as follows: Figure 9 and Figure 10 The details will not be elaborated upon here.

[0088] Please refer to Figure 16 Using the second sidewall structure 250 and the ion-doped region 220 as a mask, the interlayer dielectric layer is etched to form a plurality of isolation structures 260 on the substrate and isolation gaps between each isolation structure 260; an electrical interconnect structure 262 is formed in each isolation gap.

[0089] In this embodiment, the method for forming the isolation structure 260 and the electrical interconnection structure 262 is as follows: Figure 11 and Figure 12 This will not be elaborated upon here.

[0090] In this embodiment, the materials and structures of the isolation structure 260 and the electrical interconnection structure 262 are the same as those of the isolation structure 260 and the electrical interconnection structure 262. Figure 11 and Figure 12 The isolation structure 160 and the electrical interconnection structure 162 are made of the same material and have the same structure.

[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first material layer is formed on the substrate; Ion implantation is performed on a first material layer to form a plurality of ion-doped regions located within the first material layer. The size of the ion-doped region parallel to a first direction is a first size, and the size of the ion-doped region in a second direction perpendicular to the first direction is a second size. The first size is greater than or equal to the second size, and both the first direction and the second direction are parallel to the substrate surface. A plurality of first mask structures are formed on the first material layer, and each first mask structure is located at least on a portion of the surface of each ion-doped region; Using the first mask structure as a mask, the first material layer is etched to form a plurality of second core structures, each of the second core structures including an ion-doped region and a sacrificial structure adjacent to the ion-doped region; A second sidewall structure is formed on the sidewall of each second core shaft structure; Remove the sacrificial structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projection pattern of each of the first mask structures onto the surface of the first material layer is a first pattern, and each ion-doped region intersects with only one first pattern.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first size of each ion-doped region may be the same or different.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dimension of each of the first mask structures in the second direction perpendicular to the first direction is the third dimension, and the second dimension is greater than or equal to the third dimension.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first size is greater than 200 nanometers.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dopant ions in the ion-doped region include one of boron ions, carbon ions, or germanium ions.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before ion implantation of the first material layer, the method further includes: forming an initial mask layer on the first material layer, the initial mask layer having a mask opening that exposes a portion of the surface of the first material layer.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the sacrificial structure includes a wet etching process.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The etching solution used in the wet etching process includes an alkaline solution.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of etching the first material layer using the first mask structure as a mask is a dry etching process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming the first mask structure includes: forming a first mandrel structure on the first material layer after forming an ion-doped region; depositing a first mask material layer on the sidewalls and top surface of the first mandrel structure; etching back the first mask material layer on the top surface of the first mandrel structure to form a first mask structure on the sidewall surface of the first mandrel structure; and removing the first mandrel structure.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first mask structure includes: forming an initial material layer on the first material layer after forming an ion-doped region; and patterning the initial material layer to form the first mask structure.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes: a substrate and an interlayer dielectric layer located on the substrate.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, After removing the sacrificial structure, the method further includes: using the second sidewall structure and the ion-doped region as a mask, etching the interlayer dielectric layer to form a plurality of isolation structures on the substrate and isolation gaps between the isolation structures.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Also includes: An electrical interconnection structure is formed within each isolation gap.

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