Instruction encoding method, operation unit, operation module and operation method

Abstract

The present invention provides an encoding method, an operation unit, an operation module and an operation method of an instruction, wherein the instruction comprises an instruction block header and an instruction block body; the instruction block body comprises at least one group of operation codes, and the operation code is used to represent a specific operation operation; the instruction block header can indicate the operation type and execution mode of the operation operation, and the execution mode comprises repeated execution and non-repeated execution; the encoding method of the instruction block header is: a 1-bit operation type identification bit, a 1-bit repeated execution identification bit, and an N-bit execution mode bit arranged in sequence, wherein N is a positive integer; the operation type identification bit is used to indicate whether the operation operation is a specified operation type; the repeated execution identification bit is used to indicate whether the operation operation is repeatedly executed; when the execution mode is repeated execution, the operation code is a group, and the N-bit execution mode bit is used to indicate the number of repeated executions of the operation operation; when the execution mode is non-repeated execution, the N-bit execution mode bit is used to indicate the number of groups of the operation code.

Description

Technical Field

[0001] The present invention relates to the field of electronic digital data processing, and in particular to an instruction encoding method, a computing unit, a computing module and a computing method. Background Art

[0002] An automaton is a mathematical model for processing signal sequences. It is a machine that "jumps" through a series of states based on a transfer condition (which can be expressed as a table) given a symbol input. In the field of automatic control, it refers to a dynamic mathematical model of a discrete digital system, a logical structure, an algorithm, or a symbol string transformation. In computer science, automata are used as dynamic mathematical models of computers and computing processes to study computer architecture, logical operations, program design, and even computational complexity theory. In linguistics, automata are used as language recognizers to study various formal languages. In neurophysiology, automata are defined as dynamic models of neural networks to study neurophysiological activities and thinking patterns and explore the mechanisms of the human brain. In biology, some people use automata as growth and development models of living organisms to study metabolism and genetic variation. In mathematics, automata are used to define computable functions and study various algorithms. An automaton reads the symbols in the input one by one until they are completely exhausted. Once the input is exhausted, the automaton is said to be "stopped". An automaton is mainly composed of "states" and "state transitions" between states. The execution of the automaton "state", or the migration from one "state" to another, is usually implemented by a computer system (software program) based on a general-purpose processor (CPU). The performance that the automaton can achieve depends on the processing power of the processor's computing component, the arithmetic logic unit (ALU).

[0003] The traditional processor computing unit adopts a simple scalar or vector computing architecture. Basically, according to the requirements of the operation instruction, the operand to be processed is read from the system memory unit (mostly DRAM) and loaded into the register. The operation circuit (such as the arithmetic logic unit ALU) performs the operation to obtain the result, and then writes the result back to the system memory unit. In the process of big data computing such as artificial intelligence, it is often necessary to perform cumulative operations similar to polynomial operations on a large amount of data, such as selecting the maximum value from a certain amount of data. In the traditional processing unit, it is necessary to continuously access the memory outside the unit, read and write data for comparison operations, until the maximum value is finally generated. In this process, a large number of storage system access operations for intermediate data are generated. On the other hand, the data to be processed and the operations performed are recorded and expressed in the form of instructions, and they also need to be accessed through the storage system. Therefore, due to the huge amount of system memory access, the computing unit will be limited by the performance of the storage system and cannot meet the increasingly complex algorithm requirements such as artificial intelligence, resulting in resource waste, power loss and performance degradation. This is the so-called performance bottleneck caused by the "memory wall".

[0004] Therefore, how to optimize the use of the storage system to reduce the impact of the corresponding performance bottleneck is a problem that needs to be solved at present. Summary of the invention

[0005] The purpose of the present invention is to propose an instruction encoding method, arithmetic unit, arithmetic module and arithmetic method, which can optimize the use of a storage system and thus reduce the impact of corresponding performance bottlenecks.

[0006] In order to achieve the above object, the present invention provides an encoding method of an instruction, wherein the instruction is applied to an operation unit implemented by a digital automaton state, and the instruction includes an instruction block header and an instruction block body located after the instruction block header; the instruction block body includes at least one set of operation codes, and the operation code is used to represent a specific operation operation; the instruction block header can indicate the operation type and execution mode of the operation operation, and the execution mode includes repeated execution and non-repeated execution;

[0007] The encoding method of the instruction block header is: a 1-bit operation type identification bit, a 1-bit repeat execution identification bit, and an N-bit execution mode bit arranged in sequence, where N is a positive integer;

[0008] The operation type flag is used to indicate whether the operation is of a specified operation type;

[0009] The repeat execution flag is used to indicate whether the operation is to be repeated;

[0010] When the execution mode is repeated execution, the operation code is a group, and the N-bit execution mode bit is used to indicate the number of repeated executions of the operation;

[0011] When the execution mode is non-repeated execution, the N-bit execution mode bit is used to indicate the number of groups of the operation code.

[0012] In the optional scheme, the operation types include arithmetic operations, relational operations and logical operations; the arithmetic operations include addition operations, sign reversal operations, multiplication operations, and reciprocal operations; the relational operations include: greater than operations, less than operations, equal to operations, and inequality operations; the logical operations include: and operations, or operations, and not operations; the operations under each of the operation types have a unique operation code.

[0013] In an optional solution, the operation code of one of the arithmetic operation, the relational operation and the logical operation is a 2-bit binary code, and the operation codes of the other two operations are a 3-bit binary code or a 4-bit binary code.

[0014] In an optional solution, the specified operation type is the arithmetic operation; the operation code of the arithmetic operation is a 2-bit binary code, and the operation code of the relational operation and the logical operation is a 4-bit binary code.

[0015] In an optional solution, N is between 2-4.

[0016] The present invention also provides a digital automaton state realization operation unit, comprising:

[0017] A storage module, used to store instructions and data to be operated, wherein the instructions adopt the above-mentioned encoding method;

[0018] A processing module, used to parse the instructions and, based on the parsed results, perform computations on the input data in each working cycle;

[0019] The temporary storage module is used to temporarily store the calculation results of the current working cycle of the processing module, and input the calculation results to the processing module in the next working cycle to participate in new calculations, and after all the instructions are executed, output the final calculation results to the storage module.

[0020] In an optional solution, the processing module includes a decoding and control unit, processing units of different operation types, and a first multiple-choice module;

[0021] The multiple input terminals of the first multiple-select-one module are connected to the output terminals of the processing units of different operation types, and the output terminal of the first multiple-select-one module is connected to the input terminal of the temporary storage module;

[0022] The decoding and control unit is used to parse the instruction, determine the operation type, execution mode, number of operation code groups or the number of repeated executions of the operation contained in the instruction, and when it is determined that the data of the temporary storage module needs to participate in the operation of the next working beat, the output of the temporary storage module is input to the processing unit.

[0023] In an optional solution, the processing units of different operation types include: an arithmetic processing unit, a relational processing unit and a logical processing unit;

[0024] The corresponding operation types are arithmetic operation, relational operation and logical operation.

[0025] In an optional solution, the processing module includes an instruction input terminal, two data input terminals and a data output terminal;

[0026] The instruction input terminal is used to input the instruction;

[0027] The data input terminal is used to input data to be involved in the calculation;

[0028] The data output terminal is used to output the operation result;

[0029] The two data input terminals of the processing module input data respectively through a second multiple-choice module;

[0030] The two input ends of the second multiple-select-one module are respectively connected to the output ends of the storage module and the temporary storage module;

[0031] The decoding and control unit is used to control the effective input end of the second multiple-select-one module;

[0032] The output of the processing module is connected to an input terminal of the storage module.

[0033] In an optional solution, the computing unit further includes a transmission module, which is communicatively connected to the storage module and is capable of bidirectional transmission of information, as well as bidirectional information transmission between the computing unit and the outside.

[0034] The present invention also provides a computing method, wherein the required instructions adopt the encoding method of the above-mentioned instructions, and the method comprises:

[0035] Parsing the instruction to determine the operation type, execution mode, number of operation code groups or number of repetitions of the operation contained in the instruction, and whether the instruction is a continuous operation;

[0036] Calculations are performed based on the analysis results, and when it is determined that the instruction is a continuous operation, the calculation result of the current working beat is directly used as the input of the next working beat, and participates in the calculation of the next working beat until all the calculation operations indicated in the instruction block of the instruction are executed.

[0037] The present invention also provides a computing module, comprising a dispatching structure, a dispatching structure input unit, a dispatching structure output unit and a plurality of the above computing units;

[0038] The dispatch structure input unit has multiple input ports, each of which is connected to the output of an operation unit, and the dispatch structure input unit is used to input processed data to the dispatch structure; the dispatch structure output unit has multiple output ports, each of which is connected to the input of an operation unit, and the dispatch structure output unit is used to provide the required data to be processed to the operation unit; multiple operation units work in parallel.

[0039] The present invention also provides a processor, comprising the above-mentioned operation unit or the above-mentioned operation module implemented by the digital automaton state.

[0040] The beneficial effects of the present invention are:

[0041] The present invention proposes a new instruction encoding format and a corresponding implementation structure for continuous operation, and adopts the method of instruction block header + instruction block body to realize multiple continuous operation operations (i.e. continuous operation, which can be a repeated operation or multiple non-repeating operations). In the prior art, each operation operation requires an instruction encoding, and these instruction encodings usually contain common repeated information, such as operation type, etc. The present invention puts the repeated common information in the instruction block header, integrates the repeated information of multiple instructions into one instruction encoding, eliminates the repeated information in each instruction encoding, and saves the number of bits occupied by the entire instruction encoding. In this way, the capacity requirements for storing and transmitting instructions are saved, thereby reducing the impact of performance bottleneck factors such as "memory wall" in the computing system. On the other hand, this instruction encoding and implementation structure for the continuous execution of specified operations defaults to transferring data through the cache module, shortening the processing interval between operations, thereby improving the execution speed of operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0043] Figure 1 It is a schematic diagram of the structure of the operation unit for realizing the state of a digital automaton in one embodiment of the present invention.

[0044] Figure 2 FIG. 4 is a schematic diagram of the structure of a computing module in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0046] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0047] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] Example 1

[0050] This embodiment provides an encoding method of an instruction, wherein the instruction is applied to an operation unit implemented by a digital automaton state, and the instruction includes an instruction block header and an instruction block body located after the instruction block header; the instruction block body includes at least one set of operation codes, and the operation code is used to represent a specific operation operation; the instruction block header can indicate the operation type and execution mode of the operation operation, and the execution mode includes repeated execution and non-repeated execution;

[0051] The encoding method of the instruction block header is: a 1-bit operation type identification bit, a 1-bit repeat execution identification bit, and an N-bit execution mode bit arranged in sequence, where N is a positive integer;

[0052] The operation type flag is used to indicate whether the operation is of a specified operation type;

[0053] The repeat execution flag is used to indicate whether the operation is to be repeated;

[0054] When the execution mode is repeated execution, the operation code is a group, and the N-bit execution mode bit is used to indicate the number of repeated executions of the operation;

[0055] When the execution mode is non-repeated execution, the N-bit execution mode bit is used to indicate the number of groups of the operation code.

[0056] Specifically, the operation types include arithmetic operations, relational operations, and logical operations; the arithmetic operations include addition operations, sign reversal operations, multiplication operations, and reciprocal operations; the relational operations include: greater than operations, less than operations, equal operations, and inequality operations; the logical operations include: and operations, or operations, and negation operations; and the operations under each of the operation types have a unique operation code. Referring to Table 1, Table 2, and Table 3, in this embodiment, the operation code of the arithmetic operation operation is a 2-bit binary code, and the operation code of the relational operation and the logical operation operation is a 4-bit binary code, and the operation operation under each of the operation types has a unique operation code.

[0057] Table 1

[0058] Arithmetic operations Operation Code Add Operation 00 Sign negation operation 01 Multiplication Operation 10 Reciprocal operation 11

[0059] Table 2

[0060] Relational operations Operation Code Less Than Operation 0000 Greater Than Operation 0001 Equals Operation 0010 Not equal to operation 0011

[0061] Table 3

[0062] Relational operations Operation Code Non-operational 0100 With operation 0101 Or Operation 0110

[0063] In this embodiment, the specified operation type is an arithmetic operation. When the operation type identification bit is 1, it indicates that the operation type is an arithmetic operation. When the operation type identification bit is 0, it indicates that the operation type is a relational operation or a logical operation or that the instruction is a control instruction. In other embodiments, the operation code of the arithmetic operation operation can also be a 3-bit binary code or a 4-bit binary code, and the operation code of the relational operation or the logical operation operation can be a 3-bit binary code or a 2-bit binary code, etc.

[0064] In this embodiment, the operation code of the arithmetic operation is a 2-bit binary code, which is more suitable for situations where there are more arithmetic operations. The operation code of the relational operation and the logical operation is a 4-bit binary code, the purpose of which is to leave room for expansion and increase the completeness of the instruction set. The expansion includes input and output, control instructions such as: read, write memory, jump and other control instructions. The arithmetic operation, relational operation and logical operation of this embodiment all belong to operation instructions. The decoding and control unit controls whether to obtain data from the temporary storage module and input it to the processing module. When executing the continuous operation instruction block, the default is to obtain data from the temporary storage module and input it to the processing module. Otherwise, data is not obtained from the temporary storage module, but from the storage module.

[0065] The value of N in this embodiment is 4, which means that when the operation needs to be repeated, the maximum number of repetitions is 15 times. When the operation does not need to be repeated, the number of groups of operation codes is at most 15. In other embodiments, N can also be 2 or 3. In this embodiment, the value of N is 4, which comprehensively considers the total number of bits occupied by the instruction block header, the number of groups of subsequent operation codes, and the number of repeated executions of the operation in the entire calculation process. It can be known that if more repeated executions are required, the value of N can be increased. Therefore, the appropriate value of N depends on the function that needs to be implemented in the entire operation.

[0066] If you want to complete (a 5 +bc)|d, refer to Table 4, the required instructions are as follows, where the first six bits are the instruction block header and the following are the instruction block body.

[0067] Table 4

[0068]

[0069]

[0070] For instruction 11010110, the number of bits is 8, and this instruction completes a 5 Operation, that is, to complete 5 multiplications, the number of operations is 5. However, a traditional operation unit can only perform one operation per instruction. If 5 multiplications are implemented, 5 instructions are required. Assuming that the length of an instruction is 8 bits, 5*8=40 bits are required to implement 5 multiplication operations.

[0071] For instruction 1000101000, the number of bits is 10. This instruction first multiplies b by c and then adds a. 5 , the number of operations is 2 (1 multiplication, 1 addition), that is, 10 bits are needed to complete 2 operations, and traditional operations require 2*8=16 bits to complete two operations.

[0072] It can be seen that this embodiment can significantly save the number of bits of instructions required for consecutive operations, and is particularly suitable for situations where calculation operations need to be repeatedly executed.

[0073] If the instruction density is defined as the number of operations that can be represented by each bit, that is, the number of operations / number of bits. It can be seen that the density of the above two instructions in this embodiment is 0.625 (5 / 8) and 0.2 (2 / 10) when they are operated continuously. The encoding length of the traditional operation unit instruction is more than 8 bits, and the instruction density is less than 0.125 (1 / 8). Therefore, compared with the traditional encoding method, the instruction encoding method proposed by the present invention has the advantage of instruction density, reduces the number of bits required to read to obtain a given operation instruction, and thus improves the efficiency of accessing the storage system.

[0074] Example 2

[0075] Reference Figure 1 , this embodiment provides a digital automaton state realization operation unit, including:

[0076] A storage module M is used to store instructions and data to be operated, wherein the instructions are encoded in the manner described in Example 1;

[0077] A processing module, used to parse the instruction and, based on the parsed result, perform operation processing on the input data in each working (clock) beat;

[0078] The temporary storage module is used to temporarily store the calculation results of the current working cycle of the processing module, and input the calculation results to the processing module in the next working cycle to participate in new calculations, and after all the instructions are executed, output the final calculation results to the storage module.

[0079] Specifically, in this embodiment, the processing module includes a decoding and control unit, processing units of different operation types, and a first multiple-choice module; multiple input ends of the first multiple-choice module are connected to the output ends of the processing units of different operation types, and the output end of the first multiple-choice module is connected to the input end of the temporary storage module; the decoding and control unit is used to parse the instruction, determine the operation type, execution mode, number of groups of operation codes or the number of repeated executions of the operation operation contained in the instruction, and when it is determined that the data of the temporary storage module needs to participate in the operation of the next working beat, the output of the temporary storage module is input to the processing unit.

[0080] In this embodiment, the processing module includes an instruction input terminal, two data input terminals and a data output terminal; the instruction input terminal is used to input the instruction; the data input terminal is used to input the data to be involved in the operation; the data output terminal is used to output the operation result; the two data input terminals of the processing module respectively input data through a second multiple-choice module (the second multiple-choice module can be a two-choice module); the two input terminals of the second multiple-choice module are respectively connected to the output terminals of the storage module and the temporary storage module; the decoding and control unit is used to control the effective input terminal of the second multiple-choice module and control the processing unit to perform corresponding calculation operations; the output of the processing module is connected to an input terminal of the storage module.

[0081] In this embodiment, the processing units of different operation types include: an arithmetic processing unit, a relational processing unit and a logic processing unit; the corresponding operation types are arithmetic operation, relational operation and logic operation.

[0082] In this embodiment, the computing unit further includes a transmission module T, which is in communication with the storage module M and can perform two-way information transmission, as well as two-way information transmission between the computing unit and the outside. The instructions in the storage module M are transmitted to the storage module M through the transmission module T, the data required for the calculation is input to the storage module M through the transmission module T, and the final calculation result is transmitted to the outside through the transmission module T.

[0083] In this embodiment, the temporary storage module and the processing module together constitute the "state" performer P (Performer), which is the implementer and executor of the specified behavior. The "state" performer P implements the corresponding "state" behavior by executing the corresponding operation instructions stored in the "state" storage module M. When a "state" is completed and migrated to a new "state", the transmission module T provides information transmission function for the "state" migration, that is, the instruction code and processing data executed under the "state" are transmitted by the transmission module T to the "state" performer P in different ways.

[0084] Example 3

[0085] Reference Figure 2 , this embodiment provides a computing module, including a dispatching structure, a dispatching structure input unit, a dispatching structure output unit and a plurality of computing units described in Embodiment 2;

[0086] The dispatch structure input unit has multiple input ports, each of which is connected to the output of an operation unit, and the dispatch structure input unit is used to input processed data to the dispatch structure; the dispatch structure output unit has multiple output ports, each of which is connected to the input of an operation unit, and the dispatch structure output unit is used to provide the required data to be processed to the operation unit; multiple operation units work in parallel.

[0087] Example 4

[0088] This embodiment provides a computing method, the required instructions adopt the encoding method of the instructions described in Embodiment 1, and the method includes:

[0089] Parsing the instruction to determine the operation type, execution mode, number of operation code groups or number of repetitions of the operation contained in the instruction, and whether the instruction is a continuous operation;

[0090] Calculations are performed based on the analysis results, and when it is determined that the instruction is a continuous operation, the calculation result of the current working beat is directly used as the input of the next working beat, and participates in the calculation of the next working beat until all the calculation operations indicated in the instruction block of the instruction are executed.

[0091] In this embodiment, "using the calculation result of the current working cycle directly as the input of the next working cycle" means that the calculation result of the current working cycle does not need to be output to the outside of the calculation unit, and does not need to access the memory outside the calculation unit. Therefore, the access operation of intermediate data can be saved, and the calculation is not limited by the performance of the storage system.

[0092] Refer to Example 1 for how to determine the operation type, execution mode, number of operation code groups or number of repeated executions of the operation contained in the instruction.

[0093] The method for determining whether the instruction is a continuous operation is as follows: when the repeat flag is 1, it indicates that the operation is repeated, which means that the instruction is a continuous operation. When the repeat flag is 0 and the number of subsequent operation code groups is 2 or more, it means that the instruction is a continuous operation. When the repeat flag is 0 and the number of subsequent operation code groups is 1, it means that the instruction is not a continuous operation.

[0094] The calculation method of this embodiment can be calculated by the calculation unit described in Embodiment 2. The calculation result of the current working beat is stored in the temporary storage module.

[0095] Example 5

[0096] This embodiment provides a processor, including the operation unit for realizing the state of the digital automaton described in Embodiment 2 or the operation module described in Embodiment 3. The processor of this embodiment may be a processor of a computer or a processor of other low-end control systems.

[0097] The "state" of the automaton can be realized by one or more operation units and system memory (such as DRAM) units. Each "state" to be executed by the automaton is jointly described by the operation instruction code and the corresponding operand block, and the system dispatch structure loads the operation instruction code and the operand block in advance into the storage module M of the operation unit bound to the system through the transmission module T according to the system memory address where the operand is located according to the principle of proximity. Then the "state" executor P of this operation unit is started to execute these "state" operations pre-stored in the storage module M to realize this "state execution".

[0098] The present invention proposes a new instruction encoding format and a corresponding implementation structure for continuous operation, and adopts the method of instruction block header + instruction block body to realize multiple continuous operation operations (i.e. continuous operation, which can be a repeated operation or multiple non-repeating operations). In the prior art, each operation operation requires an instruction code, and these instruction codes usually contain common repeated information, such as operation type, etc. The present invention puts the repeated common information in the instruction block header, integrates the repeated information of multiple instructions into one instruction code, eliminates the repeated information in each instruction code, and saves the number of bits occupied by the entire instruction code. In this way, the capacity requirements for storing and transmitting instructions are saved, thereby reducing the impact of performance bottleneck factors such as "memory wall" in the computing system. On the other hand, this instruction code and implementation structure for the continuous execution of specified operations transfers data through the cache module by default, shortens the processing interval between operations, and thus improves the execution speed of operations.

[0099] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method of encoding an instruction, wherein the instruction is applied to a computing unit implemented by a digital automaton state, It is characterized in that The instruction includes an instruction block header and an instruction block body located after the instruction block header; the instruction block body includes at least one set of operation codes, and the operation code is used to represent a specific operation; the instruction block header can indicate the operation type and execution mode of the operation operation, and the execution mode includes repeated execution and non-repeated execution; The encoding method of the instruction block header is: a 1-bit operation type identification bit, a 1-bit repeat execution identification bit, and an N-bit execution mode bit arranged in sequence, where N is a positive integer; The operation type flag is used to indicate whether the operation is of a specified operation type; The repeat execution flag is used to indicate whether the operation is to be repeated; When the execution mode is repeated execution, the operation code is a group, and the N-bit execution mode bit is used to indicate the number of repeated executions of the operation; When the execution mode is non-repeated execution, the N-bit execution mode bit is used to indicate the number of groups of the operation code; The encoding method of the instructions is suitable for sequential computing operations.

2. The encoding method of the instruction as claimed in claim 1, It is characterized in that The operation types include arithmetic operations, relational operations and logical operations; The arithmetic operation includes addition operation, sign negation operation, multiplication operation and reciprocal operation; The relational operations include: greater than operation, less than operation, equal to operation, and inequality operation; the logical operations include: and operation, or operation, and negation operation; the operation operation under each operation type has a unique operation code.

3. The encoding method of the instruction as claimed in claim 2, It is characterized in that The operation code of one of the arithmetic operation, the relational operation and the logical operation is a 2-bit binary code, and the operation codes of the other two operation operations are a 3-bit binary code or a 4-bit binary code.

4. The encoding method of the instruction as claimed in claim 2, It is characterized in that The specified operation type is the arithmetic operation; the operation code of the arithmetic operation is a 2-bit binary code, and the operation code of the relational operation and the logical operation is a 4-bit binary code.

5. The encoding method of the instruction as claimed in claim 1, It is characterized in that The N is between 2-4.

6. An arithmetic unit realized by a digital automaton state, It is characterized in that include: A storage module, used for storing instructions and data to be operated, wherein the instructions are encoded in the encoding method according to any one of claims 1 to 5; A processing module, used to parse the instructions and, based on the parsed results, perform computations on the input data in each working cycle; The temporary storage module is used to temporarily store the calculation results of the current working cycle of the processing module, and input the calculation results to the processing module in the next working cycle to participate in new calculations, and after all the instructions are executed, output the final calculation results to the storage module.

7. The operation unit for realizing the state of a digital automaton as claimed in claim 6, It is characterized in that The processing module includes a decoding and control unit, processing units of different operation types, and a first multiple-choice module; The multiple input terminals of the first multiple-select-one module are connected to the output terminals of the processing units of different operation types, and the output terminal of the first multiple-select-one module is connected to the input terminal of the temporary storage module; The decoding and control unit is used to parse the instruction, determine the operation type, execution mode, number of operation code groups or the number of repeated executions of the operation contained in the instruction, and when it is determined that the data of the temporary storage module needs to participate in the operation of the next working beat, the output of the temporary storage module is input to the processing unit.

8. The operation unit for realizing the state of a digital automaton as claimed in claim 7, It is characterized in that The processing units of different operation types include: an arithmetic processing unit, a relational processing unit and a logic processing unit; The corresponding operation types are arithmetic operation, relational operation and logical operation.

9. The operation unit for realizing the state of a digital automaton as claimed in claim 7, It is characterized in that The processing module includes an instruction input terminal, two data input terminals and a data output terminal; The instruction input terminal is used to input the instruction; The data input terminal is used to input data to be involved in the calculation; The data output terminal is used to output the operation result; The two data input terminals of the processing module input data respectively through a second multiple-choice module; The two input ends of the second multiple-select-one module are respectively connected to the output ends of the storage module and the temporary storage module; The decoding and control unit is used to control the effective input end of the second multiple-select-one module; The output of the processing module is connected to an input terminal of the storage module.

10. The operation unit for realizing the state of a digital automaton according to claim 6, It is characterized in that The operation unit further includes a transmission module, which is communicatively connected with the storage module and can perform bidirectional information transmission, as well as bidirectional information transmission between the operation unit and the outside.

11. A method of operation, It is characterized in that The required instructions adopt the encoding method of the instructions described in any one of claims 1 to 5, and the method comprises: Parsing the instruction to determine the operation type, execution mode, number of operation code groups or number of repetitions of the operation contained in the instruction, and whether the instruction is a continuous operation; Calculations are performed based on the analysis results, and when it is determined that the instruction is a continuous operation, the calculation result of the current working beat is directly used as the input of the next working beat, and participates in the calculation of the next working beat until all the calculation operations indicated in the instruction block of the instruction are executed.

12. A computing module, It is characterized in that comprising a dispatching structure and a plurality of computing units as claimed in claims 6-10; The dispatch structure has a plurality of input ports, each of which is connected to an output of one of the operation units, and the dispatch structure inputs processed data into the dispatch structure through the input port; The dispatch structure has a plurality of output ports, each of which is connected to the input of one of the operation units. The dispatch structure provides the required data to be processed to the operation unit through the output port; and the plurality of operation units work in parallel.

13. A processor, It is characterized in that It comprises the operation unit for realizing the state of the digital automaton as described in any one of claims 6 to 10 or the operation module as described in claim 12.

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