True random number generator, integrated circuit and control method, chip and electronic device

Abstract

The present application provides a true random number generator, an integrated circuit and a control method, a chip and an electronic device, wherein the true random number generator comprises: a first oscillator, a second oscillator with adjustable phase and oscillation frequency; a sampling module, wherein a data input terminal is connected to a signal output terminal of the first oscillator, and a clock terminal is connected to a signal output terminal of the second oscillator; an entropy value analysis module, wherein an input terminal is respectively connected to a signal output terminal of the sampling module, a signal output terminal of the first oscillator, and a signal output terminal of the second oscillator, and an output terminal is connected to the second oscillator, and an entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator according to an output signal of the first oscillator, an output signal of the second oscillator, and an output signal of the sampling module. The present application can adjust the phase and oscillation frequency of the second oscillator through the entropy value analysis module, so that the entropy value of the output sequence can reach a target entropy value, thereby reducing chip area and power consumption.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a true random number generator, an integrated circuit and a control method, a chip and an electronic device. Background Art

[0002] Common true random number generators are usually implemented using two free-running ring oscillators, ring1 and ring2, and a D flip-flop for sampling, such as Figure 1 As shown. Among them, ring1 outputs a high-frequency clock signal f h , connected to the data input D terminal of the D flip-flop; ring2 outputs a low-frequency clock signal f s As the sampling clock, it is connected to the clk (clock) terminal of the D flip-flop. Ring1 and ring2 are independent of each other and produce different oscillation frequencies. Due to the existence of thermal noise and interference in the circuit, the clock signal f h and f s There is jitter, and f h Much larger than f s , high frequency clock f h The jitter of the sampling clock is much larger than s The jitter of the sampling clock f s The high frequency clock f is sampled by a D flip-flop h The jitter makes the output sequence Q OUT It has uncertainty, that is, a sequence with a certain degree of randomness is obtained.

[0003] For this type of true random number generator, the sampling clock f s The closer the sampling point is to the center of the high-frequency clock jitter distribution, the greater the entropy of the output sequence, and vice versa. Since the system safety requirements are related to the entropy of the output sequence, in many scenarios the entropy of the output sequence needs to reach the set target entropy value to meet the safety requirements.

[0004] At present, in order to make the entropy value of the output sequence reach the set target entropy value, the number of high-frequency ring oscillators is usually increased to fill the entire high-frequency clock cycle with jitter, thereby ensuring that the entropy value of the output sequence can reach the target entropy value. However, this method requires a large number of ring oscillators, which will lead to problems such as large chip area and high power consumption. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a true random number generator, an integrated circuit and a control method, a chip and an electronic device to solve the problem existing in the related art that, in order to ensure that the entropy value of the output sequence can reach the target entropy value, multiple high-frequency oscillators need to be set, resulting in a large chip area and high power consumption.

[0006] An embodiment of the present application provides a true random number generator, comprising: a first oscillator; a second oscillator, and the phase and oscillation frequency of the second oscillator are adjustable; a sampling module, wherein a data input end of the sampling module is connected to a signal output end of the first oscillator, a clock end of the sampling module is connected to a signal output end of the second oscillator, and the sampling module is used to sample and output an output signal of the first oscillator according to an output signal of the second oscillator; an entropy value analysis module, wherein an input end of the entropy value analysis module is respectively connected to a signal output end of the sampling module, a signal output end of the first oscillator, and a signal output end of the second oscillator, an output end of the entropy value analysis module is connected to the second oscillator, and the entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator, and the output signal of the sampling module.

[0007] In the above implementation, the entropy analysis module can adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module. This allows the true random number generator to adjust the phase and oscillation frequency of the second oscillator to a suitable position through the action of the entropy analysis module when it is working, so that even if the true random number generator does not set up multiple high-frequency oscillators, the entropy value of the output sequence can reach the target entropy value, thereby reducing the chip area and reducing power consumption.

[0008] Furthermore, the second oscillator includes: a first delay unit, an input end of the first delay unit is connected to a first output end of the entropy value analysis module, and the first delay unit generates different delays in response to different output signals of the first output end.

[0009] In the above implementation, a first delay unit is set in the second oscillator, and the delay time value from signal input to signal output in the second oscillator can be adjusted by adjusting the delay of the first delay unit, that is, the signal period of the second oscillator can be adjusted (since the signal period and the oscillation frequency are reciprocals of each other, the oscillation frequency of the second oscillator can also be adjusted).

[0010] Furthermore, the true random number generator also includes a second delay unit and an enable signal receiving end; the input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; the input end of the second delay unit is connected to the second output end of the entropy value analysis module, and the second delay unit generates different delays in response to different output signals of the second output end.

[0011] In the above implementation, since the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit, and the input end of the first oscillator is directly connected to the enable signal receiving end, once the delay time of the second delay unit changes, the time difference between the enable signal reaching the first oscillator and the second oscillator will change, thereby causing the phase of the output signal of the second oscillator relative to the output signal of the first oscillator to change, thereby achieving phase adjustment of the second oscillator.

[0012] Furthermore, the entropy analysis module includes: a first counter, a second counter and a first judgment circuit; the first counter is respectively connected to a preset reference clock source and a signal output end of the first oscillator to count the output signal of the first oscillator according to the reference clock source; the second counter is respectively connected to the reference clock source and the signal output end of the second oscillator to count the output signal of the second oscillator according to the reference clock source; the input end of the first judgment circuit is respectively connected to the output end of the first counter and the second counter, and the output end of the first judgment circuit is connected to the second oscillator; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0013] In the above implementation, the first counter can effectively record the number of rising edges or falling edges generated by the output signal of the first oscillator in a reference clock (this number reflects the frequency of the output signal of the first oscillator, that is, the oscillation frequency of the first oscillator), and the second counter can effectively record the number of rising edges or falling edges generated by the output signal of the second oscillator in a reference clock (this number reflects the frequency of the output signal of the second oscillator, that is, the oscillation frequency of the second oscillator). Based on the count values ​​of the first counter and the second counter, the first judgment circuit can judge whether the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator, and then determine whether the signal currently output by the second oscillator is suitable for sampling by the sampling module. Therefore, when it is not suitable, the oscillation frequency of the second oscillator can be adjusted.

[0014] Furthermore, the entropy analysis module includes: a third counter and a second judgment circuit; the third counter is respectively connected to the signal output end of the second oscillator and the signal output end of the sampling module to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator; the input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the second delay unit, and the second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump cycle threshold.

[0015] In the above implementation, the third counter can be used to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module. The entropy value of the output sequence output by the true random number generator (i.e., the sequence composed of the output signal of the sampling module) is related to the number of cycles experienced when a signal jump occurs in the output signal of the sampling module. The greater the number of cycles experienced when a signal jump occurs in the output signal of the sampling module, the smaller the entropy value of the output sequence is in theory. In the above implementation, by presetting the signal jump cycle threshold, the delay of the second delay unit can be adjusted when the count value of the third counter is greater than the preset signal jump cycle threshold, that is, the phase of the second oscillator is adjusted, which makes it possible to adjust the sampling point of the output signal of the second oscillator slowly to the center position of the jitter distribution of the output signal of the first oscillator by adjusting the phase of the second oscillator, so that the entropy value of the output sequence can reach the target entropy value.

[0016] The embodiment of the present application further provides an integrated circuit, comprising: an entropy value analysis module and a plurality of true random number generators; each of the true random number generators comprises: a first oscillator; a second oscillator, and the phase and oscillation frequency of the second oscillator are adjustable; a sampling module, wherein a data input end of the sampling module is connected to a signal output end of the first oscillator, a clock end of the sampling module is connected to a signal output end of the second oscillator, and the sampling module is used to sample and output an output signal of the first oscillator according to an output signal of the second oscillator;

[0017] The input end of the entropy analysis module is respectively connected to the signal output end of the sampling module of each true random number generator through a first multiplexer; the input end of the entropy analysis module is also respectively connected to the signal output end of the first oscillator of each true random number generator through a second multiplexer; the input end of the entropy analysis module is also respectively connected to the signal output end of the second oscillator of each true random number generator through a third multiplexer; the output end of the entropy analysis module is respectively connected to the second oscillator of each true random number generator through a fourth multiplexer; the entropy analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator of any true random number generator according to the output signal of the first oscillator of any true random number generator, the output signal of the second oscillator and the output signal of the sampling module.

[0018] Based on the above integrated circuit, since the entropy analysis module can adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module, this allows the true random number generator to adjust the phase and oscillation frequency of the second oscillator to a suitable position through the action of the entropy analysis module when it is working, so that even if the true random number generator does not set up multiple high-frequency oscillators, the entropy value of the output sequence can reach the target entropy value, thereby reducing the chip area and reducing power consumption.

[0019] At the same time, based on the above integrated circuit, it is only necessary to control each multiplexer so that the entropy analysis module is connected to a true random number generator each time, and then an entropy analysis module can be used to adjust the phase and oscillation frequency of the second oscillator of different true random number generators in turn, thereby realizing the reuse of multiple true random number generators for the entropy analysis module, further reducing the chip area overhead and power consumption.

[0020] Furthermore, for any one of the true random number generators, the second oscillator includes: a first delay unit; the first output end of the entropy analysis module is respectively connected to the input end of the first delay unit of each of the true random number generators through the fourth multiplexer; the first delay unit generates different delays in response to different output signals of the first output end.

[0021] Furthermore, for any one of the true random number generators, the true random number generator also includes a second delay unit and an enable signal receiving end; the input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; the second output end of the entropy value analysis module is connected to the input end of the second delay unit of each of the true random number generators through a fifth multiplexer; the second delay unit generates different delays in response to different output signals of the second output end.

[0022] Furthermore, the entropy value analysis module includes: a first counter, a second counter and a first judgment circuit; the first counter is connected to a preset reference clock source, and is respectively connected to the signal output end of the first oscillator of each of the true random number generators through a second multiplexer, so as to count the output signal of the first oscillator according to the reference clock source; the second counter is connected to the reference clock source, and is respectively connected to the signal output end of the second oscillator of each of the true random number generators through the third multiplexer, so as to count the output signal of the second oscillator according to the reference clock source; the input end of the first judgment circuit is respectively connected to the output end of the first counter and the second counter, and the output end of the first judgment circuit is respectively connected to the second oscillator of each of the true random number generators through the fourth multiplexer; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0023] Furthermore, the entropy value analysis module includes: a third counter and a second judgment circuit; the third counter is respectively connected to the signal output end of the second oscillator of each of the true random number generators through the third multiplexer, and is respectively connected to the signal output end of the sampling module of each of the true random number generators through the first multiplexer, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator; the input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is respectively connected to the input end of the second delay unit of each of the true random number generators through the fifth multiplexer, and the second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump cycle threshold.

[0024] An embodiment of the present application also provides a control method, which is applied to any of the aforementioned true random number generators, and the method includes: the entropy analysis module adjusts the oscillation frequency of the second oscillator in response to the rising edge of the output signal of the second oscillator being misaligned with the rising edge or falling edge of the output signal of the first oscillator; the entropy analysis module determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is less than or equal to a preset signal jump period threshold in response to the rising edge of the output signal of the second oscillator being aligned with the rising edge or falling edge of the output signal of the first oscillator; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is greater than the signal jump period threshold, the phase of the second oscillator is adjusted.

[0025] In the above implementation, when the rising edge of the output signal of the second oscillator is not aligned with the rising edge or falling edge of the output signal of the first oscillator, it means that the sampling module samples the output signal of the first oscillator under the triggering of the output signal of the second oscillator, and obtains a fixed value, so the random number generation requirement is not met. Therefore, it is necessary to adjust the signal frequency of the output signal of the second oscillator (i.e., the oscillation frequency of the second oscillator) so that the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator, so that when the sampling module samples the output signal of the first oscillator under the triggering of the output signal of the second oscillator, a random value in a metastable state is obtained. In the case of satisfying the conditions for random number generation, since the entropy value of the output sequence output by the true random number generator (i.e., the sequence composed of the output signal of the sampling module) is related to the number of cycles experienced when the signal jump occurs in the output signal of the sampling module, the greater the number of cycles experienced when the signal jump occurs in the output signal of the sampling module, the smaller the entropy value of the output sequence. Therefore, when the number of cycles experienced when the signal jumps is greater than the signal jump cycle threshold, the phase of the second oscillator is adjusted. This allows the sampling center of the output signal of the second oscillator to be slowly adjusted toward the center position of the jitter distribution of the output signal of the first oscillator by continuously adjusting the phase of the second oscillator (that is, the number of cycles experienced when a signal jump occurs in the output signal of the sampling module gradually decreases), so that the entropy value of the output sequence can reach the target entropy value.

[0026] The embodiment of the present application also provides a control method, which is applied to any of the above-mentioned integrated circuits, and the method includes: in response to a conduction control signal, the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer connect the entropy value analysis module with the true random number generator corresponding to the conduction control signal among the multiple true random number generators; the entropy value analysis module adjusts the true random number generator in response to the rising edge of the output signal of the second oscillator of the true random number generator and the rising edge or falling edge of the output signal of the first oscillator of the true random number generator not being aligned the entropy value analysis module determines, in response to the alignment of the rising edge of the output signal of the second oscillator of the true random number generator with the rising edge or the falling edge of the output signal of the first oscillator of the true random number generator, whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is less than or equal to a preset signal jump cycle threshold; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is greater than the signal jump cycle threshold, the phase of the second oscillator of the true random number generator is adjusted.

[0027] In the above implementation, the entropy value analysis module can be controlled by the conduction control signal to adjust the oscillation frequency and phase of the second oscillator of a certain true random number generator, so that as mentioned above, the oscillation frequency and phase of the second oscillator in the true random number transmitter can be adjusted to a range where the entropy value of the output sequence of the true random number transmitter can reach the target entropy value, without setting multiple high-frequency oscillators. At the same time, the conduction control signal can make multiple true random number generators reuse one entropy value analysis module, thereby further reducing the chip area and power consumption.

[0028] An embodiment of the present application also provides a chip, including any one of the aforementioned true random number generators, or including any one of the aforementioned integrated circuits.

[0029] An embodiment of the present application also provides an electronic device, including the aforementioned chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 Schematic diagram of a true random number generator based on ;

[0032] Figure 2 A schematic diagram of the corresponding relationship between the sampling points, the high-frequency clock signal jitter distribution, and the entropy value in the true random number generator;

[0033] Figure 3 A basic structural diagram of a true random number generator provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of the structure of a specific true random number generator provided in an embodiment of the present application;

[0035] Figure 5 A schematic diagram of the structure of a specific first delay unit provided in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of the structure of a true random number generator with a second delay unit provided in an embodiment of the present application;

[0037] Figure 7 A schematic diagram of the structure of a specific second delay unit provided in an embodiment of the present application;

[0038] Figure 8 A schematic diagram of the structure of an entropy analysis module provided in an embodiment of the present application;

[0039] Fig. 9 A flow chart of a control method provided in an embodiment of the present application and applied to a true random number generator provided in the present application;

[0040] Fig.10 A schematic diagram of the basic structure of an integrated circuit of an entropy value analysis module for multiple true random numbers provided in an embodiment of the present application;

[0041] Fig.11 A schematic diagram of a structure in which a first delay unit is set in each true random number provided in an embodiment of the present application;

[0042] Fig.12 A schematic diagram of a structure in which a second delay unit is set in each true random number provided in an embodiment of the present application;

[0043] Fig.13 A schematic diagram of the structure of a multiplexed entropy analysis module provided in an embodiment of the present application;

[0044] Fig.14 A flowchart of a control method provided in an integrated circuit provided in the present application is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0046] For Figure 1 The information entropy of the output sequence QOUT of the true random number generator shown is calculated by formula (1):

[0047] H(p)=-p*log2p –(1-p)*log2(1-p) Formula (1)

[0048] Where p is the probability of the output being 1, and 1-p is the probability of the output being 0. The high-frequency clock signal f h The jitter distribution of is a normal distribution (μ,σ), where μ is the mean value and σ is the variance value. The sampling clock signal f s The sampling points of the high-frequency clock jitter distribution are at different locations, and the output will get different entropy values. Figure 2 As shown in the figure, if the sampling point is within (μ-3σ,μ+3σ), the maximum probability of sampling 1 is 0.998, and the entropy value of the output sequence QOUT is ≥0.01; if the sampling point is within the range of (μ-2σ,μ+2σ), the maximum probability of the D flip-flop sampling 1 is 0.977, and the entropy value of the output sequence QOUT is ≥0.16; if the sampling point is within the range of (μ-σ,μ+σ), the maximum probability of the D flip-flop sampling 1 is 0.841, and the entropy value of the output sequence QOUT is ≥0.63. It can be seen that the sampling clock signal f s The closer the sampling point is to the high-frequency clock signal f h The closer the center position of the jitter distribution is, the larger the entropy value of the output sequence QOUT is, and vice versa.

[0049] Since the system safety requirements are related to the entropy value of the output sequence, in many scenarios, the entropy value of the output sequence must reach the set target entropy value to meet the safety requirements. In order to make the entropy value of the output sequence reach the set target entropy value, it is currently usually achieved by increasing the number of high-frequency ring oscillators to fill the entire high-frequency clock cycle with jitter, thereby ensuring that the entropy value of the output sequence can reach the target entropy value. Assuming that the target entropy value is 0.5, the low-frequency clock sampling points must all be within the jitter distribution (μ-1.23σ, μ+1.23σ) range of the high-frequency clock signal. Assuming that there is no overlap between the high-frequency clock jitter distributions of each high-frequency ring oscillator, the number of high-frequency ring oscillators n required to satisfy formula (2) can fill the entire high-frequency clock cycle with jitter, thereby ensuring that the entropy value of the output sequence can reach the target entropy value.

[0050] n>T / 2.46σ Formula (2)

[0051] Where T is the period of the high-frequency ring oscillator. If σ = 0.01T, 41 high-frequency ring oscillators are required; if σ = 0.001T, 410 high-frequency ring oscillators are required. It can be seen that this method requires a large number of ring oscillators, which will lead to problems such as large chip area and high power consumption. In practice, there will be overlap between the high-frequency clock jitter distributions of each high-frequency ring oscillator, so more high-frequency ring oscillators are required than in the ideal state to ensure that the entropy value of the output sequence reaches the target entropy value.

[0052] Then, in order to solve the problem in the prior art that in order to ensure that the entropy value of the output sequence can reach the target entropy value, multiple high-frequency oscillators need to be set, resulting in a large chip area and high power consumption, a new true random number generator is provided in the embodiment of the present application, which can be seen in Figure 3 As shown, it includes: a first oscillator, a second oscillator, a sampling module and an entropy value analysis module.

[0053] The second oscillator is an oscillator with adjustable phase and oscillation frequency.

[0054] The data input end of the sampling module is connected to the signal output end of the first oscillator, and the clock end of the sampling module is connected to the signal output end of the second oscillator, so that the sampling module samples and outputs the output signal of the first oscillator according to the output signal of the second oscillator.

[0055] Optionally, the sampling module can be implemented using but not limited to a D flip-flop.

[0056] Optionally, the first oscillator and the second oscillator may be, but are not limited to, a ring oscillator, a relaxation oscillator, a voltage-controlled oscillator, etc. The first oscillator and the second oscillator may be of the same type or different types. The oscillation frequency of the first oscillator may be higher than the oscillation frequency of the second oscillator, so that the sampling module can sample and obtain random numbers. Exemplarily, an oscillator whose oscillation frequency is much higher than the oscillation frequency of the second oscillator may be selected as the first oscillator.

[0057] In an embodiment of the present application, the input end of the entropy analysis module is respectively connected to the signal output end of the sampling module, the signal output end of the first oscillator, and the signal output end of the second oscillator, and the output end of the entropy analysis module is connected to the second oscillator.

[0058] The entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module.

[0059] Specifically, since the sampling module samples the output signal of the first oscillator according to the output signal of the second oscillator, that is, the sampling module samples the output signal of the first oscillator when the rising edge of the output signal of the second oscillator arrives. Then, in order to ensure the randomness of the output value of the sampling module, it is necessary to sample on the rising edge or falling edge of the output signal of the first oscillator. At this time, the output signal of the first oscillator is in a metastable state, so the randomness of the output result of the sampling module can be guaranteed. That is, in order to ensure the randomness of the output result of the sampling module, the rising edge of the output signal of the second oscillator needs to be aligned with the rising edge or falling edge of the output signal of the first oscillator.

[0060] To this end, the entropy value analysis module can adjust the oscillation frequency of the second oscillator when the rising edge of the output signal of the second oscillator is not aligned with the rising edge or falling edge of the output signal of the first oscillator. For example, the oscillation frequency of the second oscillator can be reduced or increased according to the set value. Then the above process is repeated until the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator.

[0061] In a true random number generator, assuming that every M cycles, the output of the sampling module has a 0 / 1 jump (that is, the output value jumps from 0 to 1), or a 1 / 0 jump (that is, the output value jumps from 1 to 0), then the probability that the output of the sampling module is 0 or 1 is at least 1 / M, and the entropy of the output sequence is:

[0062] H(p)=(1 / M)*log2M +(M-1) / M*log2M / (M-1) Formula (3)

[0063] Assuming M = 10, the entropy value of the output sequence is H (P) = 0.46, assuming M = 4, the entropy value of the output sequence is H (P) = 0.80. It can be seen that the entropy value of the output sequence output by the true random number generator (i.e., the sequence composed of the output signal of the sampling module) is related to the number of cycles experienced when the signal jump occurs in the output signal of the sampling module. The larger the number of cycles experienced when the signal jump occurs in the output signal of the sampling module, the smaller the entropy value of the output sequence. Based on this principle, in the embodiment of the present application, the M value can be determined according to the target entropy value required by the business, that is, the signal jump cycle threshold is determined. When the number of cycles experienced when the signal jumps (i.e., the number of sampling cycles experienced by the sampling module when the output signal output by the sampling module jumps 0 / 1 or 1 / 0) is greater than the signal jump cycle threshold, the phase of the second oscillator is adjusted, for example, the phase of the second oscillator can be reduced or increased according to the set value.

[0064] By continuously repeating the above process, the sampling point of the sampling module (i.e., the rising edge of the output signal of the second oscillator) can be continuously moved closer to the center position of the jitter distribution of the first oscillator, so that the entropy value of the sequence composed of the output signals of the sampling module (i.e., the output sequence) can reach the target entropy value.

[0065] It can be seen that based on the true random number generator adopted in the embodiment of the present application, the phase and oscillation frequency of the second oscillator can be adjusted to a suitable position through the action of the entropy analysis module, so that even if the true random number generator does not set up multiple high-frequency oscillators (i.e., the first oscillator), the entropy value of the output sequence can reach the target entropy value, thereby reducing the chip area and reducing power consumption.

[0066] In the examples of this application, see Figure 4 As shown, the first oscillator and the second oscillator can be composed of a plurality of delay units connected in series to form a ring. These delay units can be implemented by one or more logic devices such as inverters, NAND gates, etc., but are not limited to them.

[0067] The delay unit constituting the second oscillator may include at least one first delay unit, the input end of the first delay unit being connected to the first output end of the entropy analysis module, and the first delay unit generating different delays in response to different output signals of the first output end of the entropy analysis module.

[0068] Exemplarily, the first delay unit can be an inverter, in which case the first delay unit has at least two inputs, which are the delay unit in the second oscillator located before the first delay unit, and the first output end of the entropy analysis module. Then the change of the output value of the first output end of the entropy analysis module will change the current input to the first delay unit. It can be understood that the larger the current input to the inverter, the smaller the delay of the inverter, and the smaller the current input to the inverter, the larger the delay of the inverter. Therefore, the entropy analysis module can control the first delay unit to produce different delays by controlling the output value of the first output end. And by adjusting the delay of the first delay unit, the delay time from the signal input to the signal output in the second oscillator can be adjusted, that is, the signal period of the second oscillator can be adjusted (since the signal period and the oscillation frequency are reciprocal to each other, the oscillation frequency of the second oscillator can also be adjusted).

[0069] For example, Figure 5 As shown, the first delay unit can also be a delay link with different delays connected through a multiplexer, and a different number of delay units can be connected in series on each delay link. The first output end of the entropy analysis module is connected to the control end of the multiplexer, so that the selected delay link can be controlled, thereby realizing the control of the delay of the first delay unit.

[0070] It can be understood that the above are only two optional implementation methods of the first delay unit exemplified in the embodiments of the present application. In addition, the first delay unit can also be implemented using any other circuit structure that can controllably adjust the delay time, which is not limited to the embodiments of the present application.

[0071] In the embodiment of the present application, in order to adjust the phase of the second oscillator, as shown in FIG. Figure 6 As shown, the true random number generator may further include a second delay unit and an enable signal receiving terminal EN.

[0072] The input end of the first oscillator is connected to the enable signal receiving end EN, and the input end of the second oscillator is connected to the enable signal receiving end EN through the second delay unit.

[0073] The input end of the second delay unit is connected to the second output end of the entropy value analysis module, and the second delay unit generates different delays in response to different output signals of the second output end.

[0074] In this way, since the input end of the second oscillator is connected to the enable signal receiving end EN through the second delay unit, and the input end of the first oscillator is directly connected to the enable signal receiving end EN, once the delay time of the second delay unit changes, the time difference between the enable signal reaching the first oscillator and the second oscillator will change, thereby causing the phase of the output signal of the second oscillator relative to the output signal of the first oscillator to change, thereby achieving phase adjustment of the second oscillator.

[0075] Exemplarily, the second delay unit can be an inverter, in which case the second delay unit has at least two inputs, namely an enable signal and a first output terminal of the entropy analysis module. Then the change in the output value of the second output terminal of the entropy analysis module will change the magnitude of the current input to the second delay unit. It can be understood that the greater the current input to the inverter, the smaller the delay of the inverter, and the smaller the current input to the inverter, the greater the delay of the inverter. Therefore, the entropy analysis module can control the second delay unit to produce different delays by controlling the output value of the second output terminal. And by adjusting the delay of the second delay unit, the phase of the output signal of the second oscillator relative to the output signal of the first oscillator can be adjusted.

[0076] For example, Figure 7 As shown, the second delay unit can also be a delay link with different delays connected through a multiplexer, and a different number of delay units can be connected in series on each delay link. The first output end of the entropy analysis module is connected to the control end of the multiplexer, so that the selected delay link can be controlled, thereby realizing the control of the delay of the second delay unit.

[0077] It can be understood that the above are only two optional implementation methods of the second delay unit exemplified in the embodiments of the present application. In addition, the second delay unit can also be implemented using any other circuit structure that can controllably adjust the delay time, which is not limited to the embodiments of the present application.

[0078] In the embodiments of the present application, Figure 6 As shown, the first delay unit of the first oscillator and the second oscillator can be implemented by using a NAND gate, so that when forming a ring, an enable signal is connected, so that the first oscillator and the second oscillator work only after receiving the enable signal. h is the output signal of the first oscillator, f s_adj is the output signal of the second oscillator.

[0079] In the embodiments of the present application, Figure 8 As shown, the entropy value analysis module may include a first counter, a second counter and a first judgment circuit.

[0080] The first counter is respectively connected to a preset reference clock source and a signal output terminal of the first oscillator to count the output signal of the first oscillator according to the reference clock source.

[0081] The second counter is connected to the reference clock source and the signal output terminal of the second oscillator respectively, so as to count the output signal of the second oscillator according to the reference clock source.

[0082] The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0083] In the embodiment of the present application, the reference clock source is used to provide a reference clock f ref The clock source may be a clock source outside the true random number generator in the chip.

[0084] It can be understood that the first counter can effectively record the number of rising edges or falling edges generated by the output signal of the first oscillator in a reference clock (the number reflects the frequency of the output signal of the first oscillator, that is, the oscillation frequency of the first oscillator). Similarly, the second counter can effectively record the number of rising edges or falling edges generated by the output signal of the second oscillator in a reference clock (the number reflects the frequency of the output signal of the second oscillator, that is, the oscillation frequency of the second oscillator).

[0085] It can be understood that when the two consecutive rising edges of the output signal of the second oscillator are aligned with the rising edge of the output signal of the first oscillator, the oscillation frequency of the first oscillator can be divided by the oscillation frequency of the second oscillator, that is, the quotient of the oscillation frequency of the first oscillator and the oscillation frequency of the second oscillator should be an even multiple of 0.5; when the first rising edge of the output signal of the second oscillator is aligned with the rising edge of the output signal of the first oscillator and the second rising edge is aligned with the falling edge of the output signal of the first oscillator, the quotient of the oscillation frequency of the first oscillator and the oscillation frequency of the second oscillator should be an odd multiple of 0.5. Therefore, by judging the count value of the first counter to determine whether the quotient of the count value of the first counter and the count value of the second counter is an integer multiple of 0.5, it can be determined whether the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator, and then determine whether the signal currently output by the second oscillator is suitable for sampling by the sampling module. Therefore, when it is not suitable, the oscillation frequency of the second oscillator can be adjusted.

[0086] In the embodiments of the present application, still refer to Figure 8 As shown, the entropy value analysis module may include a third counter and a second judgment circuit. Figure 8 In the example, Q represents the output signal of the sampling module.

[0087] The third counter is connected to the signal output terminal of the second oscillator and the signal output terminal of the sampling module respectively, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator;

[0088] The input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the second delay unit. The second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

[0089] In this way, the number of cycles experienced when a signal jump occurs in the output signal of the sampling module can be counted by the third counter. As mentioned above, the entropy value of the output sequence output by the true random number generator is related to the number of cycles experienced when a signal jump occurs in the output signal of the sampling module. The larger the number of cycles experienced when a signal jump occurs in the output signal of the sampling module, the smaller the entropy value of the output sequence is in theory. Therefore, by presetting a reasonable signal jump cycle threshold M, the phase of the second oscillator can be adjusted by continuously adjusting the delay of the second delay unit, so that the sampling center of the output signal of the second oscillator moves toward the center position of the jitter distribution of the output signal of the first oscillator, and finally the entropy value of the output sequence can reach the target entropy value.

[0090] Optionally, in an embodiment of the present application, some post-processing modules may be connected to the output end of the sampling module, and the post-processing modules may be configured to obtain the sampling signals output by the sampling module and integrate them into a sequence for output.

[0091] Among them, the post-processing module can be implemented by a processor with signal processing capabilities, such as a CPU core, or a device with data integration capabilities such as a register, which is not limited to this embodiment of the present application.

[0092] Based on the same inventive concept, the embodiment of the present application also provides a control method based on the above-mentioned true random number generator, which can be seen in Fig. 9 As shown, including:

[0093] S901: In response to the rising edge of the output signal of the second oscillator not being aligned with the rising edge or falling edge of the output signal of the first oscillator, the entropy analysis module adjusts the oscillation frequency of the second oscillator.

[0094] Exemplarily, as described above, the first counter of the entropy value analysis module can count the output signal of the first oscillator based on the reference clock to obtain the count value C1, and at the same time, the first counter can count the output signal of the second oscillator based on the reference clock to obtain the count value C2, and then the first judgment circuit determines whether C1 / C2 is equal to an integer multiple of 0.5. If not, it indicates that the rising edge of the output signal of the second oscillator and the rising edge or falling edge of the output signal of the first oscillator are not aligned, and a new first signal is output to the second oscillator according to a preset increase value or decrease value, for example, output to the first delay unit, so as to adjust the oscillation frequency of the second oscillator. If C1 / C2 is equal to an integer multiple of 0.5, it indicates that the rising edge of the output signal of the second oscillator and the rising edge or falling edge of the output signal of the first oscillator are aligned, and the output first signal is kept unchanged at this time.

[0095] S902: In response to the alignment of the rising edge of the output signal of the second oscillator with the rising edge or falling edge of the output signal of the first oscillator, the entropy analysis module determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is less than or equal to a preset signal jump cycle threshold. If the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is greater than the signal jump cycle threshold, the phase of the second oscillator is adjusted.

[0096] Exemplarily, as described above, the third counter of the entropy analysis module can count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator to obtain a count value C3.

[0097] That is, the third counter can add 1 to the count value each time the rising edge of the output signal of the second oscillator arrives, and when the output signal of the sampling module is inconsistent with the output signal of the sampling module received by the third counter last time (that is, when a 0 / 1 jump occurs, or a 1 / 0 jump occurs), it outputs the count value C3 and resets the count value.

[0098] The second judgment circuit compares C3 with a preset signal transition period threshold M. If C3 is greater than M, a new second signal can be output to the second delay unit according to a preset increase or decrease value, thereby adjusting the phase of the second oscillator. If C3 is less than or equal to M, it indicates that the sampling point of the sampling clock signal (i.e., the output signal of the second oscillator) has fallen into the jitter distribution of the high-frequency clock signal (i.e., the output signal of the first oscillator), which can meet the target entropy value range, so there is no need to adjust the phase of the second oscillator.

[0099] To facilitate understanding of the above scheme, Figure 3 Combination Figure 6 and Figure 8 Taking the obtained structure as an example, the embodiments of the present application are exemplified as follows:

[0100] First, the first oscillator and the second oscillator work and output signals f respectively. h and f s_adj .

[0101] Thereafter, the first counter outputs the count value C1, the second counter outputs the count value C2, and the first judgment circuit judges whether C1 / C2 is equal to an integer multiple of 0.5. If not, a new first signal is output to the first delay unit according to a preset increase value or decrease value, thereby adjusting the oscillation frequency of the second oscillator. The above process is repeated until C1 / C2 is equal to an integer multiple of 0.5.

[0102] The third counter outputs the count value C3, and the second judgment circuit judges whether C3 is greater than the preset signal transition period threshold value M. M is set according to the target entropy value. If C3 is greater than M, a new second signal can be output to the second delay unit according to the preset increase value or decrease value, thereby adjusting the phase of the second oscillator. Then repeat the above process of judging whether it is necessary to adjust the oscillation frequency of the second oscillator and adjusting the phase. If C3 is less than or equal to M, the adjustment is terminated.

[0103] It can be understood that the above is only an example of a single true random number generator, and in a chip or a system, there may be a situation where multiple true random number generators are needed. In this case, one implementation method is to arrange multiple true random number generators provided by the aforementioned embodiments. Another implementation method is that multiple true random number generators that do not include an entropy analysis module reuse the same entropy analysis module, and multiple multiplexers are used to implement the gating of the entropy analysis module to the true random number generator.

[0104] For example, see Fig.10 As shown, an integrated circuit with multiple true random number generators reusing the same entropy analysis module provided by an embodiment of the present application includes an entropy analysis module and multiple true random number generators. It can be understood that Fig.10 Only two true random number generators are shown in FIG. 1 . In actual applications, more true random number generators may be included. h1 is the output signal of the first oscillator in the true random number generator 1, f h2 is the output signal of the first oscillator in the true random number generator 2, f s_adj1 is the output signal of the second oscillator in the true random number generator 1, f s_adj2 is the output signal output by the second oscillator in the true random number generator 2, Q1 is the output signal output by the sampling module in the true random number generator 1, and Q2 is the output signal output by the sampling module in the true random number generator 2.

[0105] Wherein, each true random number generator comprises:

[0106] First oscillator;

[0107] A second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable;

[0108] A sampling module, wherein a data input terminal of the sampling module is connected to a signal output terminal of the first oscillator, a clock terminal of the sampling module is connected to a signal output terminal of the second oscillator, and the sampling module is used to sample and output an output signal of the first oscillator according to an output signal of the second oscillator;

[0109] The input end of the entropy value analysis module is respectively connected to the signal output end of the sampling module of each true random number generator through the first multiplexer;

[0110] The input end of the entropy value analysis module is also connected to the signal output end of the first oscillator of each true random number generator through the second multiplexer;

[0111] The input end of the entropy value analysis module is also connected to the signal output end of the second oscillator of each true random number generator through the third multiplexer;

[0112] The output end of the entropy value analysis module is respectively connected to the second oscillator of each true random number generator through a fourth multiplexer;

[0113] The entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator of any true random number generator according to the output signal of the first oscillator of the true random number generator, the output signal of the second oscillator and the output signal of the sampling module.

[0114] It can be understood that the control ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer can be connected to the control module of the integrated circuit (for example, it can be but not limited to the processor core, the coprocessor, etc.), so that the control module can control the gating of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer, so that the entropy analysis module is only connected to one true random number generator at the same time (that is, the input end of the entropy analysis module is connected to the signal output end of the sampling module of the same true random number generator, the signal output end of the first oscillator, and the signal output end of the second oscillator, and the output end of the entropy analysis module is also connected to the second oscillator of the true random number generator).

[0115] Optionally, in the embodiments of the present application, for example Fig.11 As shown, for any true random number generator, similar to the above, the second oscillator in the true random number generator may include a first delay unit.

[0116] The first output end of the entropy value analysis module is connected to the input end of the first delay unit of each true random number generator through a fourth multiplexer, and the first delay unit generates different delays in response to different output signals of the first output end.

[0117] The specific implementation of the first delay unit is as described above and will not be repeated here.

[0118] Optionally, in the embodiments of the present application, for example Fig.12 As shown, for any true random number generator, similar to the above, the true random number generator may also include a second delay unit and an enable signal receiving terminal EN.

[0119] The input end of the first oscillator is connected to the enable signal receiving end EN, and the input end of the second oscillator is connected to the enable signal receiving end EN through a second delay unit. The second output end of the entropy value analysis module is connected to the input end of the second delay unit of each true random number generator through a fifth multiplexer; the second delay unit generates different delays in response to different output signals of the second output end.

[0120] The specific implementation of the second delay unit is as described above and will not be repeated here.

[0121] In addition, similar, e.g. Fig.13 As shown, the entropy value analysis module may include a first counter, a second counter and a first judgment circuit.

[0122] The first counter is connected to a preset reference clock source and is respectively connected to the signal output end of the first oscillator of each true random number generator through a second multiplexer to count the output signal of the first oscillator according to the reference clock source.

[0123] The second counter is connected to the reference clock source and is respectively connected to the signal output end of the second oscillator of each true random number generator through a third multiplexer to count the output signal of the second oscillator according to the reference clock source.

[0124] The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator of each true random number generator respectively through a fourth multiplexer; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0125] Optional, similar to the previous, e.g. Fig.13 As shown, the entropy value analysis module may further include a third counter and a second judgment circuit.

[0126] Among them, the third counter is connected to the signal output end of the second oscillator of each true random number generator through the third multiplexer, and is connected to the signal output end of the sampling module of each true random number generator through the first multiplexer, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator.

[0127] The input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the input end of the second delay unit of each true random number generator through a fifth multiplexer. The second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

[0128] It can be understood that the fifth multiplexer can also be controlled by the control module to achieve conduction between the entropy value analysis module and the same true random number generator.

[0129] Correspondingly, based on the same inventive concept, the embodiment of the present application also provides a control method based on the above integrated circuit, which can be seen in Fig.14 As shown, including:

[0130] S1401: In response to a conduction control signal, the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer conduct the entropy value analysis module with the true random number generator corresponding to the conduction control signal among the multiple true random number generators.

[0131] It can be understood that the conduction control signal can be issued by the control module in the integrated circuit, so that the first multiplexer connects the input end of the entropy analysis module to the signal output end of the sampling module of a true random number generator, and the second multiplexer connects the input end of the entropy analysis module to the signal output end of the first oscillator of the same true random number generator, and the third multiplexer connects the input end of the entropy analysis module to the signal output end of the second oscillator of the same true random number generator, and the fourth multiplexer connects the output end of the entropy analysis module to the control end of the second oscillator of the same true random number generator.

[0132] S1402: The entropy analysis module adjusts the oscillation frequency of the second oscillator of the true random number generator in response to the rising edge of the output signal of the second oscillator of the true random number generator being misaligned with the rising edge or falling edge of the output signal of the first oscillator of the true random number generator.

[0133] Exemplarily, as described above, the first counter of the entropy value analysis module can count the output signal of the first oscillator based on the reference clock to obtain the count value C1, and at the same time, the first counter can count the output signal of the second oscillator based on the reference clock to obtain the count value C2, and then the first judgment circuit determines whether C1 / C2 is equal to an integer multiple of 0.5. If not, it indicates that the rising edge of the output signal of the second oscillator and the rising edge or falling edge of the output signal of the first oscillator are not aligned, and a new first signal is output to the second oscillator according to a preset increase value or decrease value, for example, output to the first delay unit, so as to adjust the oscillation frequency of the second oscillator. If C1 / C2 is equal to an integer multiple of 0.5, it indicates that the rising edge of the output signal of the second oscillator and the rising edge or falling edge of the output signal of the first oscillator are aligned, and the output first signal is kept unchanged at this time.

[0134] S1403: The entropy analysis module responds to the alignment of the rising edge of the output signal of the second oscillator of the true random number generator with the rising edge or the falling edge of the output signal of the first oscillator of the true random number generator, and determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is less than or equal to a preset signal jump cycle threshold; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is greater than the signal jump cycle threshold, the phase of the second oscillator of the true random number generator is adjusted.

[0135] Exemplarily, as described above, the third counter of the entropy analysis module can count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator to obtain a count value C3.

[0136] That is, the third counter can add 1 to the count value when the rising edge of the output signal of the second oscillator arrives, and when the output signal of the sampling module is inconsistent with the output signal of the sampling module received by the third counter last time (that is, when a 0 / 1 jump occurs, or a 1 / 0 jump occurs), it outputs the count value C3 and resets the count value.

[0137] The second judgment circuit compares C3 with a preset signal transition period threshold M. If C3 is greater than M, a new second signal can be output to the second delay unit according to a preset increase or decrease value, thereby adjusting the phase of the second oscillator. If C3 is less than or equal to M, it indicates that the sampling point of the sampling clock signal (i.e., the output signal of the second oscillator) has fallen into the jitter distribution of the high-frequency clock signal (i.e., the output signal of the first oscillator), which can meet the target entropy value range, so there is no need to adjust the phase of the second oscillator.

[0138] It can be understood that after the entropy analysis module has adjusted the phase and oscillation frequency of the second oscillator in a true random number generator, the control module can output a new conduction control signal to connect the entropy analysis module to the new true random number generator, thereby adjusting the phase and oscillation frequency of the new true random number generator.

[0139] To facilitate understanding of the above scheme, Fig.10 Combination Figure 11-13 Taking the obtained structure as an example, the embodiments of the present application are exemplified as follows:

[0140] First, the control module sends a conduction control signal to the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, and the fifth multiplexer, respectively, so that the first multiplexer connects the input end of the entropy value analysis module with the signal output end of the sampling module of the true random number generator 1, the second multiplexer connects the input end of the entropy value analysis module with the signal output end of the first oscillator of the true random number generator 1, the third multiplexer connects the input end of the entropy value analysis module with the signal output end of the second oscillator of the true random number generator 1, the fourth multiplexer connects the output end of the entropy value analysis module with the first delay unit of the true random number generator 1, and the fifth multiplexer connects the output end of the entropy value analysis module with the second delay unit of the true random number generator 1.

[0141] Thereafter, the first counter outputs the count value C1, the second counter outputs the count value C2, and the first judgment circuit judges whether C1 / C2 is equal to an integer multiple of 0.5. If not, a new first signal is output to the first delay unit of the true random number generator 1 according to a preset increase value or decrease value, thereby adjusting the oscillation frequency of the second oscillator of the true random number generator 1. The above process is repeated until C1 / C2 is equal to an integer multiple of 0.5.

[0142] The third counter outputs the count value C3, and the second judgment circuit judges whether C3 is greater than the preset signal transition period threshold M. M is set according to the target entropy value. If C3 is greater than M, a new second signal can be output to the second delay unit of the true random number generator 1 according to the preset increase value or decrease value, thereby adjusting the phase of the second oscillator of the true random number generator 1. Then repeat the above process of judging whether it is necessary to adjust the oscillation frequency of the second oscillator of the true random number generator 1 and adjusting the phase. If C3 is less than or equal to M, the adjustment is ended.

[0143] Thereafter, the control module sends conduction control signals to the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, and the fifth multiplexer respectively, so that the first multiplexer connects the input end of the entropy value analysis module with the signal output end of the sampling module of the true random number generator 2, the second multiplexer connects the input end of the entropy value analysis module with the signal output end of the first oscillator of the true random number generator 2, the third multiplexer connects the input end of the entropy value analysis module with the signal output end of the second oscillator of the true random number generator 2, the fourth multiplexer connects the output end of the entropy value analysis module with the first delay unit of the true random number generator 2, and the fifth multiplexer connects the output end of the entropy value analysis module with the second delay unit of the true random number generator 2.

[0144] Thereafter, the first counter outputs the count value C1, the second counter outputs the count value C2, and the first judgment circuit judges whether C1 / C2 is equal to an integer multiple of 0.5. If not, a new first signal is output to the first delay unit of the true random number generator 2 according to a preset increase value or decrease value, thereby adjusting the oscillation frequency of the second oscillator of the true random number generator 2. The above process is repeated until C1 / C2 is equal to an integer multiple of 0.5.

[0145] The third counter outputs the count value C3, and the second judgment circuit judges whether C3 is greater than the preset signal transition period threshold value M. M is set according to the target entropy value. If C3 is greater than M, a new second signal can be output to the second delay unit of the true random number generator 2 according to the preset increase value or decrease value, thereby adjusting the phase of the second oscillator of the true random number generator 2. Then repeat the above process of judging whether it is necessary to adjust the oscillation frequency of the second oscillator of the true random number generator 2 and adjusting the phase. If C3 is less than or equal to M, the adjustment is terminated.

[0146] Based on the same inventive concept, an embodiment of the present application also provides a chip, including the aforementioned true random number generator, or including the aforementioned integrated circuit.

[0147] The chip provided in the embodiments of the present application may be a random number generation chip that only encapsulates a random number sequence generator, or may be a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, an NPU (Neural-network Processing Unit) chip, etc., but is not limited to this.

[0148] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned chip.

[0149] The electronic device may be a small electronic device such as a CPU board, a graphics card, a dedicated integrated circuit, a controller, etc. that can be integrated into a large electronic device. In addition, the electronic device may also be an electronic device such as a mobile phone, a computer, a server, etc. that can directly provide services.

[0150] It is understandable that when the electronic device is an electronic device such as a mobile phone, a computer, a server, etc. that can directly provide services, in addition to the aforementioned chip, the electronic device may also have devices such as a memory, a communication bus, etc., to cooperate with the chip to complete complex tasks or provide complex services. Among them, the memory can be RAM (Random Access Memory), ROM (Read-Only Memory), flash memory, hard disk, etc., but it is not limited. The communication bus can be a USB (Universal Serial Bus), a CAN (Controller Area Network) bus, etc., but it is not limited.

[0151] In the embodiments provided in this application, it should be understood that the modules and methods of the disclosed products can be implemented in other ways. The embodiments described above are only exemplary. Another point is that the connections shown or discussed can be direct or indirect electrical connections through some interfaces or units.

[0152] Furthermore, the features in the various embodiments of the present application can be combined without conflict to obtain new embodiments.

[0153] In this document, relational terms such as first, second, third, fourth, fifth, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0154] As used herein, a plurality refers to two or more than two.

[0155] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A true random number generator, It is characterized in that include: First oscillator; A second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable; A sampling module, wherein a data input terminal of the sampling module is connected to a signal output terminal of the first oscillator, a clock terminal of the sampling module is connected to a signal output terminal of the second oscillator, and the sampling module is used to sample and output an output signal of the first oscillator according to an output signal of the second oscillator; An entropy analysis module, wherein the input end of the entropy analysis module is respectively connected to the signal output end of the sampling module, the signal output end of the first oscillator, and the signal output end of the second oscillator, the output end of the entropy analysis module is connected to the second oscillator, and the entropy analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator, and the output signal of the sampling module; The entropy value analysis module includes: a first counter, a second counter and a first judgment circuit; The first counter is connected to a preset reference clock source and a signal output terminal of the first oscillator respectively, so as to count the output signal of the first oscillator according to the reference clock source; The second counter is connected to the reference clock source and the signal output terminal of the second oscillator respectively, so as to count the output signal of the second oscillator according to the reference clock source; The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

2. The true random number generator as claimed in claim 1, It is characterized in that The second oscillator comprises: A first delay unit, wherein an input end of the first delay unit is connected to a first output end of the entropy value analysis module, and the first delay unit generates different delays in response to different output signals of the first output end.

3. The true random number generator as claimed in claim 1, It is characterized in that The true random number generator also includes a second delay unit and an enable signal receiving terminal; The input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; The input end of the second delay unit is connected to the second output end of the entropy value analysis module, and the second delay unit generates different delays in response to different output signals of the second output end.

4. The true random number generator as claimed in claim 1, It is characterized in that The entropy value analysis module includes: a third counter and a second judgment circuit; The third counter is connected to the signal output terminal of the second oscillator and the signal output terminal of the sampling module respectively, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator; The input end of the second judgment circuit is connected to the output end of the third counter, the output end of the second judgment circuit is connected to the second delay unit, and the second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

5. An integrated circuit, It is characterized in that include: Entropy analysis module and multiple true random number generators; Each of the true random number generators comprises: First oscillator; A second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable; A sampling module, wherein a data input terminal of the sampling module is connected to a signal output terminal of the first oscillator, a clock terminal of the sampling module is connected to a signal output terminal of the second oscillator, and the sampling module is used to sample and output an output signal of the first oscillator according to an output signal of the second oscillator; The input end of the entropy value analysis module is respectively connected to the signal output end of the sampling module of each true random number generator through a first multiplexer; The input end of the entropy value analysis module is also connected to the signal output end of the first oscillator of each of the true random number generators through a second multiplexer; The input end of the entropy value analysis module is also connected to the signal output end of the second oscillator of each of the true random number generators through a third multiplexer; The output end of the entropy value analysis module is respectively connected to the second oscillator of each of the true random number generators through a fourth multiplexer; The entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator of any one of the true random number generators according to the output signal of the first oscillator of the true random number generator, the output signal of the second oscillator and the output signal of the sampling module.

6. The integrated circuit as claimed in claim 5, It is characterized in that For any one of the true random number generators, the second oscillator includes: a first delay unit; The first output end of the entropy value analysis module is respectively connected to the input end of the first delay unit of each of the true random number generators through the fourth multiplexer; The first delay unit generates different delays in response to different output signals of the first output terminal.

7. The integrated circuit as claimed in claim 5, It is characterized in that For any one of the true random number generators, the true random number generator further includes a second delay unit and an enable signal receiving end; The input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; The second output end of the entropy value analysis module is connected to the input end of each of the second delay units of the true random number generator through a fifth multiplexer; The second delay unit generates different delays in response to different output signals of the second output terminal.

8. An integrated circuit as claimed in any one of claims 5 to 7, It is characterized in that The entropy value analysis module includes: a first counter, a second counter and a first judgment circuit; The first counter is connected to a preset reference clock source, and is respectively connected to the signal output end of the first oscillator of each of the true random number generators through a second multiplexer, so as to count the output signal of the first oscillator according to the reference clock source; The second counter is connected to the reference clock source and is respectively connected to the signal output end of the second oscillator of each of the true random number generators through the third multiplexer to count the output signal of the second oscillator according to the reference clock source; The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator of each true random number generator respectively through the fourth multiplexer; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

9. The integrated circuit as claimed in claim 7, It is characterized in that The entropy value analysis module includes: a third counter and a second judgment circuit; The third counter is respectively connected to the signal output end of the second oscillator of each of the true random number generators through the third multiplexer, and is respectively connected to the signal output end of the sampling module of each of the true random number generators through the first multiplexer, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator; The input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the input end of each of the second delay units of the true random number generator through the fifth multiplexer. The second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

10. A control method, It is characterized in that Applied to the true random number generator as claimed in any one of claims 1 to 4, the method comprises: The entropy value analysis module adjusts the oscillation frequency of the second oscillator in response to the rising edge of the output signal of the second oscillator and the rising edge or the falling edge of the output signal of the first oscillator not being aligned; The entropy analysis module responds to the alignment of the rising edge of the output signal of the second oscillator with the rising edge or falling edge of the output signal of the first oscillator, and determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is less than or equal to a preset signal jump cycle threshold; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is greater than the signal jump cycle threshold, the phase of the second oscillator is adjusted.

11. A control method, It is characterized in that Applied to the integrated circuit according to any one of claims 5 to 9, the method comprises: In response to a conduction control signal, the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer conduct the entropy value analysis module with a true random number generator among the multiple true random number generators corresponding to the conduction control signal; The entropy value analysis module adjusts the oscillation frequency of the second oscillator of the true random number generator in response to the rising edge of the output signal of the second oscillator of the true random number generator and the rising edge or the falling edge of the output signal of the first oscillator of the true random number generator not being aligned; The entropy analysis module responds to the alignment of the rising edge of the output signal of the second oscillator of the true random number generator with the rising edge or falling edge of the output signal of the first oscillator of the true random number generator, and determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is less than or equal to a preset signal jump cycle threshold; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is greater than the signal jump cycle threshold, the phase of the second oscillator of the true random number generator is adjusted.

12. A chip, It is characterized in that Includes the true random number generator as described in any one of claims 1-4, or includes the integrated circuit as described in any one of claims 5-9.

13. An electronic device, It is characterized in that Comprising the chip as claimed in claim 12.

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