A liquid crystal display, a display control method, and a display device.

Abstract

This application relates to the field of display technology, specifically providing a liquid crystal display (LCD), a display control method, and a display device, aiming to solve the problem that existing panel-side black screen protection affects user experience and makes it difficult to determine the cause of the abnormality. To this end, the LCD of this application includes a power management integrated circuit (IC) for outputting a gate level signal; a timing control circuit for switching from sending a first control timing signal corresponding to a normal gate level signal to a second control timing signal corresponding to an abnormal gate level signal in response to an instruction for an abnormal gate level signal; and a source driver IC that provides a source drive signal to the display panel based on the second control timing signal, so that a portion of the display panel displays an image. This avoids the problem of a complete black screen in existing technologies, which affects user experience, and facilitates convenient analysis of defective products, enabling rapid and effective determination of the cause of the abnormality.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically providing a liquid crystal display, a display control method, and a display device. Background Technology

[0002] As end-users increasingly demand higher display performance (such as refresh rate, resolution, and brightness), the power consumption of the display panel becomes increasingly larger. When abnormal displays such as broken pieces or horizontal lines appear on the panel, the load on the panel further increases. At this time, the output voltage (VGH / VGL) of the PCB (Printed Circuit Board) circuit in the display device will be pulled down. In related technologies, when the actual value of the output voltage falls below a certain value, power-off protection will be activated, and the display device will go black with no display.

[0003] Protecting the display device using the above methods affects the user experience and makes it difficult to determine the cause of the malfunction. Summary of the Invention

[0004] This application aims to solve the aforementioned technical problems, namely, to address the issue that existing panel-side black screen protection mechanisms negatively impact user experience and make it difficult to determine the cause of the anomaly.

[0005] In a first aspect, this application provides a liquid crystal display, which includes a display panel, a power management integrated circuit, a timing control circuit, and a source driver integrated circuit;

[0006] The power management integrated circuit is used to output a gate level signal;

[0007] The timing control circuit is used to switch from sending a first control timing signal to sending a second control timing signal in response to an abnormal gate level signal. The first control timing signal is the control timing signal corresponding to a normal gate level signal, and the second control timing signal is the control timing signal corresponding to an abnormal gate level signal.

[0008] The source driver integrated circuit provides a source driver signal to the display panel based on the second control timing signal, so that a portion of the display panel displays an image.

[0009] In some embodiments, a voltage comparator is further included, wherein a first input terminal of the voltage comparator is used to input a reference voltage, a second input terminal of the voltage comparator is used to input the gate level signal, and the output terminal of the voltage comparator is connected to the timing control circuit;

[0010] The timing control circuit is used to output the second control timing signal in response to a valid signal output by the voltage comparator.

[0011] In some embodiments, the power management integrated circuit further includes a memory, wherein the memory stores a reference voltage, and the power management integrated circuit is used to compare the gate level signal with the reference voltage, and selectively send an instruction indicating that the gate level signal is abnormal to the timing control circuit based on the comparison result.

[0012] In some embodiments, the first control timing signal and the second control timing signal are stored in the timing control circuit.

[0013] In some embodiments, the source driver integrated circuit includes a plurality of source driver sub-circuits, each source driver sub-circuit corresponding to control the data writing of pixel units in different columns of the display panel.

[0014] In some embodiments, the timing control circuit is configured to switch from sending a first control timing signal to sending a second control timing signal in response to an abnormal gate level signal instruction, including:

[0015] The timing control circuit is used to switch from sending the first control timing signal to sending the second control timing signal in response to an abnormal gate level signal instruction; wherein, the second control timing signal is used to control some of the multiple source driving sub-circuits to provide source driving signals to the display panel.

[0016] In some embodiments, the timing control circuit is used to send the first control timing signal or the second control timing signal to the source driver integrated circuit based on at least one pair of differential signal pairs.

[0017] In some embodiments, the system further includes a gate driver integrated circuit, and the timing control circuit is further configured to provide a gate timing signal to the gate driver integrated circuit, and the gate driver integrated circuit provides a gate driving signal to the display panel based on the gate timing signal.

[0018] In some embodiments, a level conversion circuit is further included, wherein the input terminal of the level conversion circuit is electrically connected to the power management integrated circuit and the timing control circuit, and the output terminal of the level conversion circuit is electrically connected to the gate driver integrated circuit.

[0019] In a second aspect, this application provides a display control method, the method being implemented based on a liquid crystal display as described in any of the preceding claims, comprising:

[0020] The power management integrated circuit outputs a gate level signal;

[0021] In response to an abnormal gate level signal, the timing control circuit switches from sending the first control timing signal to sending the second control timing signal.

[0022] The source driver integrated circuit provides a source driver signal to the display panel based on the second control timing signal, so that a portion of the display panel displays an image.

[0023] In a third aspect, this application provides a display device comprising a liquid crystal display as described in any of the preceding claims.

[0024] By adopting the above technical solution, this application can provide a liquid crystal display (LCD) including a display panel, a power management integrated circuit (IC), a timing control circuit, and a source driver IC. The power management IC is used to output a gate-level signal; the timing control circuit, in response to an abnormal gate-level signal instruction, switches from sending a first control timing signal to sending a second control timing signal to the source driver IC. The first control timing signal is the control timing signal corresponding to a normal gate-level signal, and the second control timing signal is the control timing signal corresponding to an abnormal gate-level signal. The source driver IC provides a source driving signal to the display panel based on the second control timing signal, so that a portion of the display panel displays an image. This method avoids the problem of a completely black screen in existing technologies, which affects the user experience. It also facilitates convenient analysis of defective products, improves analysis efficiency, and quickly and effectively determines the cause of abnormalities, thereby helping to improve the performance of the LCD in a timely manner. Attached Figure Description

[0025] The preferred embodiments of this application are described below with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a schematic diagram of the liquid crystal display structure provided in the embodiments of this application;

[0027] Figure 2 This is a waveform diagram of the source drive signal corresponding to the existing black screen protection method provided in this application;

[0028] Figure 3 This is a schematic diagram of the structure of a liquid crystal display provided in another embodiment of this application;

[0029] Figure 4 This is a schematic diagram of the partitioned display of the display panel provided in a specific example of this application;

[0030] Figure 5 This is a waveform diagram of the source drive signal corresponding to each pixel area of ​​the display panel provided in a specific example of this application;

[0031] Figure 6 This is a schematic flowchart of the display control method provided in the embodiments of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In some embodiments, see Figure 1 As shown, Figure 1 This is a schematic diagram of the liquid crystal display structure provided in the embodiments of this application. It is mainly divided into two parts: PCB circuit and display panel. The PCB circuit mainly includes a power management integrated circuit (PMIC) and a timing control register circuit (T-con IC). The panel can include a display area and a non-display area. The non-display area can include a source driver integrated circuit (Source IC) and a gate on array (GOA). The display area can include multiple pixel units. A thin film transistor is disposed in the pixel unit. The gate of the thin film transistor is electrically connected to the GOA through the gate line extending horizontally in the figure. The source of the thin film transistor is electrically connected to the Source IC through the data line extending vertically in the figure. The drain of the thin film transistor is connected to the pixel electrode.

[0034] The power management integrated circuit (PMIC) outputs gate level signals and provides them to the gate access array (GOA). These gate level signals include a gate high (VGH) signal and a gate low (VGL) signal. Additionally, the PMIC provides operating voltage to the timing control circuit and the source IC, as well as a gamma signal to the source IC, which adjusts the brightness of the displayed image based on the received gamma signal.

[0035] The timing control circuit T-con IC receives and decodes the control signal data from the front end. Based on the decoded data, it provides various voltage signals to drive the Source IC and GOA, which are then transmitted to the Panel to enable display. In some embodiments, the various voltage signals provided by the T-con IC may include a control timing signal (Data) for driving the Source IC and a gate timing signal (CPV, Clock for Pixel Voltage) for driving the GOA. The Source IC provides a source drive signal to the display panel based on the control timing signal (Data), and the gate drive IC provides a gate drive signal to the display panel based on the gate timing signal. Additionally, the various voltage signals may also include STV (Start of Vertical Sync).

[0036] In the prior art, see Figure 2 As shown, Figure 2 This is a waveform diagram of the source drive signal corresponding to the existing black screen protection method provided in this application. S-out represents the source drive signal output by the Source IC. The arrow in the diagram indicates that when the actual gate level signal is less than the reference voltage, black screen protection will be implemented, causing the entire display panel to go black, and S-out will have no signal output. This method affects the user experience and is not conducive to fault analysis.

[0037] In this embodiment, the timing control circuit can store two sets of control timing signals for driving the source IC: a first control timing signal and a second control timing signal. The first control timing signal corresponds to a normal gate level signal, and the second control timing signal corresponds to an abnormal gate level signal. In response to an abnormal gate level signal command, the timing control circuit switches from sending the first control timing signal to sending the second control timing signal. The source driver IC provides a source drive signal to the display panel based on the second control timing signal, causing a portion of the display panel to display an image.

[0038] In some embodiments, the timing control circuit is used to send a first control timing signal or a second control timing signal to the source driver integrated circuit based on at least one pair of differential signal pairs. Using differential signal pairs to send the first or second control timing signal improves the stability and reliability of data transmission. In some embodiments, the timing control circuit can send the first or second control timing signal to the source driver integrated circuit based on multiple pairs of differential signal pairs. By using multiple pairs of differential signal pairs to transmit data simultaneously, the data transmission rate can be increased. This improves both the stability and reliability of data transmission, while also increasing the data transmission rate, which facilitates faster response of the display panel and enables real-time display.

[0039] In some embodiments, based on a first control timing signal, the source driver integrated circuit can send a high-level signal to each column of the display panel, so that the entire display panel displays an image; based on a second control timing signal, the source driver integrated circuit can send a high-level signal to some columns of the display panel and a low-level signal to the remaining columns, so that a portion of the display panel displays an image while the rest does not. This partial blackout reduces the load on the display panel, facilitates intuitive observation of display panel anomalies, and allows for convenient analysis of the cause of the anomaly, thereby improving fault analysis efficiency and user experience.

[0040] In some embodiments, such as Figure 1 As shown, the PCB circuit may also include an interface connector for connecting to the front-end system, providing power supply voltage VDD to the PMIC, and transmitting control signal data to the T-con IC. In this embodiment, the control signal data can be transmitted based on the EDP (Embedded DisplayPort) protocol.

[0041] In some embodiments, such as Figure 1 As shown, the PCB circuit may also include a level shifter IC. The input terminals of the level shifter IC are electrically connected to the power management integrated circuit and the timing control circuit, respectively, and the output terminal of the level shifter IC is electrically connected to the gate driver integrated circuit. The level shifter IC can be used to amplify the gate timing signal and transmit the amplified gate timing signal to the GOA in the panel.

[0042] In the embodiments of this application, anomalies in the gate level signal can be determined based on software or hardware methods, as described below.

[0043] The PMIC provided in this application may further include a memory storing a reference voltage Vuvp. In some implementations, when an abnormality in the gate level signal is determined in software, the PMIC compares the gate level signal (VGH or VGL) with the reference voltage Vuvp, and selectively sends a gate level signal abnormality command to the timing control circuit based on the comparison result. Specifically, in this embodiment, when the comparison result shows that the gate level signal is less than the reference voltage, the PMIC sends a gate level signal abnormality command to the timing control circuit. It should be noted that VGH and VGL correspond to different reference voltages, and the gate level signal abnormality command can be sent based on the comparison result between VGH or VGL and its corresponding reference voltage.

[0044] In other embodiments, when anomalies in the gate level signal are determined in a hardware-based manner, see [reference needed]. Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a liquid crystal display provided in another embodiment of this application, which is in Figure 1 In addition, it may include a voltage comparator, with a first input terminal of the voltage comparator for inputting a reference voltage, a second input terminal of the voltage comparator for inputting a gate level signal, and an output terminal of the voltage comparator connected to a timing control circuit; the timing control circuit is used to output a second control timing signal in response to a valid signal output by the voltage comparator.

[0045] like Figure 3 As shown, the voltage comparator is located at the output of the PMIC. The PMIC can provide its stored reference voltage Vuvp to the voltage comparator. In some embodiments, the first input terminal can be the positive input terminal of the voltage comparator, and the second input terminal can be the negative input terminal. When the gate level signal is less than the reference voltage, the output terminal of the voltage comparator outputs a high level "1", and the timing control circuit responds to the high level "1" output by the voltage comparator by outputting a second control timing signal. When the gate level signal is greater than the reference voltage, the output terminal of the voltage comparator outputs a low level "0", and the timing control circuit responds to the low level "0" output by the voltage comparator by outputting a first control timing signal.

[0046] In some embodiments, the source driver integrated circuit may include multiple source driver sub-circuits, each source driver sub-circuit corresponding to controlling the data writing of pixel units in different columns of the display panel. Figure 3Taking the illustrated source driver integrated circuit as an example, it may include four source driver sub-circuits S1, S2, S3, and S4, wherein the driver sub-circuits S1, S2, S3, and S4 respectively control the data writing of pixel units in different columns of the display panel. A timing control circuit is used to switch from sending a first control timing signal to sending a second control timing signal in response to an abnormal gate level signal instruction; wherein the second control timing signal is used to control some of the multiple source driver sub-circuits to provide source drive signals to the display panel.

[0047] In some embodiments, when the panel load is high and black screen protection is required, in order to minimize the load on the display panel, a source drive signal can be provided to only one source drive sub-circuit. See [link to relevant documentation]. Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of the partitioned display panel provided in a specific example of this application. Figure 5 This is a waveform diagram of the source drive signal corresponding to each pixel area of ​​the display panel provided in a specific example of this application.

[0048] like Figure 4 As shown, the driving sub-circuits S1, S2, S3 and S4 sequentially control the pixel units of the four rectangular display areas in the display panel. When four pairs of differential signals are used to transmit source driving signals to each source driving sub-circuit, the four pairs of differential signals corresponding to S1 (RX1_1, RX2_1, RX3_1, RX4_1) can be set to output normally, while the four pairs of differential signals corresponding to S2 (RX1_2, RX2_2, RX3_2, RX4_2), the four pairs of differential signals corresponding to S3 (RX1_3, RX2_3, RX3_3, RX4_3), and the four pairs of differential signals corresponding to S4 (RX1_4, RX2_4, RX3_4, RX4_4) are set to have no data output. In some embodiments, when the driving sub-circuits S1, S2, S3 and S4 are each responsible for a quarter column of pixel units in the entire display area, only one source driving sub-circuit is provided with a source driving signal. At this time, the overall load of the panel is reduced by 3 / 4, and the PMIC can output normally, thereby achieving the effect of black screen protection and partitioned display.

[0049] Another aspect of this application provides a display control method, which is implemented based on the liquid crystal display described in any of the above embodiments, see [link to relevant documentation]. Figure 6 As shown, Figure 6 This is a schematic flowchart of a display control method provided in an embodiment of this application, which includes:

[0050] Step S11: The power management integrated circuit outputs a gate level signal;

[0051] Step S12: In response to an abnormal gate level signal instruction, the timing control circuit switches from sending the first control timing signal to sending the second control timing signal to the source driver integrated circuit.

[0052] Step S13: The source driver integrated circuit supplies a source drive signal to the display panel based on the second control timing signal, so that a portion of the display panel displays an image.

[0053] In some embodiments, the power management integrated circuit (PMIC) is also used to provide gate level signals to the gate interface (GOA), including a gate high level signal (VGH) and a gate low level signal (VGL). Additionally, the PMIC can also provide operating voltages to the timing control circuitry and the source IC, and provide a gamma signal to the source IC, which adjusts the brightness of the displayed image based on the received gamma signal.

[0054] The timing control circuit T-con IC receives and decodes the control signal data from the front end. Based on the decoded data, it provides various voltage signals to drive the Source IC and GOA, which are then transmitted to the Panel to enable display. In some embodiments, the various voltage signals provided by the T-con IC may include a control timing signal (Data) for driving the Source IC and a gate timing signal (CPV, Clock for Pixel Voltage) for driving the GOA. The Source IC provides a source drive signal to the display panel based on the control timing signal (Data), and the gate drive IC provides a gate drive signal to the display panel based on the gate timing signal. Additionally, the various voltage signals may also include STV (Start of Vertical Sync).

[0055] The timing control circuit can store two sets of control timing signals for driving the source IC: a first control timing signal and a second control timing signal. The first control timing signal corresponds to a normal gate level signal, while the second control timing signal corresponds to an abnormal gate level signal. In response to an abnormal gate level signal command, the timing control circuit switches from sending the first control timing signal to sending the second control timing signal to the source driver IC. Based on the second control timing signal, the source driver IC provides source drive signals to the display panel, causing a portion of the display panel to display an image.

[0056] In some embodiments, the timing control circuit is used to send a first control timing signal or a second control timing signal to the source driver integrated circuit based on at least one pair of differential signal pairs. Using differential signal pairs to send the first or second control timing signal improves the stability and reliability of data transmission. In some embodiments, the timing control circuit can send the first or second control timing signal to the source driver integrated circuit based on multiple pairs of differential signal pairs. By using multiple pairs of differential signal pairs to transmit data simultaneously, the data transmission rate can be increased. This improves both the stability and reliability of data transmission, while also increasing the data transmission rate, which facilitates faster response of the display panel and enables real-time display.

[0057] In some embodiments, the source driver integrated circuit may include multiple source driver sub-circuits, each source driver sub-circuit corresponding to control the data writing of pixel units in different columns of the display panel. Step S12 may specifically involve the timing control circuit switching from sending a first control timing signal to sending a second control timing signal in response to an instruction of an abnormal gate level signal; wherein, the second control timing signal is used to control some of the multiple source driver sub-circuits to provide source driving signals to the display panel.

[0058] In some embodiments, when an abnormality in the gate level signal is determined by software, the PMIC compares the gate level signal (VGH or VGL) with a reference voltage Vuvp, and selectively sends a gate level signal abnormality command to the timing control circuit based on the comparison result. Specifically, in this embodiment, the PMIC sends a gate level signal abnormality command to the timing control circuit when the comparison result shows that the gate level signal is less than the reference voltage. It should be noted that VGH and VGL correspond to different reference voltages, and the gate level signal abnormality command can be sent based on the comparison result between VGH or VGL and its corresponding reference voltage.

[0059] In other embodiments, when an anomaly in the gate level signal is determined in a hardware-based manner, the liquid crystal display may further include a voltage comparator. The first input terminal of the voltage comparator is used to input a reference voltage, the second input terminal of the voltage comparator is used to input the gate level signal, and the output terminal of the voltage comparator is connected to a timing control circuit. The timing control circuit is used to output a second control timing signal in response to a valid signal output by the voltage comparator.

[0060] Another aspect of this application provides a display device, which may include the liquid crystal display described in any of the above embodiments. In some embodiments, the display device may include: electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, or any product or component with display function.

[0061] The technical solutions of this application have been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A liquid crystal display, characterized in that, This includes the display panel, power management integrated circuit, timing control circuit, and source driver integrated circuit; The power management integrated circuit is used to output a gate level signal; The timing control circuit is used to switch from sending a first control timing signal to sending a second control timing signal in response to an abnormal gate level signal. The first control timing signal is the control timing signal corresponding to a normal gate level signal, and the second control timing signal is the control timing signal corresponding to an abnormal gate level signal. The source driver integrated circuit provides a source driver signal to the display panel based on the second control timing signal, so that a portion of the display panel displays an image.

2. The liquid crystal display according to claim 1, characterized in that, It also includes a voltage comparator, the first input terminal of which is used to input a reference voltage, the second input terminal of which is used to input the gate level signal, and the output terminal of which is connected to the timing control circuit; The timing control circuit is used to output the second control timing signal in response to a valid signal output by the voltage comparator.

3. The liquid crystal display according to claim 1, characterized in that, The power management integrated circuit further includes a memory, wherein the memory stores a reference voltage, and the power management integrated circuit is used to compare the gate level signal with the reference voltage, and selectively send an instruction indicating that the gate level signal is abnormal to the timing control circuit based on the comparison result.

4. The liquid crystal display according to claim 1, characterized in that, The first control timing signal and the second control timing signal are stored in the timing control circuit.

5. The liquid crystal display according to any one of claims 1 to 4, characterized in that, The source driver integrated circuit includes multiple source driver sub-circuits, each of which controls the data writing of pixel units in different columns of the display panel.

6. The liquid crystal display according to claim 5, characterized in that, The timing control circuit, in response to an abnormal gate level signal instruction, switches from sending a first control timing signal to sending a second control timing signal, including: The timing control circuit is used to switch from sending the first control timing signal to sending the second control timing signal in response to an abnormal gate level signal instruction; wherein, the second control timing signal is used to control some of the multiple source driving sub-circuits to provide source driving signals to the display panel.

7. The liquid crystal display according to any one of claims 1 to 4, characterized in that, The timing control circuit is used to send the first control timing signal or the second control timing signal to the source driver integrated circuit based on at least one pair of differential signals.

8. The liquid crystal display according to any one of claims 1 to 4, characterized in that, It also includes a gate driver integrated circuit, and the timing control circuit is further used to provide a gate timing signal to the gate driver integrated circuit, and the gate driver integrated circuit provides a gate driving signal to the display panel based on the gate timing signal.

9. The liquid crystal display according to claim 8, characterized in that, It also includes a level conversion circuit, the input of which is electrically connected to the power management integrated circuit and the timing control circuit, and the output of which is electrically connected to the gate driver integrated circuit.

10. A display control method, characterized in that, The method is implemented based on the liquid crystal display according to any one of claims 1 to 9, and includes: The power management integrated circuit outputs a gate level signal; In response to an abnormal gate level signal, the timing control circuit switches from sending the first control timing signal to sending the second control timing signal. The source driver integrated circuit provides a source driver signal to the display panel based on the second control timing signal, so that a portion of the display panel displays an image.

11. A display device, characterized in that, The liquid crystal display includes any one of claims 1 to 9.

Images