A timing and synchronous sampling method and system for traveling wave ranging

Abstract

A timing and synchronous sampling method and system for traveling wave ranging, receiving an external timing pulse signal, the external signal comes from the Beidou satellite timing pulse signal or the IRIG‑B code timing signal output by other clock devices, and the external signal will be used as a time reference; implementing a crystal oscillator taming algorithm to achieve frequency and phase synchronization between the crystal oscillator in the system and the external timing pulse signal; using the tamed crystal oscillator to generate a synchronous clock pulse, which has a phase correspondence with the external timing pulse, so that the phase locking error is less than the crystal oscillator multiplication pulse width; using an amortized modulation algorithm, using a self-developed long-period amortized modulation algorithm, outputting a synchronous sampling pulse; by modulating the PWM module in the FPGA, outputting a synchronous sampling pulse, and controlling the interval deviation of the synchronous sampling pulse. The timing accuracy and sampling synchronization accuracy problems in traveling wave ranging are solved, and the total ranging error introduced by the timing link and the sampling pulse generation link is controlled within 10 meters, thereby improving the accuracy of traveling wave ranging.

Description

Technical Field

[0001] The invention belongs to the technical field of relay protection of electric power systems, and more specifically, relates to a high-precision timing and synchronous sampling technology for traveling wave ranging. Background Art

[0002] With the continuous commissioning of ultra-high voltage long-distance transmission lines in my country, improving the accuracy and precision of fault distance measurement is of great significance to reducing the pressure of on-site maintenance and shortening the power outage time. The traditional impedance distance measurement method is easily affected by factors such as system operation mode, short-circuit transition resistance and transformer transmission error, and it is difficult to meet the current precise positioning requirements. The two-terminal traveling wave distance measurement algorithm is the most accurate one among the existing fault distance measurement algorithms. It can perform fault distance measurement by measuring the time difference when the initial traveling wave of the fault reaches the measurement points at both ends of the line. The most critical indicator affecting the accuracy of two-terminal traveling wave distance measurement is the timing accuracy and synchronous sampling accuracy at both ends of the line. Since the propagation speed of the traveling wave in the line is close to the speed of light, and the timing and synchronous sampling errors at both ends of the line increase by 1 microsecond, the corresponding fault distance measurement deviation increases by about 0.3 kilometers. Therefore, high-precision timing and synchronous sampling technology are crucial to the accuracy of traveling wave distance measurement.

[0003] There are many factors that affect the accuracy of timing and synchronous sampling. The invention of the constant temperature crystal oscillator has eliminated the influence of ambient temperature on the oscillation period of the crystal oscillator to a certain extent, making it possible to obtain an oscillation source with extremely small short-term deviations. The Beidou satellite and other satellite timing systems have made it possible to obtain a clock source with extremely small long-term deviations. The combination of the two has the necessary conditions for high-precision timing.

[0004] In current engineering practice, the actual frequency of a crystal oscillator is generally not completely consistent with the nominal frequency, and the deviation is generally less than 10ppm. This deviation is often ignored, or the actual measurement value of 1 second is simply retested to replace the nominal frequency. The measurement error is still relatively large, about 16 nanoseconds / second (see the analysis in the invention content section below for details). The method proposed in this patent can reduce the error by 2 orders of magnitude.

[0005] There are also documents that disclose technical solutions related to crystal oscillator training, but their uses are all for long-term self-timekeeping logic of crystal oscillators when external clocks are lost. There is no document that uses crystal oscillator training to improve the accuracy of traveling wave ranging, nor is there any public document that proposes long-period crystal oscillator training or discloses the period length parameters of crystal oscillator training. This has led to a large timing error in the timing link.

[0006] After the time is aligned, when the sampling pulse is generated by the clock pulse, there are still problems of non-divisibility and cumulative error during continuous pulse modulation. When the number of clock pulses in 1 second is divided by the number of sampling pulses in 1 second, if it is not divisible, the error will be amortized within 1 second, which will lead to excessive error. After long-term continuous output, cumulative error will also occur, which will further affect the synchronization accuracy of the synchronous sampling pulse.

[0007] The errors generated by the above two links of timing and synchronous sampling pulse modulation are superimposed, and the superimposed errors will eventually be reflected in the accuracy of traveling wave ranging. Every 1 microsecond synchronous sampling pulse error will cause a ranging error of about 300 meters. Therefore, it is very important to improve the synchronization accuracy of timing and synchronous sampling pulses and reduce the synchronization errors introduced by related links to improve the accuracy of traveling wave ranging. Summary of the invention

[0008] In order to solve the deficiencies in the prior art, the present invention provides a high-precision timing and synchronous sampling technology for traveling wave ranging, which solves the key technical problems such as timing accuracy and sampling synchronization accuracy in traveling wave ranging, provides detailed implementation methods and steps for each module, analyzes the error source of each module, and proposes a technical solution to eliminate the error, so as to control the ranging error introduced in the timing and sampling pulse generation links within 10 meters.

[0009] The present invention adopts the following technical solution. A first aspect of the present invention provides a timing and synchronous sampling method for traveling wave ranging, comprising the following steps:

[0010] Step 1, receiving an external timing pulse signal as a time reference, the external timing pulse signal comes from the Beidou satellite timing pulse signal or the IRIG-B code timing signal output by other clock devices;

[0011] Step 2, using a long-period crystal oscillator taming algorithm to achieve frequency and phase synchronization between the crystal oscillator in the timing device and the external timing pulse signal;

[0012] Step 3, using the disciplined crystal oscillator to generate a high-frequency phase-locked clock pulse, which has a phase correspondence with the external timing pulse, so that the phase locking error is less than the crystal oscillator frequency multiplication pulse width;

[0013] Step 4: long-period amortized modulation algorithm, using the long-period amortized modulation algorithm to output synchronous sampling pulses;

[0014] Step 5: Output synchronous sampling pulses by modulating the PWM module in the FPGA to control the interval deviation of the synchronous sampling pulses.

[0015] Preferably, in step 1, the signal of the GPS satellite timing system is used as a backup solution for the Beidou satellite timing system.

[0016] Preferably, in step 2, the long period crystal oscillator taming algorithm specifically includes:

[0017] Step 2.1, continuous periodic iterative taming, through continuous periodic taming, the frequency of the crystal oscillator is adjusted to be consistent with the nominal frequency;

[0018] Step 2.2, the taming period is not less than 1 minute;

[0019] Step 2.3: The initial taming time is no less than 10 minutes, where the initial taming time refers to the time required from the device being powered on to the crystal oscillator reaching a stable working state;

[0020] Step 2.4, iterative taming. After one cycle is completed, the next taming cycle starts immediately and the iteration continues.

[0021] Preferably, in step 2.2, the taming period is 128 seconds, and the measurement error of the second period is 0.125 nanoseconds, which is used to reduce the measurement error.

[0022] Preferably, in step 2.3, the initial taming time of the long-period crystal oscillator taming algorithm is 15 minutes, which is used to gradually heat the constant-temperature crystal oscillator to a predetermined operating temperature and keep the temperature constant.

[0023] Preferably, step 3 specifically includes:

[0024] The tamed crystal oscillator frequency-doubled pulse is used to lock the phase of the external timing pulse, and the phase locking error is less than 1 crystal oscillator frequency-doubled pulse width;

[0025] The crystal oscillator frequency multiplication pulse refers to the pulse of the frequency obtained after the crystal oscillator pulse is multiplied by the FPGA phase-locked loop;

[0026] The high-frequency phase-locked clock pulse refers to the clock pulse obtained after the crystal oscillator frequency-multiplied pulse locks the phase of the external timing pulse. The high-frequency phase-locked clock pulse has a corresponding phase relationship with the external timing pulse.

[0027] Preferably, in step 3, the constant temperature crystal oscillator pulse frequency is 25 MHz, and after frequency doubling and phase locking, the phase-locked clock pulse frequency is 125 MHz; the maximum phase locking error is the width of the frequency doubling pulse, which is 8 nanoseconds for a pulse width of 125 MHz.

[0028] Preferably, step 4 specifically includes:

[0029] The long-period amortized modulation algorithm is used to modulate the PWM module set in the FPGA to output synchronous sampling pulses;

[0030] The amortization of the long-cycle amortized modulation algorithm is used when the high-frequency phase-locked clock pulse and the synchronous sampling pulse are not integer multiples. The remainder after division is evenly distributed over the entire cycle to control the deviation of the synchronous sampling pulse.

[0031] The dividend of the high-frequency phase-locked amortized modulation algorithm is selected as the total number N of the long-period high-frequency phase-locked clock pulses, rather than the frequency value of the high-frequency phase-locked clock pulses;

[0032] The divisor of the long-period amortized modulation algorithm is selected as the product of the synchronous sampling pulse frequency value Fs and the long-period second number T;

[0033] Furthermore, in step 4, the calculation formula of the remainder R of the amortized modulation algorithm is:

[0034] R = (N mod (T × Fs))

[0035] The final implementation result of the amortized modulation algorithm is that, with a total of N phase-locked clock pulses as the description object, exactly (T*Fs) sampling pulses will be output, and the maximum and minimum deviations between the sampling pulse intervals are 1 phase-locked clock pulse interval;

[0036] If the external timing pulse is an IRIG-B code timing signal output by a third-party clock device, the timing error introduced by the clock device itself needs to be added to the final timing error.

[0037] The second aspect of the present invention provides a timing and synchronous sampling system for traveling wave ranging, comprising: an external timing signal receiver, a long period crystal oscillator taming module, an external timing signal phase locking module, a synchronous clock pulse generator, an amortized modulation module and a synchronous sampling module; and running the timing and synchronous sampling method for traveling wave ranging:

[0038] The external timing signal receiver is used to receive the external timing signal;

[0039] The crystal oscillator training module uses the crystal oscillator training algorithm to make the crystal oscillator frequency in the system consistent with the external timing signal, including iterative adjustment of the crystal oscillator frequency, selection of an appropriate training cycle, and waiting for sufficient initial training time;

[0040] The external timing signal phase locking module uses the disciplined crystal oscillator frequency-doubled pulse to synchronize the phase of the external timing signal with the system clock, making the time reference consistent;

[0041] The synchronous clock pulse generator is used to generate a synchronous clock pulse or a synchronous signal from a locked external timing signal for operation in a synchronous system;

[0042] The amortized modulation module is used to generate high-precision synchronous sampling pulses to make the sampling pulses evenly distributed;

[0043] The synchronous sampling module is used to drive the analog-to-digital AD sampling chip to perform synchronous sampling through the generated synchronous sampling pulses, and obtain synchronous sampling data for traveling wave ranging.

[0044] Compared with the prior art, the beneficial effects of the present invention include at least: the invention of the constant temperature crystal oscillator eliminates the influence of the ambient temperature on the crystal oscillator oscillation period, making it possible to obtain an oscillation source with extremely small short-term deviation, and the Beidou satellite and other satellite timing systems make it possible to obtain a clock source with extremely small long-term deviation. The combination of the two has the necessary conditions for high-precision timing. Based on the above premise, the present invention analyzes the error sources and minimization methods of each link of timing and synchronous sampling, and proposes a high-precision timing and synchronous sampling technology for traveling wave ranging, which reduces the maximum error introduced by the timing and sampling pulse generation link to 16 nanoseconds, and controls the ranging error introduced by the total timing and sampling pulse generation link including the satellite timing pulse error represented by the Beidou satellite within 10 meters, greatly improving the accuracy of traveling wave ranging. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 The invention discloses a timing and synchronous sampling method for traveling wave ranging and a schematic diagram of the overall system flow. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The embodiments described in this application are only part of the embodiments of the present invention, not all of them. Based on the spirit of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0047] The present invention provides a timing and synchronous sampling technology for traveling wave ranging. By analyzing the error sources and minimization methods of each link of timing and synchronous sampling, a high-precision timing and synchronous sampling technology for traveling wave ranging is proposed, which reduces the maximum error introduced by the timing and sampling pulse generation link to 16 nanoseconds, and controls the ranging error introduced by the total timing and sampling pulse generation link including the satellite timing pulse error represented by Beidou satellite within 10 meters, thereby greatly improving the accuracy of traveling wave ranging.

[0048] like Figure 1 As shown, the present invention provides a timing and synchronous sampling method for traveling wave ranging, comprising the following steps:

[0049] Step 1, receiving an external timing pulse signal, the external signal comes from the Beidou satellite timing pulse signal or the IRIG-B code timing signal output by other clock devices, and the external signal will be used as a time reference;

[0050] Preferably, in step 1, the signal of the GPS satellite timing system can be used as a backup solution for the Beidou satellite timing system.

[0051] Step 2, implement the crystal oscillator taming algorithm to achieve frequency and phase synchronization between the crystal oscillator in the system and the external timing pulse signal;

[0052] In step 2, the long period crystal oscillator taming algorithm specifically includes:

[0053] Step 2.1, continuous periodic iterative taming, through continuous periodic taming, the frequency of the crystal oscillator is adjusted to be consistent with the nominal frequency;

[0054] Step 2.2, taming cycle, needs to be no less than 1 minute, and the typical value is 128 seconds;

[0055] Step 2.3, initial taming time, needs to be no less than 10 minutes, the typical value is 15 minutes;

[0056] Step 2.4, iterative taming, after one cycle is completed, the next taming cycle starts immediately and the iteration continues.

[0057] Preferably, in step 2.2, the crystal oscillator taming algorithm has a typical value of 128 seconds in order to control the taming error;

[0058] The theoretical maximum error of the double-ended measurement edge is calculated with two measurement pulses, and the pulse width is 8 nanoseconds. If it is tamed with a short period of 1 second, the maximum measurement error of the second period is 16 nanoseconds.

[0059] According to the long period crystal oscillator training, the total maximum deviation of 128 seconds is 16 nanoseconds, so the measurement error of the second period is 0.125 nanoseconds, which is reduced by two orders of magnitude.

[0060] Preferably, in step 2.3, the initial taming time of the crystal oscillator taming algorithm refers to the time required from the power-on of the device to the crystal oscillator reaching a stable working state, because the constant temperature crystal oscillator needs to be gradually heated to a predetermined operating temperature and keep the temperature constant. The typical value of 15 minutes here is an empirical value obtained based on the device manual of the crystal oscillator manufacturer and actual measurements. The time required for products with different processes from different manufacturers is different and does not affect the rigor of this patent.

[0061] Furthermore, there are two main methods for taming the constant temperature crystal oscillator: one is to count the crystal pulses with the long period T, and observe the product of the count value N and the nominal frequency F of the crystal oscillator multiplied by the long period seconds T, and according to the difference between the two (NF×T), adjust the voltage to adjust the temperature-compensated voltage-controlled oscillator so that the final clock frequency reaches the nominal frequency; the other is to only record and update the change of the count value N, without adjusting the crystal oscillator temperature compensation voltage, but all subsequent calculations must use the latest N value, and can no longer be based on the nominal frequency value of the crystal oscillator. Both methods can be used, and the latter method is simpler and more reliable to implement.

[0062] Step 3, using the disciplined crystal oscillator to generate a synchronous phase clock pulse, which has a phase correspondence with the external timing pulse, so that the phase locking error is less than the crystal oscillator multiplication pulse width;

[0063] Step 3 specifically includes:

[0064] The tamed crystal oscillator frequency-doubled pulse is used to lock the phase of the external timing pulse, and the phase locking error is less than 1 crystal oscillator frequency-doubled pulse width;

[0065] The crystal oscillator frequency multiplication pulse refers to the pulse of the frequency obtained after the crystal oscillator pulse is multiplied by the FPGA phase-locked loop;

[0066] The high-frequency phase-locked clock pulse refers to the clock pulse obtained after the crystal oscillator frequency-multiplied pulse locks the phase of the external timing pulse. The high-frequency phase-locked clock pulse has a corresponding phase relationship with the external timing pulse.

[0067] Preferably, in step 3, taking the typical value of the constant temperature crystal oscillator pulse frequency of 25 MHz as an example, after frequency multiplication and phase locking, the phase-locked clock pulse frequency is usually 125 MHz;

[0068] The crystal oscillator taming method actually obtains the phase-locked clock pulse count N after frequency multiplication, rather than the crystal oscillator frequency count M. There is a frequency multiplication relationship between the two. Taking 25MHz multiplied to 125MHz as an example, N=5*M;

[0069] The maximum phase locking error is the width of one phase-locked clock pulse. Taking a 25MHz crystal oscillator multiplied to 125MHz as an example, the maximum phase locking error is the width of the multiplied pulse, that is, the pulse width of 125MHz is 8 nanoseconds, not the pulse width of the 25MHz crystal oscillator pulse, which is 40 nanoseconds.

[0070] Step 4: Amortized modulation algorithm, using the self-developed amortized modulation algorithm to output synchronous sampling pulses;

[0071] Preferably, step 4 specifically includes:

[0072] The long-period amortized modulation algorithm is used to modulate the PWM module set in the FPGA to output synchronous sampling pulses;

[0073] The amortization of the long-cycle amortized modulation algorithm is used when the high-frequency phase-locked clock pulse and the synchronous sampling pulse are not integer multiples. The remainder after division is evenly distributed over the entire cycle to control the deviation of the synchronous sampling pulse.

[0074] The dividend of the high-frequency phase-locked amortized modulation algorithm is selected as the total number M of the long-period high-frequency phase-locked clock pulses, rather than the frequency value of the high-frequency phase-locked clock pulses;

[0075] The divisor of the long-period amortized modulation algorithm is selected as the product of the synchronous sampling pulse frequency value Fs and the long-period second number T;

[0076] Furthermore, in step 4, the calculation formula of the remainder R of the amortized modulation algorithm is:

[0077] R = (N mod (T × Fs))

[0078] The final implementation result of the amortized modulation algorithm is that, with a total of N phase-locked clock pulses as the description object, exactly (T*Fs) sampling pulses will be output, and the maximum and minimum deviations between the sampling pulse intervals are 1 phase-locked clock pulse interval, that is, 8 nanoseconds. Therefore, the maximum error introduced by the amortized modulation algorithm to generate synchronous sampling pulses is 8 nanoseconds.

[0079] Based on the external timing pulse, taking the 25MHz crystal oscillator multiplied to 125MHz as an example, the maximum error introduced by the crystal oscillator taming module is 8 nanoseconds, and the maximum error introduced by the amortized PWM modulation module is 8 nanoseconds. Considering only the maximum error introduced by the timing and sampling pulse generation links, the total error is 16 nanoseconds.

[0080] Considering that the external timing pulse is a satellite timing signal represented by Beidou, the total error will increase by about 10 nanoseconds, and the total will not exceed 26 nanoseconds; at 0.3 meters / nanosecond, the final traveling wave ranging deviation will not exceed 7.8 meters;

[0081] If the external timing pulse is an IRIG-B code timing signal output by a third-party clock device, the timing error introduced by the clock device itself needs to be added to the final timing error.

[0082] Step 5: Output synchronous sampling pulses by modulating the PWM module in the FPGA to control the interval deviation of the synchronous sampling pulses.

[0083] The present invention provides a timing and synchronous sampling system for traveling wave ranging, comprising: an external timing signal receiver, a long period crystal oscillator taming module, an external timing signal phase locking module, a synchronous clock pulse generator, an amortized modulation module and a synchronous sampling module; and running the timing and synchronous sampling method for traveling wave ranging:

[0084] The external timing signal receiver is used to receive the external timing signal;

[0085] The crystal oscillator training module uses the crystal oscillator training algorithm to make the crystal oscillator frequency in the system consistent with the external timing signal, including iterative adjustment of the crystal oscillator frequency, selection of an appropriate training cycle, and waiting for sufficient initial training time;

[0086] The external timing signal phase locking module uses the disciplined crystal oscillator frequency-doubled pulse to synchronize the phase of the external timing signal with the system clock, making the time reference consistent;

[0087] The synchronous clock pulse generator is used to generate a synchronous clock pulse or a synchronous signal from a locked external timing signal for operation in a synchronous system;

[0088] The amortized modulation module is used to generate high-precision synchronous sampling pulses to make the sampling pulses evenly distributed;

[0089] The synchronous sampling module is used to drive the analog-to-digital (AD) sampling chip to perform synchronous sampling by generating synchronous sampling pulses, and obtain synchronous sampling data for traveling wave ranging.

[0090] Compared with the prior art, the beneficial effects of the present invention include at least: the invention of the constant temperature crystal oscillator eliminates the influence of the ambient temperature on the crystal oscillator oscillation period, making it possible to obtain an oscillation source with extremely small short-term deviation, and the Beidou satellite and other satellite timing systems make it possible to obtain a clock source with extremely small long-term deviation. The combination of the two has the necessary conditions for high-precision timing. Based on the above premise, the present invention analyzes the error sources and minimization methods of each link of timing and synchronous sampling, and proposes a high-precision timing and synchronous sampling technology for traveling wave ranging, which reduces the maximum error introduced by the timing and sampling pulse generation link to 16 nanoseconds, and controls the ranging error introduced by the total timing and sampling pulse generation link including the satellite timing pulse error represented by the Beidou satellite within 10 meters, greatly improving the accuracy of traveling wave ranging.

[0091] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A timing and synchronous sampling method for traveling wave ranging, characterized in that: The following steps are involved: Step 1, receiving an external timing pulse signal as a time reference, the external timing pulse signal comes from the Beidou satellite timing pulse signal or the IRIG-B code timing signal output by other clock devices; Step 2: Based on the time reference, the long-period crystal oscillator taming algorithm is used to synchronize the frequency and phase of the crystal oscillator in the timing device with the external timing pulse signal; In step 2, the long-period crystal oscillator taming algorithm specifically includes: continuous period iterative taming, recording the measured frequency of the crystal oscillator, and replacing the nominal frequency of the crystal oscillator with the measured frequency; after one taming cycle is completed, the next taming cycle starts immediately; the taming cycle is not less than 1 minute; the initial taming time is not less than 10 minutes, where the initial taming time refers to the time required from the device being powered on to the crystal oscillator reaching a stable working state; Step 3, using the disciplined crystal oscillator to generate a high-frequency phase-locked clock pulse, which has a phase correspondence with the external timing pulse, so that the phase locking error is less than the crystal oscillator frequency multiplication pulse width; Step 4, based on the high-frequency phase-locked clock pulse, use the long-cycle amortized modulation algorithm to generate a synchronous sampling pulse; Step 4 specifically includes: the long-cycle amortized modulation algorithm is used to modulate the PWM module set in the FPGA to output a synchronous sampling pulse; the dividend of the long-cycle amortized modulation algorithm is selected as the total number of high-frequency phase-locked clock pulses N, rather than the frequency value of the high-frequency phase-locked clock pulse; the divisor of the long-cycle amortized modulation algorithm is selected as the product of the synchronous sampling pulse frequency value Fs and the long-cycle second number T; the calculation formula of the remainder R of the long-cycle amortized modulation algorithm is: R=(N mod(T×Fs)); when the high-frequency phase-locked clock pulse and the synchronous sampling pulse are not integer multiples, the remainder after the integer division is evenly distributed into a long period to control the deviation of the synchronous sampling pulse; the final result of the long-period amortized modulation algorithm is that, with a total of N high-frequency phase-locked clock pulses as the object, T×Fs sampling pulses are output, and the maximum deviation of the interval of the sampling pulses is 1 phase-locked clock pulse interval; the maximum deviation of the sampling pulse interval is 1 phase-locked clock pulse interval; Step 5: By modulating the PWM module in the FPGA, the synchronous sampling pulse is output, the interval deviation of the synchronous sampling pulse is controlled, and traveling wave ranging is performed.

2. The timing and synchronous sampling method for traveling wave ranging according to claim 1, characterized in that: In step 1, the timing pulse signal of the GPS satellite timing system is used as a backup solution for the Beidou satellite timing pulse signal.

3. The timing and synchronous sampling method for traveling wave ranging according to claim 1, characterized in that: Step 3 specifically includes: The tamed crystal oscillator frequency-doubled pulse is used to lock the phase of the external timing pulse, and the phase locking error is less than 1 crystal oscillator frequency-doubled pulse width; The crystal oscillator frequency multiplication pulse refers to the pulse of the frequency obtained after the crystal oscillator pulse is multiplied by the FPGA phase-locked loop; The high-frequency phase-locked clock pulse refers to the clock pulse obtained after the crystal oscillator frequency-multiplied pulse locks the phase of the external timing pulse. The high-frequency phase-locked clock pulse has a corresponding phase relationship with the external timing pulse.

4. The timing and synchronous sampling method for traveling wave ranging according to claim 3, characterized in that: In step 3, the crystal pulse frequency is 25 MHz. After frequency doubling and phase locking, the phase-locked clock pulse frequency is 125 MHz. The maximum phase locking error is the width of the frequency doubling pulse, which is 8 nanoseconds for a pulse width of 125 MHz.

5. A timing and synchronous sampling system for traveling wave ranging, comprising: Signal receiving module, long period crystal oscillator taming module, high frequency phase-locked clock generation module, synchronous sampling pulse generation module and traveling wave ranging module; characterized in that: A signal receiving module is used to receive an external timing pulse signal as a time reference, wherein the external timing pulse signal comes from a Beidou satellite timing pulse signal or an IRIG-B code timing signal output by other clock devices; A long-period crystal oscillator taming module is used to synchronize the frequency and phase of the crystal oscillator in the timing device with the external timing pulse signal based on the time reference by using a long-period crystal oscillator taming algorithm; the long-period crystal oscillator taming algorithm specifically includes: continuous period iterative taming, recording the measured frequency of the crystal oscillator, and replacing the nominal frequency of the crystal oscillator with the measured frequency; after a taming cycle is completed, the next taming cycle starts immediately, and the taming cycle is not less than 1 minute; the initial taming time is not less than 10 minutes, wherein the initial taming time refers to the time required from the device being powered on to the crystal oscillator reaching a stable working state; A high-frequency phase-locked clock generation module is used to use a disciplined crystal oscillator to generate a high-frequency phase-locked clock pulse, which has a phase correspondence with an external timing pulse, so that the phase locking error is less than the crystal oscillator frequency multiplication pulse width; The synchronous sampling pulse generation module is used to generate synchronous sampling pulses based on the high-frequency phase-locked clock pulse using a long-cycle amortized modulation algorithm; the long-cycle amortized modulation algorithm specifically includes: the long-cycle amortized modulation algorithm is used to modulate the PWM module set in the FPGA to output synchronous sampling pulses; the dividend of the long-cycle amortized modulation algorithm is selected as the total number of high-frequency phase-locked clock pulses N, rather than the frequency value of the high-frequency phase-locked clock pulse; the divisor of the long-cycle amortized modulation algorithm is selected as the product of the synchronous sampling pulse frequency value Fs and the long-cycle second number T; the calculation formula of the remainder R of the long-cycle amortized modulation algorithm is: R=(N mod(T×Fs)); when the high-frequency phase-locked clock pulse and the synchronous sampling pulse are not integer multiples, the remainder after the integer division is evenly distributed into a long period to control the deviation of the synchronous sampling pulse; the final result of the long-period amortized modulation algorithm is that, with a total of N high-frequency phase-locked clock pulses as the object, T×Fs sampling pulses are output, and the maximum deviation of the interval of the sampling pulses is 1 phase-locked clock pulse interval; the maximum deviation of the sampling pulse interval is 1 phase-locked clock pulse interval; The traveling wave ranging module outputs synchronous sampling pulses by modulating the PWM module in the FPGA, controls the interval deviation of the synchronous sampling pulses, and performs traveling wave ranging.

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