A power amplifier circuit and chip with high gain

Abstract

The present invention discloses a power amplifier circuit and chip with high gain. The power amplifier circuit includes an amplifying unit and a biasing unit; wherein the first output terminal and the second output terminal of the biasing unit are respectively connected to the first biasing terminal and the second biasing terminal of the amplifying unit; the amplifying unit adopts a circuit structure of amplifying tube and a common source and common gate structure cascaded, which is used to amplify the input radio frequency signal; the biasing unit adopts an operational amplifier and a PMOS tube to form a two-stage amplifying structure of negative feedback, combined with a voltage divider structure formed by the PMOS tube and a resistor and capacitor filter structure, which is used to provide two stable bias voltages for the common source and common gate structure of the amplifying unit. The biasing unit is combined with the technical solution of the amplifying unit to improve the output impedance of the power amplifier circuit, and effectively suppress the second harmonics generated by the circuit while achieving the improvement of the power amplifier gain.

Description

Technical Field

[0001] The invention relates to a power amplifier circuit with high gain, and also to an integrated circuit chip comprising the power amplifier circuit, belonging to the technical field of radio frequency integrated circuits. Background Art

[0002] In wireless communication systems, the signal transmission of the RF front end uses the transmitter to modulate the baseband signal onto the carrier, and then transmits the RF signal through the antenna after amplification by the power amplifier. Therefore, the power amplifier circuit is the core module of the transmission path, and its performance directly affects the communication quality of the entire system. Generally, the RF transceiver system hopes that the power of the transmitted RF signal is large enough, and at the same time, it must have sufficient harmonic suppression capability to ensure that the transmitted RF signal does not interfere with communications in other frequency bands.

[0003] In the prior art, the gain of a power amplifier can be improved by cascading amplifier tubes into a cascode structure. However, in actual operation, the gate voltage fluctuations of the two MOS tubes in the cascode structure will cause a decrease in the gain and harmonic performance of the power amplifier circuit.

[0004] In the Chinese invention application with application number 202210225767.9, a W-band high-gain power amplifier circuit is disclosed. The high-gain power amplifier circuit includes a cascaded N-stage amplifier circuit, and each stage amplifier circuit includes: an input matching network, a first bias resistor, a common emitter transistor, an interconnect inductor, a common base transistor, a bias decoupling capacitor, a second bias resistor, and an output matching network. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a power amplifier circuit with high gain.

[0006] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the power amplifier circuit.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, there is provided a power amplifier circuit with high gain, comprising an amplification unit and a bias unit; wherein:

[0009] The first output terminal and the second output terminal of the bias unit are respectively connected to the first bias terminal and the second bias terminal of the amplifying unit; the RF signal input terminal is connected to the input terminal of the amplifying unit, and the output terminal of the amplifying unit is connected to the output terminal of the power amplifier circuit;

[0010] The amplification unit includes an amplification tube and a common source and common gate structure, which is used to amplify the power of the input radio frequency signal;

[0011] The bias unit comprises an amplifier circuit, a voltage divider circuit and a filter circuit, and is used to provide two stable bias voltages for the common-source and common-gate structure of the amplifier unit.

[0012] Preferably, the amplification unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a first inductor; wherein,

[0013] The first NMOS tube is an amplifier tube;

[0014] The second NMOS tube and the third NMOS tube form a common source and common gate structure, so as to improve the output impedance;

[0015] The first inductor is used to provide impedance for high-frequency oscillation.

[0016] Preferably, the RF signal input terminal is connected to the gate terminal of the first NMOS tube, the source terminal of the first NMOS tube is connected to the ground potential terminal, the drain terminal of the first NMOS tube is connected to the source terminal of the second NMOS tube, the drain terminal of the second NMOS tube is connected to the source terminal of the third NMOS tube, the drain terminal of the third NMOS tube is connected to the first inductor and the output terminal of the power amplifier circuit, and the other end of the first inductor is connected to the power supply VDD terminal; the gate terminal of the second NMOS tube and the gate terminal of the third NMOS tube are respectively connected to the first output terminal and the second output terminal of the bias unit.

[0017] Preferably, the bias unit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, as well as an operational amplifier, a first capacitor, a second capacitor, a first resistor and a current source; wherein,

[0018] The operational amplifier and the first PMOS tube form a negative feedback structure to control the first voltage at the first output terminal of the bias unit to be equal to the reference voltage;

[0019] The first PMOS tube and the second PMOS tube constitute a second-stage amplifier, which is used to isolate the output end of the operational amplifier and the first output end of the bias unit;

[0020] The fourth PMOS tube and the fifth PMOS tube form a voltage-dividing structure for reducing voltage fluctuation at the second output end of the bias unit.

[0021] Preferably, in the negative feedback structure formed by the operational amplifier and the first PMOS tube, the non-inverting input terminal of the operational amplifier is connected to the reference voltage terminal, the output terminal of the operational amplifier is connected to the gate terminal of the first PMOS tube, the inverting input terminal of the operational amplifier is connected to the source terminal of the first PMOS tube and the first output terminal of the bias unit; and the drain terminal of the first PMOS tube is connected to the ground potential terminal.

[0022] Preferably, in the second-stage amplifier formed by the first PMOS tube and the second PMOS tube, the drain terminal of the first PMOS tube is connected to the ground potential terminal, the gate terminal of the first PMOS tube is connected to the output terminal of the operational amplifier, the source terminal of the first PMOS tube is connected to the inverting input terminal of the operational amplifier and the first output terminal of the bias unit on the one hand, and is connected to the drain terminal of the second PMOS tube on the other hand; the source terminal of the second PMOS tube is connected to the power supply VDD terminal; the gate terminal of the second PMOS tube is connected to the gate terminal of the third PMOS tube and the gate terminal of the fourth PMOS tube.

[0023] Preferably, in the voltage-dividing structure formed by the fourth PMOS tube and the fifth PMOS tube, the source end of the fourth PMOS tube is connected to the power supply VDD end, the gate end of the fourth PMOS tube is connected to the gate end of the third PMOS tube and the gate end of the second PMOS tube, the drain end of the fourth PMOS tube is connected to the source end of the fifth PMOS tube on the one hand, and is connected to the second output end of the bias unit through the first resistor on the other hand; the gate end and the drain end of the fifth PMOS tube are short-circuited and then connected to the first output end of the bias unit.

[0024] Preferably, the first capacitor is connected to the first output terminal of the bias unit, and is used to filter out voltage fluctuations at the first output terminal of the bias unit;

[0025] The second capacitor is connected to the second output end of the bias unit, and the second capacitor and the first resistor form a low-pass filter structure for filtering out voltage fluctuations at the second output end of the bias unit.

[0026] According to a second aspect of an embodiment of the present invention, an integrated circuit chip is provided, wherein the integrated circuit chip includes the above-mentioned power amplifier circuit with high gain.

[0027] Compared with the prior art, the power amplifier circuit with high gain provided by the present invention, through the technical solution of using the amplifier tube and the cascaded common source and common gate structure in the amplification unit, and the technical solution of combining the two-stage amplification structure of the negative feedback formed by the operational amplifier and the PMOS tube and the voltage divider structure and the resistor and capacitor filter structure formed by the bias unit, ensures the maximization of the output impedance of the power amplifier circuit, and effectively suppresses the second harmonic generated by the circuit while improving the gain of the power amplifier. Therefore, the power amplifier circuit with high gain provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, high amplifier gain, and excellent circuit harmonic performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A typical circuit diagram of a power amplifier in the prior art;

[0029] Figure 2 The schematic wiring diagram of a power amplifier circuit with high gain in an embodiment of the present invention;

[0030] Figure 3 It is a simulation test comparison chart of the transmission power and second harmonic of the technical solution of the present invention and the prior art solution. DETAILED DESCRIPTION

[0031] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] For ease of understanding and explanation, the present invention application first briefly introduces a typical power amplifier circuit in the prior art solution, and then describes in detail the specific technical solution of the embodiment of the present invention on this basis.

[0033] In the prior art, Figure 1 As shown, a typical power amplifier circuit includes an amplifier tube NM0, a common source and common gate structure NM1 and NM2, an inductor L0, a resistor R0, and a current source I0. In order to improve the gain of the power amplifier, the amplifier tube NM0 is cascaded with the common source and common gate structure NM1 and NM2, the drain end of the NMOS tube NM2 is used as the output end, and it is connected to the power supply Vdd through the inductor L0; the gate end of the NMOS tube NM2 is connected to the power supply Vdd, and the gate end of the NMOS tube NM1 is connected to the output end of the current source I0 and the resistor R0, and a bias voltage V0 is provided to it through the resistor R0 and the current source I0.

[0034] In order to improve the gain of the power amplifier, the gate voltage of the NMOS tubes NM1 and NM2 should be kept unchanged as much as possible. However, when the power amplifier circuit is working, the output terminal Vout will generate a relatively large high-frequency oscillation signal, which will be fed through the parasitic capacitance Cgd_nm2 of the NMOS tube NM2 and the parasitic capacitance Cgd_nm1 of the NMOS tube NM1 to the gate terminals of the NMOS tubes NM1 and NM2, causing the gate voltage to fluctuate, reducing the transconductance gnm1 and gnm2 of the NMOS tubes NM1 and NM2. At the same time, the input signal Vin is fed through the parasitic capacitance Cgd_nm0 of the amplifier tube NM0 and the parasitic capacitance Cgd_nm1 of the NMOS tube NM1 to the gate terminal of the NMOS tube NM1, causing the gate voltage to fluctuate, reducing the transconductance gnm1 of the NMOS tube NM1, thereby reducing the gain of the amplifier.

[0035] On the other hand, the output terminal Vout generates a high-frequency oscillation signal with a large amplitude, which also generates a large current fluctuation. Therefore, the power supply Vdd also generates a voltage fluctuation, so that the NMOS tube NM2 whose gate terminal is connected to the power supply Vdd is approximately a mixer tube, and the frequency of its mixing output is 2Fout and 0 (Fout is the signal frequency of the output terminal), resulting in the deterioration of the second harmonic performance of the output frequency. In order to solve the above problems existing in the prior art, the present invention provides a power amplifier circuit with high gain, which can reduce the second harmonic of the output terminal while improving the amplifier gain and improve the harmonic suppression capability.

[0036] like Figure 2 As shown, a power amplifier circuit with high gain provided by an embodiment of the present invention includes an amplifying unit and a biasing unit; wherein the first output terminal and the second output terminal of the biasing unit are respectively connected to the first biasing terminal and the second biasing terminal of the amplifying unit; the RF signal input terminal is connected to the input terminal of the amplifying unit, and the output terminal of the amplifying unit is connected to the output terminal of the power amplifier circuit.

[0037] The amplifying unit is composed of a cascade of an amplifying tube and a common source and common gate structure, and is used to amplify the power of an input radio frequency signal.

[0038] The bias unit is composed of an amplifier circuit, a voltage divider circuit and a filter circuit, and is used to provide two stable bias voltages for the common source and common gate structure of the amplifier unit.

[0039] The bias unit is combined with the amplification unit to improve the output impedance of the power amplifier circuit, thereby effectively suppressing the secondary harmonics generated by the circuit while improving the gain of the power amplifier.

[0040] In one embodiment of the present invention, Figure 2As shown, the amplification unit includes a first NMOS transistor NM0, a second NMOS transistor NM1, a third NMOS transistor NM2 and a first inductor L0. Among them, the RF signal input terminal VIN is connected to the gate terminal of the first NMOS transistor NM0, the source terminal of the first NMOS transistor NM0 is connected to the ground potential terminal, the drain terminal of the first NMOS transistor NM0 is connected to the source terminal of the second NMOS transistor NM1, the drain terminal of the second NMOS transistor NM1 is connected to the source terminal of the third NMOS transistor NM2, the drain terminal of the third NMOS transistor NM2 is connected to the first inductor L0 and the output terminal Vout of the power amplifier circuit, and the other end of the first inductor L0 is connected to the power supply VDD terminal. The gate terminal of the second NMOS transistor NM1 and the gate terminal of the third NMOS transistor NM2 are respectively connected to the first output terminal and the second output terminal of the bias unit.

[0041] In the amplifier unit, the first NMOS tube NM0 is an amplifier tube; the second NMOS tube NM1 and the third NMOS tube NM2 form a common source and common gate structure to increase the output impedance, thereby increasing the gain of the power amplifier; the first inductor L0 is used as a load inductor to provide impedance for high-frequency oscillation. After the amplifier unit adopts the cascade structure of the amplifier tube and the common source and common gate structure, the output impedance Rout satisfies the following formula:

[0042] Rout=gnm2*gnm1*rnm1*rnm2*rnm0||R L0 (1)

[0043] The gain Av of the power amplifier satisfies the following formula:

[0044] Av=gnm0*Rout (2)

[0045] Among them, gnm0 and rnm0 are the equivalent transconductance and equivalent impedance of the first NMOS tube NM0 respectively; gnm1 and rnm1 are the equivalent transconductance and equivalent impedance of the second NMOS tube NM1 respectively; gnm2 and rnm2 are the equivalent transconductance and equivalent impedance of the third NMOS tube NM2 respectively; R L0 is the equivalent impedance of the first inductor L0.

[0046] Since the first inductor L0 presents a large equivalent impedance R at the resonant frequency L0 Therefore, it can be seen from formula (1) that the size of the output impedance Rout is determined by the equivalent impedance gnm2*gnm1*rnm1*rnm2*rnm0 of the NMOS tube. The larger the value of the equivalent impedance is, the larger the output impedance Rout is, that is, the larger the amplitude of the high-frequency signal at the output end is, that is, the larger the gain Av of the power amplifier is.

[0047] In order to maximize the gain of the power amplifier, the gate voltage of the second NMOS tube NM1 and the third NMOS tube NM2 should be kept stable as much as possible, so that the equivalent transconductances gnm1 and gnm2 are kept maximized. However, due to the presence of the parasitic capacitance Cgd_nm2 of the third NMOS tube NM2, the parasitic capacitance Cgd_nm1 of the second NMOS tube NM1, and the parasitic capacitance Cgd_nm0 of the first NMOS tube NM0, the high-frequency oscillation signal will be fed through to the gate terminals of the second NMOS tube NM1 and the third NMOS tube NM2, causing the gate voltage to fluctuate, thereby reducing the equivalent transconductances gnm1 and gnm2. Therefore, the embodiment of the present invention adopts a technical solution combining a common source and common gate structure with its bias unit to solve this problem.

[0048] In one embodiment of the present invention, Figure 2 As shown, the bias unit includes a first PMOS transistor PM0, a second PMOS transistor PM1, a third PMOS transistor PM2, a fourth PMOS transistor PM3 and a fifth PMOS transistor PM4, as well as an operational amplifier A1, a first capacitor C0, a second capacitor C1, a first resistor R0 and a current source I0. Among them, the output end of the current source I0 is connected to the ground potential end, and the input end of the current source I0 is connected to the drain end of the third PMOS transistor PM2; the drain end of the third PMOS transistor PM2 is short-circuited with the gate end and then connected to the gate end of the second PMOS transistor PM1 and the gate end of the fourth PMOS transistor PM3; the source ends of the second PMOS transistor PM1, the third PMOS transistor PM2 and the fourth PMOS transistor PM3 are all connected to the power supply VDD end; the drain end (node ​​J1) of the second PMOS transistor PM1 is connected to the source end of the first PMOS transistor PM0 and the inverting input end of the operational amplifier A1 on the one hand, and is connected to the first output end of the bias unit on the other hand; the synchronous end of the operational amplifier A1 is connected to the source end of the first PMOS transistor PM0 and the inverting input end of the operational amplifier A1. The phase input terminal is connected to the reference voltage VREF terminal, the output terminal of the operational amplifier A1 is connected to the gate terminal of the first PMOS transistor PM0, and the drain terminal of the first PMOS transistor PM0 is connected to the ground potential terminal; the drain terminal (node ​​J2) of the fourth PMOS transistor PM3 is connected to the source terminal of the fifth PMOS transistor PM4 on the one hand, and is connected to the second output terminal of the bias unit through the first resistor R0 on the other hand; the gate terminal and the drain terminal of the fifth PMOS transistor PM4 are short-circuited and then connected to the first output terminal of the bias unit; the two ends of the first capacitor C0 are respectively connected to the first output terminal and the ground potential terminal of the bias unit; the two ends of the second capacitor C1 are respectively connected to the second output terminal and the ground potential terminal of the bias unit.

[0049] In the bias unit, the third PMOS tube PM2, the second PMOS tube PM1 and the fourth PMOS tube PM3 form a current mirror structure, mirroring the current of the branch where the third PMOS tube PM2 is located to the branch where the second PMOS tube PM1 is located and the branch where the fourth PMOS tube PM3 is located, providing working current for the branch.

[0050] The operational amplifier A1 and the first PMOS transistor PM0 form a negative feedback structure, and the first voltage V0 at the first output end of the bias unit (i.e., node J1) is controlled to be on the reference voltage VREF, i.e., V0=VREF. Therefore, a stable bias voltage is provided to the second NMOS transistor NM1 of the amplification unit through the first output end of the bias unit, so that the transconductance gnm1 of the second NMOS transistor NM1 will not be reduced. At the same time, the voltage V1 at the node J2 in the branch of the fourth PMOS transistor PM3 and the fifth PMOS transistor PM4 satisfies V1=V0+Vgs_pm4, where Vgs_pm4 is the gate-source voltage of the fifth PMOS transistor PM4. The node J2 is connected to the second output end of the bias unit through the first resistor R0, so the second voltage V2 at the second output end of the bias unit satisfies V2=V1=V0+Vgs_pm4. Therefore, a stable bias voltage is provided to the third NMOS transistor NM2 of the amplifying unit through the second output terminal of the bias unit, so that the transconductance gnm2 of the third NMOS transistor NM2 will not be reduced, thereby ensuring that the amplifier circuit has a higher gain. At the same time, the source voltage Vs_nm2 of the third NMOS transistor NM2 is V2-Vgs_nm2, where Vgs_nm2 is the gate-source voltage of the third NMOS transistor NM2; assuming that Vgs_pm4 is Vgs_nm2, then Vs_nm2 is V2-Vgs_nm2=V0, ensuring that the second NMOS transistor NM1 works in a better working state.

[0051] On the other hand, the first capacitor C0 provided at the first output end of the bias unit is used to filter out the voltage fluctuation at the first output end. In the circuit structure of the bias unit, the operational amplifier A1 can be a single-stage amplifier, and the first PMOS tube PM0 and the second PMOS tube PM1 connected to its output end are used as the second-stage amplifier, which can effectively isolate the output end of the operational amplifier A1 and the gate end of the second NMOS tube NM1 (i.e., the first output end), and the second NMOS tube NM1 can be used as a MOS tube in the feedback circuit. Then, the source end of the first PMOS tube PM0, i.e., the node J1, can be provided with a filter capacitor (i.e., the first capacitor C0) with a larger capacitance value, and the node J1 is used as the output main pole without affecting the stability. Thus, the voltage fluctuation fed through the parasitic capacitance Cgd_nm2 of the third NMOS tube NM2, the parasitic capacitance Cgd_nm1 of the second NMOS tube NM1, and the parasitic capacitance Cgd_nm0 of the first NMOS tube NM0 to the gate end of the second NMOS tube NM1 can be well suppressed.

[0052] The second output end of the bias unit provides a gate bias voltage for the third NMOS transistor NM2 of the amplifying unit. Since the bias voltage is not directly generated by the power supply VDD, but is generated by the first voltage V0 at the node J1 through the fifth PMOS transistor PM4 to generate the second voltage V2, when the voltage fluctuation generated on the power supply VDD reaches the node J2 through the fourth PMOS transistor PM3, since the fourth PMOS transistor PM3 and the fifth PMOS transistor PM4 form a voltage dividing structure, the fourth PMOS transistor PM3 will divide the interference signal of the power supply VDD, thereby reducing the amplitude of the fluctuation voltage reaching the gate end (i.e., the second output end) of the third NMOS transistor NM2 of the amplifying unit. At the same time, a low-pass filter structure composed of a second capacitor C1 and a first resistor R0 is provided at the second output end of the bias unit to filter out the voltage fluctuation from the power supply VDD, so as to ensure that the second voltage V2 at the second output end of the bias unit is a "clean" bias voltage, which is provided to the gate end of the third NMOS transistor NM2 of the amplifying unit.

[0053] In summary, the bias unit adopts the technical solution of using the operational amplifier A1 and the first PMOS tube PM0 to form a negative feedback structure, and the first PMOS tube PM0 and the second PMOS tube PM1 to form a second-stage amplifier structure, and combines the filtering effect of the first capacitor C0 to achieve the stability of the first voltage output from the first output terminal; on this basis, by adopting the voltage-dividing structure formed by the fourth PMOS tube PM3 and the fifth PMOS tube PM4, and combining the low-pass filter circuit formed by the second capacitor C1 and the first resistor R0, the stability of the second voltage output from the second output terminal is achieved. The bias unit provides two stable bias voltages for the amplification unit, ensuring that the equivalent transconductances gnm1 and gnm2 of the second NMOS tube NM1 and the third NMOS tube NM2 in the common source and common gate structure of the amplification unit are maximized, thereby achieving the improvement of the gain of the power amplifier while improving the suppression capability of the second harmonic.

[0054] In order to verify the technical performance of the power amplifier circuit with high gain provided by the embodiment of the present invention, the inventors conducted simulation tests on the transmission power and the second harmonic of the technical solution and the prior art solution respectively. The test results are as follows: Figure 3 shown.

[0055] exist Figure 3In the figure, the upper part is the test result of the prior art solution, and the lower part is the test result of the technical solution of the present invention; the horizontal axis is the signal frequency, and the vertical axis is the transmission power, that is, the output power of the power amplifier. It can be seen from the figure that when the transmission power of the power amplifier circuit using the prior art solution is 14.34dBm, the second harmonic power at the output end is -55.91dB; when the transmission power of the power amplifier circuit using the technical solution of the present invention is 14.77dBm, the second harmonic power at the output end is -59.04dB. By comparison, it can be seen that the technical solution of the present invention reduces the power of the second harmonic at the output end while improving the transmission power, and has obvious beneficial effects of improving gain and suppressing second harmonics.

[0056] The structure and working principle of the power amplifier circuit with high gain provided by the embodiment of the present invention are described in detail above. Based on the above power amplifier circuit with high gain, the embodiment of the present invention further provides an integrated circuit chip, which includes the above power amplifier circuit with high gain, and is used as an important component of the radio frequency front-end module in a wireless communication system to provide power amplification of radio frequency signals for the transmission path. The specific structure of the power amplifier circuit with high gain in the integrated circuit chip will not be described in detail here.

[0057] In summary, compared with the prior art, the power amplifier circuit with high gain provided by the present invention, through the technical solution of using the amplifier tube and the cascaded common source and common gate structure in the amplification unit, and the technical solution of combining the two-stage amplification structure of the negative feedback formed by the operational amplifier and the PMOS tube and the voltage divider structure and the resistor and capacitor filter structure formed by the bias unit, ensures the maximization of the output impedance of the power amplifier circuit, and effectively suppresses the second harmonic generated by the circuit while improving the gain of the power amplifier. Therefore, the power amplifier circuit with high gain provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, high amplifier gain, and excellent circuit harmonic performance.

[0058] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0059] The above is a detailed description of the power amplifier circuit and chip with high gain provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A power amplifier circuit with high gain, characterized in that It includes an amplification unit and a bias unit; wherein, The first output terminal and the second output terminal of the bias unit are respectively connected to the first bias terminal and the second bias terminal of the amplifying unit; the RF signal input terminal is connected to the input terminal of the amplifying unit, and the output terminal of the amplifying unit is connected to the output terminal of the power amplifier circuit; The amplifying unit includes an amplifying tube and a common source and common gate structure, and is used to amplify the power of the input radio frequency signal; the biasing unit is used to provide two stable bias voltages for the common source and common gate structure of the amplifying unit; The bias unit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, as well as an operational amplifier, a first capacitor, a second capacitor, a first resistor and a current source; wherein the operational amplifier and the first PMOS tube form a negative feedback structure to control the first voltage at the first output end of the bias unit to be equal to a reference voltage; the first PMOS tube and the second PMOS tube form a second-stage amplifier to isolate the output end of the operational amplifier from the first output end of the bias unit; the fourth PMOS tube and the fifth PMOS tube form a voltage divider structure to reduce the voltage fluctuation at the second output end of the bias unit.

2. The power amplifier circuit with high gain as claimed in claim 1, characterized in that The amplifying unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube and a first inductor; wherein, The first NMOS tube is an amplifier tube; The second NMOS tube and the third NMOS tube form a common source and common gate structure, so as to improve the output impedance; The first inductor is used to provide impedance for high-frequency oscillation.

3. The power amplifier circuit with high gain as claimed in claim 2, characterized in that: The RF signal input terminal is connected to the gate terminal of the first NMOS tube, the source terminal of the first NMOS tube is connected to the ground potential terminal, the drain terminal of the first NMOS tube is connected to the source terminal of the second NMOS tube, the drain terminal of the second NMOS tube is connected to the source terminal of the third NMOS tube, the drain terminal of the third NMOS tube is connected to the first inductor and the output terminal of the power amplifier circuit, and the other end of the first inductor is connected to the power supply VDD terminal; the gate terminal of the second NMOS tube and the gate terminal of the third NMOS tube are respectively connected to the first output terminal and the second output terminal of the bias unit.

4. The power amplifier circuit with high gain as claimed in claim 1, characterized in that: In the negative feedback structure formed by the operational amplifier and the first PMOS tube, the non-inverting input terminal of the operational amplifier is connected to the reference voltage terminal, the output terminal of the operational amplifier is connected to the gate terminal of the first PMOS tube, the inverting input terminal of the operational amplifier is connected to the source terminal of the first PMOS tube and the first output terminal of the bias unit; the drain terminal of the first PMOS tube is connected to the ground potential terminal.

5. The power amplifier circuit with high gain as claimed in claim 1, characterized in that: In the second-stage amplifier formed by the first PMOS tube and the second PMOS tube, the drain end of the first PMOS tube is connected to the ground potential end, the gate end of the first PMOS tube is connected to the output end of the operational amplifier, the source end of the first PMOS tube is connected to the inverting input end of the operational amplifier and the first output end of the bias unit on the one hand, and is connected to the drain end of the second PMOS tube on the other hand; the source end of the second PMOS tube is connected to the power supply VDD end; the gate end of the second PMOS tube is connected to the gate end of the third PMOS tube and the gate end of the fourth PMOS tube.

6. The power amplifier circuit with high gain as claimed in claim 1, characterized in that: In the voltage-dividing structure formed by the fourth PMOS tube and the fifth PMOS tube, the source end of the fourth PMOS tube is connected to the power supply VDD end, the gate end of the fourth PMOS tube is connected to the gate end of the third PMOS tube and the gate end of the second PMOS tube, the drain end of the fourth PMOS tube is connected to the source end of the fifth PMOS tube on the one hand, and is connected to the second output end of the bias unit through the first resistor on the other hand; the gate end and the drain end of the fifth PMOS tube are short-circuited and then connected to the first output end of the bias unit.

7. The power amplifier circuit with high gain as claimed in claim 1, characterized in that: The first capacitor is connected to the first output terminal of the bias unit and is used to filter out voltage fluctuations at the first output terminal of the bias unit.

8. The power amplifier circuit with high gain as claimed in claim 1, characterized in that: The second capacitor is connected to the second output end of the bias unit, and the second capacitor and the first resistor form a low-pass filter structure for filtering out voltage fluctuations at the second output end of the bias unit.

9. An integrated circuit chip, characterized in that A power amplifier circuit with high gain comprising any one of claims 1 to 8.

Images