Intermediate frequency digital receiving board based on VPX bus and working method
By using an intermediate frequency digital receiver board based on the VPX bus, the problem of adapting a universal receiver board to different frequency bands in digital array radar was solved, achieving broad coverage of signal processing and improved system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INST OF RADIO MEASUREMENT
- Filing Date
- 2023-12-19
- Publication Date
- 2026-06-26
AI Technical Summary
In existing digital array radars, the general-purpose digital receiver board is difficult to adapt to the signal reception and processing requirements of different frequency bands, resulting in limited frequency band coverage.
Design an intermediate frequency digital receiver board based on VPX bus, including FPGA circuit module, interface circuit module, clock distribution circuit module, IPMI unit circuit module and power supply circuit module. It provides signals and control signals through VPX bus, performs signal processing and data packaging in conjunction with FPGA chip, and realizes status monitoring and fault analysis.
It enables signal processing for different frequency bands, avoiding multiple board layout designs and program modifications, and improving the system's stability, anti-interference capabilities, and reliability.
Smart Images
Figure CN117768265B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a general-purpose intermediate frequency (IF) digital receiver board based on the VPX bus. More specifically, it relates to an IF digital receiver board based on the VPX bus and its operating method. Background Technology
[0002] Digital array radars now widely employ digital receiver components, and digital array radars across different frequency bands typically use the same double-mixing digital receiver component. In this double-mixing digital receiver component, the externally input radio frequency signal is mixed twice with the local oscillator (LO) and second LO signals to form an intermediate frequency (IF) signal, which is then sent to the digital receiver board for processing and converted into an optical fiber data stream for downstream equipment. By changing the frequencies of the LO and LO in different frequency bands, the same IF frequency signal reception function can be achieved. A universal digital receiver board, paired with different double-conversion modules, can cover signal reception and processing functions across any frequency band.
[0003] Therefore, there is a need to provide an intermediate frequency digital receiver board and operating method based on the VPX bus to suit a wider range of applications. Summary of the Invention
[0004] The purpose of this invention is to provide an intermediate frequency digital receiver board and its operating method based on the VPX bus, which is used to cover the multi-channel intermediate frequency signal processing function of digital array radar subarrays under different frequency bands.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] An intermediate frequency digital receiver board based on VPX bus includes an FPGA circuit module, an interface circuit module, a clock distribution circuit module, an IPMI unit circuit module, and a power supply circuit module. The interface circuit module includes an mLVDS interface chip, a front-end control interface circuit, a JTAG interface / test interface circuit, a level conversion circuit, and an optical module.
[0007] The VPX bus is used to provide the FPGA circuit module with mLVDS synchronization signal, clock signal, backplane reset signal and LVDS synchronization signal;
[0008] The local vibration power distribution board / secondary frequency conversion module is connected to the intermediate frequency digital receiving board through the interface circuit module, and is used to provide the intermediate frequency signal to the FPGA circuit module;
[0009] The FPGA circuit module includes an FPGA chip, which is used to complete signal processing and data packaging, and generate baseband data to be sent to the optical module.
[0010] The optical module is used to connect the baseband data to the VPX bus;
[0011] The IPMI unit circuit module is used to monitor the voltage, current and temperature of the intermediate frequency digital receiver board and output the monitoring results to the VPX bus.
[0012] Optionally, the receiving board further includes a CPLD circuit module and an ADC and front-end circuit module. The mLVDS synchronization signal, clock signal and backplane reset signal enter the FPGA chip after passing through the CPLD circuit module.
[0013] The ADC and front-end circuit module includes a transformer, a variable gain amplifier, a low-pass filter, and an ADC chip. The intermediate frequency signal enters the FPGA chip through the ADC and front-end circuit module.
[0014] Optionally, the front-end control interface circuit, JTAG interface / test interface circuit, and level conversion circuit are used to implement the front-end control interface, JTAG interface / test interface between the FPGA chip and the local oscillator power distribution board / secondary frequency conversion module.
[0015] Optionally, the FPGA chip's operating states are divided into initialization state, standby state, formal operating state, testing state, and maintenance state.
[0016] Optionally, the initialization state includes the system automatically entering the initialization state after the board is powered on, or entering the initialization state when the system clock fails in other states;
[0017] The standby state includes waiting for the arrival of system control information. If the control word verification is abnormal, the software remains in the standby state. If the control word verification passes, it enters the normal working state, maintenance state, or test state according to the control word content.
[0018] The formal working state is the normal state of the FPGA chip software, which is used to implement the normal functions required by the radar system.
[0019] The test status includes testing the working status of its own modules, external hardware environment and upper and lower level systems, which is used to assist the radar system in fault analysis.
[0020] The maintenance status includes the FPGA chip software maintaining and updating its own configuration data.
[0021] A method for operating an intermediate frequency digital receiver board based on the VPX bus, comprising the following steps:
[0022] The hardware environment information of the receiving board includes the intermediate frequency signal frequency, the sampling clock signal frequency, the working clock signal frequency, and the data stream transmission rate of the optical fiber module.
[0023] The intermediate frequency signal processing method in the receiving board includes an automatic gain control mode for the intermediate frequency signal.
[0024] The baseband signal processing method in the receiving board includes a digital domain digital quadrature downconversion processing frequency point mode, a multi-rate digital filter processing mode, and a digital domain amplitude and phase adjustment mode at the same time.
[0025] The fiber optic data stream transmission method within the board includes the number of optical fibers and the fiber optic data packetization mode.
[0026] Design the FPGA logic module parameters according to the timing information specified by the system to which the board belongs, and instantiate and call them in the integrated development environment;
[0027] In FPGA logic engineering, call the logic modules of each unit to complete the functional integration.
[0028] Optionally, the description of the hardware environment information on which the receiving board operates may further include:
[0029] The parameter settings of the internal phase-locked loop circuit of the FPGA chip are confirmed based on the intermediate frequency signal frequency, sampling clock signal frequency, and working clock signal frequency.
[0030] Configure the high-speed interface function parameters of the FPGA chip based on the data stream transmission rate of the fiber optic module.
[0031] Optionally, specifying the intermediate frequency signal processing method within the receiving board further includes performing intermediate frequency signal gain processing according to an automatic gain control mode. When in controlled control mode, link gain control is performed by issuing attenuation values according to the control word; when in automatic control mode, a gain control curve is selected according to the signal type, and link gain control is performed according to the gain control curve.
[0032] Optionally, specifying the baseband signal processing method within the receiving board further includes:
[0033] The DDC functional module inside the FPGA chip was built according to the multi-rate digital filter processing mode, and the number of filter stages and the order of a single-stage filter were determined according to the sampling rate, rectangular coefficient and out-of-band rejection requirements required by the system.
[0034] The amplitude and phase compensation module was built based on the digital domain amplitude and phase adjustment mode.
[0035] The intermediate frequency signal is down-converted according to the frequency point mode. When multiple frequency points are processed, multiple down-conversion function modules are instantiated. When a single frequency point is processed, one down-conversion function module is instantiated. The intermediate frequency signal is converted into baseband data through the down-conversion function module.
[0036] Optionally, the specified fiber optic data stream transmission method within the board further includes:
[0037] Based on the number of optical fibers, instantiate and configure the high-speed interface within the FPGA chip software.
[0038] Complete the construction of the fiber optic data packaging module based on the fiber optic data packaging mode.
[0039] The beneficial effects of this invention are as follows:
[0040] This invention standardizes the implementation process of a general intermediate frequency digital receiver board based on the VPX bus in a digital array radar system, avoiding the workload of multiple board design and program modification and re-call. At the same time, the status scheduling function implemented by the board has a complete status monitoring mechanism to prevent the system from freezing or crashing due to hardware malfunction. As a result, the system has high stability, anti-interference ability, reliability and environmental adaptability. Attached Figure Description
[0041] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0042] Figure 1 This diagram illustrates a functional block diagram of a universal intermediate frequency digital receiver board based on the VPX bus according to the present invention.
[0043] Figure 2 This illustrates the FPGA chip's operating state transition relationship in one embodiment of the present invention. Detailed Implementation
[0044] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.
[0045] This invention relates to a universal intermediate frequency digital receiver board based on the VPX bus, which is suitable for multi-channel intermediate frequency signal processing at the subarray level of digital array radar in different frequency bands, including functions such as filtering, amplification, automatic gain control, analog-to-digital conversion, digital quadrature downconversion (DDC) in the digital domain, amplitude and phase compensation, data packetization, and fiber optic transmission.
[0046] like Figure 1-2 As shown, one embodiment of the present invention provides an intermediate frequency digital receiver board based on VPX bus, including an FPGA circuit module, an interface circuit module, a clock distribution circuit module, an IPMI unit circuit module, and a power supply circuit module. The interface circuit module includes an mLVDS interface chip, a front-end control interface circuit, a JTAG interface / test interface circuit, a level conversion circuit, and an optical module.
[0047] The VPX bus is used to provide the FPGA circuit module with mLVDS synchronization signal, clock signal, backplane reset signal and LVDS synchronization signal;
[0048] The local vibration power distribution board / secondary frequency conversion module is connected to the intermediate frequency digital receiving board through the interface circuit module, and is used to provide the intermediate frequency signal to the FPGA circuit module;
[0049] The FPGA circuit module includes an FPGA chip, which is used to complete signal processing and data packaging, and generate baseband data to be sent to the optical module.
[0050] The optical module is used to connect the baseband data to the VPX bus;
[0051] The IPMI unit circuit module is used to monitor the voltage, current and temperature of the intermediate frequency digital receiver board and output the monitoring results to the VPX bus.
[0052] In an optional embodiment, the receiving board further includes a CPLD circuit module and an ADC and front-end circuit module, wherein the mLVDS synchronization signal, clock signal and backplane reset signal enter the FPGA chip after passing through the CPLD circuit module;
[0053] The ADC and front-end circuit module includes a transformer, a variable gain amplifier, a low-pass filter, and an ADC chip. The intermediate frequency signal enters the FPGA chip through the ADC and front-end circuit module.
[0054] In an optional embodiment, the front-end control interface circuit, the JTAG interface / test interface circuit, and the level conversion circuit are used to implement the front-end control interface and the JTAG interface / test interface between the FPGA chip and the local oscillator power distribution board / secondary frequency conversion module.
[0055] In an optional embodiment, the FPGA chip's operating states are divided into initialization state, standby state, formal operating state, testing state, and maintenance state.
[0056] In an optional embodiment, the initialization state includes the system automatically entering the initialization state after the board is powered on, or entering the initialization state when the system clock fails in other states.
[0057] The standby state includes waiting for the arrival of system control information. If the control word verification is abnormal, the software remains in the standby state. If the control word verification passes, it enters the normal working state, maintenance state, or test state according to the control word content.
[0058] The formal working state is the normal state of the FPGA chip software, which is used to implement the normal functions required by the radar system.
[0059] The test status includes testing the working status of its own modules, external hardware environment and upper and lower level systems, which is used to assist the radar system in fault analysis.
[0060] The maintenance status includes the FPGA chip software maintaining and updating its own configuration data.
[0061] In a specific embodiment, the mLVDS synchronization signal and clock signal from the VPX bus are sent to the CPLD circuit (1) through the mLVDS interface chip (3-1), and then sent to the FPGA chip (2-1) through the GPIO bus between the CPLD circuit (1) and the FPGA chip (2-1).
[0062] The backplane reset signal from the VPX bus is sent to the CPLD circuit (1), and then through the GPIO bus between the CPLD circuit (1) and the FPGA chip (2-1) to the FPGA chip (2-1) as a global reset signal for the board. The LVDS synchronization signal from the VPX bus is directly sent to the FPGA chip (2-1) as a synchronization reference inside the board. The intermediate frequency signal from the local oscillator power distribution board / secondary frequency conversion module that is plugged into the digital board passes through the transformer (5-1), variable gain amplifier (5-2), low-pass filter (5-3), and ADC chip (5-4) before passing through the SERDES data domain bus to the FPGA chip (2-1) to complete the multi-channel intermediate frequency signal processing and data packaging function. The packaged baseband data is connected to the VPX via the optical module (3-5). P6 connector; The front-end control interface, JTAG interface / test interface between the FPGA chip (2-1) and the local oscillator power distribution board / secondary frequency conversion module are implemented through the front-end control interface J63A-15 circuit (3-3), the JTAG interface / test interface J63A-9 circuit (3-2), and the level conversion circuit (3-4).
[0063] The IPMI smartFusion unit circuit (6) on the digital receiver board provides voltage, current and temperature monitoring for the entire board, and the monitoring results are connected to the VPX bus via the IIC bus.
[0064] The FPGA chip software on the general-purpose digital receiver board collects various software and hardware monitoring information, integrates and packages it, and then sends it to the next-level system via a high-speed serial interface. The FPGA chip's operating state is divided into five states: initialization, standby, operational, testing, and maintenance. The transition relationships between these states are as follows: Figure 2 As shown.
[0065] Specifically, the initialization state includes:
[0066] a) After the board is powered on, the system automatically enters the initialization state;
[0067] b) After the externally input system clock stabilizes, the high-speed serial data link training and establishment are completed;
[0068] c) Read the board ID information and various pre-stored data files;
[0069] d) Configure the clock chip and ADC chip after the synchronization pulse stabilizes;
[0070] e) Determine the configuration results and synchronization status of each chip. If the initialization is successful, the initialization configuration is marked as complete, and the FPGA software exits the initialization state and unconditionally enters the standby state. If the initialization fails, the initialization operation is re-executed.
[0071] In standby mode, the software awaits system control information. If the control word verification fails, the software remains in standby mode. Once the control word verification passes, the software enters normal operation, maintenance, or testing mode according to the control word content.
[0072] In standby mode, the FPGA chip software performs the following operations:
[0073] a) Set the receiver branch gain to the minimum value;
[0074] b) Perform normal external data communication and send component status information back to external communication devices.
[0075] The formal operating state is the normal software state, in which the FPGA chip software implements the standard functions required by the radar system, including:
[0076] a) Generate waveforms and acquire echo data based on the control commands and timing information in the control word;
[0077] b) The packaged echo data and monitoring information are sent to an external module via a high-speed serial interface;
[0078] c) Under normal operating conditions, if a sudden external input system clock failure occurs, the software will immediately jump back to the initialization state;
[0079] d) Under normal working conditions, if a control word verification fails, the system will jump back to the standby state.
[0080] The test state is a working mode in which the FPGA chip software tests the operating status of its own modules, external hardware environment, and upstream and downstream systems. It is mainly used to assist radar systems in fault analysis, including:
[0081] a) The test state has all the functions of the formal working state;
[0082] b) The test status has the function of testing the bit error rate of high-speed serial links;
[0083] c) The test state has the function of simulating receiving branch data;
[0084] d) The test status has the function of simulating packaged data;
[0085] e) Exiting the test state is executed by the exit command parsed from the control word, returning to the standby state;
[0086] f) If a sudden external input system clock failure occurs during testing, the software immediately jumps to the initialization state.
[0087] Maintenance mode is the operating mode in which the FPGA chip software maintains and updates its own configuration data, including:
[0088] a) Disable echo data acquisition in maintenance mode;
[0089] b) The function of communication via high-speed serial interface is retained in maintenance mode;
[0090] c) Maintenance status is used to update the fixed data;
[0091] d) Exiting the maintenance state is executed by the exit command parsed from the control word, returning to the standby state;
[0092] e) If a sudden externally input system clock failure occurs during maintenance, the software immediately jumps to the initialization state.
[0093] Another embodiment of the present invention provides a method for operating an intermediate frequency digital receiver board based on a VPX bus, the steps of which include:
[0094] The hardware environment information of the receiving board is clearly defined, including the intermediate frequency signal frequency, sampling clock signal frequency, working clock signal frequency, and fiber optic module data stream transmission rate;
[0095] The intermediate frequency (IF) signal processing method within the receiving board is specified, and the IF signal processing method includes an automatic gain control mode for the IF signal;
[0096] The baseband signal processing method within the receiving board is specified, and the baseband signal processing method includes a digital domain digital quadrature downconversion processing frequency point mode, a multi-rate digital filter processing mode, and a digital domain amplitude and phase adjustment mode at the same time.
[0097] The fiber optic data stream transmission method within the board is clearly defined, including the number of fibers and the fiber optic data packetization mode.
[0098] Design the FPGA logic module parameters according to the timing information specified by the system to which the board belongs, and instantiate and call them in the integrated development environment;
[0099] In FPGA logic engineering, call the logic modules of each unit to complete the functional integration.
[0100] Specifically, the hardware environment information of the board is specified, including the intermediate frequency signal frequency F_sig sent through the local oscillator power distribution board / secondary frequency converter module, the sampling clock signal frequency F_adcclk input through the VPX P5 connector, the working clock signal frequency F_sysclk input through the VPXP0 connector, and the data stream transmission rate F_fiber of the fiber optic module.
[0101] Define the intermediate frequency signal processing method within the board, including the automatic gain control mode (AGC_MODE) for the intermediate frequency signal;
[0102] Clearly define the baseband signal processing methods within the board, including the digital domain digital quadrature downconversion (DDC) frequency point mode DDC_FREQ_MODE, multi-rate digital filter processing mode MULTI_FILTER_MODE, and digital domain amplitude and phase adjustment mode AMP_PHASE_MODE at the same time.
[0103] Clearly define the fiber optic data stream transmission method within the board, including the number of fibers FIBER_NUM and the fiber optic data packetization mode DATA_PKG_MODE;
[0104] Design the FPGA logic module parameters according to the timing information specified by the system to which the board belongs, instantiate and call them in the integrated development environment, and call each unit logic module in the FPGA logic project to complete the functional integration.
[0105] In an optional embodiment, specifying the hardware environment information on which the receiving board operates further includes:
[0106] The parameter settings of the internal phase-locked loop circuit of the FPGA chip are confirmed based on the intermediate frequency signal frequency, sampling clock signal frequency, and working clock signal frequency.
[0107] Configure the high-speed interface function parameters of the FPGA chip based on the data stream transmission rate of the fiber optic module.
[0108] Specifically, the parameters of the internal phase-locked loop circuit of the FPGA chip are determined based on the intermediate frequency signal frequency F_sig, the sampling clock signal frequency F_adcclk, and the working clock signal frequency F_sysclk; the parameters of the high-speed interface function of the FPGA chip are configured based on the data stream transmission rate F_fiber of the fiber optic module.
[0109] In an optional embodiment, specifying the intermediate frequency signal processing method within the receiving board further includes performing intermediate frequency signal gain processing according to an automatic gain control mode. When in controlled control mode, link gain control is performed by issuing attenuation values according to the control word; when in automatic control mode, a gain control curve is selected according to the signal type, and link gain control is performed according to the gain control curve.
[0110] In an optional embodiment, specifying the baseband signal processing method within the receiving board further includes:
[0111] The DDC functional module inside the FPGA chip was built according to the multi-rate digital filter processing mode, and the number of filter stages and the order of a single-stage filter were determined according to the sampling rate, rectangular coefficient and out-of-band rejection requirements required by the system.
[0112] The amplitude and phase compensation module was built based on the digital domain amplitude and phase adjustment mode.
[0113] The intermediate frequency signal is down-converted according to the frequency point mode. When multiple frequency points are processed, multiple down-conversion function modules are instantiated. When a single frequency point is processed, one down-conversion function module is instantiated. The intermediate frequency signal is converted into baseband data through the down-conversion function module.
[0114] Specifically, (3) the baseband signal processing mode in the board is clearly defined, including the digital domain digital quadrature downconversion (DDC) frequency point mode DDC_FREQ_MODE, multi-rate digital filter processing mode MULTI_FILTER_MODE, and digital domain amplitude and phase adjustment mode AMP_PHASE_MODE at the same time.
[0115] Based on the MULTI_FILTER_MODE multi-rate digital filter processing mode: complete the construction of the DDC function module inside the FPGA chip, and determine the number of filter stages and the order of a single-stage filter according to the system's requirements for sampling rate, rectangular coefficient, out-of-band rejection, etc.
[0116] Based on the digital domain amplitude and phase adjustment mode AMP_PHASE_MODE: complete the construction of the amplitude and phase compensation module.
[0117] The intermediate frequency (IF) signal is processed by DDC according to the frequency point mode DDC_FREQ_MODE. When DDC_FREQ_MODE is multi-frequency point processing, multiple DDC function modules are instantiated. Otherwise, single-frequency point processing is the default, and only one DDC function module is instantiated. The IF signal is processed by the DDC function module to form baseband data.
[0118] In an optional embodiment, the specified method for transmitting fiber optic data streams within the board further includes:
[0119] Based on the number of optical fibers, instantiate and configure the high-speed interface within the FPGA chip software.
[0120] Complete the construction of the fiber optic data packaging module based on the fiber optic data packaging mode.
[0121] Specifically, the high-speed interface instantiation and configuration within the FPGA chip software are completed based on the fiber optic quantity FIBER_NUM; the fiber optic data packaging module functionality is built based on the fiber optic data packaging mode DATA_PKG_MODE. The design employs a general-purpose radar data packaging and fiber optic transmission module, enabling data packaging functionality for different channels and fiber optic transmission rates through simple parameter configuration.
[0122] This invention standardizes the implementation process of a general intermediate frequency digital receiver board based on the VPX bus in a digital array radar system, avoiding the workload of multiple board design and program modification and re-call. At the same time, the status scheduling function implemented by the board has a complete status monitoring mechanism to prevent the system from freezing or crashing due to hardware malfunction. As a result, the system has high stability, anti-interference ability, reliability and environmental adaptability.
[0123] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.
Claims
1. A method for operating an intermediate frequency digital receiver board based on a VPX bus, characterized in that, The methods include: The hardware environment information of the receiving board includes the intermediate frequency signal frequency, the sampling clock signal frequency, the working clock signal frequency, and the data stream transmission rate of the optical fiber module. The intermediate frequency signal processing method in the receiving board includes an automatic gain control mode for the intermediate frequency signal. The baseband signal processing method in the receiving board includes a digital domain digital quadrature downconversion processing frequency point mode, a multi-rate digital filter processing mode, and a digital domain amplitude and phase adjustment mode at the same time. The fiber optic data stream transmission method within the board includes the number of optical fibers and the fiber optic data packetization mode. Design the FPGA logic module parameters according to the timing information specified by the system to which the board belongs, and instantiate and call them in the integrated development environment; In FPGA logic engineering, call the logic modules of each unit to complete functional integration; The intermediate frequency digital receiver board based on the VPX bus includes an FPGA circuit module, an interface circuit module, a clock distribution circuit module, an IPMI unit circuit module, and a power supply circuit module. The interface circuit module includes an mLVDS interface chip, a front-end control interface circuit, a JTAG interface / test interface circuit, a level conversion circuit, and an optical module. The VPX bus is used to provide the FPGA circuit module with mLVDS synchronization signal, clock signal, backplane reset signal and LVDS synchronization signal; The local oscillator power distribution board / secondary frequency conversion module is connected to the intermediate frequency digital receiver board through the interface circuit module, and is used to provide the intermediate frequency signal to the FPGA circuit module; The FPGA circuit module includes an FPGA chip, which is used to complete signal processing and data packaging, and generate baseband data to be sent to the optical module. The optical module is used to connect the baseband data to the VPX bus; The IPMI unit circuit module is used to monitor the voltage, current and temperature of the intermediate frequency digital receiver board and output the monitoring results to the VPX bus.
2. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 1, characterized in that, The receiving board also includes a CPLD circuit module and an ADC and front-end circuit module. The mLVDS synchronization signal, clock signal and backplane reset signal enter the FPGA chip after passing through the CPLD circuit module. The ADC and front-end circuit module includes a transformer, a variable gain amplifier, a low-pass filter, and an ADC chip. The intermediate frequency signal enters the FPGA chip through the ADC and front-end circuit module.
3. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 1, characterized in that, The front-end control interface circuit, JTAG interface / test interface circuit, and level conversion circuit are used to implement the front-end control interface and JTAG interface / test interface between the FPGA chip and the local oscillator power distribution board / secondary frequency conversion module.
4. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 1, characterized in that, The FPGA chip's operating states are divided into initialization state, standby state, formal operating state, testing state, and maintenance state.
5. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 4, characterized in that, The initialization state includes the system automatically entering the initialization state after the board is powered on, or entering the initialization state when the system clock fails in other states. The standby state includes waiting for the arrival of system control information. If the control word verification is abnormal, the software remains in the standby state. If the control word verification passes, it enters the normal working state, maintenance state, or test state according to the control word content. The formal working state is the normal state of the FPGA chip software, which is used to implement the normal functions required by the radar system. The test status includes testing the working status of its own modules, external hardware environment and upper and lower level systems, which is used to assist the radar system in fault analysis. The maintenance status includes the FPGA chip software maintaining and updating its own configuration data.
6. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 1, characterized in that, The hardware environment information of the receiving board further includes: The parameter settings of the internal phase-locked loop circuit of the FPGA chip are confirmed based on the intermediate frequency signal frequency, sampling clock signal frequency, and working clock signal frequency. Configure the high-speed interface function parameters of the FPGA chip based on the data stream transmission rate of the fiber optic module.
7. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 1, characterized in that, The intermediate frequency signal processing method within the receiving board further includes performing intermediate frequency signal gain processing according to the automatic gain control mode. When it is in controlled control mode, the link gain control is performed according to the attenuation value issued by the control word; when it is in automatic control mode, the gain control curve is selected according to the signal type, and the link gain control is performed according to the gain control curve.
8. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 1, characterized in that, The baseband signal processing method within the receiving board further includes: The DDC functional module inside the FPGA chip was built according to the multi-rate digital filter processing mode, and the number of filter stages and the order of a single-stage filter were determined according to the sampling rate, rectangular coefficient and out-of-band rejection requirements required by the system. The amplitude and phase compensation module was built based on the digital domain amplitude and phase adjustment mode. The intermediate frequency signal is down-converted according to the frequency point mode. When multiple frequency points are processed, multiple down-conversion function modules are instantiated. When a single frequency point is processed, one down-conversion function module is instantiated. The intermediate frequency signal is converted into baseband data through the down-conversion function module.
9. The operating method of the intermediate frequency digital receiver board based on the VPX bus according to claim 1, characterized in that, The fiber optic data stream transmission method within the board further includes: Based on the number of optical fibers, instantiate and configure the high-speed interface within the FPGA chip software. Complete the construction of the fiber optic data packaging module based on the fiber optic data packaging mode.