Quantum circuit processing method, device and electronic equipment

Abstract

The present disclosure provides a quantum circuit processing method, device and electronic device, which relates to the field of quantum computing technology, and specifically to the field of quantum circuit technology. The specific implementation scheme is: obtain the first instruction list of the first quantum circuit, obtain the target dictionary, the target dictionary indicates the relationship between the identifier of the exchangeable group, the identifier of the quantum operation and the control type of the quantum bit; obtain the first identifier of the quantum operation corresponding to the operation instruction in the first instruction list and the first control type of each quantum bit; based on the target dictionary, the first identifier and the first control type, determine the exchangeable characteristics of the operation instruction on each quantum bit that acts on it, and when the exchangeable characteristics indicate that the operation instruction is exchangeable on the quantum bit, the exchangeable characteristics include the second identifier of the exchangeable group to which the operation instruction belongs on the quantum bit; based on the exchangeable characteristics and the first instruction list, perform equivalent compilation on the first quantum circuit to obtain the second instruction list of the second quantum circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit processing method, device and electronic device. Background Art

[0002] Quantum computing uses the unique operating rules of the quantum world to provide a new and very promising way of information processing. In many specific problems, quantum algorithms can bring advantages over classical algorithms. For example, using Shor's algorithm, large integers can be efficiently decomposed, and using Grover's algorithm, data searches can be performed faster. With the development of quantum theory, new quantum algorithms are constantly being proposed. How to efficiently simulate these algorithms or run them on real quantum hardware has always been an important issue.

[0003] At present, the classical simulation or real machine operation of quantum algorithms is mainly limited by the number of quantum bits. In classical simulation, the length of the column vector describing the quantum state grows exponentially with the number of corresponding bits (for example, the length of the column vector of an n-bit quantum state is 2 n ), it is difficult for classical computers to simulate large-scale quantum algorithms. Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support the simulation of algorithms with dozens of quantum bits at most. Therefore, it is necessary to compile quantum circuits into dynamic quantum circuits to reduce the number of quantum bits used.

[0004] Currently, a directed acyclic graph of a quantum circuit is constructed based on the execution order of quantum operations in the quantum circuit, so as to realize equivalent compilation of the quantum circuit based on the constructed directed acyclic graph. Summary of the invention

[0005] The present disclosure provides a quantum circuit processing method, device and electronic device.

[0006] According to a first aspect of the present disclosure, a quantum circuit processing method is provided, comprising:

[0007] Obtaining a first instruction list for a first quantum circuit, and obtaining a target dictionary, wherein the target dictionary indicates a relationship between an identifier of an exchangeable group, an identifier of a quantum operation, and a control type of a quantum bit, wherein two quantum operations belonging to the same exchangeable group are exchangeable if a preset condition is satisfied, wherein the preset condition includes: the two quantum operations act on the same quantum bit, and the control types of the two quantum operations on the quantum bit are control types indicated by the target dictionary;

[0008] Obtain a first identifier of a quantum operation corresponding to an operation instruction in the first instruction list and a first control type of each quantum bit acted upon by the quantum operation;

[0009] Determine, based on the target dictionary, the first identifier, and the first control type, an exchangeable feature of the operation instruction on each quantum bit on which the operation instruction acts, wherein the exchangeable feature indicates the exchangeability of the operation instruction on the quantum bit, and when the exchangeable feature indicates that the operation instruction is exchangeable on the quantum bit, the exchangeable feature includes a second identifier of the exchangeable group to which the operation instruction belongs on the quantum bit;

[0010] Based on the exchangeable feature and the first instruction list, the first quantum circuit is equivalently compiled to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

[0011] According to a second aspect of the present disclosure, there is provided a quantum circuit processing device, comprising:

[0012] A first acquisition module is used to acquire a first instruction list of a first quantum circuit, and to acquire a target dictionary, wherein the target dictionary indicates a relationship between an identifier of an exchangeable group, an identifier of a quantum operation, and a control type of a quantum bit, and two quantum operations belonging to the same exchangeable group are exchangeable if a preset condition is met, wherein the preset condition includes: the two quantum operations act on the same quantum bit, and the control types of the two quantum operations on the quantum bit are control types indicated by the target dictionary;

[0013] A second acquisition module is used to obtain a first identifier of a quantum operation corresponding to an operation instruction in the first instruction list and a first control type of each quantum bit acted upon by the quantum operation;

[0014] a determination module, configured to determine, based on the target dictionary, the first identifier, and the first control type, an exchangeable feature of the operation instruction on each quantum bit on which the operation instruction acts, wherein the exchangeable feature indicates the exchangeability of the operation instruction on the quantum bit, and when the exchangeable feature indicates that the operation instruction is exchangeable on the quantum bit, the exchangeable feature includes a second identifier of an exchangeable group to which the operation instruction belongs on the quantum bit;

[0015] An equivalent compilation module is used to perform equivalent compilation on the first quantum circuit based on the exchangeable feature and the first instruction list to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

[0016] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0017] at least one processor; and

[0018] a memory communicatively connected to at least one processor; wherein,

[0019] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the first aspect.

[0020] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute any one of the methods in the first aspect.

[0021] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements any one of the methods in the first aspect when executed by a processor.

[0022] The technology disclosed in the present invention solves the problem of relatively poor equivalent compilation effect of quantum circuits in related technologies, can improve the effect of equivalent compilation of quantum circuits, and reduce the number of quantum bits required for the compiled dynamic quantum circuits.

[0023] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0025] Figure 1 is a flowchart of a quantum circuit processing method according to the first embodiment of the present disclosure;

[0026] Figure 2 This is a schematic diagram of the structure of an example static quantum circuit;

[0027] Figure 3 is a schematic diagram of the structure of a static quantum circuit of another example;

[0028] Figure 4 yes Figure 3 The schematic diagram of the structure of converting the static quantum circuit shown into a dynamic quantum circuit;

[0029] Figure 5(a) is Figure 3 A schematic diagram of the structure of the directed acyclic graph corresponding to the static quantum circuit shown;

[0030] FIG5( b ) is a schematic diagram of the structure of the directed acyclic graph after adding directed edges;

[0031] FIG6( a ) is a schematic diagram of a structure of an example of a static quantum circuit including a swappable structure;

[0032] FIG6( b ) is a schematic diagram of a static quantum circuit equivalent to FIG6( a );

[0033] Figure 7 It is a directed acyclic graph constructed for the dependency of the execution order of quantum operations shown in Figure 6(a);

[0034] Figure 8 It is a directed acyclic graph constructed based on the quantum circuit shown in Figure 6(a) and considering the commutativity between quantum operations;

[0035] Figure 9-11 It is a schematic diagram illustrating the interchange equivalence of quantum gates with interchangeable structures;

[0036] FIG12( a ) is a schematic diagram of another example of a static quantum circuit including a swappable structure;

[0037] FIG12( b ) is a schematic diagram of a static quantum circuit equivalent to FIG12( a );

[0038] FIG13( a ) is a schematic diagram of the structure of a directed acyclic graph constructed based on exchangeable features;

[0039] FIG13( b ) is a schematic diagram of the structure of the directed acyclic graph after adding the target directed edge;

[0040] Fig.14 is a schematic diagram of the structure of a dynamic quantum circuit equivalently compiled in an example of the first embodiment of the present invention;

[0041] Fig.15 It is a schematic diagram of the equivalence of a quantum circuit with a swappable structure before and after swapping the order of quantum gates and before and after compilation;

[0042] Figure 16-Figure 17 This is a schematic diagram comparing the compilability factors of random quantum circuits using different schemes;

[0043] Fig.18 is a schematic structural diagram of a quantum circuit processing device according to a second embodiment of the present disclosure;

[0044] Fig.19 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0046] First embodiment

[0047] like Figure 1 As shown, the present disclosure provides a quantum circuit processing method, comprising the following steps:

[0048] Step S101: obtaining a first instruction list for a first quantum circuit, and obtaining a target dictionary, wherein the target dictionary indicates a relationship between an identifier of an exchangeable group, an identifier of a quantum operation, and a control type of a quantum bit, wherein two quantum operations belonging to the same exchangeable group are exchangeable if a preset condition is met, wherein the preset condition includes: the two quantum operations act on the same quantum bit, and the control types of the two quantum operations on the quantum bit are control types indicated by the target dictionary.

[0049] Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support algorithms that simulate dozens of qubits at most. For example, a laptop can simulate about 20-30 qubits, and a large supercomputer and cluster can simulate up to 30-40 qubits. In real machine operation, the scalability problem of current quantum chips has not yet been solved, resulting in a very limited number of qubits that a quantum computer can provide. Therefore, quantum circuit optimization is a fundamental issue in the field of quantum computing.

[0050] Quantum circuit optimization is a process that uses certain technical means to simplify a given quantum circuit to reduce the requirements for classical simulation and real-machine operation, thereby accelerating the research of quantum algorithms and the implementation of quantum computing in practical scenarios.

[0051] The quantum circuit processing of this embodiment can be a quantum circuit optimization process, and its purpose is to optimize and compile the quantum circuit so that the compiled quantum circuit can greatly simplify the original quantum circuit in terms of the number of quantum bits. On the one hand, it can further improve the scale of classical simulation of quantum algorithms and enhance the verification ability of classical computers on quantum algorithms. On the other hand, it can also reduce the bit number requirements of quantum algorithms on real machines, making up for the shortcomings of the current quantum chip scalability problem.

[0052] More specifically, the purpose of this embodiment is to compile a given quantum circuit into a dynamic quantum circuit to reduce the number of quantum bits in the quantum circuit and lower the requirements for its classical simulation and real machine operation.

[0053] Among them, dynamic quantum circuits are able to integrate classical communication and computing into quantum circuits by introducing intermediate circuit measurements of quantum bits and the ability to reset quantum bits to their ground state during calculations. This feature will greatly increase the diversity of circuits running on quantum hardware and is also crucial for the development of error-corrected and fault-tolerant quantum computing. Therefore, dynamic quantum circuits are expected to become an important part of many quantum applications in the future. In a mathematical sense and without experimental constraints, static and dynamic quantum circuits have the same computing power, that is, any problem that can be expressed by a dynamic quantum circuit can also be expressed as a static problem, so dynamic quantum circuits provide the possibility of a trade-off between circuit depth and width.

[0054] In addition, since the qubits in a dynamic quantum circuit can be reset and continue to be used in subsequent calculations, compared with a static quantum circuit, when running the same quantum algorithm, a dynamic quantum circuit can effectively reduce the number of qubits required for a computing task, and in theory, computing power is not affected in any way. For example, the Berstein-Vazirani algorithm, which requires n qubits in a static quantum circuit, can be implemented with only 2 qubits in a dynamic quantum circuit.

[0055] The quantum circuit model is introduced in detail below.

[0056] The quantum circuit model is a commonly used quantum computing model. The evolution of the quantum state is completed by performing quantum gate operations on the initial quantum state, and the calculation results are extracted through quantum measurements. The quantum circuit diagram represents the entire process of quantum circuit model calculation.

[0057] Figure 2 This is a schematic diagram of the structure of an example static quantum circuit. Figure 2 As shown, a quantum bit system can be represented by a horizontal line, and the quantum bits are numbered from top to bottom, where the quantum bit numbers often start from zero.

[0058] The direction of time evolution in the quantum circuit diagram is from left to right. The leftmost end is the initial quantum state, where each quantum bit is usually initialized to the zero state, and then different quantum gate operations are applied to the initial state in sequence to complete the evolution of the quantum state. At the same time, quantum measurements can be performed on certain quantum bits to obtain measurement results.

[0059] If a quantum circuit does not have any quantum measurement or quantum state preparation operations in the middle of the circuit, then such a circuit is called a static quantum circuit. An example of a static quantum circuit diagram is as follows: Figure 2shown.

[0060] The operations in a quantum circuit diagram are usually represented by an ordered list of instructions in the order in which they are used. Each element in the list represents an instruction operation. Specifically,

[0061] Each quantum state preparation (or initialization) operation is represented by a four-element instruction [Reset, qubit, None, None]. For example, [Reset, 2, None, None] means initializing qubit 2 to the zero state.

[0062] Each single-qubit gate (such as H, X, Y, Z, S, T, Rx, Ry, Rz, etc.) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is the quantum bit acted on by the quantum gate, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [Rx, 2, π, None] means to apply an Rx rotation gate to the quantum bit on qubit 2, with a rotation angle of π.

[0063] Each two-qubit gate (such as a controlled NOT gate, CNOT gate, SWAP gate) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is a list of qubits that the two-qubit gate acts on. For a controlled quantum gate, qubit is a list of control bits and controlled bits, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [SWAP, [1, 2], None, None] means to act on SWAP gates between qubits 1 and 2; and [CNOT, [1, 3], None, None] means to act on qubits 1 and 3, where 1 is the control bit and 3 is the controlled bit.

[0064] Each multi-qubit gate (such as CCX gate) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is a list of qubits that the multi-qubit gate acts on, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [CCX, [1, 2, 3], None, None] means to act on the CCX gate between qubits 1, 2, and 3, where 1 and 2 are control bits and 3 is a controlled bit.

[0065] A measurement in a computational basis is represented by a four-element instruction [Measure, qubit, None, None]. For example, [Measure, 2, None, None] represents a computational basis measurement on qubit 2.

[0066] Figure 2 The instruction list of the static quantum circuit shown is: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[SWAP,[1,2],None,None],[Rx,0,α,None],[Ry,1,β,None],[Rz,2,γ,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0067] In some application scenarios, it is allowed to measure some quantum bits in the middle of a quantum circuit, and reset these quantum bits to zero state after the measurement results are obtained, so that they can be used for subsequent calculations. A quantum circuit that includes intermediate measurements and reset operations is called a dynamic quantum circuit. Figure 3 The static quantum circuit shown is transformed into a dynamic quantum circuit. Figure 4 As shown, it can be seen that the dynamic circuit reduces the number of quantum bits by one, but the operating effects of the two quantum circuits are equivalent.

[0068] Figure 3The instruction list of the static quantum circuit shown is: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[CNOT,[1,2],None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0069] Figure 4 The circuit instruction list of the dynamic quantum circuit obtained after the equivalent compilation shown is: dynamic_circuit = [[Reset,0,None,None],[Reset,1,None,None],[H,0,None,None],[H,1,None,None],[CNOT,[0,1],None,None],[Measure,0,None,None],[Reset,0,None,None],[H,0,None,None],[CNOT,[1,0],None,None],[Measure,0,None,None],[Measure,1,None,None]].

[0070] A given static quantum circuit can be compiled into an equivalent dynamic quantum circuit, so that the number of quantum bits required for the compiled quantum circuit is less than the number of quantum bits in the original quantum circuit. The compilation problem of static quantum circuits can be transformed into an equivalent graph optimization problem. To ensure the equivalence of quantum circuits before and after compilation, it is necessary to ensure that the order of operation instructions with execution restrictions in the original static quantum circuit is not changed during compilation.

[0071] In the implementation process, the execution order of quantum circuit operation instructions can be represented by a directed acyclic graph. Each operation instruction in the quantum circuit corresponds to a node in the graph, and the execution order of the quantum circuit operation instructions can be represented by a directed acyclic graph. i Point to v j The directed edge of v i The corresponding operation instruction must be in v j The corresponding operation instruction is executed before execution.

[0072] For example, Figure 3 The directed acyclic graph corresponding to the static quantum circuit in is shown in Figure 5(a). Figure 3The same as the operation instruction number in Figure 5(a). Figure 4 The dynamic quantum circuit is to Figure 3 The initialization operation on the quantum bit corresponding to quantum bit 2 (numbered 2) is postponed until the measurement operation on the quantum bit corresponding to quantum bit 0 (numbered 8), which is equivalent to adding a directed edge from node 8 to node 2 to the graph in the corresponding graph representation. As shown in Figure 5(b), the directed acyclic graph after adding the directed edge corresponds to the compiled dynamic quantum circuit.

[0073] At the same time, considering the specific problems of circuit compilation, the following restrictions need to be met in the graph optimization process: Since the directed acyclic graph represents the timing relationship of the execution of the operation instructions of the quantum circuit, it is necessary to ensure that the entire graph is still acyclic after adding directed edges; a quantum bit can only be used to perform operations on other quantum bits starting from the initialization operation after the measurement is completed. Therefore, the directed edges in the graph can only be connected between the nodes corresponding to the measurement operation instructions (hereinafter referred to as output nodes) and the nodes corresponding to the quantum bit initialization and reset operation instructions (hereinafter referred to as input nodes); a quantum bit can only be re-occupied by one other quantum bit at the same time after the measurement is completed. Therefore, at most one edge is added to each input / output node.

[0074] That is, this embodiment can transform the compilation problem of the static quantum circuit into an equivalent graph optimization problem, and compile the static quantum circuit into an equivalent dynamic quantum circuit by searching for directed edges from the output node to the input node in the directed acyclic graph of the static quantum circuit. The more directed edges from the connected output node to the input node, the better the effect of the equivalent compilation, that is, the fewer quantum bits of the obtained dynamic quantum circuit.

[0075] However, in many scenarios, the order of action of quantum operations in quantum circuits is not unique. For example, in the instantaneous quantum polynomial (IQP) circuit, the general form of the IQP circuit is Here, H represents the Hadamard gate, and D is composed of a series of quantum gates diagonalized in the computational basis. For example, Quantum gates are randomly selected for construction in D, so the operation order of each quantum gate in D can be modified arbitrarily.

[0076] Another example is the Quantum Approximate Optimization Algorithm (QAOA) circuit, where the execution order of many quantum gates in the circuit is interchangeable, and these circuits do not have a predetermined structure. In other words, the order of some quantum gate operations in these quantum circuits is interchangeable, and has no effect on the final circuit operation results.

[0077] FIG6(a) and FIG6(b) are equivalent quantum circuits. The quantum circuit shown in FIG6(b) is obtained by exchanging the execution order of CZ gates numbered 5 and 6 in the quantum circuit shown in FIG6(a).

[0078] It is worth noting that for quantum circuits with commutative structures, imposing execution dependencies between commutative quantum operations may limit the opportunities for qubit reuse, and commutative structures are an important feature in quantum applications. For example, all CZ gates in Figure 6(a) are commutative. If these commutative properties are ignored when constructing a directed acyclic graph representation of a quantum circuit, unnecessary execution dependencies will be introduced in the directed acyclic graph.

[0079] like Figure 7 As shown in FIG. 6( a ), it is a directed acyclic graph constructed for the dependency of the execution order of the quantum operations shown in FIG. 6( a ). The directed edges 701 and 702 are introduced according to the mandatory dependency of the quantum gates shown in FIG. 6( a ), which results in Figure 7 At most, only one directed edge 703 from the output node to the input node can be added, that is, only one quantum bit can be reduced.

[0080] The purpose of this embodiment is to automatically mark the commutative features of quantum operations of a quantum circuit containing a commutative structure, and to make full use of the commutativity between quantum operations in the commutative structure to equivalently compile a static quantum circuit into a dynamic quantum circuit.

[0081] In some implementations, the commutativity between quantum operations in the commutative structure can be used to construct a directed acyclic graph of the quantum circuit, and the equivalent compilation of the quantum circuit is performed based on the directed acyclic graph to improve the compilation effect of the quantum circuit.

[0082] for example, Figure 8It is a directed acyclic graph constructed by utilizing the interchangeability between quantum operations in the interchangeable structure 601 as shown in FIG6(a). The constructed directed acyclic graph contains flexible dependencies and does not limit the execution dependencies of quantum operations numbered 4, 5, and 6. Two directed edges can be added from the output node to the input node, namely directed edge 801 and directed edge 802. Therefore, the compiled quantum circuit can reduce two quantum bits, and its equivalent compilation effect is better, which can make the quantum circuit equivalent compilation reduce the number of quantum bits by a greater magnitude.

[0083] The first quantum circuit may be a static quantum circuit, which includes a quantum measurement operation and a quantum gate operation, and the quantum measurement operation is always located after the quantum gate operation.

[0084] The order of action of quantum operations in the first quantum circuit can be represented by an ordered instruction list, which is the first instruction list. The representation method has been described in detail in the above description and will not be repeated here.

[0085] The first instruction list of the first quantum circuit may be obtained by pre-storing, or the first instruction list of the first quantum circuit input by a user may be obtained, which is not specifically limited here.

[0086] In order to automatically identify the commutative structures existing in the quantum circuit, some groups of commutative gates can be predefined, and when traversing the instruction list of the quantum circuit, the group to which the quantum operations of the commutative structure belong can be marked.

[0087] For example, for the quantum gates in the set {Z, S, T, Rz, CZ}, since their matrix representations are all diagonalized under the computational basis, the order of the quantum gates in the set can be arbitrarily exchanged, such as Fig. 9 shown.

[0088] For another example, as shown in Figure 10(a), when the qubits acted on by the X and Rx gates are the same as the target qubits of the two-qubit CX gate, the order of their actions is also interchangeable. Similarly, as shown in Figure 10(b), when the qubits acted on by the Y and Ry gates are the same as the target qubits of the two-qubit CY gate, the order of their actions is also interchangeable.

[0089] For example, when the controlled qubit of the controlled two-qubit gate (CX, CY, CZ) is the same as the qubit acted on by the quantum gate in the set {Z, S, T, Rz}, the order of their actions can also be exchanged, such as Fig.11 shown.

[0090] Therefore, the target dictionary can be constructed in advance based on commutative quantum operations. For example, three commutative groups can be predefined, namely Z_Group = {Z, S, T, Rz, CZ c ,CZ t ,CX c ,CY c}; X_Group = {Rx, X, CX t}; Y_Group = {Ry, Y, CY t}, the target dictionary can include these three exchangeable groups, where Z_Group, X_Group and Y_Group are the identifiers of the exchangeable groups, and Z, S, T, Rz, CZ c ,CZ t ,CX c ,CY c is the quantum operation belonging to the commutative group Z_Group. Quantum operations belonging to the same commutative group are commutative with each other.

[0091] The target dictionary can be used to query whether a quantum operation is commutative, which commutative group it belongs to, and on which control type of qubit the quantum operation is commutative. There are two types of control types of qubits, namely controlled qubits and target qubits (i.e., control qubits).

[0092] That is, the target dictionary may indicate that two quantum operations belonging to the same commutative group are commutative if preset conditions are met, and the preset conditions include that the two quantum operations act on the same quantum bit, and the control types of the two quantum operations on the quantum bit are the control types indicated by the target dictionary.

[0093] For example, for two quantum gates, namely quantum gate X and quantum gate CX, the commutative group X_Group in the target dictionary includes X and CX t , indicating that the quantum gate CX can only be exchanged with the X gate on the target quantum bit (the control type of the exchangeable quantum bit indicated by CX in the target dictionary). That is to say, if the quantum bit where the quantum gate CX and the quantum gate X intersect is the target quantum bit, the two quantum gates can be exchanged, otherwise they cannot be exchanged.

[0094] Step S102: Obtain a first identifier of a quantum operation corresponding to an operation instruction in the first instruction list and a first control type of each quantum bit acted upon by the quantum operation.

[0095] The first instruction list can be traversed, and for each operation instruction in the first instruction list, the commutative group to which the operation instruction belongs on each quantum bit acted on by the operation instruction is marked.

[0096] The first identifier of the quantum operation corresponding to the operation instruction and the first control type of each quantum bit acted upon by the quantum operation can be obtained based on the parameters in the operation instruction. The first identifier of the quantum operation corresponding to the operation instruction can be determined based on the name parameter of the operation instruction, and the first control type of each quantum bit acted upon by the quantum operation can also be determined based on the qubit parameter.

[0097] Step S103: Based on the target dictionary, the first identifier and the first control type, determine the exchangeable feature of the operation instruction on each quantum bit on which it acts, the exchangeable feature indicating the exchangeability of the operation instruction on the quantum bit. When the exchangeable feature indicates that the operation instruction is exchangeable on the quantum bit, the exchangeable feature includes a second identifier of the exchangeable group to which the operation instruction belongs on the quantum bit.

[0098] The commutative feature of the operation instruction on the quantum bit on which it acts characterizes the commutativeness of the operation instruction with other operation instructions on the quantum bit, and has two properties. The first is to characterize whether the operation instruction is a commutative operation on the quantum bit, and the second is to characterize whether the operation instruction is commutative with other operation instructions on the quantum bit. The commutative feature can be represented by a numerical value or by a character. For example, the commutative feature is the identifier Z_Group of the commutative group, which is represented by a character and is not specifically limited here.

[0099] The commutative features of each operation instruction on the quantum bit it acts on can be stored in an additional list, or the commutative features can be stored in the parameters of the operation instruction. For example, for each operation instruction, the commutative group to which the operation instruction belongs on the quantum bit it acts on can be marked through the group_tags parameter of the operation instruction. The quantum operations acting on the same quantum bit and belonging to the same commutative group can be interchanged in their order of action.

[0100] For a controlled dual / multi-qubit gate, its controlled qubit and target qubit may belong to different exchangeable groups. Therefore, it is necessary to mark the exchangeable groups to which the quantum operation belongs on the controlled qubit and the target qubit respectively. In one embodiment, the group_tags parameter of each operation instruction is set to a list, and the length of the list is equal to the number of qubits acted on by the operation instruction. Each element in the group_tags list corresponds one-to-one to the qubit in the qubit parameter list of the operation instruction, indicating the exchangeable group to which the operation instruction belongs on different qubits. For example, for a CX gate whose qubit list is [1,2], its controlled qubit 1 belongs to Z_Group, and the target qubit 2 belongs to X_Group. Therefore, the group_tags list of the operation instruction should be [Z_Group, X_Group].

[0101] For non-commutative operation instructions, such as reset operations or measurement operations, the group_tags parameter can be set to None.

[0102] Among them, if two operation instructions act on the same quantum bit and the two have the same exchangeable characteristics on the quantum bit, it means that the two operation instructions are exchangeable on the quantum bit. For example, the operation instructions [CX, [1, 2], None, None, [Z_Group, X_Group]] and [X, [2], None, None, X_Group], then quantum gate CX and quantum gate X are exchangeable on quantum bit 2. For another example, the operation instructions [CX, [1, 2], None, None, [Z_Group, X_Group]] and [X, [1], None, None, [X_Group]], because the exchangeable group of quantum gate CX on quantum bit 1 is Z_Group, and the exchangeable group of quantum gate X on quantum bit 1 is X_Group, the exchangeable characteristics of the two on quantum bit 1 are different, so quantum gate CX and quantum gate X are not exchangeable on quantum bit 1.

[0103] In an optional embodiment, it is possible to query in the target dictionary whether there is an exchangeable group corresponding to the first identifier based on the first identifier. If not, the exchangeable feature of the quantum bit is marked as None. If it exists, based on the first control type of the quantum bit, further query is performed in the target dictionary to determine the exchangeable group of the operation instruction on the quantum bit. For example, for the first identifier CX, the exchangeable groups Z_Group and X_Group in the target dictionary both include CX, and the first control type of the quantum bit is a controlled quantum bit, then the exchangeable group of the operation instruction on the quantum bit is Z_Group, and its exchangeable feature is Z_Group.

[0104] In another optional implementation, the identifier of the exchangeable group matching the first identifier and the first control type may also be queried in the target dictionary to obtain the exchangeable characteristics of the quantum bit.

[0105] Optionally, the target dictionary includes a first dictionary and a second dictionary, the first dictionary indicates a correspondence between an identifier of a first exchangeable group and an identifier of a quantum operation, the second dictionary indicates a correspondence between an identifier of a second exchangeable group and an identifier of a quantum operation, the first exchangeable group is an exchangeable group of quantum operations on controlled quantum bits when the control type is indicated, and the second exchangeable group is an exchangeable group of quantum operations on target quantum bits when the control type is indicated;

[0106] The step S103 specifically includes at least one of the following:

[0107] When the first control type indicates a controlled quantum bit, determining, based on the first dictionary and the first identifier, a commutative feature of the operation instruction on the controlled quantum bit on which the operation instruction acts;

[0108] When the first control type indicates a target quantum bit, based on the second dictionary and the first identifier, the exchangeable characteristics of the operation instruction on the target quantum bit are determined.

[0109] Two dictionaries can be used to store the group information of the commutative groups to which the pre-defined quantum operations belong on the controlled quantum bits and the target quantum bits, respectively. The key in the dictionary is the identifier of the group, and the corresponding value is the quantum operation included in the group.

[0110] For example, the three groups of exchangeable groups defined above can be divided into a first dictionary and a second dictionary, which are respectively called the exchangeable group dictionary Control_Group to which quantum operations belong on controlled quantum bits and the exchangeable group dictionary Target_Group to which quantum operations belong on target quantum bits.

[0111] Where, Control_Group = {Z_Group: {CX, CY, CZ}};

[0112] Target_Group={X_Group:{X,Rx,CX},

[0113] Y_Group:{Y,Ry,CY},

[0114] Z_Group:{Z,S,T,Rz,CZ}}.

[0115] First, a dictionary matching the first control type can be selected from the first dictionary and the second dictionary, and then, based on the selected dictionary, the exchangeable characteristics of the operation instruction on the quantum bit are determined. If the first control type indicates that the quantum bit is a controlled quantum bit, the selected dictionary is Control_Group, and the exchangeable characteristics of the operation instruction on the controlled quantum bit are determined based on the dictionary. If the first control type indicates that the quantum bit is a target quantum bit, the selected dictionary is Target_Group, and the exchangeable characteristics of the operation instruction on the target quantum bit are determined based on the dictionary.

[0116] In this way, the matching speed of the exchangeable group identifiers based on the target dictionary can be improved.

[0117] Optionally, determining the exchangeable feature of the operation instruction on the quantum bit on which the operation instruction acts based on the dictionary indicating the correspondence between the identifier of the exchangeable group and the identifier of the quantum operation and the first identifier includes:

[0118] In a case where the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations includes the first identifier, determining an identifier corresponding to the first identifier in the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations as a second identifier of the commutative group to which the operation instruction belongs on the quantum bit on which the operation instruction acts;

[0119] When the first identifier is not included in the dictionary indicating the correspondence between the identifier of the exchangeable group and the identifier of the quantum operation, the target information is determined as the exchangeable feature of the operation instruction on the quantum bit on which it is applied, and the target information indicates that the operation instruction is not exchangeable on the quantum bit on which it is applied.

[0120] The dictionary indicating the correspondence between the identifier of the exchangeable group and the identifier of the quantum operation may be a first dictionary or a second dictionary, which is determined according to the first control type.

[0121] If the identifier of the exchangeable group corresponding to the first identifier can be found in the dictionary, the identifier is determined as the exchangeable feature of the operation instruction on the quantum bit. If the identifier of the exchangeable group corresponding to the first identifier cannot be found in the dictionary, the exchangeable feature of the operation instruction on the quantum bit can be marked as None.

[0122] In this way, the exchangeable characteristics of operation instructions on quantum bits can be easily annotated based on the dictionary.

[0123] In some embodiments, the specific process of automatically identifying and marking the commutative features of the operation instructions of the quantum circuit on each quantum bit on which the operation instructions act is as follows:

[0124] Input: static quantum circuit instruction list Static_Circuit, predefined exchangeable group dictionary Control_Group of operation instructions on controlled quantum bits and exchangeable group dictionary Target_Group of operation instructions on target quantum bits;

[0125] Output: The instruction list Static_Circuit of the static quantum circuit after marking the commutative characteristics on the quantum bits.

[0126] Step 1: Loop through the instruction list of the input static quantum circuit, and set the element currently looped to be Instruction;

[0127] Step 2: Get the number of qubits acted upon by Instruction, record it as k; initialize a list Tags of length k, where each element is initialized to None, and execute step 2.1 or step 2.2;

[0128] Step 2.1: If Instruction is a single-qubit operation, traverse the key-value pairs of the Target_Group dictionary, set the currently traversed key to tag and the value to group; if the name parameter of Instruction is included in group, rewrite the element value in Tags to tag;

[0129] Step 2.2: If Instruction is a multi-qubit gate operation, obtain the qubit list of the qubits it acts on; record the indexes of the controlled qubits and the control qubits in the qubit list in the Control list and the Target list, respectively, and perform operations a and b respectively;

[0130] Operation a: Traverse the key-value pairs of the Control_Group dictionary, set the currently traversed key to tag and the value to group; if the name parameter of Instruction is included in group, traverse the Control list, set the currently traversed element to idx, and change the element with index idx in the Tags list to tag;

[0131] Operation b: Traverse the key-value pairs of the Target_Group dictionary, set the currently traversed key to tag and the value to group; if the name parameter of Instruction is included in group, traverse the Target list, set the currently traversed element to idx, and modify the element with index idx in the Tags list to tag;

[0132] Step 3: Set the group_tags parameter of the Instruction instruction to the Tags list; if the instruction list of the static quantum circuit has not been traversed, return to step 2;

[0133] Step 4: Return the instruction list Static_Circuit of the static quantum circuit annotated with the commutative features on the qubits as output.

[0134] Step S104: Based on the exchangeable feature and the first instruction list, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

[0135] At least one directed acyclic graph can be created based on the exchangeable feature and the first instruction list. Afterwards, the first quantum circuit can be equivalently compiled based on the created directed acyclic graph.

[0136] In an optional implementation, a directed acyclic graph may be created according to the mandatory dependency relationship of the operation instructions in the target instruction list, the directed acyclic graph may include a directed acyclic graph of the first quantum circuit and directed acyclic graphs of other quantum circuits equivalent to the first quantum circuit, and the target instruction list may include the first instruction list and an instruction list for exchanging the operation instructions in the first instruction list based on the exchangeable feature.

[0137] In another optional implementation, based on the exchangeable feature, the operation instructions in the first instruction list can be used as nodes to construct a first directed acyclic graph of the first quantum circuit, in which the action quantum bits have an intersection, and there are no directed edges between the nodes corresponding to different operation instructions that are exchangeable on the quantum bits of the intersection.

[0138] If there are multiple directed acyclic graphs created based on the exchangeable feature and the first instruction list, the first quantum circuit can be equivalently compiled based on each directed acyclic graph, and the quantum circuit with the least number of quantum bits compiled is selected as the second quantum circuit to obtain a second instruction list for the second quantum circuit.

[0139] In this embodiment, by automatically marking the exchangeable features of each operation instruction in the first quantum circuit on the quantum bit on which it acts based on the target dictionary, and based on the exchangeable features of the operation instruction on the quantum bit and the first instruction list, the first quantum circuit is equivalently compiled. In this way, a directed acyclic graph can be created with the help of the exchangeable features of the operation instruction on the quantum bit, avoiding the forced dependency relationship imposed on the execution between the exchangeable operation instructions to limit the opportunity of quantum bit reuse, thereby helping to fully explore the quantum bit reuse opportunities in the quantum circuit containing the exchangeable structure, so that more directed edges from the output node to the input node can be added in the constructed directed acyclic graph, thereby improving the effect of quantum circuit equivalent compilation, reducing the number of quantum bits required for the compiled dynamic quantum circuit, and making the quantum circuit equivalent compilation reduce the number of quantum bits by a larger magnitude, which is more suitable for quantum computers with ion trap architectures with long coherence time but poor scalability.

[0140] Moreover, by automatically identifying and annotating quantum operations of commutative structures existing in quantum circuits, it is applicable to large-scale quantum circuits and can improve the efficiency of annotating commutative features.

[0141] Optionally, the step S104 specifically includes:

[0142] Based on the exchangeable feature, taking the operation instructions in the first instruction list as nodes, constructing a first directed acyclic graph of the first quantum circuit, wherein the action qubits in the first directed acyclic graph have an intersection, and there are no directed edges between the nodes corresponding to different operation instructions that are exchangeable on the qubits of the intersection;

[0143] Based on the first directed acyclic graph, the first quantum circuit is equivalently compiled to obtain a second instruction list of a second quantum circuit.

[0144] The first directed acyclic graph includes nodes corresponding to instructions in the first instruction list and directed edges between the nodes. The directed edges between the nodes are used to characterize the timing relationship between different operation instructions in the first instruction list, and the path formed by the directed edges between the nodes does not include a directed loop.

[0145] In constructing the first directed acyclic graph, it is necessary to avoid adding directed edges between nodes corresponding to the operation instructions that are exchangeable on the qubits of the intersection. In an optional implementation, the first instruction list can be traversed in the order of the instructions from left to right, and the instruction sublist in the first instruction list that is sorted before the instruction currently traversed and the qubits acted on by the instruction currently traversed are obtained; the instruction sublist is traversed in the order of the instructions from right to left, and the operation instructions whose qubits acted on and the qubits acted on by the instruction currently traversed are obtained; the exchangeable characteristics of the two on the qubits of the intersection are compared. If the comparison result indicates that the two are not exchangeable, the identifier of the operation instruction is used as the source node and the identifier of the instruction currently traversed is used as the target node to construct a directed edge; if the comparison result indicates that the two are exchangeable, the instruction sublist is continued to be traversed to search for the operation instruction that is not exchangeable between the qubits of the intersection and the instruction currently traversed, and a directed edge between the two is constructed. When the traversal of the first instruction list is completed, the first directed acyclic graph is obtained based on the constructed directed edges.

[0146] Optionally, based on the exchangeable feature, taking the operation instructions in the first instruction list as nodes to construct a first directed acyclic graph of the first quantum circuit includes:

[0147] forwardly traverse the first instruction list according to the arrangement order of the operation instructions;

[0148] Taking the first operation instruction currently traversed as a node, and for each first qubit acted upon by the first operation instruction, when the first list corresponding to the first qubit is not an empty list, based on the exchangeable feature of the operation instructions in the first list on the first qubit, constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction; on the first qubit, the target operation instruction and the first operation instruction are not exchangeable;

[0149] The first operation instruction is added to the end of the first list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

[0150] In this way, by creating a list corresponding to each quantum bit to store its corresponding operation instructions in order, it is very convenient to find the predecessor operation instruction associated with each operation instruction, and search for the target operation instruction from the predecessor operation instruction to construct a directed edge between the target operation instruction and the operation instruction, so that the first directed acyclic graph can be constructed very quickly and at high speed.

[0151] Among them, the target operation instruction is not interchangeable with the first operation instruction on the quantum bits of the intersection, and it is the operation instruction that is closest to the position of the first operation instruction and is not interchangeable with the first operation instruction on the quantum bits of the intersection. That is, by comparing the interchangeable characteristics of the operation instruction in the first list on the first quantum bit and the interchangeable characteristics of the first operation instruction on the first quantum bit, the target operation instruction in the first list that is closest to the position of the first operation instruction and is not interchangeable with the first operation instruction on the first quantum bit can be searched to build a dependency relationship between the two and add a directed edge between the two. In this way, dependencies can be added only between the operation instructions that are not interchangeable on the quantum bits of the intersection, and it can be avoided to impose a forced dependency between the corresponding nodes of the interchangeable operation instructions in the directed acyclic graph, so that the dependency relationship between the corresponding nodes of the operation instructions in the directed acyclic graph is more flexible, that is, the execution dependency relationship between the interchangeable operation instructions on the quantum bits of the intersection is not limited in the directed acyclic graph, so that there are more candidate directed edges from the output node to the input node that can be added in the directed acyclic graph.

[0152] Afterwards, the first operation instruction is added to the end of the first list as a preceding operation instruction of the next traversed operation instruction. Accordingly, when the traversal of the first instruction list is completed, the construction of the directed acyclic graph of the quantum circuit is completed, and the first directed acyclic graph can be obtained. In this way, the first directed acyclic graph with flexible dependencies can be constructed very quickly and at high speed, so that more directed edges from output nodes to input nodes can be added in the constructed directed acyclic graph, thereby improving the effect of equivalent compilation of quantum circuits, reducing the number of quantum bits required for the compiled dynamic quantum circuit, and compared with the equivalent compilation of quantum circuits based on directed acyclic graphs with mandatory dependencies, the quantum circuit equivalent compilation can reduce the number of quantum bits by a greater magnitude.

[0153] Optionally, constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction based on the exchangeable feature of the operation instruction in the first list on the first qubit includes:

[0154] In a case where it is determined based on the exchangeable feature that the second operation instruction is not exchangeable on the first quantum bit, determining the second operation instruction as a target operation instruction, wherein the second operation instruction is an operation instruction at the end of the first list;

[0155] Add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

[0156] In this embodiment, if the exchangeable characteristic of the second operation instruction at the end of the first list on the first quantum bit is None, it can be indicated that the second operation instruction is a non-commutative operation on the first quantum bit. At this time, the first operation instruction and the second operation instruction have an execution dependency relationship on the first quantum bit. The second operation instruction can be added to the target directed edge of the first operation instruction, which will not introduce unnecessary dependencies and can ensure the accuracy of the dependencies between the quantum operations of the first quantum circuit represented by the constructed directed acyclic graph.

[0157] Optionally, constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction based on the exchangeable feature of the operation instruction in the first list on the first qubit includes:

[0158] In a case where it is determined based on the exchangeable feature that the second operation instruction is exchangeable on the first qubit, comparing the exchangeable feature of the operation instruction in the first list on the first qubit with the exchangeable feature of the first operation instruction on the first qubit to obtain a comparison result;

[0159] Based on the comparison result, at least one target operation instruction of the previous group on the first qubit is obtained from the first list to obtain a first sublist, wherein in the same group, on the first qubit, different target operation instructions are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction;

[0160] Add each target operation instruction corresponding node in the first sublist to the directed edge of the first operation instruction corresponding node.

[0161] If the exchangeable feature of the second operation instruction at the end of the first list on the first quantum bit is not None, it can be indicated that the second operation instruction is an exchangeable operation on the first quantum bit. In this scenario, the exchangeable feature of the operation instruction in the first list on the first quantum bit and the exchangeable feature of the first operation instruction on the first quantum bit can be compared to search for at least one target operation instruction of the previous group of the first operation instruction on the first quantum bit from the first list, and correspondingly add the directed edge of each target operation instruction corresponding node in the first sublist to the corresponding node of the first operation instruction to obtain the first directed acyclic graph.

[0162] When the operation instruction is a non-commutative operation, it can form a group alone. When the commutative characteristics of two operation instructions on the first quantum bit are not None and are the same, the two belong to the same group. When the commutative characteristics of two operation instructions on the first quantum bit are different, the two belong to different groups.

[0163] The previous group of the first operation instruction on the first quantum bit refers to the group whose active bit is the first quantum bit, whose arrangement position is before the first operation instruction, and whose distance to the position of the first operation instruction is the closest. For example, the exchangeable characteristics of the operation instruction on the first quantum bit in the first list are node 1: 'None', node 2: 'None', node 3: 'Z_Group', node 4: 'Z_Group', and their groups are two groups with exchangeable characteristics of 'None' and a group with exchangeable characteristics of 'Z_Group', respectively. The exchangeable characteristics of the first operation instruction on the first quantum bit are 'X_Group' or 'None'. Since the preceding operation instruction associated with the first operation instruction is placed at the end of the first list as the first instruction list is traversed, the group with exchangeable characteristics of 'Z_Group' is closer to the first operation instruction in the first instruction list, and the previous group of the first operation instruction on the first quantum bit is the group with exchangeable characteristics of 'Z_Group'.

[0164] Among them, in some scenarios, the previous group may be a group of non-interchangeable operations, which contains only one target operation instruction. In other scenarios, the previous group may be an interchangeable group different from the first operation instruction group, which may include at least one target operation instruction.

[0165] For example, the exchangeable characteristics of the operation instructions in the first list on the first quantum bit are node 1: 'None', node 2: 'None', node 3: 'X_Group', node 4: 'X_Group', and the exchangeable characteristic of the first operation instruction is 'X_Group'. The previous group of the first operation instruction obtained from the first list only includes the target operation instruction corresponding to node 2.

[0166] For another example, the exchangeable characteristics of the operation instructions in the first list on the first quantum bit are node 1: 'None', node 2: 'None', node 3: 'Z_Group', node 4: 'Z_Group', and the exchangeable characteristic of the first operation instruction on the first quantum bit is 'X_Group' or 'None', then the previous group of the first operation instruction obtained from the first list includes the target operation instruction corresponding to node 3 and the target operation instruction corresponding to node 4.

[0167] In an optional embodiment, the groups to which the operation instructions of the first list belong on the first quantum bit and the operation instructions of each group can be obtained, the exchangeable characteristics of each group can be compared with the exchangeable characteristics of the first operation instruction on the first quantum bit, and an adjacent group that is different from the group to which the first operation instruction belongs on the first quantum bit and is located before the group of the first operation instruction is selected, and the adjacent group is the previous group of the first operation instruction.

[0168] In another optional embodiment, at least one target operation instruction of the previous group of the first operation instruction can be obtained from the first list by traversing the first list in reverse and comparing the exchangeable characteristics of its operation instructions on the first quantum bit with the exchangeable characteristics of the first operation instruction on the first quantum bit.

[0169] All target operation instructions of the previous group of the first operation instruction may be obtained first, and then a directed edge from a node corresponding to each target operation instruction to a node corresponding to the first operation instruction may be added. Alternatively, each time a target operation instruction is obtained, a directed edge from a node corresponding to the target operation instruction to a node corresponding to the first operation instruction may be added until the directed edge is added.

[0170] In this way, by obtaining at least one target operation instruction of the previous group of the first operation instruction and adding the target operation instruction to the directed edge of the first operation instruction, it will not introduce unnecessary dependencies and can ensure the accuracy of the dependencies between the quantum operations of the first quantum circuit represented by the constructed directed acyclic graph.

[0171] Optionally, based on the comparison result, obtaining at least one target operation instruction of a previous group on the first qubit from the first list to obtain a first sub-list includes:

[0172] When the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first quantum bit is the same as the exchangeable characteristic of the first operation instruction on the first quantum bit, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions;

[0173] When the first target operation instruction is not exchangeable on the first qubit, obtaining the first sublist, wherein the first sublist includes only the first target operation instruction;

[0174] In the case where the first target operation instruction is exchangeable on the first quantum bit, other target operation instructions with the same first exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the first exchangeable characteristic is the exchangeable characteristic of the first target operation instruction on the first quantum bit.

[0175] The second operation instruction is the operation instruction at the end of the first list. If the first operation instruction is commutative on the first qubit, and the commutative feature of the second operation instruction on the first qubit is the same as the commutative feature of the first operation instruction on the first qubit, it means that the second operation instruction and the first operation instruction belong to the same group of commutative groups on the first qubit, and at this time, a directed edge between the two cannot be added.

[0176] By traversing the first list in reverse, and comparing the exchangeable characteristics of the operation instructions in the first list on the first quantum bit with the exchangeable characteristics of the first operation instruction on the first quantum bit, a target operation instruction on the first quantum bit that is different from the exchangeable characteristics of the first operation instruction on the first quantum bit can be searched from the first list. It is determined whether the target operation instruction is exchangeable on the first quantum bit. If it is not exchangeable, the previous group of the first operation instruction only includes one target operation instruction. If it is exchangeable, it is necessary to continue the reverse traversal. If there are other operation instructions on the first quantum bit that have the same exchangeable characteristics as the target operation instruction on the first quantum bit, they are obtained and classified into the previous group of the first operation instruction, so that all target operation instructions in the previous group of the first operation instruction can be searched. In this way, all target operation instructions in the previous group of the first operation instruction can be quickly and accurately obtained.

[0177] Optionally, based on the comparison result, obtaining at least one target operation instruction of a previous group on the first qubit from the first list to obtain a first sub-list includes:

[0178] If the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first qubit is different from the exchangeable characteristic of the first operation instruction on the first qubit, determining the second operation instruction as the target operation instruction;

[0179] Other target operation instructions having the same second exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the second exchangeable characteristic is an exchangeable characteristic of the second operation instruction on the first quantum bit.

[0180] The second operation instruction is the operation instruction at the end of the first list. If the first operation instruction is exchangeable on the first quantum bit, and the exchangeability feature of the second operation instruction on the first quantum bit is different from the exchangeability feature of the first operation instruction on the first quantum bit, then the second operation instruction and the first operation instruction belong to different groups on the first quantum bit.

[0181] By traversing the first list in reverse, other target operation instructions on the first qubit that have the same exchangeable characteristics as the second operation instruction on the first qubit can be searched in the first list, so that all target operation instructions in the previous group of the first operation instruction can be searched. In this way, all target operation instructions in the previous group of the first operation instruction can be quickly and accurately obtained.

[0182] In one embodiment, based on the commutative characteristics of operation instructions on quantum bits, the specific process of constructing a directed acyclic graph of a quantum circuit is as follows:

[0183] Input: static quantum circuit instruction list Static_Circuit, quantum circuit width n;

[0184] Output: directed acyclic graph Digraph, input node list Inputs and output node list Outputs.

[0185] Step 1: Initialize an empty directed acyclic graph Digraph; initialize a list Causal_Lists of length n, where each element is initialized to an empty list; initialize two lists Inputs and Outputs of length n, where each element is initialized to None;

[0186] Step 2: Loop through Static_Circuit, assuming the element currently being traversed is Instruction and its index is Index:

[0187] Step 2.1: Add a node Vertex to the Digraph, which is identified as Index;

[0188] Step 2.2: If Instruction is a qubit reset operation, obtain the qubit it acts on, and modify the value of qubit indexed in the Inputs list to Index;

[0189] Step 2.3: If Instruction is a quantum bit measurement operation, obtain the quantum bit qubit it acts on, and modify the value of the Outputs list indexed as qubit to Index;

[0190] Step 2.4: Get the qubit parameter list of the Instruction instruction and traverse it. Set the index of the currently traversed element to be i, and its value to be q. Record the element with index i in the group_tags parameter list of Instruction as Group. Find the last element of the list Causal_Lists[q] and record it as PreVertex. If PreVertex is not an empty element, get the element with value q in the qubit parameter list of the operation instruction corresponding to PreVertex, and record its index as idx. Record the element with index idx in the group_tags parameter list of the instruction as PreGroup.

[0191] Step 2.4.1: If PreGroup is None, add a directed edge from PreVertex to Vertex to the Digraph and execute step 2.4.4;

[0192] Step 2.4.2: If PreGroup is different from Group, traverse the Causal_Lists[q] list in reverse order, set the currently traversed element to CurrentVertex, and perform operation a:

[0193] Operation a: Get the element with the value q in the qubit parameter list of the operation instruction corresponding to CurrentVertex and record its index as idx, and record the element with the index idx in the group_tags parameter list of the instruction as CurrentGroup; if CurrentGroup is the same as PreGroup, add a directed edge from CurrentVertex to Vertex to Digraph; if CurrentGroup is different from Group, jump out of the loop and execute step 2.4.4;

[0194] Step 2.4.3: If PreGroup is the same as Group, initialize a Boolean variable Found to False, traverse the Causal_Lists[q] list in reverse loop, set the currently traversed element to CurrentVertex, and perform operation b:

[0195] Operation b: Get the element with the value q in the qubit parameter list of the operation instruction corresponding to CurrentVertex and record its index as idx, and record the element with the index idx in the group_tags parameter list of the instruction as CurrentGroup; if CurrentGroup is the same as Group, continue to loop through the next element; if CurrentGroup is different from Group and Found is False, set the value of PreGroup to CurrentGroup, and set Found to True; add a directed edge from CurrentVertex to Vertex to Digraph; if the value of PreGroup is None, exit the loop and execute step 2.4.4; if CurrentGroup is different from Group and Found is True, then if CurrentGroup is equal to PreGroup, add a directed edge from CurrentVertex to Vertex to Digraph; if CurrentGroup is not equal to PreGroup, exit the loop and execute step 2.4.4;

[0196] Step 2.4.4: Add Vertex to the end of the list Causal_Lists[q].

[0197] Step 3: Return Digraph, Inputs, Outputs as output.

[0198] In this implementation, a list is used to store the commutative groups to which the multi-qubit gate belongs on each qubit it acts on. Therefore, it is necessary to analyze and process the commutative status of each qubit of the multi-qubit gate.

[0199] Optionally, performing equivalent compilation on the first quantum circuit based on the first directed acyclic graph to obtain a second instruction list for a second quantum circuit includes:

[0200] Adding a target directed edge from the output node to the input node in the first directed acyclic graph to obtain a second directed acyclic graph;

[0201] Based on the second directed acyclic graph, the second list consisting of the added target directed edges, and the first instruction list, the first quantum circuit is equivalently compiled to obtain a second instruction list for a second quantum circuit.

[0202] Based on the first directed acyclic graph, and the input node list and output node list of the first directed acyclic graph, a target directed edge from the output node to the input node can be added in the first directed acyclic graph to obtain a second directed acyclic graph, wherein the second directed acyclic graph includes the target directed edge and the directed edges in the first directed acyclic graph, and the path formed by the target directed edge and the directed edges in the first directed acyclic graph does not include a directed loop.

[0203] Among them, the input node list includes nodes corresponding to the reset operation instruction type in the first instruction list, the output node list includes nodes corresponding to the quantum measurement operation instruction type in the first instruction list, and in the second directed acyclic graph, each output node is connected to at most one input node, and different output nodes cannot be connected to the same input node.

[0204] In this step, since one quantum circuit is compiled into another quantum circuit, it is essentially to reset and recycle the measured quantum bits for use in subsequent instructions. Corresponding to the first directed acyclic graph, it is equivalent to adding directed edges from output nodes to input nodes to the graph as much as possible to indicate that the measured bits are reset and reused, which can reduce the number of quantum bits required in the quantum circuit.

[0205] In order to ensure the equivalence of the compiled quantum circuit with the original quantum circuit and to ensure the timing relationship between the instructions in the quantum circuit, the following constraints need to be met when adding directed edges:

[0206] 1) In order to make the entire graph still conform to the timing relationship of the circuit instructions, it is necessary to ensure that the entire graph is still acyclic after adding more directed edges. It should be noted that the direction of the directed edges in the graph represents the timing relationship of the instructions, and the ring structure will destroy this relationship. That is, after adding directed edges, there should still be no ring structure path in the graph (called a directed loop);

[0207] 2) Each output node can only be connected to one input node at most, indicating that after the output node is measured, the input node it points to continues to perform operations on the qubit;

[0208] 3) Different output nodes cannot be connected to the same input node.

[0209] Correspondingly, after adding the target directed edge that meets the above constraints to the first directed acyclic graph, a second directed acyclic graph can be obtained.

[0210] A brute force search method, a heuristic search method, or a combination of the two can be used to determine the target directed edge from the output node to the input node added in the first directed acyclic graph to obtain the second directed acyclic graph. In some embodiments, the target directed edge from the output node to the input node added in the first directed acyclic graph can be determined based on the candidate edge matrix of the first directed acyclic graph, and the candidate edge matrix is ​​used to characterize the connectivity of the output node to the input node in the first directed acyclic graph.

[0211] Afterwards, the first quantum circuit can be equivalently compiled based on the second directed acyclic graph, the second list consisting of the target directed edges, and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

[0212] After adding a directed edge from the output node to the input node, the timing relationship between the nodes can be determined based on the second directed acyclic graph, and the first instruction list can be reordered based on the timing relationship. Afterwards, the relationship between the input node and the output node in the second list can be used to equivalently compile instructions that act on other quantum bits (i.e., the quantum bits acted on by the instructions corresponding to the input nodes that are directionally connected to the output nodes corresponding to the measurement operation instructions) after the measurement instruction into instructions that act on the quantum bits acted on by the measurement instruction. In this way, equivalent compilation of the first quantum circuit can be achieved, and a second instruction list for a second quantum circuit equivalent to the first quantum circuit can be obtained, and the quantum bits required in the second quantum circuit are fewer than the quantum bits required in the first quantum circuit.

[0213] Taking a method of heuristic search as an example, the step of adding a target directed edge from an output node to an input node in the first directed acyclic graph to obtain a second directed acyclic graph includes:

[0214] Determine target directed edges from the candidate directed edges of the first directed acyclic graph in sequence, and add the target directed edges in sequence until there is no directed edge from the output node to the input node in the directed acyclic graph obtained after adding the target directed edges, thereby obtaining a second directed acyclic graph;

[0215] Among them, the target directed edge is the candidate directed edge with the largest score value among the candidate directed edges based on the first directed acyclic graph, and the score value is used to characterize the total number of directed edges that can be connected from the output node to the input node in the third directed acyclic graph, and the third directed acyclic graph is obtained after adding the candidate directed edges to the first directed acyclic graph.

[0216] Optionally, the score value of the candidate directed edge is determined by:

[0217] Obtaining a candidate edge matrix of a first directed acyclic graph, wherein elements in the candidate edge matrix are used to characterize the connectivity from an output node to an input node in the first directed acyclic graph;

[0218] For the candidate directed edge corresponding to the target element in the candidate edge matrix, obtain the column index whose element value in the row corresponding to the target element is a first value to obtain a first set, and obtain the row index whose element value in the column corresponding to the target element is the first value to obtain a second set, wherein the first value indicates that the output node is not connectable to the input node;

[0219] Performing a Cartesian product on the second set and the first set to obtain a third list;

[0220] Update the first element in the candidate edge matrix to a first value to obtain a target matrix, wherein the first element includes the elements indicated by the third list, the target element, and each element indicated by a row corresponding to the row index of the target element and each element indicated by a column corresponding to the column index of the target element;

[0221] Based on the number of elements in the target matrix whose element values ​​are second values, a score value of the candidate directed edge corresponding to the target element is determined, wherein the second value indicates that the output node is connectable to the input node.

[0222] In an optional implementation manner, the specific process of this embodiment is as follows:

[0223] Automatically identifying and marking the commutative features of the operation instructions of the first instruction list of the first quantum circuit on each quantum bit;

[0224] Based on the exchangeable feature, the operation instructions in the first instruction list are used as nodes to construct a first directed acyclic graph of the first quantum circuit;

[0225] Obtaining a candidate edge matrix of the first directed acyclic graph by using a graph search algorithm such as a depth-first search algorithm;

[0226] A heuristic search method is used to obtain all target directed edges from output nodes to input nodes that can be added to the first directed acyclic graph of the first quantum circuit;

[0227] According to the second directed acyclic graph after adding the target directed edge, the first quantum circuit is compiled into an equivalent second quantum circuit.

[0228] Obviously, due to the restrictions of the directed acyclic graph conditions, not all edges pointing from output nodes to input nodes can be added to the graph. For example, in Figure 5(a), adding an edge from node 9 to node 2 will introduce a loop structure of 2→5→7→9→2. In fact, after obtaining the graph representation of the static quantum circuit, all edges that do not directly introduce a loop structure can be obtained through a graph search algorithm. If there is no path between the input node with index i and the output node with index j in the directed acyclic graph corresponding to the static quantum circuit, that is, the input node i cannot reach the output node j, then connecting the output node with index j and the input node with index i will not directly introduce a loop in the graph, so such an edge is a candidate directed edge.

[0229] Assume that a static quantum circuit contains n input nodes and m output nodes. All candidate directed edges can be stored in an m×n matrix, called a candidate edge matrix. The jth row corresponds to the output node with index j, and the ith column corresponds to the input node with index i. The matrix element (j, i) = 1 indicates that the edge between the output node with index j and the input node with index i is a candidate directed edge; otherwise, the matrix element is 0.

[0230] Since unnecessary dependencies between commutative quantum operations are avoided when constructing a directed acyclic graph, the generated directed acyclic graph actually contains more candidate directed edges, which helps to add more candidate directed edges to the directed acyclic graph, thereby improving the equivalent compilation effect of the quantum circuit.

[0231] For example, based on Figure 7 The candidate edge matrix generated by the directed acyclic graph shown is: based on Figure 8 The candidate edge matrix generated by the directed acyclic graph shown is: It can be seen that based on Figure 8 The generated candidate edge matrix is ​​relative to the Figure 7 The generated candidate edge matrix contains at most two candidate directed edges.

[0232] To illustrate the quantum circuit processing process of this embodiment in detail, a compilation example of a specific circuit can be provided. Taking the static quantum circuit shown in FIG. 12( a) as an example, if the commutativity of the quantum gates therein is ignored, the quantum circuit cannot be compiled by reusing quantum bits to reduce the number of quantum bits.

[0233] The instruction list of the static quantum circuit shown in Figure 12(a) is: static_circuit = [[Reset,0,None,None], [Reset,1,None,None], [Reset,2,None,None], [Rx,0,θ 1,None],[Rz,1,θ 2 ,None],[H,2,None,None],[CNOT,[1,0],None,None],[CNOT,[1,2],None,None],[CZ,[0,1],None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0234] According to the target dictionary, the quantum circuit instruction list after the exchangeable feature annotation is: static_circuit = [[Reset,0,None,None,[None]], [Reset,1,None,None,[None]], [Reset,2,None,None,[None]], [Rx,0,θ 1 ,None,[X_Group]],[Rz,1,θ 2 ,None,[Z_Group]],[H,2,None,None,[None]],[CNOT,[1,0],None,None,[Z_Group,X_Group]],[CNOT,[1,2],None,None,[Z_Group,X_Group]],[C Z,[0,1],None,None,[Z_Group,Z_Group]],[Measure,0,None,None,[None]],[Measure,1,None,None,[None]],[Measure,2,None,None,[None]]].

[0235] It can be seen that the CZ gate [CZ, [0, 1], None, None, [Z_Group, Z_Group]] acting on quantum bits 0 and 1 and the CX gate [CNOT, [1, 2], None, None, [Z_Group, X_Group] acting on quantum bits 1 and 2 have the same commutative feature Z_Group of quantum bit 1, so their order of action can be exchanged. The quantum circuit after exchanging these two quantum gates is shown in Figure 12(b), which is a compilable circuit.

[0236] According to the instruction list of the quantum circuit after the exchangeable quantum gate is marked, it can be converted into a directed acyclic graph representation based on the exchangeable feature, as shown in Figure 13(a). It can be seen that there is no directed edge between the CZ gate acting on quantum bits 0 and 1 (corresponding to node 8) and the CX gate acting on quantum bits 1 and 2 (corresponding to node 7), that is, there is no execution dependency. In addition, as shown in Figure 13(b), a directed edge from output node 9 to input node 2 can be added to the directed acyclic graph representation without introducing any ring structure.

[0237] Based on the directed acyclic graph with directed edges from the output node to the input node, the static quantum circuit of the input can be compiled into a dynamic quantum circuit using two quantum bits through circuit compilation. The compiled quantum circuit is as follows Fig.14 shown.

[0238] In addition, in order to verify the equivalence of the quantum circuit equivalently compiled by this embodiment and the quantum circuit equivalently compiled by the related technology, the quantum circuit after the initial quantum circuit (Figure 12 (a)) is exchanged (Figure 12 (b)) and the compiled quantum circuit (Figure 12 (c)) is exchanged. Fig.14 ) was simulated and the simulation results are shown in Fig.15 As shown, it can be seen that the operating results of these three quantum circuits are the same, that is, the three quantum circuits are equivalent.

[0239] In order to demonstrate the advantages of the equivalent compilation effect of this embodiment over related technologies, the equivalent compilation effects of different schemes on quantum circuits are compared through some numerical experiments of circuit compilation.

[0240] The number of quantum bits n can be fixed to 80, and the randomly generated quantum circuits can be equivalently compiled when the ratio of the number of quantum gates m and the number of quantum bits n in the quantum circuit is {2.5, 3, 3.5}. For each quantum circuit, quantum gates can be randomly selected from the set {H, X, T, S, Z, Rx, Ry, Rz, CX, CZ}, and the quantum bits they act on can be randomly sampled to construct the quantum circuit, which can be compiled using different quantum circuit compilation schemes.

[0241] For the ratio of the number of gates per qubit to the number of qubits, 100 different quantum circuit instances were tested. The compilability factor can be used to represent the effect of circuit compilation, which is specifically defined as: Among them, n is the width of the input static quantum circuit, and n' is the width of the output dynamic quantum circuit. It can be seen that the higher the r value, the better the circuit compilation effect.

[0242] Fig.16 and Fig.17The figures show the comparison of the compilability factors of the quantum circuit compilation scheme of this embodiment with those of the quantum circuit compilation schemes of related technologies 1 and 2 for random quantum circuits. The horizontal axes of the two figures are the compilability factors of related technologies 1 and 2 for random quantum circuits, respectively, and the vertical axes are the compilability factors of the quantum circuit compilation scheme of this embodiment for random quantum circuits.

[0243] Fig.16 and Fig.17 The black auxiliary line in represents y=x. It can be seen that for all random quantum circuits, the data points fall within the auxiliary line and the area within the line. It can be seen that the quantum circuit compilation scheme of this embodiment has a significantly better compilation effect on random quantum circuits than the compilation effects of related technologies 1 and 2 on random quantum circuits.

[0244] Second embodiment

[0245] like Fig.18 As shown, the present disclosure provides a quantum circuit processing device 1800, comprising:

[0246] A first acquisition module 1801 is used to acquire a first instruction list of a first quantum circuit, and to acquire a target dictionary, wherein the target dictionary indicates a relationship between an identifier of an exchangeable group, an identifier of a quantum operation, and a control type of a quantum bit, and two quantum operations belonging to the same exchangeable group are exchangeable if a preset condition is met, wherein the preset condition includes: the two quantum operations act on the same quantum bit, and the control types of the two quantum operations on the quantum bit are control types indicated by the target dictionary;

[0247] A second acquisition module 1802 is used to obtain a first identifier of a quantum operation corresponding to an operation instruction in the first instruction list and a first control type of each quantum bit acted upon by the quantum operation;

[0248] A determination module 1803 is used to determine, based on the target dictionary, the first identifier and the first control type, an exchangeable feature of the operation instruction on each quantum bit on which the operation instruction acts, where the exchangeable feature indicates the exchangeability of the operation instruction on the quantum bit, and when the exchangeable feature indicates that the operation instruction is exchangeable on the quantum bit, the exchangeable feature includes a second identifier of the exchangeable group to which the operation instruction belongs on the quantum bit;

[0249] An equivalent compiling module 1804 is used to perform equivalent compiling on the first quantum circuit based on the exchangeable feature and the first instruction list to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

[0250] Optionally, the target dictionary includes a first dictionary and a second dictionary, the first dictionary indicates a correspondence between an identifier of a first exchangeable group and an identifier of a quantum operation, the second dictionary indicates a correspondence between an identifier of a second exchangeable group and an identifier of a quantum operation, the first exchangeable group is an exchangeable group of quantum operations on controlled quantum bits when the control type is indicated, and the second exchangeable group is an exchangeable group of quantum operations on target quantum bits when the control type is indicated; the determining module 1803 is specifically used to:

[0251] When the first control type indicates a controlled quantum bit, determining, based on the first dictionary and the first identifier, a commutative feature of the operation instruction on the controlled quantum bit on which the operation instruction acts;

[0252] When the first control type indicates a target quantum bit, based on the second dictionary and the first identifier, the exchangeable characteristics of the operation instruction on the target quantum bit are determined.

[0253] Optionally, the determining module 1803 is specifically configured to:

[0254] In a case where the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations includes the first identifier, determining an identifier corresponding to the first identifier in the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations as a second identifier of the commutative group to which the operation instruction belongs on the quantum bit on which the operation instruction acts;

[0255] When the first identifier is not included in the dictionary indicating the correspondence between the identifier of the exchangeable group and the identifier of the quantum operation, the target information is determined as the exchangeable feature of the operation instruction on the quantum bit on which it is applied, and the target information indicates that the operation instruction is not exchangeable on the quantum bit on which it is applied.

[0256] Optionally, the equivalent compilation module 1804 includes:

[0257] A construction submodule is used to construct a first directed acyclic graph of the first quantum circuit based on the exchangeable feature and using the operation instructions in the first instruction list as nodes, wherein the action qubits in the first directed acyclic graph have an intersection, and there are no directed edges between the nodes corresponding to different operation instructions that are exchangeable on the qubits of the intersection;

[0258] The equivalent compilation submodule is used to perform equivalent compilation on the first quantum circuit based on the first directed acyclic graph to obtain a second instruction list of the second quantum circuit.

[0259] Optionally, the construction submodule includes:

[0260] A traversal unit, used for forward traversing the first instruction list according to the arrangement order of the operation instructions;

[0261] a construction unit, configured to take the currently traversed first operation instruction as a node, and for each first qubit acted upon by the first operation instruction, and based on the exchangeable feature of the operation instructions in the first list on the first qubit, construct a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction for each first qubit acted upon by the first operation instruction, when the first list corresponding to the first qubit is not an empty list; on the first qubit, the target operation instruction is not exchangeable with the first operation instruction;

[0262] An adding unit is used to add the first operation instruction to the end of the first list, and obtain the first directed acyclic graph when the traversal of the first instruction list is completed.

[0263] Optionally, the construction unit is specifically used for:

[0264] In a case where it is determined based on the exchangeable feature that the second operation instruction is not exchangeable on the first quantum bit, determining the second operation instruction as a target operation instruction, wherein the second operation instruction is an operation instruction at the end of the first list;

[0265] Add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

[0266] Optionally, the construction unit is specifically used for:

[0267] In a case where it is determined based on the exchangeable feature that the second operation instruction is exchangeable on the first qubit, comparing the exchangeable feature of the operation instruction in the first list on the first qubit with the exchangeable feature of the first operation instruction on the first qubit to obtain a comparison result;

[0268] Based on the comparison result, at least one target operation instruction of the previous group on the first qubit is obtained from the first list to obtain a first sublist, wherein in the same group, on the first qubit, different target operation instructions are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction;

[0269] Add each target operation instruction corresponding node in the first sublist to the directed edge of the first operation instruction corresponding node.

[0270] Optionally, the construction unit is specifically used for:

[0271] When the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first quantum bit is the same as the exchangeable characteristic of the first operation instruction on the first quantum bit, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions;

[0272] When the first target operation instruction is not exchangeable on the first qubit, obtaining the first sublist, wherein the first sublist includes only the first target operation instruction;

[0273] In the case where the first target operation instruction is exchangeable on the first quantum bit, other target operation instructions with the same first exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the first exchangeable characteristic is the exchangeable characteristic of the first target operation instruction on the first quantum bit.

[0274] Optionally, the construction unit is specifically used for:

[0275] If the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first qubit is different from the exchangeable characteristic of the first operation instruction on the first qubit, determining the second operation instruction as the target operation instruction;

[0276] Other target operation instructions having the same second exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the second exchangeable characteristic is an exchangeable characteristic of the second operation instruction on the first quantum bit.

[0277] The quantum circuit processing device 1800 provided in the present disclosure can implement each process implemented in the quantum circuit processing method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0278] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0279] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0280] Fig.19A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0281] like Fig.19 As shown, the device 1900 includes a computing unit 1901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1902 or a computer program loaded from a storage unit 1908 into a random access memory (RAM) 1903. In the RAM 1903, various programs and data required for the operation of the device 1900 can also be stored. The computing unit 1901, the ROM 1902, and the RAM 1903 are connected to each other via a bus 1904. An input / output (I / O) interface 1905 is also connected to the bus 1904.

[0282] A number of components in the device 1900 are connected to the I / O interface 1905, including: an input unit 1906, such as a keyboard, a mouse, etc.; an output unit 1907, such as various types of displays, speakers, etc.; a storage unit 1908, such as a disk, an optical disk, etc.; and a communication unit 1909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1909 allows the device 1900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0283] The computing unit 1901 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1901 performs the various methods and processes described above, such as the quantum circuit processing method. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1900 via the ROM 1902 and / or the communication unit 1909. When the computer program is loaded into the RAM 1903 and executed by the computing unit 1901, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 1901 may be configured to execute the quantum circuit processing method in any other appropriate manner (for example, by means of firmware).

[0284] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0285] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0286] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0287] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0288] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0289] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0290] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0291] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A quantum circuit processing method, comprising: Obtaining a first instruction list for a first quantum circuit, and obtaining a target dictionary, wherein the target dictionary indicates a relationship between an identifier of an exchangeable group, an identifier of a quantum operation, and a control type of a quantum bit, wherein two quantum operations belonging to the same exchangeable group are exchangeable if a preset condition is satisfied, wherein the preset condition includes: the two quantum operations act on the same quantum bit, and the control types of the two quantum operations on the quantum bit are control types indicated by the target dictionary; Obtain a first identifier of a quantum operation corresponding to an operation instruction in the first instruction list and a first control type of each quantum bit acted upon by the quantum operation; Determine, based on the target dictionary, the first identifier, and the first control type, an exchangeable feature of the operation instruction on each quantum bit on which the operation instruction acts, wherein the exchangeable feature indicates the exchangeability of the operation instruction on the quantum bit, and when the exchangeable feature indicates that the operation instruction is exchangeable on the quantum bit, the exchangeable feature includes a second identifier of the exchangeable group to which the operation instruction belongs on the quantum bit; Based on the exchangeable feature, taking the operation instructions in the first instruction list as nodes, constructing a first directed acyclic graph of the first quantum circuit, wherein the action qubits in the first directed acyclic graph have an intersection, and there are no directed edges between the nodes corresponding to different operation instructions that are exchangeable on the qubits of the intersection; Based on the first directed acyclic graph, the first quantum circuit is equivalently compiled to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

2. The method according to claim 1, wherein: The target dictionary includes a first dictionary and a second dictionary, the first dictionary indicates a correspondence between an identifier of a first exchangeable group and an identifier of a quantum operation, the second dictionary indicates a correspondence between an identifier of a second exchangeable group and an identifier of a quantum operation, the first exchangeable group is an exchangeable group of quantum operations on controlled quantum bits when the control type is indicated, and the second exchangeable group is an exchangeable group of quantum operations on target quantum bits when the control type is indicated; The step of determining, based on the target dictionary, the first identifier, and the first control type, a commutative feature of each quantum bit acted upon by the operation instruction comprises at least one of the following: When the first control type indicates a controlled quantum bit, determining, based on the first dictionary and the first identifier, a commutative feature of the operation instruction on the controlled quantum bit on which the operation instruction acts; When the first control type indicates a target quantum bit, based on the second dictionary and the first identifier, the exchangeable characteristics of the operation instruction on the target quantum bit are determined.

3. The method according to claim 2, wherein: Determining the commutative feature of the operation instruction on the quantum bit on which the operation instruction acts based on the dictionary indicating the correspondence between the identifier of the commutative group and the identifier of the quantum operation and the first identifier, comprises: In a case where the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations includes the first identifier, determining an identifier corresponding to the first identifier in the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations as a second identifier of the commutative group to which the operation instruction belongs on the quantum bit on which the operation instruction acts; When the first identifier is not included in the dictionary indicating the correspondence between the identifier of the exchangeable group and the identifier of the quantum operation, the target information is determined as the exchangeable feature of the operation instruction on the quantum bit on which it is applied, and the target information indicates that the operation instruction is not exchangeable on the quantum bit on which it is applied.

4. The method according to claim 1, wherein: The step of constructing a first directed acyclic graph of the first quantum circuit by using the operation instructions in the first instruction list as nodes based on the exchangeable feature includes: forwardly traverse the first instruction list according to the arrangement order of the operation instructions; Taking the first operation instruction currently traversed as a node, and for each first qubit acted upon by the first operation instruction, when the first list corresponding to the first qubit is not an empty list, based on the exchangeable feature of the operation instructions in the first list on the first qubit, constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction; on the first qubit, the target operation instruction and the first operation instruction are not exchangeable; The first operation instruction is added to the end of the first list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

5. The method according to claim 4, wherein: The step of constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction based on the exchangeable feature of the operation instruction in the first list on the first qubit includes: In a case where it is determined based on the exchangeable feature that the second operation instruction is not exchangeable on the first quantum bit, determining the second operation instruction as a target operation instruction, wherein the second operation instruction is an operation instruction at the end of the first list; Add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

6. The method according to claim 4, wherein: The step of constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction based on the exchangeable feature of the operation instruction in the first list on the first qubit includes: In a case where it is determined based on the exchangeable feature that the second operation instruction is exchangeable on the first qubit, comparing the exchangeable feature of the operation instruction in the first list on the first qubit with the exchangeable feature of the first operation instruction on the first qubit to obtain a comparison result; Based on the comparison result, at least one target operation instruction of the previous group on the first quantum bit is obtained from the first list to obtain a first sub-list, wherein in the same group, on the first quantum bit, different target operation instructions are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction; Add each target operation instruction corresponding node in the first sublist to the directed edge of the first operation instruction corresponding node.

7. The method according to claim 6, wherein: The step of acquiring, based on the comparison result, at least one target operation instruction of a previous group on the first quantum bit from the first list to obtain a first sub-list includes: When the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first quantum bit is the same as the exchangeable characteristic of the first operation instruction on the first quantum bit, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions; When the first target operation instruction is not exchangeable on the first qubit, obtaining the first sublist, wherein the first sublist includes only the first target operation instruction; In the case where the first target operation instruction is exchangeable on the first quantum bit, other target operation instructions with the same first exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the first exchangeable characteristic is the exchangeable characteristic of the first target operation instruction on the first quantum bit.

8. The method according to claim 6, wherein: The step of acquiring, based on the comparison result, at least one target operation instruction of a previous group on the first quantum bit from the first list to obtain a first sub-list includes: If the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first qubit is different from the exchangeable characteristic of the first operation instruction on the first qubit, determining the second operation instruction as the target operation instruction; Other target operation instructions having the same second exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the second exchangeable characteristic is an exchangeable characteristic of the second operation instruction on the first quantum bit.

9. A quantum circuit processing device, comprising: A first acquisition module is used to acquire a first instruction list of a first quantum circuit, and to acquire a target dictionary, wherein the target dictionary indicates a relationship between an identifier of an exchangeable group, an identifier of a quantum operation, and a control type of a quantum bit, and two quantum operations belonging to the same exchangeable group are exchangeable if a preset condition is met, wherein the preset condition includes: the two quantum operations act on the same quantum bit, and the control types of the two quantum operations on the quantum bit are control types indicated by the target dictionary; A second acquisition module is used to obtain a first identifier of a quantum operation corresponding to an operation instruction in the first instruction list and a first control type of each quantum bit acted upon by the quantum operation; a determination module, configured to determine, based on the target dictionary, the first identifier, and the first control type, an exchangeable feature of the operation instruction on each quantum bit on which the operation instruction acts, wherein the exchangeable feature indicates the exchangeability of the operation instruction on the quantum bit, and when the exchangeable feature indicates that the operation instruction is exchangeable on the quantum bit, the exchangeable feature includes a second identifier of an exchangeable group to which the operation instruction belongs on the quantum bit; an equivalent compilation module, configured to perform equivalent compilation on the first quantum circuit based on the exchangeable feature and the first instruction list to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit; The equivalent compilation module includes: A construction submodule is used to construct a first directed acyclic graph of the first quantum circuit based on the exchangeable feature and using the operation instructions in the first instruction list as nodes, wherein the action qubits in the first directed acyclic graph have an intersection, and there are no directed edges between the nodes corresponding to different operation instructions that are exchangeable on the qubits of the intersection; The equivalent compilation submodule is used to perform equivalent compilation on the first quantum circuit based on the first directed acyclic graph to obtain a second instruction list of the second quantum circuit.

10. The device according to claim 9, wherein: The target dictionary includes a first dictionary and a second dictionary, the first dictionary indicates a correspondence between an identifier of a first exchangeable group and an identifier of a quantum operation, the second dictionary indicates a correspondence between an identifier of a second exchangeable group and an identifier of a quantum operation, the first exchangeable group is an exchangeable group of quantum operations on controlled quantum bits when the control type is indicated, and the second exchangeable group is an exchangeable group of quantum operations on target quantum bits when the control type is indicated; the determining module is specifically used to: When the first control type indicates a controlled quantum bit, determining, based on the first dictionary and the first identifier, a commutative feature of the operation instruction on the controlled quantum bit on which the operation instruction acts; When the first control type indicates a target quantum bit, based on the second dictionary and the first identifier, the exchangeable characteristics of the operation instruction on the target quantum bit are determined.

11. The device according to claim 10, wherein: The determination module is specifically used for: In a case where the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations includes the first identifier, determining an identifier corresponding to the first identifier in the dictionary indicating the correspondence between identifiers of commutative groups and identifiers of quantum operations as a second identifier of the commutative group to which the operation instruction belongs on the quantum bit on which the operation instruction acts; When the first identifier is not included in the dictionary indicating the correspondence between the identifier of the exchangeable group and the identifier of the quantum operation, the target information is determined as the exchangeable feature of the operation instruction on the quantum bit on which it is applied, and the target information indicates that the operation instruction is not exchangeable on the quantum bit on which it is applied.

12. The device according to claim 9, wherein: The construction submodule includes: A traversal unit, used for forward traversing the first instruction list according to the arrangement order of the operation instructions; a construction unit, configured to take the currently traversed first operation instruction as a node, and for each first qubit acted upon by the first operation instruction, and based on the exchangeable feature of the operation instructions in the first list on the first qubit, construct a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction for each first qubit acted upon by the first operation instruction, when the first list corresponding to the first qubit is not an empty list; on the first qubit, the target operation instruction is not exchangeable with the first operation instruction; An adding unit is used to add the first operation instruction to the end of the first list, and obtain the first directed acyclic graph when the traversal of the first instruction list is completed.

13. The device according to claim 12, wherein: The building block is specifically used for: In a case where it is determined based on the exchangeable feature that the second operation instruction is not exchangeable on the first quantum bit, determining the second operation instruction as a target operation instruction, wherein the second operation instruction is an operation instruction at the end of the first list; Add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

14. The device according to claim 12, wherein: The building block is specifically used for: In a case where it is determined based on the exchangeable feature that the second operation instruction is exchangeable on the first qubit, comparing the exchangeable feature of the operation instruction in the first list on the first qubit with the exchangeable feature of the first operation instruction on the first qubit to obtain a comparison result; Based on the comparison result, at least one target operation instruction of the previous group on the first quantum bit is obtained from the first list to obtain a first sub-list, wherein in the same group, on the first quantum bit, different target operation instructions are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction; Add each target operation instruction corresponding node in the first sublist to the directed edge of the first operation instruction corresponding node.

15. The device according to claim 14, wherein: The building block is specifically used for: When the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first quantum bit is the same as the exchangeable characteristic of the first operation instruction on the first quantum bit, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions; When the first target operation instruction is not exchangeable on the first qubit, obtaining the first sublist, wherein the first sublist includes only the first target operation instruction; In the case where the first target operation instruction is exchangeable on the first quantum bit, other target operation instructions with the same first exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the first exchangeable characteristic is the exchangeable characteristic of the first target operation instruction on the first quantum bit.

16. The device according to claim 14, wherein: The building block is specifically used for: If the comparison result indicates that the exchangeable characteristic of the second operation instruction on the first qubit is different from the exchangeable characteristic of the first operation instruction on the first qubit, determining the second operation instruction as the target operation instruction; Other target operation instructions having the same second exchangeable characteristic on the first quantum bit are obtained to obtain the first sub-list, where the second exchangeable characteristic is an exchangeable characteristic of the second operation instruction on the first quantum bit.

17. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

18. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-8.

19. A computer program product, comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 8.

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