A laminated ceramic substrate structure and power module for improving ceramic substrate utilization

Abstract

The present invention provides a laminated ceramic substrate structure and a power module for improving the utilization rate of ceramic substrates, wherein the laminated ceramic substrate structure includes at least two layers of ceramic substrates arranged in sequence from bottom to top, each layer of ceramic substrates includes at least one ceramic substrate, any ceramic substrate in the upper layer of ceramic substrates is connected to at least one ceramic substrate in the adjacent lower layer of ceramic substrates; and each ceramic substrate is provided with at least one chip. The present invention adopts a laminated layout of ceramic substrates of different types or the same type, which can improve the packaging density of the module and reduce the cost under the premise of ensuring high reliability and low thermal resistance, and can also significantly reduce the area of ​​the bottom ceramic substrate by improving the utilization rate of the ceramic substrate, directly reducing the sintering area of ​​the ceramic substrate and the heat sink.

Description

Technical Field

[0001] The present invention relates to the technical field of power modules, and in particular to a laminated ceramic substrate structure and a power module for improving the utilization rate of a ceramic substrate. Background Art

[0002] The development of power semiconductors has promoted the iteration of power modules, and direct bonding aluminum (DBA) substrates, direct bonding copper (DBC) substrates and active metal brazing (AMB) substrates have provided solutions for the design and production of high-power power electronic modules. DBC has good electrical properties, and its manufacturing process and preparation are relatively simple, but its reliability is poor and its thermal resistance is high. With the development of the third-generation power semiconductors, it seems difficult for the DBC substrate to meet the high reliability requirements of SiC chips. The ceramic layers of the AMB substrate are Si with higher fracture toughness. 3 N 4 The ceramic layer of the DBA substrate is AlN with better thermal conductivity, which can have higher reliability and lower thermal resistance under the stress caused by temperature shock (-40℃-125℃), thereby increasing the life of the power module. At present, SiC chips are mainly mounted on single-layer AMB substrates. In order not to affect the flow function of the upper metal layer of the AMB substrate, the area of ​​the substrate needs to be increased. The packaging density of the power module will increase significantly, which will directly lead to an increase in cost and cause unnecessary waste. Therefore, the utilization rate of the substrate is significantly reduced. Although the AMB substrate has higher reliability, the manufacturing cost is about three times that of the DBC substrate, and cost reduction is also a long-term goal pursued by the semiconductor industry.

[0003] In addition, the continuous iteration of SiC has put forward further requirements for the packaging of power modules: with the development of SiC chips, the traditional reflow process is difficult to serve for a long time at the maximum operating junction temperature of 175°C, resulting in reduced reliability. However, the use of silver sintering process can greatly improve the reliability of the chip. The silver particles are necked under high temperature and pressure, have a higher melting point (about 900°C), and can serve at higher temperatures. In addition, the thermal resistance of the sintered silver layer is significantly lower than that of the solder layer, which can better dissipate heat. At present, the connection between the ceramic substrate and the heat sink still uses the traditional reflow process, but this traditional reflow process power has been difficult to meet the reliability requirements. The future development trend is to use large-area sintered silver. The technical difficulty of large-area sintering silver is that the sintering area is too large, which will lead to uneven local pressure, the difficulty of volatilization of organic components in the central area, resulting in organic residues and excessive voids. Therefore, improving the utilization rate of ceramic substrates and reducing the sintering area of ​​modules are technical problems that need to be solved urgently. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a laminated ceramic substrate structure for improving the utilization rate of ceramic substrates, including at least two layers of ceramic substrates arranged in sequence from bottom to top, each layer of ceramic substrates includes at least one ceramic substrate, and any ceramic substrate in the upper layer of ceramic substrates is connected to at least one ceramic substrate in the adjacent lower layer of ceramic substrates; each ceramic substrate is provided with at least one chip.

[0005] The present invention does not limit the number of ceramic substrates included in each layer of ceramic substrate, which may be one, two or more. If the lower ceramic substrate includes one ceramic substrate, at least one upper ceramic substrate is disposed on the lower ceramic substrate, and each upper ceramic substrate is disposed on the lower ceramic substrate; if the lower ceramic substrate includes two or more ceramic substrates, two adjacent ceramic substrates in the lower ceramic substrate are connected through at least one ceramic substrate in the upper ceramic substrate.

[0006] The present invention does not limit the type of each ceramic substrate, which may be an AMB substrate, a DBA substrate or a DBC substrate, and each ceramic substrate is provided with a chip. The present invention does not limit the type of chip on each ceramic substrate, that is, each ceramic substrate may be provided with a chip with high heat dissipation requirements such as a SiC chip, or may be provided with a chip with low heat dissipation requirements such as a gate resistor, a thermistor, an IGBT and a diode.

[0007] AMB and DBA substrates are high thermal conductivity ceramic substrates, and DBC substrate is a low thermal conductivity ceramic substrate.

[0008] For chips with high heat dissipation requirements, such as SiC chips, DBC substrates are difficult to meet the heat dissipation requirements of SiC chips. 3 N 4 Materials, DBA substrate uses AlN material with higher thermal conductivity, and both AMB substrate and DBA substrate adopt active metal brazing, and the heat dissipation and thermal conductivity are higher than DBC substrate. Under the action of SiC high-frequency switching, a high junction temperature difference will be generated, which puts high requirements on heat dissipation and reliability, so SiC chips are mounted on AMB or DBA substrates.

[0009] For chips with low heat dissipation requirements, such as gate resistors (Positive temperature coefficient, PTC), thermistors (Gate resistance, GR), IGBTs, and diodes, since GR, PTC, IGBTs, diodes and other chips generate less heat during operation and do not require high heat dissipation performance and reliability, if GR, PTC, IGBTs, diodes and the like are mounted on AMB substrates and DBA substrates, unnecessary waste will result. Therefore, chips with low heat dissipation requirements, such as GR, PTC, IGBTs, diodes and the like, are placed on DBC substrates.

[0010] Preferably, the type of any ceramic substrate is determined according to the type of chip thereon. If the chip is a chip with high requirements for heat dissipation, the ceramic substrate on which the chip is located is an AMB substrate or a DBA substrate.

[0011] If the chip has low requirements on heat dissipation, the ceramic substrate on which the chip is located is a DBC substrate.

[0012] Preferably, the chip with high requirements for heat dissipation is a SiC chip;

[0013] The chip with low heat dissipation requirement is a gate resistor, a thermistor, an IGBT or a diode.

[0014] Preferably, all or part of the upper ceramic substrate is located on the lower ceramic substrate.

[0015] Preferably, the lower metal layer of the upper ceramic substrate is entirely or partially located on the upper metal layer of the lower ceramic substrate.

[0016] Preferably, the total area of ​​the upper ceramic substrates is smaller than the total area of ​​the lower ceramic substrates.

[0017] Preferably, the upper ceramic substrate and the lower ceramic substrate are stacked by diffusion welding, brazing or sintering.

[0018] Preferably, if a SiC chip is selected, the ceramic substrate connected to the heat sink is an AMB substrate or / and a DBA substrate.

[0019] Preferably, the laminated ceramic substrate structure comprises two layers of ceramic substrates arranged sequentially from bottom to top, the lower ceramic substrate comprises an AMB substrate or a DBA substrate, and at least one SiC chip is arranged on the AMB substrate or the DBA substrate;

[0020] The upper ceramic substrate includes at least one DBC substrate, the DBC is arranged on the AMB substrate or the DBA substrate, and at least one of a gate resistor, a thermistor, an IGBT or a diode is arranged on the DBC substrate.

[0021] Preferably, the laminated ceramic substrate structure comprises three layers of ceramic substrates arranged sequentially from bottom to top, the bottom ceramic substrate comprises an AMB substrate or a DBA substrate, and at least one SiC chip is arranged on the AMB substrate or the DBA substrate;

[0022] The intermediate ceramic substrate includes at least one intermediate DBC substrate, which is disposed on the AMB substrate or the DBA substrate, and is provided with at least one of a gate resistor, a thermistor, an IGBT or a diode;

[0023] The uppermost ceramic substrate includes at least one uppermost DBC substrate, which is arranged on the middle DBC substrate. At least one of a gate resistor, a thermistor, an IGBT or a diode is arranged on the uppermost DBC substrate.

[0024] Preferably, the laminated ceramic substrate structure comprises two layers of ceramic substrates arranged in sequence from bottom to top, the lower ceramic substrate comprises two ceramic substrates arranged at intervals, and the two ceramic substrates are two AMB substrates, two DBA substrates, two DBC substrates, one AMB substrate and one DBA, one AMB substrate and one DBC substrate, one DBC substrate and one DBA substrate;

[0025] The upper ceramic substrate includes at least one DBC substrate, and the at least one DBC substrate is connected to the two ceramic substrates in the lower layer.

[0026] The present invention also provides a power module for improving the utilization rate of a ceramic substrate, comprising the above-mentioned laminated ceramic substrate structure.

[0027] Preferably, the bottom ceramic substrate of the laminated ceramic substrate structure is arranged on the heat sink by sintering or brazing.

[0028] Compared with the prior art, the present invention has the following technical effects:

[0029] The present invention adopts a stacking layout of different or same types of ceramic substrates, which can improve the packaging density of the module and reduce the cost while ensuring high reliability and low thermal resistance. It can also significantly reduce the area of ​​the bottom ceramic substrate by improving the utilization rate of the ceramic substrate, directly reduce the sintering area of ​​the ceramic substrate and the heat sink, and provide a new optimization design scheme for future large-area sintering processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figures 1 to 6 Schematic diagram of the structure of the multilayer ceramic substrate with various structures provided in Example 1 of the present invention;

[0032] Figure 7 is a structural schematic diagram of a multilayer ceramic substrate structure provided by Example 2 of the present invention;

[0033] Figure 8 is a side view of a power module provided in Embodiment 3 of the present invention;

[0034] Fig. 9 It is a three-dimensional diagram of a power module provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0037] Example 1

[0038] Please refer to Figures 1 to 6 The present embodiment provides a laminated ceramic substrate structure for improving the utilization rate of ceramic substrates, including at least two layers of ceramic substrates arranged in sequence from bottom to top, the two adjacent layers of ceramic substrates including a lower ceramic substrate 1 and an upper ceramic substrate 2, and at least one upper ceramic substrate 2 is arranged on the lower ceramic substrate 1. The present embodiment does not limit the number of lower ceramic substrates 1, which may be one, or two or more. If there are two or more lower ceramic substrates 1, the adjacent lower ceramic substrates are connected by at least one upper ceramic substrate.

[0039] This embodiment does not impose any specific restrictions on the types of the lower ceramic substrate and the upper ceramic substrate 2. For example, the upper ceramic substrate 2 can be a DBC substrate, a DBA substrate or an AMB substrate, and the lower ceramic substrate 1 can also be a DBC substrate, a DBA substrate or an AMB substrate. That is, the types of the adjacent upper and lower ceramic substrates can be the same or different. The specific type of substrate depends on the layout of the chip. For example, it can be an AMB substrate superimposed on a DBC substrate or / and a DBA substrate, or a DBC substrate superimposed on an AMB substrate or / and a DBA substrate, or a DBA substrate superimposed on an AMB substrate or / and a DBC substrate.

[0040] The AMB substrate includes an upper copper layer, an intermediate ceramic layer and a lower copper layer. The upper and lower surfaces of the intermediate ceramic layer are connected to the upper copper layer and the lower copper layer respectively using active metal solder as the connecting intermediate layer to form a copper-solder-ceramic-solder-copper structure. The intermediate ceramic layer of the AMB substrate is Si 3 N 4 .

[0041] The DBA substrate is a substrate formed by bonding aluminum and a ceramic layer, which includes an upper aluminum layer, a middle ceramic layer and a lower aluminum layer, and is an aluminum-ceramic-aluminum structure. The middle ceramic layer of the DBA substrate is AlN.

[0042] The intermediate insulating material of the DBC substrate is Al 2 O 3 Or AlN, sinter the copper foil directly to Al at high temperature 2 O 3 Or AlN ceramic surface to make a composite substrate, which is a copper-ceramic-copper structure.

[0043] If the DBC substrate or / and the DBA substrate are stacked on the AMB substrate, the lower copper layer of the DBC substrate or / and the lower aluminum layer of the DBA substrate are connected to the upper copper layer of the AMB substrate by diffusion welding, brazing or sintering.

[0044] If the AMB substrate or / and the DBA substrate are stacked on the DBC substrate, the lower copper layer of the AMB substrate or / and the lower aluminum layer of the DBA substrate are connected to the upper copper layer of the DBC substrate by diffusion welding, brazing or sintering.

[0045] If the AMB substrate or / and the DBC substrate are stacked on the DBA substrate, the lower copper layer of the AMB substrate or / and the lower copper layer of the DBC substrate are connected to the upper aluminum layer of the DBA substrate by diffusion welding, brazing or sintering.

[0046] AMB and DBA substrates are high thermal conductivity ceramic substrates, and DBC substrates are low thermal conductivity ceramic substrates. In this embodiment, for chips with high heat dissipation requirements, such as SiC chips, it is difficult for DBC substrates to meet the heat dissipation requirements of SiC chips. 3 N 4 Materials, DBA substrate uses AlN material with higher thermal conductivity, and both AMB substrate and DBA substrate adopt active metal brazing, and the heat dissipation and thermal conductivity are higher than DBC substrate. Under the action of SiC high-frequency switching, a high junction temperature difference will be generated, which puts high requirements on heat dissipation and reliability, so SiC chips are mounted on AMB or DBA substrates.

[0047] For chips with low heat dissipation requirements, such as gate resistors (Positive temperature coefficient, PTC), thermistors (Gate resistance, GR), IGBTs, and diodes, since GR, PTC, IGBTs, diodes and other chips generate less heat during operation and do not require high heat dissipation performance and reliability, if GR, PTC, IGBTs, diodes and the like are mounted on AMB substrates and DBA substrates, unnecessary waste will result. Therefore, chips with low heat dissipation requirements, such as GR, PTC, IGBTs, diodes and the like, are placed on DBC substrates.

[0048] The existing SiC power module packaging is mainly concentrated on the single-layer AMB substrate and DBA substrate. Taking the AMB substrate as an example, considering that chips such as GR and PTC that have low requirements for heat dissipation also need to occupy the space of the AMB substrate. For example, 8 SiC chips usually require 8 GRs and 1-2 PTCs. In this case, if all are mounted on the AMB substrate, the AMB substrate with only SIC chips needs to be expanded by 1-2 times. The present invention mounts GR and PTC on the DBC substrate, and then places the DBC substrate on the upper copper layer of the AMB substrate. The three-dimensional space used is the two-dimensional space, which reduces the area by 1-2 times, and the lower copper layer of the DBC substrate does not affect the flow of the SiC chip. Therefore, the layout of the laminated ceramic substrate structure adopted by the present invention can improve the packaging density of the module and reduce costs under the premise of ensuring high reliability and low thermal resistance, and can also significantly reduce the area of ​​the ceramic substrate by improving the utilization rate of the ceramic substrate, directly reducing the sintering area of ​​the ceramic substrate and the radiator.

[0049] The laminated ceramic substrate structure provided in the present application is suitable for all photovoltaic energy storage modules or vehicle-mounted electric drive module applications.

[0050] In this embodiment, there is no limitation on how many layers of ceramic substrates are arranged in sequence from bottom to top in the laminated ceramic substrate structure, and the number of layers can be two or more. Figures 1 to 4 As shown, the structure of the laminated ceramic substrate is a two-layer ceramic substrate, which are an upper ceramic substrate 2 and a lower ceramic substrate 1. In this embodiment, the lower ceramic substrate is taken as one piece. The upper ceramic substrate 2 is located above the lower ceramic substrate 1, and the lower metal layer of the upper ceramic substrate 2 is connected to the upper metal layer of the lower ceramic substrate. The upper ceramic substrate 2 can be located on the left, middle or right side of the lower ceramic substrate 1, that is, this embodiment does not impose specific restrictions on the position of the upper ceramic substrate 2 on the lower ceramic substrate 1. The upper ceramic substrate 2 located on the lower ceramic substrate 1 can be one piece, or two or more pieces, and this embodiment does not impose any restrictions on this. Figures 1 to 4 What is shown is that an upper ceramic substrate 2 is arranged on a lower ceramic substrate 1. Figure 5 It is shown that two upper ceramic substrates 2 are arranged on a lower ceramic substrate 1. In this embodiment, the lower ceramic substrate 1 is an AMB substrate or a DBA substrate, and the upper ceramic substrate 2 is a DBC substrate.

[0051] like Figure 6 As shown, the laminated ceramic substrate structure is a three-layer ceramic substrate, which includes from bottom to top a lower ceramic substrate 1, an intermediate ceramic substrate 3 and an upper ceramic substrate 2, the lower metal layer of the upper ceramic substrate 2 is connected to the upper metal layer of the intermediate ceramic substrate 3, and the lower metal layer of the intermediate ceramic substrate 3 is connected to the upper metal layer of the lower ceramic substrate 1. In this embodiment, the lower ceramic substrate 1 is an AMB substrate or a DBA substrate, and the upper ceramic substrate 2 and the intermediate ceramic substrate 3 are both DBC substrates.

[0052] Regardless of how many layers of ceramic substrates the laminated ceramic substrate structure has, for two adjacent ceramic substrates, the lower metal layer of the upper ceramic substrate must all be located on the upper metal layer of the lower ceramic substrate, but the total area of ​​all upper ceramic substrates must be smaller than the area of ​​the lower ceramic substrate, and the total projected area of ​​the upper ceramic substrate accounts for 1% to 100% of the total area of ​​the lower ceramic substrate. The reason is that there is a chip on the lower ceramic substrate. If the area of ​​the upper ceramic substrate is larger than the area of ​​the lower ceramic substrate, the chip may be crushed. If there is no etching on the upper metal layer of the lower ceramic substrate, the back of the upper ceramic substrate can be directly connected to the upper metal layer of the lower ceramic substrate without etching, and the flow function of the lower ceramic substrate will not be affected; if there is etching on the upper metal layer of the lower ceramic substrate, the lower metal layer of the upper ceramic substrate also needs to be etched at the corresponding position to avoid short circuits. Generally, it is not recommended to vertically stack the upper ceramic substrate on the chip of the lower ceramic substrate to avoid loss of function and damage to the chip.

[0053] In this embodiment, the bottom ceramic substrate of the preferred laminated ceramic substrate structure is an AMB substrate or a DBA substrate, and the SiC chip with high heat dissipation requirements is arranged on the AMB substrate or the DBA substrate. The upper ceramic substrate is a DBC substrate, and the chips with low heat dissipation requirements such as GR, PTC, IGBT, and diode are arranged on the DBC substrate.

[0054] Example 2

[0055] The present embodiment provides a laminated ceramic substrate structure for improving the utilization rate of a ceramic substrate, comprising at least two layers of ceramic substrates arranged in sequence from bottom to top, wherein the two adjacent layers of ceramic substrates include a lower ceramic substrate 1 and an upper ceramic substrate 2. In the present embodiment, please refer to Figure 7 The lower ceramic substrates 1 have two pieces, and the two lower ceramic substrates 1 are connected through an upper ceramic substrate 2, that is, the left and right sides of the lower metal layer of the upper ceramic substrate 2 are respectively connected to the upper metal layers of the left and right lower ceramic substrates 1. Therefore, part of an upper ceramic substrate 2 is located on a lower ceramic substrate 1, that is, part of the lower metal layer of an upper ceramic substrate 2 is located on the upper metal layer of a lower ceramic substrate 1.

[0056] A chip is arranged on the upper metal layer of the upper ceramic substrate 2, and the chip is shared by the two lower ceramic substrates 1. Other chips or ceramic substrates can also be arranged in other vacant places on the upper metal layer of the two lower ceramic substrates 1, and this embodiment does not make any specific restrictions on this, and it can be set according to actual use requirements.

[0057] The two lower ceramic substrates 1 of the lower layer can be ceramic substrates of the same type, such as two AMB substrates, two DBA substrates or two DBC substrates. The two lower ceramic substrates 1 of the lower layer can also be ceramic substrates of different types, such as a combination of any two substrates among an AMB substrate, a DBA substrate and a DBC substrate. The two lower ceramic substrates 1 arranged at intervals in the lower layer can be used in photovoltaic energy storage modules, because the circuit topology is involved, such as DNPC inverter circuits. For example: As in this design scheme, in the current photovoltaic energy storage module, the two lower ceramic substrates 1 of the bottom layer carry IGBT chips, and it is recommended to use DBC ceramic substrates; the second layer is provided with fast recovery diodes or PTCs, which are shared by the two IGBT chips at the bottom layer, and it is recommended to use DBC substrates. If SiC is also used in photovoltaics in future development, the ceramic substrate needs to be changed to an AMB substrate (based on the chip); if SiC and IGBT are mixed, the bottom ceramic substrate will have a "heterogeneous" situation.

[0058] Example 3

[0059] This embodiment provides a power module that improves the utilization rate of a ceramic substrate, including the multilayer ceramic substrate structure and power chips described in Embodiments 1 and 2. The power chips include chips with high heat dissipation requirements and chips with low heat dissipation requirements. The chips with high heat dissipation requirements are mounted on an AMB substrate and a DBA substrate, and the chips with low heat dissipation requirements are mounted on a DBC substrate.

[0060] For example, the chip with high heat dissipation requirement is SiC chip, and the chip with low heat dissipation requirement is GR and PTC.

[0061] Please refer to Figure 8 and Fig. 9 The structure of the laminated ceramic substrate includes an AMB substrate 11 at the bottom layer and a DBC substrate 12 at the upper layer. The lower copper layer of the DBC substrate 12 is connected to the upper copper layer of the AMB substrate 11. A plurality of GR4 and PTC5 are also provided on the upper copper layer of the DBC substrate 12. The GR4 and PTC5 are mounted on the upper copper layer of the DBC substrate 12 through a chip connection layer. A SiC chip 6 is also provided on the upper copper layer of the AMB substrate 11. The SiC chip 6 is mounted on the upper copper layer of the AMB substrate 11 through a chip connection layer.

[0062] The bottom ceramic substrate 11 of the laminated ceramic substrate structure is disposed on the heat sink 7 by sintering. The heat sink may be Pin-Fin or Cu-Base.

[0063] This embodiment can significantly reduce the area of ​​the AMB substrate 11 by improving the utilization rate of the ceramic substrate, which directly leads to a reduction in the sintering area.

[0064] The power module provided in this embodiment can be single-sided water-cooled or double-sided water-cooled. Since both the AMB substrate and the DBA substrate are high thermal conductivity ceramic substrates, the ceramic substrate generally connected to the radiator is the AMB substrate or / and the DBA substrate (of course, the DBC substrate can also be connected to the radiator, but the high thermal conductivity ceramic substrate is preferred). Therefore, for double-sided water-cooled heat dissipation, the first and third ceramic substrates can both be AMB substrates or / and DBA substrates, and the middle layer can be a DBC substrate.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A laminated ceramic substrate structure for improving the utilization rate of a ceramic substrate, characterized in that: It comprises at least two layers of ceramic substrates arranged in sequence from bottom to top, each layer of ceramic substrates comprises at least one ceramic substrate, any ceramic substrate in the upper layer of ceramic substrates is connected to at least one ceramic substrate in the adjacent lower layer of ceramic substrates; each ceramic substrate is provided with at least one chip; The type of any ceramic substrate is determined according to the type of chip thereon. If the chip has high requirements for heat dissipation, and the chip with high requirements for heat dissipation is a SiC chip, then the ceramic substrate where the chip is located is an AMB substrate or a DBA substrate, and the ceramic substrate where the chip with low requirements for heat dissipation required by the SiC chip is located is a DBC substrate, and the DBC substrate is located on the AMB substrate or the DBA substrate where the SiC chip is located.

2. The multilayer ceramic substrate structure according to claim 1, characterized in that: If the chip has low requirements on heat dissipation, the ceramic substrate on which the chip is located is a DBC substrate.

3. The multilayer ceramic substrate structure according to claim 2, characterized in that: The chip with low heat dissipation requirement is a gate resistor, a thermistor, an IGBT or a diode.

4. The multilayer ceramic substrate structure according to claim 1, characterized in that: The entirety or a portion of the upper ceramic substrate is located on the lower ceramic substrate.

5. The multilayer ceramic substrate structure according to claim 4, characterized in that: The lower metal layer of the upper ceramic substrate is entirely located on the upper metal layer of the lower ceramic substrate.

6. The multilayer ceramic substrate structure according to claim 1, characterized in that: The total area of ​​the upper ceramic substrates is smaller than the total area of ​​the lower ceramic substrates.

7. The multilayer ceramic substrate structure according to claim 1, characterized in that: The upper ceramic substrate and the lower ceramic substrate are stacked by diffusion welding, brazing or sintering.

8. The multilayer ceramic substrate structure according to claim 1, characterized in that: The ceramic substrate connected to the heat sink is an AMB substrate or / and a DBA substrate.

9. The multilayer ceramic substrate structure according to claim 1, characterized in that: It comprises two layers of ceramic substrates arranged sequentially from bottom to top, the lower ceramic substrate comprises an AMB substrate or a DBA substrate, and at least one SiC chip is arranged on the AMB substrate or the DBA substrate; The upper ceramic substrate includes at least one DBC substrate, the DBC is arranged on the AMB substrate or the DBA substrate, and at least one of a gate resistor, a thermistor, an IGBT or a diode is arranged on the DBC substrate.

10. The multilayer ceramic substrate structure according to claim 1, characterized in that: It comprises three layers of ceramic substrates arranged in sequence from bottom to top, the bottom ceramic substrate comprises an AMB substrate or a DBA substrate, and at least one SiC chip is arranged on the AMB substrate or the DBA substrate; The intermediate ceramic substrate includes at least one intermediate DBC substrate, which is disposed on the AMB substrate or the DBA substrate, and is provided with at least one of a gate resistor, a thermistor, an IGBT or a diode; The uppermost ceramic substrate includes at least one uppermost DBC substrate, which is arranged on the middle DBC substrate. At least one of a gate resistor, a thermistor, an IGBT or a diode is arranged on the uppermost DBC substrate.

11. The multilayer ceramic substrate structure according to claim 1, characterized in that: It includes two layers of ceramic substrates arranged in sequence from bottom to top, the lower ceramic substrate includes two ceramic substrates arranged at intervals, and the two ceramic substrates are two AMB substrates, two DBA substrates, two DBC substrates, one AMB substrate and one DBA, one AMB substrate and one DBC substrate, and one DBC substrate and one DBA substrate; The upper ceramic substrate includes at least one DBC substrate, and the at least one DBC substrate is connected to the two ceramic substrates in the lower layer.

12. A power module for improving the utilization rate of a ceramic substrate, characterized in that: The invention comprises a multilayer ceramic substrate structure as claimed in any one of claims 1 to 9.

13. The power module according to claim 12, characterized in that: The bottom ceramic substrate of the laminated ceramic substrate structure is arranged on the heat sink by sintering or brazing.

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