A junction terminal structure and preparation method thereof, and semiconductor device

Abstract

The present invention relates to a junction terminal structure and a preparation method thereof, and a semiconductor device, and belongs to the field of semiconductor technology. The junction terminal structure includes: a substrate, an epitaxial layer, a first oxide layer, and a source metal; the epitaxial layer is arranged on one side of the substrate, and includes a P+ region and a JTE region, the P+ region is arranged on the side of the epitaxial layer away from the substrate, the JTE region is arranged on the periphery of the cell region on the side of the epitaxial layer away from the substrate, and contacts with the P+ region, and its thickness gradually increases or decreases from the side close to the cell region to the side away from the cell region; the first oxide layer is arranged on the surface of the epitaxial layer away from the substrate; the source metal is arranged on the surface of the epitaxial layer away from the substrate, and its bottom contacts with the P+ region. By designing a JTE region with a gradually increasing or decreasing thickness on the periphery of the cell region, not only can the breakdown voltage of the device be increased, and the withstand voltage performance of the device be improved, but also as the thickness of the JTE region gradually decreases, the device finally reaches an ideal breakdown position.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a junction terminal structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] The junction termination structure of a semiconductor refers to a structure in a semiconductor power device that is arranged outside the device cell region, which is used to increase the device's withstand voltage to an ideal value and break down in the terminal region, thereby protecting the device and improving its performance.

[0003] The current junction terminal structure uses a single-injection P ring to withstand voltage, that is, a P ring is formed by ion implantation around the device cell area to protect the device. However, in order to ensure that the device can work normally, the thickness of the P ring is usually relatively small, which leads to a relatively concentrated distribution of resistance and electric field on the P ring, and a higher electric field is generated on the P ring, which leads to premature breakdown and cannot effectively improve the withstand voltage value of the device. In order to further improve the withstand voltage value of the device, the existing technology uses field limiting ring technology to design multiple P rings around the cell area, that is, a P ring is formed by ion implantation around the cell area, and a P ring is formed by ion implantation around the P ring, so as to improve the withstand voltage value of the device through multiple P rings around the device cell area. However, forming multiple P rings around the device cell area will increase the chip area and increase the device cost.

[0004] In summary, the junction termination structure in the prior art cannot effectively improve the voltage resistance performance of the device while reducing the chip area and lowering the device cost. Summary of the invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the problem that the junction terminal structure in the prior art cannot effectively improve the device's voltage resistance performance, reduce the chip area and reduce the device cost.

[0006] In order to solve the above technical problems, the present invention provides a junction terminal structure, comprising:

[0007] substrate;

[0008] The epitaxial layer is arranged on one side of the substrate and comprises:

[0009] A P+ region, arranged in the epitaxial layer at a side away from the substrate;

[0010] A JTE region is arranged in the epitaxial layer at the periphery of the cell region on a side away from the substrate, in contact with the P+ region, and its thickness gradually increases or decreases from a side close to the cell region to a side away from the cell region;

[0011] A first oxide layer is disposed on a surface of the epitaxial layer away from the substrate;

[0012] The source metal is arranged on the surface of the epitaxial layer away from the substrate, and the bottom of the source metal is in contact with the P+ region.

[0013] In one embodiment of the present invention, it also includes:

[0014] A plurality of first grooves are arranged on a side of the JTE region away from the substrate, and are spaced from a side of the JTE region close to the cell region to a side away from the cell region, with first columns between adjacent first grooves;

[0015] A second oxide layer is disposed on the bottom wall and two side walls of the first trench;

[0016] A first polysilicon layer is disposed on the second oxide layer and fills the first trench.

[0017] In one embodiment of the present invention, it also includes:

[0018] A third oxide layer is disposed on the surface of the first pillar, and a second groove is formed between the third oxide layers on two adjacent first pillars;

[0019] The second polysilicon layer is disposed on the surface of the first polysilicon layer to fill the second trench and extends to the surface of the third oxide layer.

[0020] In one embodiment of the present invention, the substrate is an N-type doped silicon carbide substrate, and the epitaxial layer is an N-type doped silicon carbide epitaxial layer.

[0021] The present invention also provides a method for preparing a junction terminal structure, comprising:

[0022] Providing a substrate, and growing an epitaxial layer on one side of the substrate;

[0023] Injecting P+ ions into the epitaxial layer at a side away from the substrate to form a P+ region, and injecting P- ions into the epitaxial layer at a side away from the substrate at the periphery of the cell region to form a JTE region in contact with the P+ region, the thickness of which gradually increases or decreases from a side close to the cell region to a side away from the cell region;

[0024] A first oxide layer is grown by thermal oxidation on a surface of the epitaxial layer away from the substrate, the first oxide layer is etched and a source metal is deposited, and the bottom of the source metal contacts the top of the P+ region.

[0025] In one embodiment of the present invention, before thermally oxidizing the surface of the epitaxial layer away from the substrate to grow the first oxide layer, the method further includes:

[0026] Etching the JTE region by a wet etching process to form a plurality of first grooves along the JTE region from a side close to the cell region to a side away from the cell region, and forming first columns between adjacent first grooves;

[0027] A second oxide layer is grown on the bottom wall and both side walls of the first trench by thermal oxidation, and a first polysilicon layer is deposited on the surface of the second oxide layer. The upper surface of the first polysilicon layer is flush with the upper surface of the first column.

[0028] In one embodiment of the present invention, after depositing the first polysilicon layer on the surface of the second oxide layer, the method further comprises:

[0029] Growing a third oxide layer on the surface of the first pillar by thermal oxidation, and forming a second groove between the third oxide layers on the surfaces of two adjacent first pillars;

[0030] A second polysilicon layer is deposited in the second trench by chemical vapor deposition, and the second polysilicon layer extends to the surface of the third oxide layer.

[0031] In one embodiment of the present invention, thermally oxidizing and growing a first oxide layer on a surface of the epitaxial layer away from the substrate, etching the first oxide layer and depositing a source metal, wherein the bottom of the source metal contacts the top of the P+ region, comprises:

[0032] growing a first oxide layer on the surface of the third oxide layer and the second polysilicon layer by thermal oxidation;

[0033] The first oxide layer above the P+ region is etched and a source metal is deposited, wherein the bottom of the source metal contacts the top of the P+ region.

[0034] In one embodiment of the present invention, P+ ions are injected into the epitaxial layer at a side away from the substrate to form a P+ region, and P- ions are injected into the epitaxial layer at a side away from the substrate at the periphery of the cell region to form a JTE region in contact with the P+ region and whose thickness gradually increases or decreases from a side close to the cell region to a side away from the cell region, comprising:

[0035] Thermally oxidizing and growing a fourth oxide layer on a surface of the epitaxial layer away from the substrate;

[0036] forming a first photoresist layer on a surface of the fourth oxide layer away from the epitaxial layer, and exposing and developing the first photoresist layer using a mask;

[0037] Injecting P+ ions into the epitaxial layer through the fourth oxide layer below the exposure and development area to form a P+ region in the epitaxial layer away from the substrate;

[0038] removing the first photoresist layer, forming a second photoresist layer on the surface of the fourth oxide layer away from the epitaxial layer, and exposing and developing the second photoresist layer located at the periphery of the cell region using a mask;

[0039] Injecting P- ions into the epitaxial layer through the fourth oxide layer below the exposure and development area, forming a JTE region in contact with the P+ region at the periphery of the cell region away from the substrate in the epitaxial layer, the JTE region gradually increasing or decreasing in thickness from the side close to the cell region to the side away from the cell region;

[0040] The second photoresist layer and the fourth oxide layer are removed.

[0041] The present invention also provides a semiconductor device, which comprises the above-mentioned junction terminal structure.

[0042] The junction terminal structure provided by the present invention forms a JTE region with a thickness gradually increasing or decreasing from the side close to the cell region to the side far from the cell region at the periphery of the cell region, so that the electric field in the device gradually decreases as the length of the JTE region increases, and as the thickness of the JTE region gradually decreases, the electric field gradually tends to the surface of the device, and finally reaches the position where breakdown is required, so that the device obtains an ideal breakdown voltage. The junction terminal structure provided by the present application can not only improve the breakdown voltage of the device and improve the withstand voltage performance of the device by only designing a JTE region with a thickness gradually increasing or decreasing at the periphery of the cell region, but also as the thickness of the JTE region gradually decreases, the device can finally reach an ideal breakdown position. Compared with the prior art of forming multiple P rings spaced a certain distance apart at the periphery of the cell region to improve the withstand voltage performance of the device, the present application can not only improve the withstand voltage performance of the device, so that the device obtains an ideal breakdown voltage, but also save chip area and reduce system cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein

[0044] Figure 1 A junction terminal structure provided for this application;

[0045] Figure 2 The second junction terminal structure provided for this application;

[0046] Figure 3 The third junction terminal structure provided for this application;

[0047] Figure 4 A schematic diagram of an epitaxial wafer structure provided in this application;

[0048] Figure 5 For Figure 4 A schematic diagram of a structure in which a JTE region is formed on the structure shown; wherein, Figure 5 (a) in Figure 4 Schematic diagram of the structure of forming an oxide layer on the structure shown, Figure 5 (b) in Figure 5 A schematic diagram of a structure in which a P+ region is formed on the structure shown in (a). Figure 5 (c) in Figure 5 Schematic diagram of the structure in which the JTE region is formed on the structure shown in (b);

[0049] Figure 6 For Figure 5 A schematic diagram of a structure in which a first polysilicon layer is formed on the structure shown; wherein, Figure 6 (a) in Figure 5 A schematic diagram of a structure in which a first groove is formed on the structure shown in FIG. Figure 6 (b) in Figure 6 A schematic diagram of a structure in which a first polysilicon layer is formed on the structure shown in (a);

[0050] Figure 7 For Figure 6 A schematic diagram of a junction terminal structure formed on the structure shown; wherein, Figure 7 (a) in Figure 6 A schematic diagram of a structure in which a second groove is formed on the structure shown in FIG. Figure 7 (b) in Figure 7 A schematic diagram of a structure in which a second polysilicon layer is formed on the structure shown in (a), Figure 7 (c) in Figure 7 A schematic diagram of a structure in which a source metal is formed on the structure shown in (b);

[0051] Explanation of the reference numerals in the specification: 1. substrate; 2. epitaxial layer; 21. P+ region; 22. JTE region; 221. first trench; 222. second oxide layer; 223. first polysilicon layer; 224. first pillar; 3. first oxide layer; 4. source metal; 5. third oxide layer; 51. second trench; 6. second polysilicon layer; 7. fourth oxide layer; 8. first photoresist layer; 9. second photoresist layer. DETAILED DESCRIPTION

[0052] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0053] See also Figure 1 , Figure 1A schematic diagram of a junction terminal structure provided in the present application, the junction terminal structure specifically includes: a substrate 1, an epitaxial layer 2, a first oxide layer 3 and a source metal 4.

[0054] As a specific example of the present application, the substrate 1 is an N-type doped silicon carbide substrate.

[0055] The epitaxial layer 2 is disposed on one side of the substrate 1 , and includes a P+ region 21 and a JTE region 22 .

[0056] As a specific example of the present application, the epitaxial layer 2 is an N-type doped silicon carbide epitaxial layer.

[0057] The P+ region 21 is disposed in the epitaxial layer 2 on a side away from the substrate 1 .

[0058] The JTE region 22 is disposed at the periphery of the cell region on the side away from the substrate 1 in the epitaxial layer 2 and contacts the P+ region 21 . The thickness of the JTE region 22 gradually increases or decreases from the side close to the cell region to the side away from the cell region.

[0059] Optionally, in some embodiments of the present application, the thickness of the JTE region may gradually increase from the side close to the cell region to the side far from the cell region, that is, the thickness is the smallest on the side close to the cell region, and the thickness is the largest on the edge far from the cell region; in other embodiments of the present application, the thickness of the JTE region may gradually decrease from the side close to the cell region to the side far from the cell region, that is, the thickness is the largest on the side close to the cell region, and the thickness is the smallest on the edge far from the cell region.

[0060] The first oxide layer 3 is arranged on the surface of the epitaxial layer 2 away from the substrate 1;

[0061] The source metal 4 is disposed on the surface of the epitaxial layer 2 away from the substrate 1 , and its bottom is in contact with the top of the P+ region 21 .

[0062] The junction terminal structure provided by the present application forms a JTE region whose thickness gradually increases or decreases from the side close to the cell region to the side far from the cell region at the periphery of the cell region, so that the electric field in the device gradually decreases as the length of the JTE region increases, and as the thickness of the JTE region gradually decreases, the electric field gradually tends to the surface of the device, and finally reaches the position where breakdown is required, so that the device obtains an ideal breakdown voltage. The junction terminal structure provided by the present application can not only improve the breakdown voltage of the device and improve the withstand voltage performance of the device by only designing a JTE region with a gradually increasing or decreasing thickness at the periphery of the cell region, but also as the thickness of the JTE region gradually decreases, the device can finally reach an ideal breakdown position. Compared with the prior art of forming multiple P rings at a certain distance at the periphery of the cell region to improve the withstand voltage performance of the device, the present application can not only improve the withstand voltage performance of the device, so that the device obtains an ideal breakdown voltage, but also save chip area and reduce system cost.

[0063] Furthermore, due to the long length of the JTE region, a high electric field may appear in some regions, thereby causing the device to break down prematurely. Based on this, the embodiment of the present application provides a second junction terminal structure based on the above-mentioned junction terminal structure, such as Figure 2 As shown, the junction termination structure further includes: a plurality of first trenches 221 , a second oxide layer 222 and a first polysilicon layer 223 .

[0064] A plurality of first trenches 221 are arranged on a side of the JTE region 22 away from the substrate 1 , and are spaced from a side of the JTE region close to the cell region to a side away from the cell region, and a first column 224 is provided between adjacent first trenches 221 ;

[0065] The second oxide layer 222 is disposed on the bottom wall and two side walls of the first trench 221 .

[0066] The first polysilicon layer 223 is disposed on the second oxide layer 222 and fills the first trench 221 .

[0067] The junction termination structure provided in the embodiment of the present application has multiple grooves opened in the JTE region to improve the premature breakdown caused by the high electric field that may appear in the JE region. In addition, due to process problems, a higher electric field may appear in the groove region. Therefore, the embodiment of the present application fills the first polysilicon layer in the groove to transfer the high electric field at the groove in the JTE region to the first polysilicon layer in the groove, thereby avoiding premature breakdown caused by the high electric fields in the JTE region and the groove region, and further improving the voltage resistance performance of the device.

[0068] See also Figure 3 , Figure 3 The third junction terminal structure provided in the embodiment of the present application is compared with Figure 2 The junction terminal structure shown, Figure 3 The junction termination structure shown further includes: a third oxide layer 5 and a second polysilicon layer 6 .

[0069] The third oxide layer 5 is disposed on the surface of the first pillar 224 , and a second groove 51 is formed between the third oxide layers 5 on two adjacent first pillars 224 ;

[0070] The second polysilicon layer 6 is disposed on the surface of the first polysilicon layer 223 to fill the second trench 51 and extend to the surface of the third oxide layer 5 .

[0071] When the electric field strength at the first polysilicon layer in the first groove is too high, ions gather on the surface of the first polysilicon layer, causing the device surface to break down, thereby causing the device to break down prematurely and failing to reach the ideal breakdown voltage. Therefore, the junction terminal structure provided in the embodiment of the present application deposits a third oxide layer on the surface of the first column, and uses the third oxide layer on the adjacent column to form a second groove on the surface of the first polysilicon layer, and forms a stepped second polysilicon layer in the second groove and on the surface of the third oxide layer. The first polysilicon layer and the second polysilicon layer are connected to form a polysilicon field plate, which improves ion aggregation on the device surface, prevents device surface breakdown, enables the device to achieve a higher breakdown voltage, and further improves the device's voltage resistance performance.

[0072] The present application also provides a Figure 3 The preparation method of the junction terminal structure shown in the figure specifically comprises:

[0073] S10: Provide a substrate 1, grow an epitaxial layer 2 on one side of the substrate 1, and obtain Figure 4 The epitaxial wafer shown.

[0074] S11: thermally oxidize and grow a fourth oxide layer 7 on the surface of the epitaxial layer 2 away from the substrate 1, such as Figure 5 As shown in (a) in .

[0075] S12: forming a first photoresist layer 8 on the surface of the fourth oxide layer 7 away from the epitaxial layer 2, and exposing and developing the first photoresist layer 8 using a mask; injecting P+ ions into the epitaxial layer 2 through the fourth oxide layer 7 below the exposed and developed area, and forming a P+ region 21 in the epitaxial layer 2 away from the substrate 1, such as Figure 5 As shown in (b) in .

[0076] S13: removing the first photoresist layer 8, forming a second photoresist layer 9 on the surface of the fourth oxide layer 7 away from the epitaxial layer 2, and using a mask to expose and develop the second photoresist layer 9 located at the periphery of the cell area; injecting P- ions into the epitaxial layer 2 through the fourth oxide layer 7 below the exposed and developed area, forming a JTE region 22 with a gradually decreasing thickness in contact with the P+ region 21 at the periphery of the cell area away from the substrate 1 in the epitaxial layer 2, such as Figure 5 As shown in (c) in .

[0077] S14: removing the second photoresist layer 9 and the fourth oxide layer 7.

[0078] S15: Etching the JTE region 22 by wet etching to form a plurality of first trenches 221, and forming first pillars 224 between adjacent first trenches 221. Figure 6 As shown in (a) in .

[0079] S16: growing a second oxide layer 222 on the bottom wall and both side walls of the first trench 221 by thermal oxidation, depositing a first polysilicon layer 223 on the surface of the second oxide layer 222, and the upper surface of the first polysilicon layer 223 is flush with the upper surface of the first pillar 224, as shown in FIG. Figure 6 As shown in (b) in .

[0080] S17: growing a third oxide layer 5 on the surface of the first pillar 224 by thermal oxidation, and forming a second groove 51 between the third oxide layers 5 on the surfaces of two adjacent first pillars 224, such as Figure 7 As shown in (a) in .

[0081] S18: Depositing a second polysilicon layer 6 in the second trench 51 by chemical vapor deposition, wherein the second polysilicon layer 6 extends to the surface of the third oxide layer 5. Figure 7 As shown in (b) in .

[0082] When the second polysilicon layer is deposited in the second trench by chemical vapor deposition, the second polysilicon contacts the third oxide layer and extends toward the upper surface of the third oxide layer, eventually forming a Figure 7 The stepped second polysilicon layer shown in (b) .

[0083] S19: thermally oxidize and grow a first oxide layer 3 on the surface of the epitaxial layer 2 away from the substrate 1, etch the first oxide layer 3 and deposit a source metal 4, the bottom of the source metal 4 contacts the top of the P+ region 21, as shown in FIG. Figure 7 As shown in (c) in .

[0084] An embodiment of the present application also provides a semiconductor device, which includes the above-mentioned junction terminal structure.

[0085] Obviously, the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A junction termination structure, characterized in that: include: substrate; The epitaxial layer is arranged on one side of the substrate and comprises: A P+ region, arranged in the epitaxial layer at a side away from the substrate; A JTE region is arranged in the epitaxial layer at the periphery of the cell region on a side away from the substrate, in contact with the P+ region, and its thickness gradually increases or decreases from a side close to the cell region to a side away from the cell region; A plurality of first grooves are arranged on a side of the JTE region away from the substrate, and are spaced from a side of the JTE region close to the cell region to a side away from the cell region, with first columns between adjacent first grooves; A second oxide layer is disposed on the bottom wall and two side walls of the first trench; a first polysilicon layer, disposed on the second oxide layer and filling the first trench; A first oxide layer is disposed on a surface of the epitaxial layer away from the substrate; The source metal is arranged on the surface of the epitaxial layer away from the substrate, and the bottom of the source metal is in contact with the P+ region.

2. The junction termination structure according to claim 1, characterized in that: Also includes: A third oxide layer is disposed on the surface of the first pillar, and a second groove is formed between the third oxide layers on two adjacent first pillars; The second polysilicon layer is disposed on the surface of the first polysilicon layer to fill the second trench and extends to the surface of the third oxide layer.

3. The junction termination structure according to claim 1, characterized in that: The substrate is an N-type doped silicon carbide substrate, and the epitaxial layer is an N-type doped silicon carbide epitaxial layer.

4. A method for preparing a junction terminal structure according to any one of claims 1 to 3, characterized in that: include: Providing a substrate, and growing an epitaxial layer on one side of the substrate; Injecting P+ ions into the epitaxial layer at a side away from the substrate to form a P+ region, and injecting P- ions into the epitaxial layer at a side away from the substrate at the periphery of the cell region to form a JTE region in contact with the P+ region, the thickness of which gradually increases or decreases from a side close to the cell region to a side away from the cell region; Etching the JTE region by a wet etching process to form a plurality of first grooves along the JTE region from a side close to the cell region to a side far from the cell region, and forming first columns between adjacent first grooves; Growing a second oxide layer on the bottom wall and both side walls of the first trench by thermal oxidation, depositing a first polysilicon layer on the surface of the second oxide layer, wherein the upper surface of the first polysilicon layer is flush with the upper surface of the first column; A first oxide layer is grown by thermal oxidation on a surface of the epitaxial layer away from the substrate, the first oxide layer is etched and a source metal is deposited, and the bottom of the source metal contacts the top of the P+ region.

5. The method for preparing a junction terminal structure according to claim 4, characterized in that: After depositing the first polysilicon layer on the surface of the second oxide layer, the method further comprises: Growing a third oxide layer on the surface of the first pillar by thermal oxidation, and forming a second groove between the third oxide layers on the surfaces of two adjacent first pillars; A second polysilicon layer is deposited in the second trench by chemical vapor deposition, and the second polysilicon layer extends to the surface of the third oxide layer.

6. The method for preparing a junction terminal structure according to claim 5, characterized in that: Thermally oxidizing and growing a first oxide layer on a surface of the epitaxial layer away from the substrate, etching the first oxide layer and depositing a source metal, wherein the bottom of the source metal contacts the top of the P+ region, comprises: growing a first oxide layer on the surface of the third oxide layer and the second polysilicon layer by thermal oxidation; The first oxide layer above the P+ region is etched and a source metal is deposited, wherein the bottom of the source metal contacts the top of the P+ region.

7. The method for preparing a junction terminal structure according to claim 4, characterized in that: Injecting P+ ions into the epitaxial layer at a side away from the substrate to form a P+ region, and injecting P- ions into the periphery of the cell region at a side away from the substrate in the epitaxial layer to form a JTE region in contact with the P+ region and having a thickness gradually increasing or decreasing from a side close to the cell region to a side away from the cell region, including: Thermally oxidizing and growing a fourth oxide layer on a surface of the epitaxial layer away from the substrate; forming a first photoresist layer on a surface of the fourth oxide layer away from the epitaxial layer, and exposing and developing the first photoresist layer using a mask; Injecting P+ ions into the epitaxial layer through the fourth oxide layer below the exposure and development area to form a P+ region in the epitaxial layer away from the substrate; removing the first photoresist layer, forming a second photoresist layer on the surface of the fourth oxide layer away from the epitaxial layer, and exposing and developing the second photoresist layer located at the periphery of the cell region using a mask; Injecting P- ions into the epitaxial layer through the fourth oxide layer below the exposure and development area, forming a JTE region in contact with the P+ region at the periphery of the cell region away from the substrate in the epitaxial layer, the JTE region gradually increasing or decreasing in thickness from the side close to the cell region to the side away from the cell region; The second photoresist layer and the fourth oxide layer are removed.

8. A semiconductor device, characterized in that: The semiconductor device comprises a junction termination structure as claimed in any one of claims 1 to 3.

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