Superjunction semiconductor devices

Abstract

This invention relates to a superjunction semiconductor device, comprising a first conductivity type substrate, a first conductivity type epitaxial layer, multiple layers disposed on the front side of the first conductivity type substrate, second conductivity type ions implanted into the first conductivity type epitaxial layer to form second conductivity type first pillar regions, at least two rows of second conductivity type first pillar regions, each row of second conductivity type first pillar regions connected to form second conductivity type first pillars, a first conductivity type second epitaxial layer disposed on the front side of the first conductivity type first epitaxial layer, a first trench formed on the first conductivity type second epitaxial layer, the first trench filled with a second conductivity type material to form second conductivity type second pillars, the second conductivity type second pillars and the second conductivity type first pillars being correspondingly disposed and connected to the corresponding second conductivity type first pillars. This invention has the effect of reducing uneven electric field distribution and reducing electromagnetic interference.

Description

Technical Field

[0001] This utility model relates to the technical field of semiconductor devices, and in particular to a superjunction semiconductor device. Background Technology

[0002] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the special electrical properties of semiconductor materials to perform specific functions and are the core components of power electronic systems. They can be used to generate, control, receive, transform, and amplify signals and perform energy conversion. Their performance directly affects energy conversion efficiency and system reliability. With the rapid development of emerging industries such as new energy, the demand for high-power, high-voltage, and high-reliability power semiconductor devices is increasing. Among them, superjunction devices, as a new type of power device, are widely used in high-voltage and high-power power electronic equipment due to their advantages of low on-resistance and high breakdown voltage, achieving a better balance between breakdown voltage and on-resistance.

[0003] For superjunction semiconductor devices, the N-type drift region is replaced by alternating P-type pillars and N-type pillars. The P-type pillars in superjunction semiconductor devices are usually fabricated using deep trench technology. This involves etching deep trenches in the epitaxial layer and filling the deep trenches with P-type material to form P-type pillars.

[0004] Although this type of superjunction semiconductor device has low on-resistance and high breakdown voltage, it is prone to uneven electric field distribution, which aggravates electromagnetic interference under high-frequency operating conditions. There is currently no publicly available technical solution that can achieve both low on-resistance and high breakdown voltage while reducing electromagnetic interference. Utility Model Content

[0005] In view of this, the purpose of this utility model is to provide a superjunction semiconductor device to solve the technical problems of uneven electric field distribution and large electromagnetic interference in the existing superjunction semiconductor device.

[0006] This invention provides a superjunction semiconductor device, comprising:

[0007] First conductivity type substrate;

[0008] A first epitaxial layer of a first conductivity type is disposed on the front side of a substrate of the first conductivity type and is provided in multiple layers. Second conductivity type ions are implanted into each of the first epitaxial layers of the first conductivity type to form a first pillar region of the second conductivity type. The first pillar region of the second conductivity type is provided in at least two rows, and each row of the first pillar region of the second conductivity type is connected to form a first pillar of the second conductivity type.

[0009] A second epitaxial layer of a first conductivity type is disposed on the front side of the first epitaxial layer of the first conductivity type. A first trench is formed on the second epitaxial layer of the first conductivity type. The first trench is filled with a material of a second conductivity type to form a second pillar of the second conductivity type. The second pillar of the second conductivity type is correspondingly disposed with the first pillar of the second conductivity type and is connected to the corresponding first pillar of the second conductivity type.

[0010] Optionally, n layers of the first conductive type first epitaxial layer are stacked sequentially from the front side of the first conductive type substrate toward the direction of the first conductive type second epitaxial layer, wherein the thickness of the nth first conductive type first epitaxial layer is not greater than the thickness of the (n-1)th first conductive type first epitaxial layer, and the thickness of the nth first conductive type first epitaxial layer is less than the thickness of the first first conductive type first epitaxial layer.

[0011] Optionally, the first epitaxial layer of the first conductivity type has 4-5 layers.

[0012] Optionally, the depth of the first trench is greater than the thickness of the second epitaxial layer of the first conductivity type along the first direction.

[0013] Optionally, it also includes:

[0014] The second conductivity type body region is disposed on the front side of the second epitaxial layer of the first conductivity type and located within the second epitaxial layer of the first conductivity type;

[0015] A gate structure is disposed between two adjacent second pillars of the second conductivity type;

[0016] The first conductivity type source region is disposed on the front side of the second conductivity type body region and located within the second conductivity type body region.

[0017] Optionally, the gate structure includes a second trench formed on the front side of the second epitaxial layer of the first conductivity type, a gate is disposed in the second trench, and a gate oxide layer is disposed between the gate and the inner wall of the second trench.

[0018] Optionally, the gate structure further includes a shielding gate disposed in the second trench, and a gate oxide layer is disposed between the shielding gate, the inner wall of the second trench, and the gate.

[0019] Optionally, one or two gates are provided in the second trench.

[0020] Optionally, it also includes:

[0021] An insulating dielectric layer is disposed on the front side of the second conductive type body region, and a plurality of metal contact through holes corresponding to the second pillars of the second conductive type are formed in the insulating dielectric layer;

[0022] A front metal layer is disposed on the front side of the insulating dielectric layer and extends into the metal contact via until it fills the metal contact via.

[0023] A back metal layer is disposed on the back side of the first conductivity type substrate.

[0024] Optionally, the thickness of the first epitaxial layer of the second conductivity type along the first direction is greater than the thickness of the second epitaxial layer of the first conductivity type along the first direction.

[0025] The technical solution of this utility model has the following advantages:

[0026] The superjunction semiconductor device provided by this invention forms a first pillar of the second conductivity type by implanting ions of the second conductivity type into a first epitaxial layer of the first conductivity type. A first trench is formed in a second epitaxial layer of the first conductivity type on the front side of the first epitaxial layer of the first conductivity type, and then filled to form a second pillar of the second conductivity type. The first pillar of the second conductivity type and the second pillar of the second conductivity type are correspondingly arranged and connected to form a superjunction structure. It can achieve low on-resistance and high breakdown voltage while forming the second pillar of the second conductivity type by only forming a first trench in the second epitaxial layer of the first conductivity type. Only part of the superjunction structure is formed by deep trench, while the other part is formed by ion implantation. This reduces the size of the first trench, thereby reducing uneven electric field distribution and reducing the occurrence of electromagnetic interference. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the overall structure of the superjunction semiconductor device in this utility model;

[0029] Figure 2 This is a schematic diagram of another embodiment of the superjunction semiconductor device of this utility model.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1. Substrate of first conductivity type; 2. First epitaxial layer of first conductivity type; 3. Second epitaxial layer of first conductivity type; 4. First pillar of second conductivity type; 41. First pillar region of second conductivity type; 5. Second pillar of second conductivity type; 6. First trench; 7. Gate structure; 71. Second trench; 72. Gate; 73. Gate oxide layer; 74. Shielding gate; 8. Body region of second conductivity type; 9. Source region of first conductivity type; 10. Insulating dielectric layer; 11. Metal contact via; 12. Front metal layer; 13. Back metal layer. Detailed Implementation

[0032] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of this utility model. Based on the description of this utility model, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this utility model.

[0033] Unless otherwise explicitly specified and limited, the terms "setup," "installation," and "connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms based on the specific circumstances.

[0034] The terms “upper,” “lower,” “left,” “right,” “front,” “back,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of description and simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0035] The terms “first,” “second,” “third,” etc., are used merely to distinguish elements with similar properties, not to indicate or imply relative importance or a specific order.

[0036] The terms “include,” “comprising,” or any other variation thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0037] Example

[0038] Reference Figure 1 and Figure 2As shown, this utility model provides a superjunction semiconductor device, which is configured as a MOSFET device or an IGBT device. In this embodiment, a MOSFET device is used as an example. The MOSEFT device includes an N-type MOSEFT device and a P-type MOSEFT device. For the N-type MOSEFT device, the first conductivity type is N-type and the second conductivity type is P-type; for the P-type MOSEFT device, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, an N-type MOSEFT device is used as an example, and the top surface is set as the front surface and the bottom surface as the back surface. The arrow X direction in the figure is the first direction.

[0039] Reference Figure 1 As shown, the superjunction semiconductor device includes a first conductivity type substrate 1, a first conductivity type epitaxial layer 2, and a first conductivity type second epitaxial layer 3. The first conductivity type substrate 1 is selected as N-type silicon as the substrate. The first conductivity type first epitaxial layer 2 is disposed on the front side of the first conductivity type substrate 1 and multiple layers are stacked thereon. The concentration of first conductivity type ions in the first conductivity type substrate 1 is greater than the concentration of first conductivity type ions in the first conductivity type first epitaxial layer 2. Each first conductivity type first epitaxial layer 2 is grown on the front side of the first conductivity type substrate 1 by epitaxial process. The multiple first conductivity type first epitaxial layers 2 are arranged and epitaxially grown in sequence along the first direction. Second conductivity type ions are implanted in a certain area of ​​each first conductivity type first epitaxial layer 2 to form multiple second conductivity type first pillar regions 41. The second conductivity type first pillar regions 41 in the multiple first conductivity type first epitaxial layers 2 are correspondingly arranged, so that at least two rows of second conductivity type first pillar regions 41 are arranged along the first direction. Each row of second conductivity type first pillar regions 41 is advanced by high temperature to diffuse the second conductivity type first pillar regions 41, thereby forming multiple second conductivity type first pillars 4.

[0040] The second conductive type second epitaxial layer is disposed on the front side of the first conductive type first epitaxial layer 2 at the top of the plurality of first conductive type first epitaxial layers 2. The front side of the first conductive type second epitaxial layer 3 has a plurality of first trenches 6 corresponding to the second conductive type first pillar 4. The first trenches 6 are filled with second conductive type material to form second conductive type second pillars 5. The plurality of second conductive type second pillars 5 and the plurality of second conductive type first pillars 4 are arranged in a one-to-one correspondence, and the second conductive type second pillar 5 is connected to the near end of the corresponding second conductive type first pillar 4, so that the connection process of the second conductive type first pillar 4 and the second conductive type second pillar 5 is a superjunction pillar.

[0041] The depth of the first trench 6 along the first direction is greater than the length of the second epitaxial layer 3 of the first conductive type along the first direction, so as to ensure that the second epitaxial layer 3 of the first conductive type directly above the first pillar 4 of the second conductive type can be removed, so that the first pillar 4 of the second conductive type is exposed, ensuring the stability and reliability of the subsequent connection between the second pillar 5 of the second conductive type and the first pillar 4 of the second conductive type.

[0042] A first pillar 4 of the second conductivity type is formed by implanting ions of the second conductivity type into the first epitaxial layer 2 of the first conductivity type. A first trench 6 is opened in the second epitaxial layer 3 of the first conductivity type on the front side of the first epitaxial layer 2 of the first conductivity type, and filled to form a second pillar 5 of the second conductivity type. The first pillar 4 and the second pillar 5 of the second conductivity type are correspondingly arranged and connected to form a superjunction structure. This structure can achieve low on-resistance and high breakdown voltage. The second pillar 5 of the second conductivity type is formed only by opening the first trench 6 in the second epitaxial layer 3 of the first conductivity type. Only part of the superjunction structure is formed by deep trench, while the other part is formed by ion implantation. This reduces the size of the first trench 6, thereby reducing the uneven electric field distribution and reducing the occurrence of electromagnetic interference.

[0043] In one specific implementation, n layers of the first conductive type first epitaxial layer 2 are stacked sequentially from the front side of the first conductive type substrate 1 to the first conductive type second epitaxial layer 3, i.e., from bottom to top. The thickness of the nth first conductive type first epitaxial layer 2 is not greater than the thickness of the (n-1)th first conductive type first epitaxial layer 2, and the thickness of the nth first conductive type first epitaxial layer 2 is less than the thickness of the first first conductive type first epitaxial layer 2.

[0044] In this embodiment, the first epitaxial layer 2 of the first conductivity type is provided with 4-5 layers, and further, in this embodiment, the first epitaxial layer 2 of the first conductivity type is provided with 4 layers. By gradually reducing the thickness of the multiple first epitaxial layers 2 of the first conductivity type from bottom to top, the electric field is uniformly distributed, making the electric field more uniformly distributed throughout the entire first epitaxial layer 2 of the first conductivity type, improving the withstand voltage capability of the device, effectively controlling the electric field gradient of each first epitaxial layer 2 of the first conductivity type, so that the electric field changes gradually between different layers, avoiding the possible abrupt change in electric field in a single first epitaxial layer 2 of the first conductivity type, refining the current carrying capacity, and achieving charge balance.

[0045] As a specific practical approach, refer to Figure 1As shown, a second epitaxial layer 3 of the first conductivity type is disposed on the front side of a multilayer first epitaxial layer 2 of the first conductivity type. The thickness of the second epitaxial layer 3 of the first conductivity type along the first direction is greater than the thickness of the first epitaxial layer 2 of the first conductivity type along the first direction. The resistivity of the second epitaxial layer 3 of the first conductivity type is different from that of the first epitaxial layer 2 of the first conductivity type. Specifically, the resistivity of the second epitaxial layer 3 of the first conductivity type is less than that of the first epitaxial layer 2 of the first conductivity type. By adjusting the resistivity of the first epitaxial layer 2 of the first conductivity type and the second epitaxial layer 3 of the first conductivity type, the voltage requirements of different products can be met, thereby achieving higher withstand voltage capability.

[0046] In one specific implementation, the superjunction semiconductor device further includes a second conductivity type body region 8, a first conductivity type source region 9, and a gate structure 7. The second conductivity type body region 8 is disposed on the front side of the first conductivity type second epitaxial layer 3 and located within the first conductivity type second epitaxial layer 3. The gate structure 7 is disposed on the front side of the first conductivity type second epitaxial layer 3 and between two adjacent second conductivity type second pillars 5. Specifically, at least one gate structure 7 is provided, and a gate structure 7 is provided between each of two adjacent second conductivity type second pillars 5. The gate structure 7 also extends from the front side of the first conductivity type second epitaxial layer 3 having the second conductivity type body region 8 towards the first conductivity type second epitaxial layer 3. The back side of layer 3 extends from the second conductivity type body region 8 to the first conductivity type second epitaxial layer 3 below the second conductivity type body region 8. For the gate structure 7, it is not limited to being a trench gate, but can also be a planar gate, which can be directly set on the front side of the first conductivity type second epitaxial layer 3. The first conductivity type source region 9 is set on the front side of the second conductivity type body region 8 and located in the second conductivity type body region 8. In this embodiment, there are multiple first conductivity type source regions 9. Two first conductivity type source regions 9 are set at each gate structure 7, respectively located on both sides of the gate structure 7 facing the second conductivity type second pillar 5, and extending in the direction of the second conductivity type second pillar 5.

[0047] Specifically, the gate structure 7 includes a second trench 71 formed on the front side of the second epitaxial layer 3 of the first conductivity type. The second trench 71 extends from the front side of the second epitaxial layer 3 of the first conductivity type with the body region 8 of the second conductivity type to the back side of the second epitaxial layer 3 of the first conductivity type, until it extends into the first epitaxial layer 3 of the second conductivity type on the back side of the body region 8. A gate 72 is disposed in the second trench 71. A gate oxide layer 73 is disposed between the gate 72 and the inner wall of the second trench 71. The gate 72 is separated by the gate oxide layer 73 and the inner wall of the second trench 71. The gate 72 is conductive polysilicon. The thickness of the gate oxide layer 73 between the gate 72 and the bottom wall of the second trench 71 is greater than the thickness of the gate oxide layer 73 between the gate 72 and the inner sidewall of the second trench 71. The thicker gate oxide layer 73 at the bottom can improve the gate oxide reliability of the device.

[0048] In another embodiment, the gate structure 7 further includes a shielding gate 74 disposed in the second trench 71. The shielding gate 74 is located below the gate 72, and the depth of the shielding gate 74 in the second trench 71 is greater than the depth of the gate 72 in the second trench 71. The shielding gate 74 and the inner wall of the second trench 71 are also separated by a gate oxide layer 73. There is a gap between the shielding gate 74 and the gate 72, which is also separated by the gate oxide layer 73. By providing the shielding gate 74, faster switching speed and lower switching loss can be achieved, further reducing the on-resistance and Miller capacitance, and improving the switching speed.

[0049] As another implementation method, refer to Figure 2 As shown, the gate structure 7 has two gates 72, and a shielding gate 74 is located between the two gates 72. Both the gates 72 and the shielding gate 74 extend from the opening of the second trench 71 into the second trench 71. Gaps are left between the gates 72 and the inner walls of the second trench 71, and between the shielding gate 74 and the gates 72. Gate oxide layers 73 are provided between the shielding gate 74 and the gates 72, between the gates 72 and the inner sidewall of the second trench 71, and between the shielding gate 74 and the bottom wall of the second trench 71, which serve as separations. The depth of the second trench 71 is set to 1.5μm-3μm, and the depth of the shielding gate 74 in the second trench 71 is greater than the depth of the gate 72 in the first trench 6. In another embodiment, the number of gates 72 is not uniquely limited and can also be multiple.

[0050] As one specific implementation method, refer to Figure 1As shown, it also includes an insulating dielectric layer 10, a front metal layer 12, and a back metal layer 13. The insulating dielectric layer 10 is disposed on the front side of the second conductive type body region 8 and covers the entire second conductive type body region 8. Multiple metal contact vias 11 are formed in the insulating dielectric layer 10. The metal contact vias 11 are corresponding to the second conductive type second pillar 5. The metal contact vias 11 extend into the second conductive type body region 8 above the second conductive type second pillar 5 and communicate with the first conductive type source region 9. The front metal layer 12 is disposed on the front side of the insulating dielectric layer 10, and the portion of the front metal layer 12 located at the metal contact vias 11 extends into the metal contact vias 11 until it fills the metal contact vias 11. At this time, part of the front metal layer 12 in the metal contact vias 11 corresponding to the second conductive type second pillar 5 will contact the second conductive type body region 8 and the first conductive type source region 9. The back metal layer 13 is disposed on the back side of the first conductive type substrate 1 and covers the entire back side of the first conductive type substrate 1.

[0051] When a shielding gate 74 is provided and two gates 72 are provided, a metal contact through hole 11 is also provided at the insulating dielectric layer 10 located directly above the shielding gate 74, and the front metal layer 12 will also extend into the metal contact through hole 11 to fill the metal contact through hole 11.

[0052] The above description is only a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model.

Claims

1. A superjunction semiconductor device, characterized in that, include: First conductivity type substrate; A first epitaxial layer of a first conductivity type is disposed on the front side of a substrate of the first conductivity type and is provided in multiple layers. Second conductivity type ions are implanted into each of the first epitaxial layers of the first conductivity type to form a first pillar region of the second conductivity type. The first pillar region of the second conductivity type is provided in at least two rows, and each row of the first pillar region of the second conductivity type is connected to form a first pillar of the second conductivity type. A second epitaxial layer of a first conductivity type is disposed on the front side of the first epitaxial layer of the first conductivity type. A first trench is formed on the second epitaxial layer of the first conductivity type. The first trench is filled with a material of a second conductivity type to form a second pillar of the second conductivity type. The second pillar of the second conductivity type is correspondingly disposed with the first pillar of the second conductivity type and is connected to the corresponding first pillar of the second conductivity type.

2. The superjunction semiconductor device as described in claim 1, characterized in that, The first conductive type first epitaxial layer is stacked n layers sequentially from the front side of the first conductive type substrate toward the direction of the first conductive type second epitaxial layer, wherein the thickness of the nth first conductive type first epitaxial layer is not greater than the thickness of the (n-1)th first conductive type first epitaxial layer, and the thickness of the nth first conductive type first epitaxial layer is less than the thickness of the first first conductive type first epitaxial layer.

3. The superjunction semiconductor device as described in claim 1, characterized in that, The first conductive type has 4-5 epitaxial layers.

4. The superjunction semiconductor device as described in claim 1, characterized in that, The depth of the first trench is greater than the thickness of the second epitaxial layer of the first conductivity type along the first direction.

5. The superjunction semiconductor device as described in claim 1, characterized in that, Also includes: The second conductivity type body region is disposed on the front side of the second epitaxial layer of the first conductivity type and located within the second epitaxial layer of the first conductivity type; A gate structure is disposed between two adjacent second pillars of the second conductivity type; The first conductivity type source region is disposed on the front side of the second conductivity type body region and located within the second conductivity type body region.

6. The superjunction semiconductor device as described in claim 5, characterized in that, The gate structure includes a second trench formed on the front side of the second epitaxial layer of the first conductivity type, a gate is disposed in the second trench, and a gate oxide layer is disposed between the gate and the inner wall of the second trench.

7. The superjunction semiconductor device as described in claim 6, characterized in that, The gate structure further includes a shielding gate, which is disposed in the second trench. A gate oxide layer is disposed between the shielding gate, the inner wall of the second trench, and the gate.

8. The superjunction semiconductor device as described in claim 6 or 7, characterized in that, The second trench contains one or two gates.

9. The superjunction semiconductor device as described in claim 1, characterized in that, Also includes: An insulating dielectric layer is disposed on the front side of the second conductive type body region, and a plurality of metal contact through holes corresponding to the second pillars of the second conductive type are formed in the insulating dielectric layer; A front metal layer is disposed on the front side of the insulating dielectric layer and extends into the metal contact via until it fills the metal contact via. A back metal layer is disposed on the back side of the first conductivity type substrate.

10. The superjunction semiconductor device as claimed in claim 1, characterized in that, The thickness of the first epitaxial layer of the second conductivity type along the first direction is greater than the thickness of the second epitaxial layer of the first conductivity type along the first direction.

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