Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate comprising a plurality of first regions and an isolation region located between adjacent first regions; a first doped well region located within the first regions; an initial well region located within the isolation region, the initial well region having a conductivity type opposite to that of the first doped well regions, and the initial well region being in contact with the first doped well regions; and a first isolation well region located within the first doped well regions, the first isolation well region having a conductivity type opposite to that of the first doped well regions, wherein the distance from the edge of the first isolation well region to the edge of the initial well region is greater than zero and less than half the width of the initial well region, the width being the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions. The semiconductor structure and the method for forming the same improve the electrical isolation effect of different regions in a transistor device, thereby improving device stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the development of integrated circuit technology, the size of devices is getting smaller and the integration level is gradually increasing. For highly integrated semiconductor devices, effective isolation between different device structures is an important guarantee for stable device performance.

[0003] In recent years, improving the isolation between device structures has received widespread attention. For transistor devices, in particular, each transistor region must operate independently to achieve the overall functionality of the device. Especially for small-sized, highly integrated transistor devices, improving the electrical isolation between transistor regions is crucial for enhancing device performance.

[0004] However, in the existing technology, there is still much room for improvement in the electrical isolation effect of different regions in transistor devices. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which improves the electrical isolation effect in different regions of a transistor device and enhances device stability.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a plurality of first regions and an isolation region located between adjacent first regions; a first doped well region located within the first regions; an initial well region located within the isolation region, the initial well region having a conductivity type opposite to that of the first doped well region, and the initial well region being in contact with the first doped well region; a first isolation well region located within the first doped well region, the first isolation well region having a conductivity type opposite to that of the first doped well region, the distance from the edge of the first isolation well region to the edge of the initial well region being greater than zero and less than half the width of the initial well region, the width being the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions.

[0007] Optionally, the number of first isolation well regions in each first doped well region is equal to 1.

[0008] Optionally, the number of first isolation well regions in each first doped well region is greater than 1.

[0009] Optionally, it also includes: a laterally diffused metal-oxide-semiconductor transistor located on the first region.

[0010] Optionally, the laterally diffused metal-oxide-semiconductor transistor includes: a second doped well region located on the first region, the second doped well region being located on the side of the first doped well region away from the initial well region; a gate oxide layer spanning the first doped well region and the second doped well region and a gate structure located on the gate oxide layer; a source region and a drain region located on both sides of the gate structure, the source region being located within the second doped well region and the drain region being located within the first doped well region.

[0011] Optionally, the first doped well region contains N-type conductive ions; the initial well region contains P-type conductive ions.

[0012] Optionally, the second doped well region contains P-type conductive ions.

[0013] Optionally, the first isolation trap region contains P-type conductive ions.

[0014] Optionally, the depth of the first doped well region ranges from 8 micrometers to 10 micrometers.

[0015] Optionally, the width of the initial well region ranges from 5 micrometers to 10 micrometers.

[0016] Optionally, the distance from the edge of the first isolation trap region to the edge of the initial trap region ranges from 2 micrometers to 5 micrometers.

[0017] Optionally, the dopant concentration of the first isolated well region may be the same as or different from the dopant concentration of the initial well region.

[0018] Optionally, the depth of the first isolation trap region may be the same as or different from the depth of the initial trap region.

[0019] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of first regions and an isolation region located between adjacent first regions; forming a first doped well region within the first regions; forming an initial well region within the isolation region, the initial well region having a conductivity type opposite to that of the first doped well region, and the initial well region being in contact with the first doped well region; forming a first isolation well region within the first doped well region, the first isolation well region having a conductivity type opposite to that of the first doped well region, the distance from the edge of the first isolation well region to the edge of the initial well region being greater than zero and less than half the width of the initial well region, the width being the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions.

[0020] Optionally, the distance from the edge of the first isolation trap region to the edge of the initial trap region ranges from 2 micrometers to 5 micrometers.

[0021] Optionally, the doped ion concentration of the first isolation well region is the same as that of the initial well region, the depth of the first isolation well region is the same as that of the initial well region, and the first isolation well region and the initial well region are formed simultaneously.

[0022] Optionally, the doped ion concentration of the first isolation well region is different from that of the initial well region, and the depth of the first isolation well region is different from that of the initial well region.

[0023] Optionally, the number of first isolation well regions in each first doped well region is equal to 1.

[0024] Optionally, the number of first isolation well regions in each first doped well region is greater than 1.

[0025] Optionally, it also includes: forming a laterally diffused metal-oxide-semiconductor transistor located on the first region.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the semiconductor structure provided by the technical solution of the present invention, since there is a first isolation well region within the first doped well region, and the conductivity type of the first isolation well region is opposite to that of the first doped well region, it enhances the PN junction at the junction of the initial well region and the first doped well region, thereby improving the isolation effect of the device structure on both sides and increasing the breakdown voltage between devices. At the same time, by controlling the distance from the edge of the first isolation well region to the edge of the initial well region, making the distance greater than zero and less than half the width of the initial well region, the overall isolation effect of the first isolation well region and the initial well region is better.

[0028] Furthermore, the first doped well region is the drift region of the laterally diffused metal-oxide-semiconductor transistor. Since the drift region of the laterally diffused metal-oxide-semiconductor transistor is relatively deep, the isolation requirements for different regions are higher. The existence of the first isolation well region can specifically improve the isolation effect between the laterally diffused metal-oxide-semiconductor transistor and other device structures, thereby improving the stability of the device.

[0029] In the semiconductor structure formation method provided by the technical solution of the present invention, since a first isolation well region is formed in the first doped well region, and the conductivity type of the first isolation well region is opposite to that of the first doped well region, it enhances the PN junction at the junction of the initial well region and the first doped well region, thereby improving the isolation effect of the device structure on both sides of it; at the same time, by controlling the distance from the edge of the first isolation well region to the edge of the initial well region, making the distance greater than zero and less than half the width of the initial well region, the overall isolation effect of the first isolation well region and the initial well region is better. Attached Figure Description

[0030] Figures 1 to 5 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, under current technology, there is still considerable room for improvement in the electrical isolation effect of different regions within small-sized, highly integrated transistor devices.

[0032] In one embodiment of a semiconductor structure, the semiconductor structure includes a plurality of laterally diffused metal-oxide-semiconductor transistors (MOSFETs). By forming an initial isolation well region between adjacent MOSFETs with a conductivity type opposite to that of their drift regions, leakage current between adjacent MOSFETs is suppressed, achieving an electrical isolation effect. However, in the prior art, the electrical isolation effect of the initial isolation well region on different regions of the device structure is still limited, and the device stability needs to be further improved.

[0033] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising a first doped well region, an initial well region, and a first isolation well region located within the first doped well region. The conductivity type of the first isolation well region is opposite to that of the first doped well region, thereby enhancing the PN junction at the boundary between the initial well region and the first doped well region, and thus improving the isolation effect of the device structures on both sides. Simultaneously, by controlling the distance from the edge of the first isolation well region to the edge of the initial well region, making this distance greater than zero and less than half the width of the initial well region, the isolation effect of the first isolation well region is further improved.

[0034] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 1 to 5 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0036] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a plurality of first regions I and an isolation region II located between adjacent first regions I; a first doped well region 101 is formed in the first region I.

[0037] In this embodiment, the first region I provides a platform for the subsequently formed laterally diffused metal-oxide-semiconductor transistors; the isolation region II provides a platform for the subsequently formed initial well region, which is used to isolate adjacent laterally diffused metal-oxide-semiconductor transistors.

[0038] The substrate 100 is made of materials including silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), and germanium-on-insulator (GOI). Specifically, in this embodiment, the substrate 100 is made of silicon.

[0039] In this embodiment, the first doped well region 101 is used as the drift region for the subsequently formed laterally diffused metal-oxide-semiconductor transistor.

[0040] Specifically, the first doped well region 101 contains N-type conductive ions.

[0041] Please refer to Figure 2 An initial well region 103 is formed within the isolation region II. The conductivity type of the initial well region 103 is opposite to that of the first doped well region 101, and the initial well region 103 is in contact with the first doped well region 101. A first isolation well region 105 is formed within the first doped well region 101.

[0042] In this embodiment, the conductivity type of the initial well region 103 is opposite to that of the first doped well region 101, and the initial well region 103 is in contact with the first doped well region 101. Therefore, a PN junction is formed at the boundary between the initial well region 103 and the first doped well region 101, thereby suppressing leakage current between adjacent laterally diffused metal-oxide-semiconductor transistors.

[0043] Specifically, the initial well region 103 contains P-type conductive ions.

[0044] In this embodiment, the conductivity type of the first isolation well region 105 is opposite to that of the first doped well region 101. The distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103 is greater than zero and less than half of the width d1 of the initial well region 103. The width d1 is the size of the initial well region 103 along the direction parallel to the substrate 100 and located between adjacent first regions I.

[0045] Specifically, the first isolation trap region 105 contains P-type conductive ions.

[0046] In this embodiment, the first isolation well region 105 is located within the first doped well region 101, and its conductivity type is opposite to that of the first doped well region 101. Therefore, the presence of the first isolation well region 105 increases the concentration of P-type conductive ions near the edge of the first doped well region 101, thereby enhancing the PN junction at the junction of the initial well region 103 and the first doped well region 101, further improving the isolation effect on the device structures on both sides, and increasing the breakdown voltage between devices.

[0047] Specifically, the width d1 of the initial well region 103 ranges from 5 micrometers to 10 micrometers; the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103 ranges from 2 micrometers to 5 micrometers. By controlling the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103, making this distance d2 greater than zero and less than half the width d1 of the initial well region 103, the isolation effect between the first isolation well region 105 and the initial well region 103 is improved.

[0048] In this embodiment, the first isolation well region 105 and the initial well region 103 are formed simultaneously, thereby simplifying the process. The doped ion concentration of the first isolation well region 105 is the same as that of the initial well region 103, and the depth of the first isolation well region 105 is the same as that of the initial well region 103.

[0049] Specifically, the method for forming the first isolation well region 105 and the initial well region 103 includes: forming a mask layer (not shown) on the substrate 100, the mask layer exposing the isolation region II and a portion of the surface of the first doped well region 101; and performing ion implantation using the mask layer as a mask to form the first isolation well region 105 and the initial well region 103.

[0050] In another embodiment, the doped ion concentration of the first isolation well region is different from that of the initial well region, and the depth of the first isolation well region is different from that of the initial well region. The first isolation well region and the initial well region are formed separately.

[0051] In the above embodiments, since the first isolation well region and the initial well region are formed separately, the doping ion concentration and depth of the first isolation well region and the initial well region can be different. Therefore, the depth and concentration of the first isolation well region can be flexibly adjusted based on the initial well region, thereby adjusting the overall isolation capability of the first isolation well region and the initial well region.

[0052] In this embodiment, the number of first isolation well regions 105 in each first doped well region 101 is equal to 1.

[0053] In another embodiment, the number of first isolation well regions within each first doped well region is greater than 1. By increasing the number of first isolation well regions, the isolation effect between adjacent device structures in the first region I can be further enhanced more flexibly according to the device structure on the first region I.

[0054] In this embodiment, a laterally diffused metal-oxide-semiconductor transistor is then formed on the first region I. The laterally diffused metal-oxide-semiconductor transistor includes: a second doped well region on the first region I, the second doped well region being located on the side of the first doped well region 101 away from the initial well region 103; a gate oxide layer spanning the first doped well region 101 and the second doped well region, and a gate structure located on the gate oxide layer; a source region and a drain region located on both sides of the gate structure, the source region being located within the second doped well region, and the drain region being located within the first doped well region 101.

[0055] Specifically, the process of forming a laterally diffused metal-oxide-semiconductor transistor is as follows: Figures 3 to 5 As shown.

[0056] Please refer to Figure 3 A second doped well region 102 is formed in the first region I, and the second doped well region 102 is located on the side of the first doped well region 101 away from the initial well region 103.

[0057] In this embodiment, the second doped well region 102 contains P-type conductive ions.

[0058] Please refer to Figure 4 A gate oxide layer 112 is formed that spans the first doped well region 101 and the second doped well region 102, and a gate structure 111 is located on the gate oxide layer 112.

[0059] Specifically, the method for forming the gate oxide layer 112 and the gate structure 111 includes: forming a gate oxide material layer (not shown) on the first region I; forming an initial gate material layer (not shown) on the gate oxide material layer; patterning the gate oxide material layer and the initial gate material layer; and forming the gate oxide layer 112 and the gate structure 111 on the first doped well region 101 and the second doped well region 102.

[0060] Please refer to Figure 5 A source region 121 and a drain region 122 are formed on both sides of the gate structure 111. The source region 121 is located in the second doped well region 102, and the drain region 122 is located in the first doped well region 101.

[0061] In this embodiment, the source region 121 and the drain region 122 contain N-type conductive ions.

[0062] Specifically, since a first isolation well region 105 is formed within the first doped well region 101, and the conductivity type of the first isolation well region 105 is opposite to that of the first doped well region 101, it enhances the PN junction at the boundary between the initial well region 103 and the first doped well region 101, thereby improving the isolation effect on the laterally diffused metal-oxide-semiconductor transistors on both sides. At the same time, by controlling the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103, making the distance d2 greater than zero and less than half the width d1 of the initial well region 103, the overall isolation effect of the first isolation well region 105 and the initial well region 103 is better.

[0063] Accordingly, embodiments of the present invention also provide a semiconductor structure formed using the above method.

[0064] Please continue to refer to this. Figure 5 The semiconductor structure includes: a substrate 100, the substrate 100 including a plurality of first regions I and an isolation region II located between adjacent first regions I; a first doped well region 101 located within the first regions I; an initial well region 103 located within the isolation region II, the initial well region 103 having a conductivity type opposite to that of the first doped well region 101, and the initial well region 103 being in contact with the first doped well region 101; a first isolation well region 105 located within the first doped well region 101, the first isolation well region 105 having a conductivity type opposite to that of the first doped well region 101, the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103 being greater than zero and less than half the width d1 of the initial well region 103, the width d1 being the dimension of the initial well region 103 along a direction parallel to the substrate 100 and located between adjacent first regions I.

[0065] In this embodiment, the semiconductor structure further includes a laterally diffused metal-oxide-semiconductor transistor located on the first region I.

[0066] Specifically, the laterally diffused metal-oxide-semiconductor transistor includes: a second doped well region 102 located on the first region I, the second doped well region 102 being located on the side of the first doped well region 101 away from the initial well region 103; a gate oxide layer 112 spanning the first doped well region 101 and the second doped well region 102, and a gate structure 111 located on the gate oxide layer 112; a source region 121 and a drain region 122 located on both sides of the gate structure 111, the source region 121 being located within the second doped well region 102, and the drain region 122 being located within the first doped well region 101. The first doped well region 101 serves as the drift region of the laterally diffused metal-oxide-semiconductor transistor.

[0067] In this embodiment, the conductivity type of the initial well region 103 is opposite to that of the first doped well region 101, and the initial well region 103 is in contact with the first doped well region 101. Therefore, a PN junction is formed at the boundary between the initial well region 103 and the first doped well region 101, thereby suppressing leakage current between adjacent laterally diffused metal-oxide-semiconductor transistors.

[0068] The laterally diffused metal-oxide-semiconductor transistor (LMS) features high operating voltage and high current. When the operating voltage of the LMS is high, the first isolation well region 105 within the first doped well region 101 has a conductivity type opposite to that of the first doped well region 101. This enhances the PN junction at the boundary between the initial well region 103 and the first doped well region 101. On one hand, this improves the isolation effect of the LMS on both sides, increasing the breakdown voltage between devices. On the other hand, while maintaining a constant breakdown voltage, it reduces the width d1 of the initial well region, improving the device integration density.

[0069] In this embodiment, the depth of the first doped well region 101 is in the range of 8 micrometers to 10 micrometers. The first doped well region 101 is the drift region of the laterally diffused metal-oxide-semiconductor transistor. Since the depth of the drift region is relatively large, the isolation requirements for adjacent transistors are higher. The existence of the first isolation well region 105 can specifically improve the isolation effect between laterally diffused metal-oxide-semiconductor transistors or between laterally diffused metal-oxide-semiconductor transistors and other device structures, thereby improving the stability of the device.

[0070] In this embodiment, the width d1 of the initial well region 103 ranges from 5 micrometers to 10 micrometers. The width of the first isolation well region 105 ranges from 3 micrometers to 5 micrometers.

[0071] In this embodiment, the first isolation well region 105 and the initial well region 103 together constitute an isolation structure between adjacent laterally diffused metal-oxide-semiconductor transistors. Specifically, by optimizing the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103, the overall isolation effect of the first isolation well region 105 and the initial well region 103 can be optimized. By controlling the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103 to be greater than zero and less than half the width d1 of the initial well region 103, the overall isolation effect of the first isolation well region 105 and the initial well region 103 is improved.

[0072] Furthermore, if the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103 is too far, the enhancement effect of the first isolation well region 105 on the PN junction at the junction of the initial well region 103 and the first doped well region 101 is limited, resulting in a negligible improvement in isolation performance. Conversely, if the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103 is too close, mutual interference exists between the first isolation well region 105 and the initial well region 103, which is detrimental to device stability. Therefore, in this embodiment, the distance d2 from the edge of the first isolation well region 105 to the edge of the initial well region 103 ranges from 2 micrometers to 5 micrometers, which can improve the overall isolation effect between the first isolation well region 105 and the initial well region 103 without affecting the initial well region 103.

[0073] In this embodiment, the first doped well region 101 contains N-type conductive ions; the initial well region 103 contains P-type conductive ions. The second doped well region 102 contains P-type conductive ions. The first isolation well region 105 contains P-type conductive ions. The source region 121 and the drain region 122 contain N-type conductive ions.

[0074] In another embodiment, the first doped well region contains P-type conductive ions; the initial well region contains N-type conductive ions; the second doped well region contains N-type conductive ions; the first isolation well region contains N-type conductive ions; and the source and drain regions contain P-type conductive ions.

[0075] In this embodiment, the number of first isolation well regions 105 in each first doped well region 101 is equal to 1.

[0076] In other embodiments, the number of first isolation well regions in each first doped well region is greater than 1, thereby enabling more flexible adjustment of the isolation effect between adjacent laterally diffused metal-oxide-semiconductor transistors.

[0077] In this embodiment, the doped ion concentration of the first isolation well region 105 is the same as that of the initial well region 103; the depth of the first isolation well region 105 is the same as that of the initial well region 103.

[0078] In another embodiment, the doping ion concentration of the first isolation well region is different from that of the initial well region; the depth of the first isolation well region is different from that of the initial well region. Thus, based on the initial well region, the overall isolation structure of the first isolation well region and the initial well region can be better adapted to the structure of the laterally diffused metal-oxide-semiconductor transistor, thereby improving the overall isolation effect of the first isolation well region and the initial well region and improving device performance.

[0079] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: A substrate, the substrate comprising a plurality of first regions and an isolation region located between adjacent first regions; The first doped well region located within the first region; An initial well region is located within the isolation region, the conductivity type of the initial well region is opposite to that of the first doped well region, and the initial well region is in contact with the first doped well region; A first isolation well region is located within the first doped well region. The conductivity type of the first isolation well region is opposite to that of the first doped well region. The distance from the edge of the first isolation well region to the edge of the initial well region is greater than zero and less than half the width of the initial well region, where the width is the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions.

2. The semiconductor structure of claim 1, wherein, The number of first isolation well regions in each first doped well region is equal to 1.

3. The semiconductor structure of claim 1, wherein, Each first doped well region has a number of first isolation well regions greater than 1.

4. The semiconductor structure of claim 1, wherein, Also includes: Laterally diffused metal-oxide-semiconductor transistor located in the first region.

5. The semiconductor structure of claim 4, wherein, The laterally diffused metal-oxide-semiconductor transistor includes: a second doped well region located on the first region, the second doped well region being located on the side of the first doped well region away from the initial well region; a gate oxide layer spanning the first doped well region and the second doped well region and a gate structure located on the gate oxide layer; a source region and a drain region located on both sides of the gate structure, the source region being located within the second doped well region and the drain region being located within the first doped well region.

6. The semiconductor structure of claim 5, wherein, The first doped well region contains N-type conductive ions; the initial well region contains P-type conductive ions.

7. The semiconductor structure of claim 5, wherein, The second doped well region contains P-type conductive ions.

8. The semiconductor structure of claim 5, wherein, The first isolation trap region contains P-type conductive ions.

9. The semiconductor structure of claim 1, wherein, The depth of the first doped well region ranges from 8 micrometers to 10 micrometers.

10. The semiconductor structure of claim 1, wherein, The width of the initial well region ranges from 5 micrometers to 10 micrometers.

11. The semiconductor structure of claim 1, wherein, The distance from the edge of the first isolation trap region to the edge of the initial trap region ranges from 2 micrometers to 5 micrometers.

12. The semiconductor structure of claim 1, wherein, The doped ion concentration in the first isolation well region may be the same as or different from the doped ion concentration in the initial well region.

13. The semiconductor structure of claim 1, wherein, The depth of the first isolation trap region may be the same as or different from the depth of the initial trap region.

14. A method of forming a semiconductor structure, comprising: include: A substrate is provided, the substrate comprising a plurality of first regions and an isolation region located between adjacent first regions; A first doped well region is formed within the first region; An initial well region is formed within the isolation region, the conductivity type of the initial well region being opposite to that of the first doped well region, and the initial well region being in contact with the first doped well region; A first isolation well region is formed within the first doped well region. The conductivity type of the first isolation well region is opposite to that of the first doped well region. The distance from the edge of the first isolation well region to the edge of the initial well region is greater than zero and less than half the width of the initial well region, where the width is the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The distance from the edge of the first isolation trap region to the edge of the initial trap region ranges from 2 micrometers to 5 micrometers.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The doped ion concentration of the first isolation well region is the same as that of the initial well region, the depth of the first isolation well region is the same as that of the initial well region, and the first isolation well region and the initial well region are formed simultaneously.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The doped ion concentration of the first isolation well region is different from that of the initial well region, and the depth of the first isolation well region is different from that of the initial well region.

18. The method for forming a semiconductor structure as described in claim 14, characterized in that, The number of first isolation well regions in each first doped well region is equal to 1.

19. The method for forming a semiconductor structure as described in claim 14, characterized in that, Each first doped well region has a number of first isolation well regions greater than 1.

20. The method for forming a semiconductor structure as described in claim 14, characterized in that, Also includes: A laterally diffused metal-oxide-semiconductor transistor is formed on the first region.

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