A low-capacitance, low-clamping longitudinal SCR device for ESD protection

Abstract

This invention relates to a low-capacitance, low-clamping vertical SCR device for ESD protection, comprising an N-type silicon substrate, a P-type epitaxial layer formed on the front side of the N-type silicon substrate, a back metal layer formed on the back side, and deep trench metal interconnects within the substrate; each deep trench metal interconnect is filled with aluminum, with one end connected to the back metal layer and the other end extending into the P-type epitaxial layer, forming a short-circuit via structure; an N-type epitaxial layer is disposed on the P-type epitaxial layer, and an N-type buried layer is disposed between the P-type and N-type epitaxial layers; a heavily doped P-type region and an isolation trench are formed on the N-type epitaxial layer; the isolation trench sequentially passes through the N-type buried layer and the P-type epitaxial layer, extending into the N-type silicon substrate; the heavily doped P-type region is connected to the front metal layer; a dielectric layer is formed on the heavily doped P-type region and the N-type epitaxial layer. This invention has a simple structure, low cost, and strong ESD and surge protection capabilities, meeting application requirements.

Description

Technical Field

[0001] This invention belongs to the field of electrostatic discharge protection technology, and particularly relates to a low-capacitance, low-clamping longitudinal SCR device for ESD protection. Background Technology

[0002] Silicon controlled rectifiers (SCRs) are widely used in power devices. Because they can switch between high and low resistance states, they can be used as power switches. They are also commonly used for electrostatic discharge (ESD) protection, possessing excellent electrostatic discharge capabilities to better meet requirements. Compared to diodes, transistors, and field-effect transistors, their positive feedback mechanism gives SCRs advantages such as strong current discharge capability, high discharge efficiency per unit area, low on-resistance, strong robustness, and high protection level. This allows for achieving high ESD protection levels with a relatively small chip area on a semiconductor planar process.

[0003] As process linewidths shrink, IC chips become increasingly fragile, demanding higher protection capabilities and lower forward and reverse clamping voltages from ESD and surge protection devices. Currently, most existing ESD and surge protection devices utilize PN junction structures, but these devices suffer from high clamping voltage, poor protection, and high capacitance. With the increasing frequency of IC chip applications, high-impedance protection devices will struggle to meet the demands of these applications. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a low-capacitance, low-clamping-voltage longitudinal SCR device with simple structure, low cost, and strong ESD and surge protection capabilities.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A low-capacitance, low-clamping longitudinal SCR device for ESD protection includes an N-type silicon substrate. A P-type epitaxial layer is formed on the front side of the N-type silicon substrate, and a back metal layer is formed on the back side. Multiple deep trench metal connection holes are also provided inside the substrate at intervals. Each deep trench metal connection hole is filled with aluminum, and one end of the hole is connected to the back metal layer, while the other end extends out of the front side of the N-type silicon substrate and penetrates into the P-type epitaxial layer to form a short-circuit hole structure.

[0007] An N-type epitaxial layer is disposed on the P-type epitaxial layer, and an N-type buried layer is disposed between the P-type epitaxial layer and the N-type epitaxial layer; a P-type heavily doped region is formed on the N-type epitaxial layer, and isolation deep trenches are located on both sides of the P-type heavily doped region.

[0008] The isolation trench extends downwards, passing through the N-type buried layer and the P-type epitaxial layer in sequence, and penetrates into the N-type silicon substrate; the P-type heavily doped region is in contact with the front metal layer; a dielectric layer is formed on the P-type heavily doped region and the N-type epitaxial layer, and the dielectric layer is located around the front metal layer.

[0009] The aforementioned low-capacitance, low-clamping vertical SCR device for ESD protection has a front metal layer connected to a P-type heavily doped region as the anode of the SCR device; and a back metal layer connected to an N-type silicon substrate as the cathode of the SCR device.

[0010] The aforementioned low-capacitance, low-clamping longitudinal SCR device for ESD protection comprises an N-type buried layer and an N-type epitaxial layer forming the base region of a PNP structure, which can also serve as the emitter region of an NPN structure; the P-type epitaxial layer serves as the base region of an NPN structure; and the N-type silicon substrate serves as the collector region of an NPN structure.

[0011] The aforementioned low-capacitance, low-clamping longitudinal SCR device for ESD protection has a P-type heavily doped region implanted with boron, with an implantation energy of 80 keV to 100 keV and a dose of 2e14 to 1e16.

[0012] The aforementioned low-capacitance, low-clamping longitudinal SCR device for ESD protection has an N-type epitaxial layer with a thickness of 3µm to 9µm and an epitaxial resistivity of 5Ω·cm to 100Ω·cm.

[0013] The aforementioned low-capacitance, low-clamping longitudinal SCR device for ESD protection has an N-type buried layer with phosphorus implantation, an implantation energy of 70keV to 120keV, and a dose of 5e13 to 2e15.

[0014] The aforementioned low-capacitance, low-clamping longitudinal SCR device for ESD protection has a P-type epitaxial layer with a thickness of 3µm to 10µm and a resistivity of 0.01Ω·cm to 0.4Ω·cm.

[0015] The aforementioned low-capacitance, low-clamping longitudinal SCR device for ESD protection comprises an 8k-10k deposited borosilicate glass layer, a 4µm high-silicon aluminum alloy front metal layer, and a 150µm titanium-nickel-silver alloy target back metal layer.

[0016] The aforementioned low-capacitance, low-clamping longitudinal SCR device for ESD protection uses an N-type silicon substrate with a resistivity of 0.002–0.006 Ω·cm. <100> Material formation with crystal orientation.

[0017] The technical effects and advantages of this invention are as follows:

[0018] 1. This invention provides a low-capacitance, low-clamping longitudinal SCR device for ESD protection. Its capacitance is equivalent to three PN capacitors connected in series, with the total capacitance less than the minimum of the three. The device capacitance is primarily determined by the PN junction with the smallest capacitance in the structure. In this invention, the PN junction capacitance formed by the heavily doped P-type region and the N-type epitaxial layer is very small because the area and depth of the heavily doped P-type region are small, and the concentration of the N-type epitaxial layer is very low. The lower the SCR holding current IH, the lower its clamping voltage. The amplification factor of the PNP structure (composed of a heavily doped P-type region, an N-type epitaxial layer, an N-type buried layer, and a P-type epitaxial layer) and the NPN structure (composed of an N-type buried layer, a P-type epitaxial layer, and an N-type silicon substrate) can change their holding current. By increasing the depth or reducing the area of ​​the heavily doped P-type region, reducing the concentration and thickness of the N-type epitaxial layer, reducing the concentration or depth of the N-type buried layer, and reducing the concentration or thickness of the P-type epitaxial layer, a low clamping voltage can be obtained.

[0019] 2. The present invention provides a low-capacitance, low-clamping longitudinal SCR device for ESD protection, which effectively reduces the parasitic capacitance of the SCR device by using a set isolation deep trench for isolation.

[0020] 3. The present invention provides a low-capacitance, low-clamping longitudinal SCR device for ESD protection. By using deep-groove metal connection holes in the cathode of the longitudinal NPN structure and the anode of the PNP structure, the switching characteristics and sustaining current characteristics of the SCR device are improved. Attached Figure Description

[0021] Figure 1 This is a cross-sectional structural schematic diagram of the present invention;

[0022] Figure 2 This is a schematic diagram of step 2 of the present invention for fabricating a low-capacitance, low-clamping longitudinal SCR device;

[0023] Figure 3 This is a schematic diagram of step 3 in the fabrication of the low-capacitance, low-clamp longitudinal SCR device according to the present invention.

[0024] Figure 4 This is a schematic diagram of step 4 in the fabrication of the low-capacitance, low-clamp longitudinal SCR device according to the present invention.

[0025] Figure 5 This is a schematic diagram of steps 5 and 6 of the present invention for fabricating a low-capacitance, low-clamp longitudinal SCR device;

[0026] Figure 6 This is a schematic diagram of steps 7 and 8 of the present invention for fabricating a low-capacitance, low-clamping longitudinal SCR device;

[0027] Figure 7This is a schematic diagram of step 9 in the fabrication of a low-capacitance, low-clamp longitudinal SCR device according to the present invention.

[0028] Figure 8 This is a schematic diagram of the IV characteristic curve of the low-capacitance, low-clamping longitudinal SCR device of the present invention.

[0029] The following labels are used in the figure: 101, N-type silicon substrate; 102, P-type epitaxial layer; 103, N-type buried layer; 104, N-type epitaxial layer; 105, P-type heavily doped region; 106, isolation trench; 107, dielectric layer; 108, front metal layer; 109, deep trench metal interconnect; 110, back metal layer. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the embodiments given in the accompanying drawings.

[0031] See Figure 1 As shown, a low-capacitance, low-clamping longitudinal SCR device for ESD protection includes an N-type silicon substrate 101. A P-type epitaxial layer 102 is formed on the front side of the N-type silicon substrate 101, and a back metal layer 110 is formed on the back side. Multiple deep trench metal connection holes 109 are also provided at intervals inside the substrate. Each deep trench metal connection hole 109 is filled with aluminum, and one end of the hole is connected to the back metal layer 110, while the other end extends out of the front side of the N-type silicon substrate 101 and penetrates into the P-type epitaxial layer 102 to form a short-circuit hole structure.

[0032] An N-type epitaxial layer 104 is disposed on the P-type epitaxial layer 102, and an N-type buried layer 103 is disposed between the P-type epitaxial layer 102 and the N-type epitaxial layer 104; a P-type heavily doped region 105 is formed on the N-type epitaxial layer 104, and isolation deep trenches 106 are located on both sides of the P-type heavily doped region 105.

[0033] The isolation trench 106 extends downward, passing through the N-type buried layer 103 and the P-type epitaxial layer 102 in sequence, and penetrates into the N-type silicon substrate 101; the P-type heavily doped region 105 is in contact with the front metal layer 108; a dielectric layer 107 is formed on the P-type heavily doped region 105 and the N-type epitaxial layer 104, and the dielectric layer 107 is located around the front metal layer 108.

[0034] In a specific implementation, the front metal layer 108 is connected to the P-type heavily doped region 105 to form the anode of the SCR device; the back metal layer 109 is connected to the N-type silicon substrate 101 to form the cathode of the SCR device.

[0035] Furthermore, the N-type buried layer 103 and the N-type epitaxial layer 104 constitute the base region of the PNP structure and can also serve as the emitter region of the NPN structure; the P-type epitaxial layer 102 serves as the base region of the NPN structure; and the N-type silicon substrate 101 serves as the collector region of the NPN structure.

[0036] Specifically, the capacitance of the SCR device in this application is equivalent to three PN capacitors connected in series, and the total capacitance is less than the minimum value among the three. That is, the device capacitance is basically determined by the PN junction with the smallest capacitance in the structure. In this invention, the PN junction capacitance formed by the P-type heavily doped region 105 and the N-type epitaxial layer 104 is very small because the P-type heavily doped region 105 has a small area and shallow depth, and the N-type epitaxial layer 104 has a low concentration. Generally, the smaller the holding current IH of the SCR, the lower its clamping voltage. The amplification factor of the PNP structure composed of the P-type heavily doped region 105, the N-type epitaxial layer 104, the N-type buried layer 103 and the P-type epitaxial layer 102 and the NPN structure composed of the N-type buried layer 103, the P-type epitaxial layer 102 and the N-type silicon substrate 101 can change their holding current.

[0037] Furthermore, by increasing the depth or reducing the area of ​​the heavily doped P-type region 105; reducing the concentration and thickness of the N-type epitaxial layer 104; reducing the concentration or depth of the N-type buried layer 103; and reducing the concentration or thickness of the P-type epitaxial layer 102, these adjustments can be easily achieved, thereby obtaining a low clamping voltage.

[0038] In specific implementation, the P-type heavily doped region 105 of this application is implanted with boron, and the implantation energy is 80keV to 100keV, and the dose is 2e14 to 1e16.

[0039] In specific implementation, the thickness of the N-type epitaxial layer 104 in this application is 3um to 9um, and its epitaxial resistivity is 5Ω·cm to 100Ω·cm.

[0040] In specific implementation, the N-type buried layer 103 is phosphorus implanted, with an implantation energy of 70keV to 120keV and a dose of 5e13 to 2e15.

[0041] In a specific implementation, the thickness of the P-type epitaxial layer 102 is 3µm to 10µm, and its resistivity is 0.01Ω·cm to 0.4Ω·cm.

[0042] In a specific implementation, the dielectric layer 107 is an 8k-10k deposited borosilicate glass layer; the front metal layer 108 is a 4µm high-silicon aluminum alloy; and the back metal layer 109 is a 150µm titanium-nickel-silver alloy target.

[0043] In specific implementation, the N-type silicon substrate 101 has a resistivity of 0.002–0.006 Ω·cm. <100> Material formation with crystal orientation.

[0044] This application improves the switching characteristics and sustaining current characteristics of the SCR device by using deep-groove metal connection holes 109 in the vertical NPN structure cathode and PNP structure anode of the SCR device and filling the deep-groove metal connection holes 109 with aluminum.

[0045] join Figure 8 The diagram shows the IV characteristic curve of the low-capacitance, low-clamping longitudinal SCR device of this application. When a positive voltage is applied to the anode, and the voltage is less than the reverse breakdown voltage of the PN junction formed by the N-type buried layer 103 and the P-type epitaxial layer 102, almost no current flows through the device, resulting in a cutoff state (0→VRWM). When the voltage increases to a value greater than this breakdown voltage, current begins to flow through the circuit. The current path is: (108→105→104→103→102→109→110). As the voltage increases... As the current increases (VRWM→VT), the forward voltage of the PN junction formed by the P-type epitaxial layer 102 and the N-type silicon substrate 101 also increases. When this voltage exceeds its forward turn-on voltage, PNPN is triggered to turn on (VT→VH) (current path at this time: 108→105→104→103→102→101→110). Due to its negative resistance characteristics, the voltage across the device decreases rapidly and reaches its lowest point VH when the current is IH. After that, it increases slowly as the current increases.

[0046] See 2- Figure 7 As shown, the fabrication method of the low-capacitance, low-clamp longitudinal SCR device of this application includes the following steps:

[0047] 1) Use materials with resistivity of 0.002~0.006Ω·cm. <100> The crystal orientation material is used as the N-type silicon substrate 101;

[0048] 2) For example Figure 2 As shown, a P-type epitaxial layer 102 is grown on an N-type silicon substrate 101 using an epitaxial process. The resistivity of the P-type epitaxial layer 102 is 0.01 to 0.4 Ω·cm, and the thickness is 2 μm to 8 μm.

[0049] 3) For example Figure 3 As shown, an N-type buried layer 103 is formed using Photo, Implant, and Drive In processes. The process conditions for forming the N-type buried layer 103 are as follows: phosphorus implantation, implantation energy of 100keV to 120keV, and dosage of 1e15 to 2e14; annealing conditions are: temperature of 1100℃ and time of 20min to 60min.

[0050] 4) For example Figure 4 As shown, an N-type epitaxial layer 104 is generated using an epitaxial process. The epitaxial resistivity of the N-type epitaxial layer 104 is 5 to 100 Ω·cm, and the thickness ranges from 3 μm to 9 μm.

[0051] 5) For example Figure 5 As shown, the P-type heavily doped region 105 is formed using Photo, Implant, and Drive In processes. The formation process conditions for the P-type heavily doped region 105 are as follows: the PSD is boron implantation at 80keV to 100keV with a dose of 7e15 to 1e16; the annealing conditions are: temperature 950 to 1050℃ and time 20 min to 50 min.

[0052] 6) For example Figure 5 As shown, vertical isolation trenches 106 are formed on both sides of the heavily doped P-type region 105. The isolation trenches 106 pass through the N-type epitaxial layer 104, the N-type buried layer 103 and the P-type epitaxial layer 102, and extend into the N-type silicon substrate 101.

[0053] 7) For example Figure 6 As shown, the front metal layer 108 and the P-type heavily doped region 105 are connected to the device anode using Photo, Etch, Sputter, and Alloy processes; and the dielectric layer 107 is formed using PECVD process, with BPSG deposited at 8k to 10k.

[0054] 8) For example Figure 6 As shown, six deep trench metal connection holes 109 are spaced apart on the back side of the N-type silicon substrate 101 and extend into the P-type epitaxial layer 102, and the deep trench metal connection holes 109 are filled with aluminum.

[0055] 9) For example Figure 7 As shown, a thinning and back metallization process is used to connect the back metal layer 110 to the N-type silicon substrate 101 to lead out the cathode Cathode.

[0056] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A low-capacitance, low-clamping longitudinal SCR device for ESD protection, characterized in that: The substrate includes an N-type silicon substrate (101), on which a P-type epitaxial layer (102) is formed on the front side and a back metal layer (110) is formed on the back side. Multiple deep trench metal connection holes (109) are also provided at intervals inside the substrate. Each deep trench metal connection hole (109) is filled with aluminum, and one end of the hole is connected to the back metal layer (110), while the other end extends out of the front side of the N-type silicon substrate (101) and penetrates into the P-type epitaxial layer (102) to form a short-circuit hole structure. An N-type epitaxial layer (104) is disposed on the P-type epitaxial layer (102), and an N-type buried layer (103) is disposed between the P-type epitaxial layer (102) and the N-type epitaxial layer (104); a P-type heavily doped region (105) is formed on the N-type epitaxial layer (104), and isolation deep trenches (106) are located on both sides of the P-type heavily doped region (105); The isolation trench (106) extends downward, passing through the N-type buried layer (103) and the P-type epitaxial layer (102) in sequence, and penetrates into the N-type silicon substrate (101); the P-type heavily doped region (105) is in contact with the front metal layer (108); a dielectric layer (107) is formed on the P-type heavily doped region (105) and the N-type epitaxial layer (104), and the dielectric layer (107) is located around the front metal layer (108); The front metal layer (108) is connected to the P-type heavily doped region (105) to form the anode of the SCR device; the back metal layer (110) is connected to the N-type silicon substrate (101) to form the cathode of the SCR device.

2. A low-capacitance, low-clamping longitudinal SCR device for ESD protection according to claim 1, characterized in that: The N-type buried layer (103) and the N-type epitaxial layer (104) constitute the base region of the PNP structure and can also serve as the emitter region of the NPN structure; the P-type epitaxial layer (102) serves as the base region of the NPN structure; and the N-type silicon substrate (101) serves as the collector region of the NPN structure.

3. A low-capacitance, low-clamping longitudinal SCR device for ESD protection according to claim 1, characterized in that: The P-type heavily doped region (105) is implanted with boron, with an implantation energy of 80 keV to 100 keV and a dose of 2e14 to 1e16.

4. A low-capacitance, low-clamping longitudinal SCR device for ESD protection according to claim 1, characterized in that: The thickness of the N-type epitaxial layer (104) is 3µm to 9µm, and its epitaxial resistivity is 5Ω·cm to 100Ω·cm.

5. A low-capacitance, low-clamping longitudinal SCR device for ESD protection according to claim 1, characterized in that: The N-type buried layer (103) is phosphorus implanted with an implantation energy of 70keV to 120keV and a dose of 5e13 to 2e15.

6. A low-capacitance, low-clamping longitudinal SCR device for ESD protection according to claim 1, characterized in that: The thickness of the P-type epitaxial layer (102) is 3um to 10um, and its resistivity is 0.01Ω·cm to 0.4Ω·cm.

7. A low-capacitance, low-clamping longitudinal SCR device for ESD protection according to claim 1, characterized in that: The dielectric layer (107) is an 8k-10k deposited borosilicate glass layer; the front metal layer (108) is a 4µm high-silicon aluminum alloy; and the back metal layer (110) is a 150µm titanium-nickel-silver alloy target.

8. A low-capacitance, low-clamping longitudinal SCR device for ESD protection according to claim 1, characterized in that: The N-type silicon substrate (101) has a resistivity of 0.002–0.006 Ω·cm. <100> Material formation with crystal orientation.

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