Memory read circuit

Abstract

The present invention provides a memory reading circuit, comprising: a reference resistor; a switch module, one side of which is connected to the reference resistor and a variable resistor of the memory, and is used to control the on-off between the reference resistor and the variable resistor of the memory and a clamping module; a clamping module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of a node between the clamping module and the switch module in a precharging step; a cross-coupling output module, one side of which is connected to the other side of the clamping module, and is used to convert a difference current formed in the precharging step into an output signal and an inverted output signal with a difference of a power supply voltage through positive feedback; and a precharging module, which is connected to the other side of the cross-coupling output module and is used to precharge the memory reading circuit.

Description

Technical Field

[0001] The invention relates to a reading circuit of a memory. Background Art

[0002] Resistive Random Access Memory (RRAM) is an emerging non-volatile storage technology based on the reversible conversion of the resistance of non-conductive materials between high resistance and low resistance under the action of an external electric field. It has the high-speed read and write capabilities of static random access memory, the high integration of dynamic random access memory, and can basically achieve unlimited data writing. After applying different voltage conditions, RRAM can show two resistance states of high and low resistance and can permanently retain stored data after power failure. RRAM is currently mainly used in IoT devices, neural networks, artificial intelligence and other fields. In terms of commercialization, RRAM has two main application directions-storage applications and storage and computing applications. In terms of storage applications, some manufacturers have applied RRAM to the MCU field; in terms of storage and computing integration, some companies are currently trying to realize AI high-computing chips based on RRAM through a storage and computing integrated architecture, and apply them in application scenarios on the center and edge sides.

[0003] The way to read RRAM storage information is to convert its resistance signal into a current or voltage signal that can be read by the peripheral circuit. As the process continues to be optimized, the current reading structure of RRAM memory faces problems such as high power consumption, slow speed and large area. An existing RRAM reading circuit is as follows Figure 1 As shown. The transistors M0 and M1 of the same size are used as switch tubes to connect the read circuit and the array resistors during the period when the read enable voltage Vread is pulled high. The LDO (Low Dropout Regulaor) structure composed of the transistors M2 and M3 of the same size and two identical OTAs (Operational Transconductance Amplifiers) clamps the voltages at points A and B, and converts the information of the variable resistor of the RRAM and the information of the reference resistor into current information. The two currents generated at points A and B are respectively sent to the transistors M4 and M5 of the same size. The transistors M4 and M5 are PMOS transistors connected as diodes, which can convert the current information into voltage information and send it to the two ends of the comparator CMP for comparison, and then output the read data Dout.

[0004] In addition, magnetoresistive random access memory (MRAM) is a non-volatile magnetic random access memory. MRAM has the high-speed read and write capabilities of static random access memory (SRAM) and the high integration of dynamic random access memory (DRAM), and can basically be rewritten indefinitely. Unlike traditional RAM technology, MRAM does not store data in the form of charge or current, but magnetically stores data in the form of magnetic tunnel junctions (MTJ). MTJ is the basic storage unit of MRAM, and its core part is a nano-multilayer film with a sandwich structure consisting of two ferromagnetic metal layers sandwiching a tunnel barrier layer. One of the ferromagnetic layers is called a reference layer or a fixed layer, and its magnetization is fixed along the easy magnetization axis. The other ferromagnetic layer is called a free layer, and its magnetization has two stable orientations, which are parallel or antiparallel to the reference layer. In addition, the data in MRAM is stored in a magnetic state and is sensed by measuring resistance, so the reading circuit of MRAM is similar to the principle and structure of the reading circuit of RRAM. Summary of the invention

[0005] Although the above RRAM read circuit can realize the reading of RRAM resistance information, the structure has the following defects. First, as the process node continues to shrink, the window between the high resistance and low resistance of RRAM is also shrinking; the above RRAM read circuit only generates two comparison currents in the storage unit and the reference unit and then converts them into comparison voltages, which does not increase the reading margin. As the resistance window decreases, there is a risk of reading failure. Secondly, the memory generally requires more than 8-bit output, which means that an RRAM memory requires at least 8 read circuits to output data in parallel, and the structure of the above RRAM read circuit will occupy at least 16 operational transconductance amplifiers (OTA) area, which will affect the storage density of the chip. In addition, the operational transconductance amplifier and comparator of the structure will consume a large amount of power, and if the accuracy and setup time are required to be improved, the power consumption will be higher. In addition, since the principle and structure of the MRAM read circuit are similar to those of the RRAM read circuit, the same problem also exists in the existing MRAM read circuit.

[0006] The present invention is proposed in view of the above situation, and its purpose is to provide a memory reading circuit, which includes a reference resistor, a switch module, a clamping module, a cross-coupled output module, and a pre-charge module. Through a pre-charge step and a comparison read step, the read enable voltage, the clamping voltage, and the pre-charge voltage are set so that the memory reading circuit can be used for reading, so as to convert the resistance signal of the variable resistor of the memory into an output signal whose difference is the power supply voltage and an inverted output signal.

[0007] Technical solutions to technical problems

[0008] In order to solve the above problem, the memory reading circuit involved in the first aspect of the present invention includes:

[0009] Reference resistor;

[0010] A switch module, one side of which is connected to the reference resistor and the variable resistor of the memory, and is used to control the on-off between the reference resistor and the variable resistor of the memory and the clamp module;

[0011] A clamping module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of the node between the clamping module and the switch module in the pre-charging step;

[0012] a cross-coupling output module, one side of which is connected to the other side of the clamping module, and is used to convert the difference current formed in the pre-charging step into an output signal with a difference of a power supply voltage and an inverted output signal through positive feedback; and

[0013] A pre-charging module is connected to the other side of the cross-coupling output module and is used to pre-charge the read circuit of the memory.

[0014] Furthermore, the memory is RRAM or MRAM.

[0015] Furthermore, the reading circuit of the memory performs the following steps when reading:

[0016] a precharging step for charging a first output terminal and a second output terminal of a read circuit of the memory to a power supply voltage; and

[0017] A comparison readout step is used to convert the difference current formed in the pre-charging step into an output signal whose difference is the power supply voltage and an inverted output signal through positive feedback.

[0018] Further, the switch module includes a first transistor and a tenth transistor,

[0019] The clamping module includes a second transistor and a third transistor.

[0020] The cross-coupled output module includes a fourth transistor, a fifth transistor, an eighth transistor and a ninth transistor,

[0021] The pre-charging module includes a sixth transistor and a seventh transistor,

[0022] The source of the tenth transistor is connected to the variable resistor of the RRAM, the gate of the tenth transistor is connected to the gate of the first transistor, the drain of the tenth transistor is connected to the source of the second transistor, the source of the first transistor is connected to the reference resistor, and the drain of the first transistor is connected to the source of the third transistor.

[0023] The gate of the second transistor is connected to the gate of the third transistor, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the third transistor is connected to the source of the fifth transistor.

[0024] The gate of the fourth transistor is connected to the gate of the eighth transistor, the drain of the fifth transistor, the drain of the ninth transistor, the drain of the seventh transistor, and the first output terminal of the read circuit of the memory,

[0025] The gate of the fifth transistor is connected to the gate of the ninth transistor, the drain of the fourth transistor, the drain of the eighth transistor, the drain of the sixth transistor, and the second output terminal of the read circuit of the memory,

[0026] The gate of the sixth transistor is connected to the gate of the seventh transistor, the source of the sixth transistor is connected to the source of the seventh transistor, the source of the eighth transistor, and the source of the ninth transistor,

[0027] The driving capability of the ninth transistor is higher than that of the fifth transistor, and the driving capability of the eighth transistor is higher than that of the fourth transistor.

[0028] A power supply voltage is applied to the source of the sixth transistor, the source of the seventh transistor, the source of the eighth transistor, and the source of the ninth transistor,

[0029] A read enable voltage is applied to the gate of the tenth transistor and the gate of the first transistor, a clamp voltage is applied to the gate of the second transistor and the gate of the third transistor, and a precharge voltage is applied to the gate of the sixth transistor and the gate of the seventh transistor.

[0030] The read enable voltage, the clamp voltage, and the precharge voltage are set so that the memory can be read using a read circuit to convert the resistance signal of the variable resistor of the RRAM into an output signal with a difference of a power supply voltage and an inverted output signal.

[0031] Further, a node between the drain of the tenth transistor and the source of the second transistor is set to L1, and a node between the drain of the first transistor and the source of the third transistor is set to L2,

[0032] The reading circuit of the memory performs the following steps when reading:

[0033] a precharging step, in which the read enable voltage is set to a high level and the precharging voltage is set to a low level, so that the tenth transistor, the first transistor, the sixth transistor, and the seventh transistor are turned on, so that the first output terminal and the second output terminal are charged to the power supply voltage, and L1 and L2 are clamped at the clamping voltage; and

[0034] A comparison readout step, in which the read enable voltage is maintained at a high level, and the pre-charge voltage is set to a high level, so that the tenth transistor and the first transistor remain turned on, and the sixth transistor and the seventh transistor are turned off, so as to convert the difference current formed in the pre-charge step into an output signal and an inverted output signal whose difference is the power supply voltage through positive feedback.

[0035] Furthermore, in the comparison and reading step,

[0036] When the resistance value of the variable resistor of the memory is lower than the resistance value of the reference resistor, the voltage of the second output terminal decreases faster than the voltage of the first output terminal in the initial stage, so that the ninth transistor is turned on before the eighth transistor, and the driving capability of the ninth transistor is higher than that of the fifth transistor, so that the voltage of the first output terminal stops decreasing and rises to the power supply voltage, and the voltage of the second output terminal decreases to 0.

[0037] When the resistance of the variable resistor of the memory is higher than the resistance of the reference resistor, the voltage of the first output terminal drops faster than the voltage of the second output terminal in the initial stage, so that the eighth transistor is turned on before the ninth transistor, and by utilizing the characteristic that the driving capability of the eighth transistor is higher than that of the fourth transistor, the voltage of the second output terminal stops dropping and rises to the power supply voltage, and the voltage of the first output terminal drops to 0.

[0038] Furthermore, the lowest value of the high resistance of the variable resistor of the memory is set to R H , the maximum value of the low resistance of the variable resistor of the memory is set to R L , set the resistance of the reference resistor to R ref ,

[0039] The resistance of the reference resistor is calculated by the following formula:

[0040]

[0041] Furthermore, the high resistance of the variable resistor of the memory is greater than 500KΩ, the low resistance of the variable resistor of the memory is less than 100KΩ, and the resistance value of the reference resistor is 166.67KΩ.

[0042] Furthermore, the high resistance of the variable resistor of the memory is greater than 40KΩ, the low resistance of the variable resistor of the memory is less than 10KΩ, and the resistance value of the reference resistor is 16KΩ.

[0043] Further, the specification of the tenth transistor is the same as that of the first transistor,

[0044] The specification of the second transistor is the same as that of the third transistor,

[0045] The specification of the fourth transistor is the same as that of the fifth transistor,

[0046] The specification of the sixth transistor is the same as that of the seventh transistor,

[0047] The specification of the eighth transistor is the same as the specification of the ninth transistor.

[0048] Further, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the tenth transistor are NMOS transistors, and the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS transistors.

[0049] Effects of the Invention

[0050] In the present invention, the process of reading the resistance value of RRAM is mainly divided into two stages: a pre-charging stage and a comparison readout stage. In the pre-charging stage, since only the parasitic capacitance of the MOS transistor and the parasitic capacitance of the line connected to the RRAM array exist, a stable I L1 ,I L2In the comparison readout stage, a cross-coupled NMOS transistor and PMOS transistor pair consisting of a fourth transistor M4, a fifth transistor M5, a ninth transistor M9, and an eighth transistor M8 is used to convert the current signal into a voltage signal through positive feedback, thereby increasing the read margin, increasing the reliability of RRAM reading data, and greatly speeding up the comparison speed (for example, in a 28nm process, when the resistance of RRAM is 100KΩ and the line parasitic capacitance is 300fF, the complete read action time under normal process angle is within 1ns).

[0051] In addition, since the power supply voltage V core The parasitic capacitance between the variable resistor and the reference resistor of the RRAM is low, so the precharge time is short and the first output terminal D out and the second output terminal D outn Charge to the power supply voltage V core The power consumption is low and the clamping voltage V clamp Clamp the voltage of L1 and L2 to a low value, thus limiting I L1 with I L2 In addition, the cross-coupled positive feedback structure in the comparison readout stage makes the first output terminal D out and the second output terminal D outn It is quickly pulled to 0 or 1, after which the circuit no longer has dynamic current, so the power consumption generated by the entire readout process is very low.

[0052] In addition, in order to avoid miswriting of the variable resistor of the RRAM, a stable anti-interference clamping voltage V is required to be applied to the gate terminals of the second transistor M2 and the third transistor M3. clamp ; This structure has no floating point at any time, so it does not require a discharge transistor, and does not require structures such as an operational amplifier or a comparator, and occupies a small area.

[0053] In addition, since the principle and structure of the MRAM read circuit are similar to those of the RRAM read circuit, the MRAM read circuit can achieve a similar technical effect as the above-mentioned RRAM read circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 FIG. 4 is a circuit diagram showing the structure of a RRAM read circuit in the prior art.

[0055] Figure 2 Schematic diagram showing various modules of the RRAM reading circuit according to the embodiment of the present invention.

[0056] Figure 3 is a circuit diagram showing a specific structure of an RRAM reading circuit according to an embodiment of the present invention.

[0057] Figure 4 1 is a timing chart showing a reading method of the RRAM reading circuit according to the embodiment of the present invention.

[0058] Description of symbols

[0059] 101 Switch Module

[0060] 102 Clamp Module

[0061] 103 Cross-coupled output module

[0062] 104 Pre-charge module

[0063] M1 first transistor

[0064] M2 Second transistor

[0065] M3 The third transistor

[0066] M4 Fourth transistor

[0067] M5 Fifth transistor

[0068] M6 Sixth transistor

[0069] M7 Seventh transistor

[0070] M8 Eighth transistor

[0071] M9 Ninth transistor

[0072] M0 tenth transistor

[0073] D out First output terminal

[0074] D outn Second output terminal

[0075] V read Read Enable Voltage

[0076] V sa_pren Pre-charge voltage

[0077] V core Supply voltage

[0078] R cell Variable resistance of RRAM

[0079] R ref Reference resistor DETAILED DESCRIPTION

[0080] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation manners and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.

[0081] For convenience of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature.

[0082] Unless otherwise defined, the terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. The terms should be understood to have a meaning consistent with the context of the related art and should not be understood in an idealized or overly formalized manner unless clearly so defined herein.

[0083] Hereinafter, taking the RRAM read circuit and the MRAM read circuit as examples, the read circuit of the memory involved in the embodiment of the present invention will be described.

[0084] <RRAM read circuit>

[0085] Figure 2 is a schematic diagram showing each module of the RRAM read circuit involved in the embodiment of the present invention. Hereinafter, referring to Figure 2 , each module of the RRAM read circuit involved in the embodiment of the present invention will be described in detail.

[0086] As Figure 2 shown, the RRAM read circuit involved in the embodiment of the present invention includes a reference resistor R ref , a switch module 101, a clamping module 102, a cross-coupled output module 103, and a pre-charge module 104. One side of the switch module 101 is connected to the reference resistor R ref and the variable resistor R of the RRAM cell for connecting the reference resistor R ref and the variable resistor R of the RRAM cellThe on-off between the clamp module 102 and the switch module 101 is controlled. One side of the clamp module 102 is connected to the other side of the switch module 101, and is used to clamp the voltages of nodes L1 and L2 between the clamp module 102 and the switch module 101 in the pre-charging step. One side of the cross-coupling output module 103 is connected to the other side of the clamp module 102, and is used to convert the difference current formed in the pre-charging step into a difference of the power supply voltage V through positive feedback. core The precharge module 104 is connected to the other side of the cross-coupled output module 103 and is used to precharge the RRAM read circuit.

[0087] The RRAM read circuit performs the following steps when reading. First, a precharge step is performed to make the first output terminal D of the RRAM read circuit out and the second output terminal D outn Charge to power supply voltage V core Then, a comparison readout step is performed to convert the difference current formed in the pre-charging step into a difference of the power supply voltage V by positive feedback. core output signal and inverted output signal.

[0088] Specifically, in the RRAM read circuit involved in the embodiment of the present invention, the switch module 101 includes a first transistor M1 and a tenth transistor M0, the clamp module 102 includes a second transistor M2 and a third transistor M3, the cross-coupled output module 103 includes a fourth transistor M4, a fifth transistor M5, an eighth transistor M8 and a ninth transistor M9, and the pre-charge module 104 includes a sixth transistor M6 and a seventh transistor M7.

[0089] Figure 3 1 is a circuit diagram showing a specific structure of an RRAM reading circuit according to an embodiment of the present invention. Figure 3 , the specific structure of the RRAM reading circuit involved in the embodiment of the present invention is described in detail.

[0090] like Figure 3 As shown, the source of the tenth transistor M0 is connected to the variable resistor R cell The gate of the tenth transistor M0 is connected to the gate of the first transistor M1, the drain of the tenth transistor M0 is connected to the source of the second transistor M2, the source of the first transistor M1 is connected to the reference resistor Rref, and the drain of the first transistor M1 is connected to the source of the third transistor M3.

[0091] The gate of the second transistor M2 is connected to the gate of the third transistor M3 , the drain of the second transistor M2 is connected to the source of the fourth transistor M4 , and the drain of the third transistor M3 is connected to the source of the fifth transistor M5 .

[0092] The gate of the fourth transistor M4 is connected to the gate of the eighth transistor M8, the drain of the fifth transistor M5, the drain of the ninth transistor M9, the drain of the seventh transistor M7, and the first output terminal D of the RRAM read circuit. out The gate of the fifth transistor M5 is connected to the gate of the ninth transistor M9, the drain of the fourth transistor M4, the drain of the eighth transistor M8, the drain of the sixth transistor M6, and the second output terminal D of the RRAM read circuit. outn connect.

[0093] The gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7 , and the source of the sixth transistor M6 is connected to the source of the seventh transistor M7 , the source of the eighth transistor M8 , and the source of the ninth transistor M9 .

[0094] The driving capability of the ninth transistor M9 is higher than that of the fifth transistor M5 , and the driving capability of the eighth transistor M8 is higher than that of the fourth transistor M4 .

[0095] The source of the sixth transistor M6, the source of the seventh transistor M7, the source of the eighth transistor M8, and the source of the ninth transistor M9 are applied with the power supply voltage V core .

[0096] The gate of the tenth transistor M0 and the gate of the first transistor M1 are applied with a read enable voltage V read , the gate of the second transistor M2 and the gate of the third transistor M3 are applied with a clamping voltage V clamp , the gate of the sixth transistor M6 and the gate of the seventh transistor M7 are applied with a pre-charge voltage V sa_pren .

[0097] Read enable voltage V read , Clamping voltage V clamp , pre-charge voltage V sa_pren It is set to be read by the RRAM read circuit to convert the resistance signal of the variable resistor of the RRAM into a difference of the power supply voltage V core output signal and inverted output signal.

[0098] In the present invention, preferably, the specification of the tenth transistor M0 is the same as that of the first transistor M1, the specification of the second transistor M2 is the same as that of the third transistor M3, the specification of the fourth transistor M4 is the same as that of the fifth transistor M5, and the specification of the sixth transistor M6 is the same as that of the seventh transistor M7, but the present invention is not limited thereto. In addition, preferably, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the tenth transistor M0 are NMOS transistors, and the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are PMOS transistors, but the present invention is not limited thereto.

[0099] Next, the reading operation of the RRAM reading circuit according to the embodiment of the present invention will be described in detail. Figure 4 1 is a timing chart showing a reading method of the RRAM reading circuit according to the embodiment of the present invention.

[0100] Here, a node between the drain of the tenth transistor M0 and the source of the second transistor M2 is set as L1, and a node between the drain of the first transistor M1 and the source of the third transistor M3 is set as L2.

[0101] Specifically, in the present invention, the RRAM reading circuit performs the following steps when reading.

[0102] (1) First, perform the pre-charge step (corresponding to Figure 3 That is, the read enable voltage V read Set to high level, the precharge voltage V sa_pren = is set to a low level, so that the tenth transistor M0, the first transistor M1, the sixth transistor M6, and the seventh transistor M7 are turned on, so that the first output terminal D out and the second output terminal D outn Charge to power supply voltage V core , and clamp L1 and L2 at the clamping voltage V clamp .

[0103] (2) Then, a comparison readout step (corresponding to Figure 3 That is, the read enable voltage V read Keep it high, the precharge voltage V sa_pren = is set to a high level, so that the tenth transistor M0 and the first transistor M1 remain turned on, and the sixth transistor M6 and the seventh transistor M7 are turned off, so as to convert the difference current formed in the pre-charging step into a difference of the power supply voltage V through positive feedback. core output signal and inverted output signal.

[0104] More specifically, in the initial state, the RRAM read circuit does not work and the read enable voltage V read is low level, the pre-charge voltage V sa_pren is high level, since the first output terminal D out and the second output terminal D outn The initial voltage state will not affect the read action timing function. At this time, it is assumed that D out =V core , D outn = 0. Next, enter the read operation and set V read is pulled high, the tenth transistor M0 and the first transistor M1 act as switch tubes to connect the read circuit with the RRAM array; at the same time, V sa_pren Pulled to a low level, the sixth transistor M6 and the seventh transistor M7 are turned on, and the reading circuit performs a pre-charging operation. At this time, the first output terminal D out and the second output terminal D outn Charge to power supply voltage V core Since the second transistor M2 and the third transistor M3 have the same specifications, the fourth transistor M4 and the fifth transistor M5 have the same specifications, the sixth transistor M6 and the seventh transistor M7 have the same specifications, the eighth transistor M8 and the ninth transistor M9 have the same specifications, and the gate voltage of each pair of transistors is the same, the current flowing through L1 and L2 depends on R cell With R ref The size of the resistance.

[0105] When the variable resistance R cell The resistance value is greater than the reference resistor R ref The resistance value should be low (R cell <R ref ), at the beginning, the second output terminal D outn The voltage at the first output terminal D decreases faster than out The voltage of the first output terminal D out The voltage drop rate of the second output terminal D outn The faster drop will cause the ninth transistor M9 to be turned on before the eighth transistor M8. In addition, since the driving capability of the ninth transistor M9 is higher than that of the fifth transistor M5, the ninth transistor M9 is turned on to provide the first output terminal D out The charging speed of the fifth transistor M5 is greater than the discharging speed of the fifth transistor M5, so that the first output terminal D out Stop descending and quickly pull to V core , thereby making the fourth transistor M4 fully conductive, D outnPulling to ground causes the fifth transistor M5 to be completely turned off, and finally the second output terminal D outn The voltage of the first output terminal D out The voltage becomes the power supply voltage V core .

[0106] Similarly, when the variable resistance R cell The resistance value is greater than the reference resistor R ref The resistance value should be high (R cell >R ref ), at the beginning, the first output terminal D out The voltage at the second output terminal D drops faster than outn The voltage drop speed of the second output terminal D is faster, so that the eighth transistor M8 is turned on before the ninth transistor M9, and the driving capability of the eighth transistor M8 is higher than that of the fourth transistor M4, so that the second output terminal D outn The voltage drop stops and rises to the power supply voltage V core , and the first output terminal D out The voltage drops to 0.

[0107] Thus, the RRAM can be read by the RRAM reading circuit to change the variable resistance of the RRAM to Rcell The resistance signal is converted into a difference value, which is the power supply voltage V core output signal and inverted output signal.

[0108] In addition, in the present invention, if the variable resistor R cell The minimum value of the high impedance is set to R H , the variable resistor R cell The maximum value of the low resistance is set to R L , set the reference resistor value to R ref , then the resistance of the reference resistor can be calculated by the following formula:

[0109]

[0110] In addition, as an example, the variable resistance R of RRAM cell The high resistance of RRAM is greater than 500KΩ. cell The low resistance is less than 100KΩ, the reference resistance R ref The resistance value is 166.67KΩ, but the present invention is not limited to this.

[0111] Therefore, in the present invention, the process of reading the resistance value of the RRAM is mainly divided into two stages: the pre-charge stage and the comparison and read stage. In the pre-charge stage, since there are only the parasitic capacitances of the MOS transistors and the wire parasitic capacitances connected to the RRAM array, a stable I can be quickly formed. L1 I L2 ; In the comparison and read stage, by using the cross-coupled NMOS transistors and PMOS transistor pair composed of the fourth transistor M4, the fifth transistor M5, the ninth transistor M9, and the eighth transistor M8, the current signal is converted into a voltage signal through positive feedback, thereby increasing the read margin, enhancing the reliability of reading data from the RRAM, and greatly accelerating the comparison speed (for example, in a 28nm process, when the resistance value of the RRAM is 100KΩ and the wire parasitic capacitance is 300fF, the complete read operation time is within 1ns under normal process corners).

[0112] In addition, since the parasitic capacitance between the variable resistor of the RRAM and the reference resistor from the power supply voltage V core is low in the pre-charge stage, the pre-charge time is short, and the power consumption for charging the first output terminal D out and the second output terminal D outn to the power supply voltage V core is low. Moreover, the clamping voltage V clamp clamps the voltages of L1 and L2 at a low value, thereby limiting the currents of I L1 and I L2 . In addition, in the comparison and read stage, the cross-coupled positive feedback structure quickly pulls the first output terminal D out and the second output terminal D outn to 0 or 1, and then there is no dynamic current in the circuit. Therefore, the power consumption of the entire read process is very low.

[0113] In addition, in order to avoid miswriting the variable resistor of the RRAM, a stable anti-interference clamping voltage V clamp needs to be applied to the gate terminals of the second transistor M2 and the third transistor M3; and since there is no floating point at any time in this structure, a discharge transistor is not required, and structures such as operational amplifiers or comparators are not required either, thus occupying a smaller area.

[0114] <MRAM Read Circuit>

[0115] As mentioned above, although the structure of the RRAM read circuit has been described, since the principles and structures of the MRAM read circuit and the RRAM read circuit are similar, the above-described structure of the RRAM read circuit can also be applied to the MRAM read circuit.

[0116] Specifically, the present invention also provides an MRAM reading circuit, comprising: a reference resistor; a switch module, one side of which is connected to the reference resistor and the variable resistor of the MRAM, and is used to control the on-off between the reference resistor and the variable resistor of the MRAM and the clamping module; a clamping module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of the node between the clamping module and the switch module in the precharging step; a cross-coupling output module, one side of which is connected to the other side of the clamping module, and is used to convert the difference current formed in the precharging step into an output signal and an inverted output signal whose difference is the power supply voltage through positive feedback; and a precharging module, which is connected to the other side of the cross-coupling output module and is used to precharge the MRAM reading circuit.

[0117] In addition, other specific structures of the MRAM read circuit are similar to the above-mentioned specific structures of the RRAM read circuit, and repeated descriptions are omitted here.

[0118] In particular, as an example, the high resistance of the MRAM variable resistor is greater than 40KΩ, the low resistance of the MRAM variable resistor is less than 10KΩ, and the resistance of the reference resistor in the MRAM read circuit is 16KΩ, but the present invention is not limited thereto.

[0119] In the present invention, since the principle and structure of the reading circuit of MRAM are similar to those of the reading circuit of RRAM, the technical effect similar to that of the above-mentioned RRAM reading circuit can be achieved.

[0120] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present invention. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present invention, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

[0121] Industrial Applicability

[0122] The memory reading circuit of the present invention can be applied to reading memories such as RRAM and MRAM.

Claims

1. A memory reading circuit, characterized in that: include: Reference resistor; A switch module, one side of which is connected to the reference resistor and the variable resistor of the memory, and is used to control the on-off between the reference resistor and the variable resistor of the memory and the clamp module; A clamping module, one side of which is connected to the other side of the switch module, and is used to clamp the voltage of the node between the clamping module and the switch module in the pre-charging step; A cross-coupling output module, one side of which is connected to the other side of the clamping module, and is used to convert the difference current formed in the pre-charging step into an output signal with a difference of a power supply voltage and an inverted output signal through positive feedback; as well as a pre-charging module, which is connected to the other side of the cross-coupling output module and is used to pre-charge the read circuit of the memory, The cross-coupled output module includes a fourth transistor, a fifth transistor, an eighth transistor and a ninth transistor, The pre-charging module includes a sixth transistor and a seventh transistor, The gate of the fourth transistor is connected to the gate of the eighth transistor, the drain of the fifth transistor, the drain of the ninth transistor, the drain of the seventh transistor, and the first output terminal of the read circuit of the memory, The gate of the fifth transistor is connected to the gate of the ninth transistor, the drain of the fourth transistor, the drain of the eighth transistor, the drain of the sixth transistor, and the second output terminal of the read circuit of the memory, The gate of the sixth transistor is connected to the gate of the seventh transistor, the source of the sixth transistor is connected to the source of the seventh transistor, the source of the eighth transistor, and the source of the ninth transistor, The driving capability of the ninth transistor is higher than that of the fifth transistor, and the driving capability of the eighth transistor is higher than that of the fourth transistor.

2. The memory reading circuit according to claim 1, characterized in that: The memory is RRAM or MRAM.

3. The memory reading circuit according to claim 1 or 2, characterized in that: The reading circuit of the memory performs the following steps when reading: A precharging step for charging a first output terminal and a second output terminal of a read circuit of the memory to a power supply voltage; as well as A comparison readout step is used to convert the difference current formed in the pre-charging step into an output signal whose difference is the power supply voltage and an inverted output signal through positive feedback.

4. The memory reading circuit according to claim 1 or 2, characterized in that: The switch module includes a first transistor and a tenth transistor, The clamping module includes a second transistor and a third transistor. The source of the tenth transistor is connected to the variable resistor of the RRAM, the gate of the tenth transistor is connected to the gate of the first transistor, the drain of the tenth transistor is connected to the source of the second transistor, the source of the first transistor is connected to the reference resistor, and the drain of the first transistor is connected to the source of the third transistor. The gate of the second transistor is connected to the gate of the third transistor, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the third transistor is connected to the source of the fifth transistor. A power supply voltage is applied to the source of the sixth transistor, the source of the seventh transistor, the source of the eighth transistor, and the source of the ninth transistor, A read enable voltage is applied to the gate of the tenth transistor and the gate of the first transistor, a clamp voltage is applied to the gate of the second transistor and the gate of the third transistor, and a precharge voltage is applied to the gate of the sixth transistor and the gate of the seventh transistor. The read enable voltage, the clamp voltage, and the precharge voltage are set so that the memory can be read using a read circuit to convert the resistance signal of the variable resistor of the RRAM into an output signal with a difference of a power supply voltage and an inverted output signal.

5. The memory reading circuit according to claim 4, characterized in that: A node between the drain of the tenth transistor and the source of the second transistor is set as L1, and a node between the drain of the first transistor and the source of the third transistor is set as L2, The reading circuit of the memory performs the following steps when reading: a precharging step, in which the read enable voltage is set to a high level and the precharging voltage is set to a low level, so that the tenth transistor, the first transistor, the sixth transistor, and the seventh transistor are turned on, so that the first output terminal and the second output terminal are charged to the power supply voltage, and L1 and L2 are clamped at the clamping voltage; as well as A comparison readout step, in which the read enable voltage is maintained at a high level, and the pre-charge voltage is set to a high level, so that the tenth transistor and the first transistor remain turned on, and the sixth transistor and the seventh transistor are turned off, so as to convert the difference current formed in the pre-charge step into an output signal and an inverted output signal whose difference is the power supply voltage through positive feedback.

6. The memory reading circuit according to claim 5, characterized in that: In the comparison readout step, When the resistance value of the variable resistor of the memory is lower than the resistance value of the reference resistor, the voltage of the second output terminal decreases faster than the voltage of the first output terminal in the initial stage, so that the ninth transistor is turned on before the eighth transistor, and the driving capability of the ninth transistor is higher than that of the fifth transistor, so that the voltage of the first output terminal stops decreasing and rises to the power supply voltage, and the voltage of the second output terminal decreases to 0. When the resistance of the variable resistor of the memory is higher than the resistance of the reference resistor, the voltage of the first output terminal drops faster than the voltage of the second output terminal in the initial stage, so that the eighth transistor is turned on before the ninth transistor, and by utilizing the characteristic that the driving capability of the eighth transistor is higher than that of the fourth transistor, the voltage of the second output terminal stops dropping and rises to the power supply voltage, and the voltage of the first output terminal drops to 0.

7. The memory reading circuit according to claim 1 or 2, characterized in that: The lowest value of the high resistance of the variable resistor of the memory is set to R H , the maximum value of the low resistance of the variable resistor of the memory is set to R L , set the resistance of the reference resistor to R ref , The resistance of the reference resistor is calculated by the following formula:

8. The memory reading circuit according to claim 7, characterized in that: The high resistance of the variable resistor of the memory is greater than 500KΩ, the low resistance of the variable resistor of the memory is less than 100KΩ, and the resistance value of the reference resistor is 166.67KΩ.

9. The memory reading circuit according to claim 7, characterized in that: The high resistance of the variable resistor of the memory is greater than 40KΩ, the low resistance of the variable resistor of the memory is less than 10KΩ, and the resistance value of the reference resistor is 16KΩ.

10. The memory reading circuit according to claim 4, characterized in that: The specification of the tenth transistor is the same as that of the first transistor, The specification of the second transistor is the same as that of the third transistor, The specification of the fourth transistor is the same as that of the fifth transistor, The specification of the sixth transistor is the same as that of the seventh transistor, The specification of the eighth transistor is the same as the specification of the ninth transistor.

11. The memory reading circuit according to claim 4, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the tenth transistor are NMOS transistors, and the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS transistors.

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