67results about How to "Improve comparison speed" patented technology

The invention relates to a detection method on similarity of academic thesis based on a computer searching system, to provide a searching model and a similarity algorithm with pertinence through using structures and language features of the academic thesis, thereby increasing speed and efficiency of copy edit of the expert when the thesis is submitted to a higher level for approval or revision. A technical scheme of the invention comprises: an academic thesis copy detecting method based on the computer searching system, comprising the steps of: the step of building an academic thesis database on a server; the step of building a storage space of the academic thesis data based on the computer searching system; the step of building an alternation window on the server for the user to input searching condition; the step of submitting the academic thesis to be detected; building the academic thesis data ans storing according to the set searching condition; the step of comparing the academic thesis data and the data in a source database; the step of submitting the compacting result to the user by the server.

The invention discloses a gene sequence comparison method. The method comprises steps that a to-be-compared sequence and a reference sequence are determined, and a pointer table and a candidate comparison position table are determined according to the reference sequence; a seed sequence of a preset length is extracted from the to-be-compared sequence, and an index value of the seed sequence is determined; the pointer table and the candidate comparison position table are queried according to the index value of the seed sequence; whether the position information corresponding to the seed sequence exists in the reference sequence is determined; if yes, the seed sequence is used as a to-be-extended sequence, according to the position information, on the basis of the reference sequence, the to-be-extended sequence is extended to obtain an intermediate sequence, and the intermediate sequence and the to-be-compared sequence are compared to obtain the gene sequence comparison result. The method is advantaged in that the storage space of the table storing the reference sequence index value can be reduced, and the gene sequence comparison rate can be increased. The invention further discloses a gene sequence comparison system, a computer readable storage medium and an electronic device. The advantages are realized.

The invention discloses a file access filtering method which belongs to the technical field of network safety. The file access filtering method comprises the following steps: S1) processing an IRP (input/output request package) request category and a request of withdrawing from drive, and mounting a corresponding dispatch function; S2) processing calling of a user layer, and emitting a calling command to an inner nuclear layer; S3) getting an afferent Handle through a parameter when calling a Windows inner nuclear function in user-defined functions, and inquiring whether a path corresponding to the Handle is a file folder path or not by calling the inner nuclear function of a system, if the path is the file holder path and does not contain a magnetic disk drive, not performing contrast, if the path is a file path, comparing in a white list; and S4) notifying an application program of the user layer of retrieving illegal access file information recorded in a BackList through a shared event created between the user layer and the inner nuclear layer, and using the application program of the user layer to write the illegal access file information into a log file. By adopting the file access filtering method, a user can conveniently further adopt measures for protecting personal files.

The invention discloses an intelligent cleaning method for structured data, being applied to the technical field of data processing. The intelligent cleaning method comprises the following steps: acquiring a to-be-cleaned data file based on a local file read-write interface, and establishing a file list; merging all the to-be-cleaned data files into a to-be-cleaned file; identifying a data type and a file format contained in the to-be-cleaned file by using the hash table, and marking a template type to which the identifiable file data belongs; loading a file list according to the marked template type, and sequentially carrying out header identification, data verification, format screening and duplicate checking data cleaning processing on the file data; and inputting the cleaned data intoa database one by one by using an SQL querier. According to the intelligent cleaning method, the workload of manual secondary input in the multi-file data cleaning process can be effectively reduced,and the data cleaning efficiency is remarkably improved.

The invention suitable for the field of image processing and provides a picture taking method and device. The method comprises the steps that a picture obtained through last time picture taking is obtained; the obtained picture is processed, and the picture with a foreground region removed and a remaining background region is obtained; semi-transparent processing is carried out on the picture with the remaining background region, a semi-transparent background region is obtained, and the semi-transparent background region and a current scenery background region which are superposed are displayed in a display window; the angle of a camera is adjusted, and the scenery background region and the semi-transparent background region are made to be at least partially superposed. The picture taking method and device can improve the accuracy of comparison of people or objects in different times.

The invention discloses a biological characteristic recognition-based identity card verification method and system. The method includes the following steps that: acquiring the information of an identity card; recognizing the information of the identity card; carrying out blacklisted identity card verification; acquiring biological characteristic information; carrying out blacklisted biological characteristic verification; carrying out biological characteristic recognition; and updating basic information in a basic information storage module. The information of the identity card itself is verified, so that the identity card itself can be a valid identity card, and therefore, the counterfeiting of the identity card can be prevented; the information of the identity card is compared with blacklisted identity cards, the biological characteristic information card of the holder of the identity card are compared with that of blacklisted people, so that the holder of the identity card can be judged, and therefore, a dangerous person can be prevented from being mixed himself or herself into ordinary people, and the safety of coming and going people can be improved; grading setting is adopted when the information of the identity card is compared with the basic information, and therefore, comparison rate can be improved; and the basic information of people is updated, so that the time interval of the acquired biological characteristic information of the holder of the identity card and the basic information of the people can be shortened, and the accuracy of biological recognition can be improved.

The invention is a low-power, high-speed, high-precision comparator circuit compatible with standard CMOS technology, characterized in that: the low-power, high-speed, high-precision comparator circuit includes sequentially connected input sampling switches, preamplifiers, and two-stage preamplifiers And latch; input sampling switch includes a pair of switches for sampling input signal and a pair of switches for sampling reference voltage; The terminal output further increases the amplification factor, and the capacitor link between the secondary amplifier and the preamplifier eliminates the offset input offset and output offset. Control the working state of the latch; its advantage lies in: the low power consumption, high speed and high precision comparator circuit can greatly improve the speed and precision of the comparator.

The invention relates to the field of winches, in particular to an automatic gear shifting and speed changing planet gear transmission and a winch provided with the automatic gear shifting and speed changing planet gear transmission. The automatic gear shifting and speed changing planet gear transmission comprises a motor or hydraulic motor, a transmission body, a gear shifting mechanism, a reel, a brake, a rack and the like. A flange at the end portion of the motor or hydraulic motor is installed at one end of the rack through a bolt. A hollow motor rotor shaft or hydraulic motor power output shaft is internally provided with an inner spline in clearance fit with an outer spline at the end portion of a transmission drive shaft. During gear shifting, the drive shaft can move linearly in a reciprocating manner in the hollow shaft. The planet gear transmission which is simple in structure, small in size, large in torque, high in transmission efficiency and capable of shifting the gear and adjusting the speed according to loads and the winch provided with the transmission are provided, electric utilization and fuel are greatly reduced, and the economic effect is good.

The present invention relates to a system for managing IFC versions by comparing two or more IFC files produced with a time interval therebetween so as to trace the alteration history, and to a method for managing the IFC file version thereof. A system for managing the IFC versions includes: a comparison target processing unit for acquiring first IFC file attribute information concerning a first IFC file and second IFC file attribute information concerning at least one second IFC file; a GUID comparison engine for comparing a first IFC file GUID set containing first IFC GUIDs with a second IFC file GUID set containing second IFC GUIDs; and a spatial object comparison engine for comparing a first IFC file spatial object information set containing first IFC file spatial objects with a second IFC file spatial object information set containing second IFC file spatial objects.

The invention discloses an optimization method for accurate species identification of human flora through high-throughput 16S rDNA sequencing. The optimization method comprises the following steps: 1)establishing a human metagenome bacterium genome database based on human microorganism samples; 2) extracting full-length 16S rDNA sequences of the human metagenomic bacterium genome database, and establishing 16S rDNA species annotation databases of different human body parts; and 3) establishing a sample-strain 16S sequence abundance correlation network, and training a machine learning model byusing the data. The invention also provides a method for performing species identification and abundance calculation on the high-throughput sequencing 16S rDNA sequences by using the constructed database and model. According to the invention, the species classification resolution and accuracy of 16S rDNA can be greatly improved, so an analyst can find more accurate and clear strains according toresults.

The invention relates to the design field of the integrated circuit, and especially relates to a successive approximation type ADC circuit for solving the problem that the low conversion precision isexistent in the traditional SAR ADC architecture in the prior art. The successive approximation type ADC circuit comprises a digital-to-analog converter DAC, a comparator, and a successive approximation register SAR, wherein the DAC comprises a first capacitor array and a second capacitor array, is used for inputting sampling hold of an analog signal, and is further used for the conversion outputof a DA signal; the comparator is used for comparing two analog voltage signals output by the DAC; and the SAR is used for controlling the quantization output of the analog voltage signals in the DACcycle-by-cycle, and determining the value of each bit in the SAR one-by-one according to an output result of the comparator, thereby acquiring a digital signal and outputting the digital signal. The novel SAR ADC circuit simplifies the complexity of the circuit design, reduces the loss of a silicon wafer area, and improves the conversion precision of the successive approximation type ADC.

The invention discloses a method, a device and equipment of strategy consistency auditing, and belongs to the technical field of terminal equipment. The method comprises the steps that characteristic values of strategy data of a webmaster server and the equipment are respectively calculated, the characteristic values of each strategy datum comprises a first cyclic redundancy check value and a second cyclic redundancy check value, the first cyclic redundancy check values are the cyclic redundancy check values of the strategy data, the second cyclic redundancy check values are cyclic redundancy check values of a common target referenced by the strategy data, and the characteristic values of the strategy data of the webmaster server and the equipment are contrasted to obtain an auditing result. The characteristic value of the strategy data of the webmaster server and the equipment are contrasted, so an auditing result error due to the fact that strategies which are different in sequence number and identical in business content are erroneously judged to be inconsistent can be avoided, contrast speed is accelerated, and auditing efficiency is improved.

A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N≧2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed.

The invention discloses a rapid analog-to-digital conversion method and an analog-to-digital converter. The analog-to-digital conversion method comprises steps that a precise regulated high power supply Ug and a precise regulated low power supply Ud form a precise voltage range, n serial reference divider resistors are connected with two ends of the precise voltage range, and reference voltages ofn comparators are formed due to voltage division; a to-be-tested analog voltage and a reference voltage are compared, and a turning point Uk exists in a comparison result; a next comparison voltage range is created based on the turning point Uk, the steps are recycled till set precision is obtained through comparison; and in the final comparison, the to-be-tested analog voltage U is a mean valueof Uk and U(k+1) and is output. According to the method, the next comparison is based on the previous comparison, comparison is not started from zero and is performed only in one comparison time, so that the comparison speed is improved.

The invention discloses a method for increasing comparison speed of a comparator circuit, a charge pump and an improved comparator circuit, and relates to the field of comparator circuits. The limit of a power voltage to the speed of a comparator is reduced, and the comparison speed of the comparator is increased at the low power voltage. The charge pump comprises a first switch, a second switch, a third switch and a charge pump capacitor, wherein one end of the first switch is connected with a voltage boost source of the charge pump, and the other end of the first switch is connected with the comparator circuit; one end of the second switch is grounded, and the other end of the second switch is connected with the charge pump capacitor; one end of the third switch is connected with the power voltage and the other end of the third switch is connected with the charge pump capacitor; the second switch and the third switch are connected with the same side of the charge pump capacitor; and one end of the charge pump capacitor not connected with one end of the second switch is connected with the comparator circuit. The method for increasing comparison speed of the comparator circuit is applied to the comparator circuit.

The invention discloses a high-speed dynamic comparator with a metastable state suppression technology. The high-speed dynamic comparator comprises a pre-amplifier, a post-latch and a metastable state suppression circuit, the pre-stage amplifier amplifies an input differential signal, drains of a first PMOS tube and a second PMOS tube of the pre-stage amplifier are connected with the post-stage latch, the positive feedback characteristic of the latch is utilized, a pull-down NMOS tube and a pull-up PMOS tube are added, and pull-up or pull-down of an amplifier positive end output signal and an amplifier negative end output signal is completed. And a relatively high comparison speed is realized. And after comparison is completed, the tail current tube is quickly turned off, so that the comparator has no static power consumption, and the power consumption of the comparator is effectively reduced. The invention adopts a metastable state suppression technology, effectively suppresses the metastable state of the comparator without introducing obvious delay, and does not obviously increase the comparison time of the comparator.